Calibration circuit for comparator and comparator calibration method

Abstract

The invention relates to the technical field of analog-to-digital conversion, and discloses a calibration circuit for a comparator, and the comparator comprises a pre-stage preamplifier and a pre-stage latch. The calibration circuit comprises two groups of calibration MOS (Metal Oxide Semiconductor) tube arrays which are respectively connected in parallel with the source electrode and the drain electrode of the input geminate transistors of the pre-stage latch; each group of calibration MOS tube array comprises a plurality of calibration MOS tubes which are connected in parallel, each calibration MOS tube is grounded by being connected with a switch in series, and the grid electrode of each calibration MOS tube is connected with the grid electrode of the input tube on the corresponding side; when the switches are turned on, the corresponding series-connected calibration MOS tubes work, and the working state of the series-connected calibration MOS tubes is the same as the working state of the parallel-connected input tubes. And when the offset voltage of the comparator is calibrated, the calibration MOS tube in the working state is adjusted for calibration. The circuit is simple in structure, and the layout area of the circuit can be effectively reduced. The invention further discloses a calibration method for the comparator.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, for example, to a calibration circuit for a comparator and a method for calibrating a comparator. Background Art

[0002] SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a type of analog-to-digital converter. A common N-bit SAR ADC includes a capacitor array in binary ratio, digital logic, and a comparator. SAR ADC uses only one comparator and converts data using the binary division principle. The comparator determines the performance, operating speed, and signal-to-noise ratio of the SAR ADC to a large extent. At the same time, the offset of the comparator also determines the accuracy of the ADC quantization result.

[0003] For SAR ADC, offset is caused by factors such as device mismatch, different temperature stress in different parts of the layout, and layout mismatch. This offset is equivalent to adding a DC offset voltage to the differential input of the comparator, thereby affecting the accuracy of the ADC quantization result. In severe cases, this offset also affects the full swing range and signal-to-noise ratio of the system, and the offset often changes with factors such as the temperature inside the chip. Therefore, the offset needs to be calibrated to eliminate the quantization error caused by the offset.

[0004] The related technology discloses an offset voltage correction circuit and an offset voltage correction method, wherein the offset voltage correction circuit includes: a data acquisition module, which is used to receive a data signal and a reference signal, and obtain a data indication signal according to a comparison result between the reference signal and the offset data signal, wherein the offset data signal is a data signal after the offset signal is superimposed; an adjustment enable module, which is used to receive a data signal, a reference signal, a data indication signal and an enable signal; if the enable signal is a high level, a theoretical indication signal is obtained according to a comparison result between the data signal and the reference signal, and an enable identification signal is generated based on a comparison result between the theoretical indication signal and the data indication signal; an offset correction module, which is used to offset the offset signal based on the enable identification signal; and the input offset voltage is offset at the input stage of the operational amplifier.

[0005] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0006] Although the related technology can offset the input offset voltage, the correction circuit structure is relatively complex, resulting in a larger circuit layout area.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0009] The embodiments of the present disclosure provide a calibration circuit for a comparator and a method for calibrating the comparator to reduce the layout area of ​​a chip.

[0010] In some embodiments, the comparator includes a front-stage preamplifier and a front-stage latch; the calibration circuit includes: two groups of calibration MOS tube arrays, which are respectively connected in parallel to the source and drain of the input pair of tubes of the front-stage latch; each group of calibration MOS tube arrays includes a plurality of parallel calibration MOS tubes, and each calibration MOS tube is grounded by a series switch, and the gate of the calibration MOS tube is connected to the gate of the corresponding side input tube; wherein, when the switch is turned on, the corresponding series-connected calibration MOS tube works and the working state is the same as the working state of the parallel-connected input tube; when the offset voltage of the calibrator is calibrated, the calibration MOS tube in the working state is adjusted to perform calibration.

[0011] In some embodiments, the method includes: when the comparator is in a calibration mode, sampling the output result of the comparator; determining whether the comparator is misaligned based on the output result; when it is determined that the comparator is misaligned, determining the target calibration MOS tube array to be adjusted based on the misalignment direction, and performing adjustment.

[0012] The calibration circuit for a comparator and the method for calibrating a comparator provided in the embodiments of the present disclosure can achieve the following technical effects:

[0013] In the disclosed embodiment, a set of calibration MOS tube arrays controlled by switches are added to the input pair of the pre-stage latch of the comparator. When the comparator performs offset voltage calibration, the calibration MOS tubes in the two sets of calibration MOS tube arrays that are in working state are controlled. This affects the discharge speed at both ends of the differential to eliminate the offset voltage. The calibration circuit can be calibrated in the background without affecting the quantization behavior of the comparator. At the same time, the simple circuit structure can effectively reduce the circuit layout area.

[0014] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0016] Figure 1 It is a partial circuit diagram of a comparator in the prior art provided by an embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram of a framework of a calibration circuit for a comparator provided by an embodiment of the present disclosure;

[0018] Figure 3 is a schematic diagram of a partial circuit structure of a comparator provided by an embodiment of the present disclosure;

[0019] Figure 4 is a schematic diagram of a circuit structure of a calibration MOS tube array provided by an embodiment of the present disclosure;

[0020] Figure 5 is a structural schematic diagram of a common-mode voltage generating circuit provided by an embodiment of the present disclosure;

[0021] Figure 6 is a schematic diagram of a calibration method for a comparator provided by an embodiment of the present disclosure;

[0022] Figure 7 is a schematic diagram of another calibration method for a comparator provided by an embodiment of the present disclosure;

[0023] Figure 8 is a schematic diagram of a calibration device for a comparator provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0025] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0026] Unless otherwise stated, the term "plurality" means two or more.

[0027] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0028] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0029] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0030] Combination Figure 1 As shown, the comparator 100 generally includes a preamplifier 10, a pre-latch 20 and a storage latch. The preamplifier 10 is used to amplify the input differential signal and suppress noise; wherein, the preamplifier in the low-power design is a dynamic amplifier. The pre-latch 20 uses the principle of positive feedback to enhance the amplification of the difference between the two input signals. The storage latch (not shown in the figure) is used to save the current result when the latch is set. Among them, the step response of the preamplifier 10 is fast at first and then full, while the pre-latch 20 is the opposite. The preamplifier 10 is used to amplify the differential signal input to a slow change interval beyond the pre-latch 20, thereby reducing the delay of the comparator 100.

[0031] Specifically, the differential mode signal includes Vip and Vim, which are respectively used as the positive input signal and the negative input signal of the front stage pre-amplifier 10; after being amplified by the front stage pre-amplifier 10, the differential mode voltages Vp and Vm are output. The differential mode voltages Vp and Vm are used as two input signals of the front stage latch 20, and the differential mode voltages are compared and the comparison results are output. Among them, the front stage latch includes input pair tubes M1 and M4, MOS tubes M2, M3, M5, and M6 constituting inverters, and MOS tube M7 of the current source. The gates of the input pair tubes M1 and M4 are respectively connected to the differential mode signals Vp and Vm; the drain voltages of the MOS tubes M5 and M6 are respectively used as the output voltages Vop and Vom. The gate of the MOS tube M7 is connected to the clock signal clk_b for resetting.

[0032] The working principle of the comparator 100 is as follows: When the clock signal clk_b is a high-level signal, the comparator is in the setting stage. The output of the pre-amplifier is set to high, so that the gate input signal of the pre-latch input to the tubes M1 and M4 is a high-level signal, and the two differential outputs of the pre-latch are pulled down, that is, the output voltages Vop and Vom are low-level signals. When the clock signal clk_b is a low-level signal, the comparator is in the comparison stage. The differential mode voltages Vp and Vm output by the pre-amplifier begin to discharge. Due to the different magnitudes of the differential mode voltages input to the comparator, the discharge speeds of Vp and Vm are different. When the voltage Vm is greater than the threshold voltage of the input tube M1, the input tube M1 is turned on, the drain of the input tube M1 begins to discharge, and the gate of M5 also begins to discharge (similarly, when the voltage Vp is greater than the threshold voltage of the input tube M4, the gate of M6 also begins to discharge). When Vm is greater than Vp, the gate voltage of M5 is pulled down to ground before the gate voltage of M6, and M2 is turned off first, thereby outputting two comparison results, a high level and a low level (ie, Vom=1, Vop=0).

[0033] Based on the above basic principles, in order to solve the comparator offset problem, combined with Figure 2 , 3 As shown, the embodiment of the present disclosure provides a calibration circuit for a comparator, including: two groups of calibration MOS tube arrays 31 and 32, which are respectively connected in parallel to the source and drain of the input pair tubes M1 and M4 of the previous latch; each group of calibration MOS tube arrays includes a plurality of parallel calibration MOS tubes, and each calibration MOS tube is grounded by connecting a switch in series, and the gate of the calibration MOS tube is connected to the gate of the corresponding side input tube (i.e., M1 or M4).

[0034] Among them, when the switch is turned on, the corresponding series-connected calibration MOS tube works and the working state is the same as the working state of the parallel-connected input tube; when calibrating the comparator offset voltage, the number of calibration MOS tubes in the working state is adjusted to perform calibration.

[0035] Here, the second calibration MOS tube array 32 is connected in parallel to the drain-source ends of the input tube M1 of the previous latch, and the first calibration MOS tube array 31 is connected in parallel to the drain-source ends of the input tube M4. Each calibration MOS tube in the calibration MOS tube array is connected in series with a switch and then grounded. When the switch is disconnected, the calibration MOS tube is not turned on and there is no current path to the bottom, which does not affect the normal operation of the comparator. When the switch is turned on, because the drain of the calibration MOS tube is connected to the drain of the input tube and is consistent with the gate signal of the corresponding side input tube (that is, the gates of the two are also connected). Therefore, the working state of the calibration MOS tube is the same as the working state of the corresponding input tube M1 or M4. In this way, the drain discharge capacity of the input tube M1 or M4 is increased. Among them, the calibration MOS tube connected to the comparator circuit in the calibration MOS tube array is adjusted so that there is a difference in the discharge capacity at both ends of the difference to eliminate the offset voltage.

[0036] As an example, when the sizes of the calibration MOS tubes are consistent, the number of calibration MOS tubes connected to the comparator circuit is adjusted to adjust the discharge capacity. As another example, when the sizes of the calibration MOS tubes are different, the number and / or size of the calibration MOS tubes connected to the comparator circuit is adjusted to adjust the discharge capacity.

[0037] In the disclosed embodiment, a set of calibration MOS tube arrays controlled by switches are added to the input pair of tubes of the pre-stage latch of the comparator. When the comparator performs offset voltage calibration, the calibration MOS tubes in the two sets of calibration MOS tube arrays that are in working state are controlled. This affects the discharge speed at both ends of the differential to eliminate the offset voltage. The calibration circuit can be calibrated in the background without affecting the quantization behavior of the comparator. At the same time, the simple circuit structure can effectively reduce the layout area of ​​the circuit. In addition, the calibration circuit can be used as a submodule circuit and transplanted between different analog-to-digital converters.

[0038] Combination Figure 4 Optionally, the switch in the calibration MOS transistor array is a MOS transistor switch, wherein the gate signal of the MOS transistor switch is controlled to control the on and off of the MOS transistor switch.

[0039] Here, the MOS tube switch is an NMOS tube, whose source is grounded, and whose drain is connected to the source of the calibration MOS tube. In this way, when the gate signal of the MOS tube switch is at a high level, the MOS tube switch is controlled to be turned on, so that the drain of the calibration MOS tube connected in series to the ground begins to discharge. As an example, each group of calibration MOS tube arrays includes 6 parallel calibration MOS tubes (respectively NM6 to NM1), and the corresponding MOS tube switches are also 6, namely D[5]...D[0], D[1]. The state machine 200 adjusts the state of the switch by controlling the signal of D[i]. As an example, a 6-bit binary control word can be used to adjust the standard MOS tube in each group of calibration MOS tube arrays connected to the comparator. For example, if the control word is 100010, it means that the MOS tube switches of D[1] and D[5] are turned on.

[0040] Optionally, the two groups of calibration MOS tube arrays have the same number of calibration MOS tubes, and the size of each MOS tube in each group of calibration MOS tube array increases exponentially in sequence.

[0041] When calibrating the comparator offset voltage, the calibration MOS tubes in the two groups of calibration MOS tube arrays that are in working state are different.

[0042] Here, the number of calibration MOS tubes in the two groups of calibration MOS tube arrays is the same, such as 6 calibration MOS tubes in both groups. In this way, it is easy to control and transplant. However, during the calibration process, since an offset voltage is added to one input end of the comparator, the discharge speed of one side needs to be adjusted in order to eliminate the offset voltage. It can be understood that when the input differential mode voltage is different, the two differential ends of the previous latch end discharge before the other end, that is, the voltage is pulled down to the ground. After one end is added to the calibration MOS tube array, the discharge speed of the end is accelerated. And the more calibration MOS tubes are added, the faster the discharge speed. If the calibration MOS tubes added to the two differential ends are the same, the difference in the discharge capacity of the two differential ends cannot be improved. Therefore, in order to calibrate the offset voltage, the MOS tubes added to the circuit in the two groups of calibration MOS tube arrays need to be different (including the number and / or size of calibration MOS tubes).

[0043] In addition, the size of each MOS tube in each group of calibration MOS tube array increases exponentially means that the size of each MOS tube is different, and the size between adjacent MOS tubes increases exponentially. As an example, there are 6 MOS tubes in each group of calibration MOS tube array, namely NM1 to NM6. Among them, the size of NM1 is the smallest, which is S1. Then the size of NM2 is 2 times S1, the size of NM3 is 4 times S1, and so on. The size of NM6 is 2 5 times S1. This helps to increase the adjustment range of the calibration MOS tube array and helps to select the adjustment range.

[0044] Optionally, the change amount of the offset voltage caused by the smallest unit calibration MOS tube in each group of calibration MOS tube arrays is greater than the equivalent input noise of the comparator.

[0045] Among them, the smallest unit of calibration MOS tube is the smallest size MOS tube.

[0046] Usually, the offset voltage of the comparator is measured by the equivalent input noise of the comparator. If the offset voltage is small, it will not significantly affect the performance of the comparator, so it is not calibrated at this time. If the offset voltage is large, the offset voltage of the comparator needs to be calibrated. During the calibration process, when the calibration amplitude is small, multiple calibrations are required and it may not even be possible to calibrate to the ideal state. Therefore, it is stipulated here that the change in the offset voltage of the smallest unit calibration MOS tube is greater than the equivalent input noise of the comparator. In this way, the calibration MOS tube in the working state can be selected based on the size of the offset voltage. Thereby achieving effective calibration.

[0047] Based on the aforementioned calibration circuit, combined with Figure 4 As shown, the embodiment of the present disclosure provides a method for comparator calibration, comprising:

[0048] S101, when the comparator is in a calibration mode, the state machine samples the output result of the comparator.

[0049] S102: The state machine determines whether the comparator is out of adjustment according to the output result.

[0050] S103, when it is determined that the comparator is misaligned, the state machine determines the target calibration MOS transistor array to be adjusted according to the misalignment direction, and performs adjustment.

[0051] Here, the state machine is a system with processing logic, which is used to control the workflow of the system on chip, etc. The state machine receives the output result of the comparator and controls the calibration of the MOS tube array based on the control word. The offset voltage refers to the input voltage difference corresponding to the jump of the comparator output when there is no input signal. In order to determine the size of the offset voltage, the output result of the comparator is sampled when the comparator is in calibration mode. Among them, in the calibration mode, the voltage signals connected to the two input terminals of the comparator are equal, such as connecting equal common-mode voltage signals. The comparator compares the input voltage signals and outputs two voltage signals. When the offset voltage is large, one of the output voltage signals Vop and Vom is high and the other is low. In this case, it is determined that the comparator offset needs to be calibrated.

[0052] After determining the comparator offset, the target calibration MOS tube array to be adjusted is determined based on the offset direction. The target calibration MOS tube array is adjusted to improve the discharge capacity of the differential end on this side. Specifically, the offset direction can be determined based on the size of the output voltage signal. When the positive end output signal Vop is connected to the state machine, if the output voltage signal Vop is a high level signal, it indicates that the current discharge speed of the differential end is faster; while the discharge speed of the other differential end is slower. In this way, the input signal Vp end offset is determined, that is, the comparator's in-phase input end offset. Then, the number of calibration MOS tubes incorporated into the circuit in the first calibration MOS tube array, that is, the number of calibration MOS tubes in working state, can be adjusted. Thereby improving the discharge capacity of the inverting differential end to eliminate the offset.

[0053] Using the method for comparator calibration provided by the embodiment of the present disclosure, when the comparator is in calibration mode, the output result of the comparator is sampled. Based on the sampled output result, it is determined whether the comparator needs to be calibrated. If calibration is required, the target calibration MOS tube array to be adjusted is determined based on the offset direction. In this way, the offset voltage of the comparator can be calibrated in real time, and the power consumption required for calibration can be effectively reduced.

[0054] Optionally, in step S101, the state machine determines that the comparator is in the calibration mode in the following manner:

[0055] When the quantization cycle of the comparator ends, the state machine receives the calibration control clock signal, and the signals at the two input terminals of the comparator are equal common mode voltage signals.

[0056] Here, after a quantization cycle of the comparator ends, if the state machine receives a calibration control clock signal, the two input terminals of the control comparator are connected to equal common-mode voltage signals. The comparator enters calibration mode. Among them, the calibration clock is generated by synchronous timing logic and is the same as the sampling period of the comparator. In this way, the embodiment of the present disclosure does not need to be calibrated first after the analog-to-digital converter is turned on, and only the calibration cycle needs to be inserted in the adjacent quantization cycle. Thereby, the background calibration technology is realized, and the real-time calibration can also make the calibration result change with the change of PVT (Process-Voltage-Temperature). This helps to improve the accuracy and adaptability of the analog-to-digital converter.

[0057] In addition, the common-mode signal is generated by a resistor string controlled by a switch, see Figure 5 .

[0058] Optionally, in step S102, the state machine determines whether the comparator is out of adjustment according to the output result, including:

[0059] In a plurality of consecutive sampling cycles, when the absolute difference between the number of high voltage signals and the number of low voltage signals outputted is greater than a preset threshold and the positive and negative values ​​of the difference are consistent, the state machine determines that the comparator is out of adjustment.

[0060] The output result includes an output high voltage signal and an output low voltage signal.

[0061] Here, in order to improve the accuracy of the judgment, the comparator is determined to be out of adjustment when the output results of multiple consecutive sampling cycles are basically consistent. Specifically, the output results are basically consistent, including that the absolute difference between the number of high voltage signals num_h and the number of low voltage signals num_l output is greater than the preset threshold diff_target, and the positive and negative conditions of the difference are consistent. Among them, the positive and negative conditions of the difference are the same, which means that the difference ΔV=num_h-num_l is greater than zero in multiple consecutive calibration cycles, or ΔV is less than zero; the absolute difference is |ΔV|. Among them, the number of sampling cycles is greater than or equal to 5.

[0062] As an example, the positive output signal Vop of the comparator is connected to the state machine and is sampled 6 times continuously. If |ΔV|>diff_target and ΔV>0 are satisfied, the comparator is out of adjustment.

[0063] Optionally, in step S103, the state machine determines the misalignment direction in the following manner:

[0064] In the case that the number of high voltage signals in the output result is greater than the number of low voltage signals, the state machine determines that the offset direction is the non-inverting input terminal.

[0065] In the case where the high voltage signal in the output result is less than the low voltage signal, the state machine determines that the offset direction is the inverting input terminal.

[0066] Here, the positive output signal Vop of the comparator is connected to the state machine. If the number of high voltage signals output by the previous latch is greater than the number of low voltage signals, the offset direction is determined to be the non-inverting input of the comparator. Otherwise, the offset direction is determined to be the inverting input of the comparator. In this way, the offset direction can be determined based on the output signal. Furthermore, the target calibration MOS tube array to be adjusted can be determined based on the offset direction. Thus, the calibration MOS tube is effectively adjusted to eliminate the offset voltage.

[0067] Optionally, in S103, the state machine determines a target calibration MOS tube array to be adjusted according to the misalignment direction, including:

[0068] In the case where the misalignment direction is the in-phase input terminal, if the switch state of the calibration MOS tube array is all off, the state machine determines that the target calibration MOS tube array to be adjusted is the second calibration MOS tube array; if the switch state of the calibration MOS tube array is partially off, the state machine determines that the target MOS tube array to be adjusted is the first calibration MOS tube array or the second calibration MOS tube array.

[0069] In the case where the misalignment direction is the inverting input terminal, if the state of the switch of the calibration MOS tube array is all turned off, the state machine determines that the target calibration MOS tube array to be adjusted is the first calibration MOS tube array; if the switch state of the calibration MOS tube array is partially turned off, the state machine determines that the target MOS tube array to be adjusted is the first calibration MOS tube array or the second calibration MOS tube array.

[0070] Combination Figure 3 As shown, the non-inverting input terminal of the previous latch is Vp, and the inverting input terminal is Vm; the positive output Vop is connected to the state machine. When the misalignment direction is the non-inverting input terminal, it indicates that the discharge speed of the differential end MOS tube M6 is faster. In order to eliminate the misalignment, the discharge speed of the other differential end MOS tube M5 can be increased, or the discharge speed of the differential end MOS tube M6 can be reduced. Specifically, it depends on the current state of the calibration MOS tube array. If the switches of the two groups of calibration MOS tube arrays are currently in the off state, that is, the calibration MOS tubes are not connected to the circuit, then the second calibration MOS tube array 32 is determined to be the target array. That is, by controlling the switch state of the second calibration MOS tube array 32, the calibration MOS tube is connected to the circuit, thereby increasing the discharge speed of M5 to eliminate the misalignment.

[0071] If one or two of the switches of the two current calibration MOS tube arrays are partially turned on, then when the switches of the first calibration MOS tube array 31 are partially turned on, the first calibration MOS tube array 31 is determined to be the adjustment target. And the number or size of the calibration MOS tubes connected to the circuit is reduced, thereby reducing the discharge speed of the differential end. Alternatively, when the switches of the second calibration MOS tube array 32 are partially turned on, the second calibration MOS tube array 32 is determined to be the adjustment target. And the number or size of the calibration MOS tubes connected to the circuit is increased, thereby increasing the discharge speed of the differential end. If two of the switches of the two current calibration MOS tube arrays are partially turned on, it can also be determined that the first calibration MOS tube array 31 and the second calibration MOS tube array 32 are both adjustment targets.

[0072] Similarly, when the misalignment direction is the inverting input terminal, the discharge speed of the non-inverting input terminal is increased, or the discharge speed of the inverting input terminal is decreased based on the above principle.

[0073] Optionally, in step S103, the state machine adjusts the target calibration MOS tube array, including:

[0074] The state machine uses the minimum calibration step as the minimum unit and the calibration step is in ascending order, and uses the binary control target to calibrate the number of switch MOS tubes in the MOS tube array.

[0075] The minimum calibration step size depends on the minimum size of the calibration MOS tube.

[0076] Here, the minimum calibration step is determined based on the calibration MOS tube of the smallest size. In the calibration process, taking the minimum calibration step as the smallest unit means that only one calibration MOS tube in working state is added for each calibration. Following the order of the calibration step from small to large means that the calibration MOS tube of smaller size is turned on first during calibration. If the output result characterizes that calibration is still required, the calibration MOS tube currently in working state is turned off, and another calibration MOS tube is turned on at the same time. Among them, the size of the other calibration MOS tube is larger than the size of the calibration MOS tube turned on previously, and the sizes of the two are adjacent. As an example, the control word of the first calibration MOS tube during the first calibration is 000010, that is, the second switch D[1] is turned on. The comparison result after this adjustment does not meet the corresponding conditions and needs to be adjusted further. Then the control word during the second calibration is 000100, that is, the third switch D[2] is turned on. The size of the standard MOS tube corresponding to the third switch is twice the size of the MOS tube corresponding to the second switch. In this way, the calibration step of the calibration MOS tube is adjusted from small to large in sequence to avoid excessive adjustment steps, resulting in repeated calibration.

[0077] Combination Figure 7 As shown, the embodiment of the present disclosure provides another method for comparator calibration, comprising:

[0078] S101, when the comparator is in a calibration mode, the state machine samples the output result of the comparator.

[0079] S102: The state machine determines whether the comparator is out of adjustment according to the output result.

[0080] S103, when it is determined that the comparator is misaligned, the state machine determines the target calibration MOS transistor array to be adjusted according to the misalignment direction, and performs adjustment.

[0081] S204: When the absolute difference between the high voltage signal and the low voltage signal in the adjusted output result is less than or equal to a preset threshold, the state machine determines that the calibration is completed.

[0082] Here, in the process of adjusting the target calibration MOS tube array, the output result of the comparator is still collected based on the sampling period. If the absolute difference between the number of high voltage signals and the number of low voltage signals in the adjusted output result is less than or equal to the preset threshold, it indicates that the adjusted offset voltage meets the requirements. At this time, the control word of the target calibration MOS tube array is saved, and the calibration of the offset voltage is stopped. If the output result after one adjustment does not meet the above conditions, the calibration MOS tube is adjusted again. This is repeated until it is determined that the above conditions are met, and the working state of the target calibration MOS tube array is maintained.

[0083] Combination Figure 8 As shown, an embodiment of the present disclosure provides a calibration device 300 for a comparator, including a processor 301 and a memory 302. Optionally, the device may also include a communication interface 303 and a bus 304. The processor 301, the communication interface 303, and the memory 302 may communicate with each other through the bus 304. The communication interface 303 may be used for information transmission. The processor 301 may call the logic instructions in the memory 302 to execute the calibration method for the comparator of the above embodiment.

[0084] In addition, the logic instructions in the memory 302 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0085] The memory 302 is a computer-readable storage medium that can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 301 executes the functional application and data processing by running the program instructions / modules stored in the memory 302, that is, the calibration method for the comparator in the above embodiment is implemented.

[0086] The memory 302 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 302 may include a high-speed random access memory and may also include a non-volatile memory.

[0087] The disclosed embodiment provides a calibration circuit for a comparator, including: two groups of calibration MOS tube arrays, a state machine, and the above-mentioned calibration device 200 for the comparator. The calibration device 200 for the comparator is installed in the state machine. The installation relationship described here is not limited to the internal placement of the calibration of the comparator, but also includes the installation connection with other components of the calibration of the comparator, including but not limited to physical connection, electrical connection or signal transmission connection, etc. It can be understood by those skilled in the art that the calibration device 200 for the comparator can be adapted to the calibration body of a feasible comparator, thereby realizing other feasible embodiments.

[0088] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned calibration method for a comparator.

[0089] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0090] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0091] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0092] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0093] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A calibration circuit for a comparator, characterized in that: The comparator includes a pre-stage pre-amplifier and a pre-stage latch; the calibration circuit includes: Two groups of calibration MOS tube arrays are respectively connected in parallel to the source and drain of the input pair of tubes of the previous latch; each group of calibration MOS tube arrays includes a plurality of calibration MOS tubes connected in parallel, and each calibration MOS tube is grounded by connecting a switch in series, and the gate of the calibration MOS tube is connected to the gate of the corresponding side input tube; Among them, when the switch is turned on, the corresponding series-connected calibration MOS tube works and the working state is the same as the working state of the parallel-connected input tube; when calibrating the comparator offset voltage, the calibration MOS tube in the working state is adjusted to perform calibration.

2. The calibration circuit according to claim 1, characterized in that: The number and size layout of the calibration MOS tubes in the two groups of calibration MOS tube arrays are the same, and the size of each MOS tube in each group of calibration MOS tube arrays increases exponentially in sequence; When calibrating the comparator offset voltage, the calibration MOS tubes in the two groups of calibration MOS tube arrays that are in working state are different.

3. The calibration circuit according to claim 1, characterized in that: The change of the offset voltage by the smallest unit calibration MOS tube in each group of calibration MOS tube array is greater than the equivalent input noise of the comparator; Among them, the smallest unit calibration MOS tube is a calibration MOS tube of the smallest size.

4. A method for comparator calibration, characterized in that: Based on the calibration circuit according to any one of claims 1 to 3, the method comprises: When the comparator is in the calibration mode, the output result of the comparator is sampled; According to the output result, determine whether the comparator is out of adjustment; When the comparator is determined to be misaligned, the target calibration MOS tube array to be adjusted is determined according to the misalignment direction, and the adjustment is performed.

5. The method according to claim 4, characterized in that The comparator is in calibration mode by: When the quantization cycle of the comparator ends, the calibration control clock signal is received, and the signals at the two input terminals of the comparator are equal common-mode voltage signals, it is determined that the comparator is in the calibration mode.

6. The method according to claim 4, characterized in that Based on the output results, determine whether the comparator is out of adjustment, including: In a plurality of consecutive calibration cycles, when the absolute difference between the number of high voltage signals and the number of low voltage signals outputted is greater than a preset threshold value and the positive and negative conditions of the difference are consistent, it is determined that the comparator is out of adjustment; The output result includes a high voltage signal and a low voltage signal.

7. The method according to claim 4, characterized in that The direction of the misalignment is determined by: When the number of high voltage signals in the output result is greater than the number of low voltage signals, determining that the offset direction is the in-phase input terminal; When the number of high voltage signals in the output result is less than the number of low voltage signals, the offset direction is determined to be the inverting input terminal.

8. The method according to claim 4, characterized in that Determine the target calibration MOS tube array to be adjusted according to the misalignment direction, including: In the case where the misalignment direction is the in-phase input terminal, if the switch state of the calibration MOS tube array is all turned off, it is determined that the target calibration MOS tube array to be adjusted is the second calibration MOS tube array; if the switch state of the calibration MOS tube array is partially turned off, it is determined that the target MOS tube array to be adjusted is the first calibration MOS tube array or the second calibration MOS tube array; In the case where the misalignment direction is the inverting input terminal, if the state of the switches of the calibration MOS tube array is all turned off, it is determined that the target calibration MOS tube array to be adjusted is the first calibration MOS tube array; if the switch state of the calibration MOS tube array is partially turned off, it is determined that the target MOS tube array to be adjusted is the first calibration MOS tube array or the second calibration MOS tube array.

9. The method according to claim 4, characterized in that Adjusting the target calibration MOS tube array includes: Taking the minimum calibration step length as the minimum unit and following the order of the calibration step length from small to large, the binary control word is used to control the state of the switch MOS tube in the target calibration MOS tube array; The minimum calibration step depends on the smallest unit of calibration MOS tube.

10. The method according to any one of claims 4 to 9, characterized in that: After adjusting the target calibration MOS tube array, also: When the absolute difference between the number of high voltage signals and the number of low voltage signals in the adjusted output result is less than or equal to a preset threshold, it is determined that the calibration is completed.

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