Network processor and related instruction scheduling method

Abstract

The invention provides a network processor and a related instruction scheduling method, relates to the technical field of chips, and can improve the execution efficiency of instructions. The network processor comprises a scheduler, a plurality of scheduling control modules and a plurality of cache queues. The plurality of scheduling control modules are used for obtaining a first number of instructions from each cache queue in the plurality of non-empty cache queues, generating a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue so as to obtain a plurality of scheduling requests, and sending the plurality of scheduling requests to the scheduler, the scheduler is used for responding to a plurality of scheduling requests and sending at least one scheduling response signal to the at least one scheduling control module, and the at least one scheduling control module is further used for responding to the at least one scheduling response signal and generating to-be-executed instruction words based on a first number of instructions in a target cache queue and a target scheduling mode.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a network processor and a related instruction scheduling method. Background Art

[0002] A network processor (NP) is a device that supports flexible programmability and is widely used in switches and routers. NPs can be used to handle various tasks in the communication field, such as protocol analysis, message classification, media access control (MAC) switching, routing lookup, firewalls, quality of service (QoS), and message editing. Summary of the invention

[0003] The present application provides a network processor and a related instruction scheduling method, which can improve the execution efficiency of instructions.

[0004] In a first aspect, the present application provides a network processor, which includes: a scheduler, multiple scheduling control modules and multiple cache queues, and the multiple scheduling control modules correspond to the multiple cache queues one by one. The multiple scheduling control modules are used to obtain a first number of instructions from each cache queue in a plurality of non-empty cache queues, respectively, and generate scheduling requests based on the first indication information of the first number of instructions in each non-empty cache queue to obtain multiple scheduling requests. Each scheduling request corresponds to each non-empty cache queue, and the first indication information is used to indicate the scheduling mode of the first number of instructions. The multiple scheduling control modules are also used to send multiple scheduling requests to the scheduler; the scheduler is used to respond to the multiple scheduling requests and send at least one scheduling response signal to at least one scheduling control module, and the scheduling response signal is used to indicate the target cache queue to be scheduled and the target scheduling mode of the first number of instructions. At least one scheduling control module is also used to respond to at least one scheduling response signal, and generate instruction words to be executed based on the first number of instructions in the target cache queue and the target scheduling mode.

[0005] Thus, the network processor provided by the present application can support multiple scheduling modes, such as supporting both superscalar scheduling mode and very long instruction word scheduling mode, and flexibly selecting scheduling modes based on instructions. For example, for instructions with high inter-instruction dependency, a superscalar scheduling mode can be used to improve the execution efficiency of instructions, and for instructions with low inter-instruction dependency, a very long instruction word scheduling mode can be used to package multiple instructions to reduce the delay in executing instructions. Thus, the network processor provided by the present application can provide an adaptive scheduling mode for instructions, which can improve the execution efficiency of instructions and reduce the delay in the execution of instructions.

[0006] In a possible design, the scheduling mode includes a very long instruction word scheduling mode. When the scheduling mode corresponding to multiple scheduling requests includes the very long instruction word scheduling mode, the scheduling request also includes instruction distribution information, and the instruction distribution information is used to indicate the distribution position of valid instructions and empty instructions in the first number of instructions in the cache queue. The scheduling response signal includes an extremely long instruction word scheduling response signal, and the extremely long instruction word scheduling response signal is used to indicate that the target scheduling mode is the extremely long instruction word scheduling mode. The scheduler is specifically used to respond to multiple scheduling requests and send an extremely long instruction word scheduling response signal to a scheduling control module corresponding to the scheduling request whose scheduling mode is the extremely long instruction word scheduling mode. Thus, the network processor can schedule instructions according to the extremely long instruction word scheduling mode, and the parallel degree of the instructions is high and the processing delay is low. In addition, the scheduling control module can also identify the distribution position of valid instructions and empty instructions, generate instruction distribution information, and subsequently schedule instructions based on the instruction distribution information, which can reduce the number of beats of executing multiple instructions and improve the execution efficiency of instructions.

[0007] In a possible design, the instruction word includes an extra-long instruction word. When the first scheduling request corresponding to the first cache queue in the target cache queue indicates that the scheduling mode of the first cache queue is an extra-long instruction word scheduling mode, the scheduler is also used to respond to the second scheduling request corresponding to the second cache queue in the target cache queue and send a superscalar scheduling response signal to the scheduling control module corresponding to the second cache queue when the instruction distribution information of the first scheduling request indicates that there is an empty instruction. The scheduling control module is also used to perform shift operations and OR operations on the instructions in the first cache queue and the instructions in the second cache queue to generate an extra-long instruction word to be executed. Therefore, by performing shift operations and OR operations on the instructions in the first cache queue and the instructions in the second cache queue, the instructions in the extra-long instruction word generated by the network processor are all valid instructions, which improves the instruction density, can reduce the number of beats for executing multiple instructions, improve the execution efficiency of instructions, and improve the problems of large circuit area and high power consumption of network processing.

[0008] In one possible design, the scheduling mode includes a superscalar scheduling mode, the scheduling response signal includes a superscalar scheduling response signal, and the superscalar scheduling response signal is used to indicate that the target scheduling mode is the superscalar scheduling mode. When the scheduling modes corresponding to multiple scheduling requests are all superscalar scheduling modes, the scheduler is specifically used to respond to multiple scheduling requests and send multiple superscalar scheduling response signals to multiple scheduling control modules. Thus, the network processor can schedule instructions based on the superscalar scheduling mode, and can improve the execution efficiency of instructions with low inter-instruction dependencies.

[0009] In a possible design, the instruction word includes a superscalar instruction word, and a scheduling control module, which is specifically used to respond to multiple superscalar scheduling response signals, and generate a superscalar instruction word to be executed based on the first number of instructions in the target cache queue and the superscalar scheduling mode, the number of instructions in the superscalar instruction word is the same as the first number, the position of the valid instructions in the superscalar instruction word corresponds to the identifier of the target cache queue, and the superscalar instruction word contains empty instructions except for the valid instructions. Therefore, for instructions with high inter-instruction dependency, a superscalar scheduling mode can be adopted, and the superscalar instruction word contains empty instructions except for the valid instructions, which can be adapted to a network processor, and the network processor can simultaneously support the very long instruction word scheduling mode and the superscalar scheduling module, thereby improving the execution efficiency of instructions and reducing the delay of instructions.

[0010] In one possible design, multiple cache queues are used to cache received instructions to a target cache queue based on received second indication information, where the second indication information is used to indicate an identifier of a target cache queue of the instruction.

[0011] In one possible design, the network processor also includes an execution module, which is used to execute instruction words to be executed.

[0012] In a possible design, the execution module includes: a plurality of first multiplexers, a plurality of registers, a second multiplexer, and a plurality of third multiplexers; the plurality of first multiplexers correspond to the plurality of registers one-to-one, and the plurality of registers correspond to the plurality of third multiplexers one-to-one. The output end of each first multiplexer is coupled to the input end of the corresponding register, the output ends of the plurality of registers are respectively coupled to the plurality of input ends of the second multiplexer, the output end of each register is also coupled to the first input end of the corresponding third multiplexer, and the output end of the second multiplexer is also coupled to the second input end of the third multiplexer. The second multiplexer is used to obtain the operands of the instructions in the super-long instruction word to be executed. The third multiplexer is used to determine the operands to be executed corresponding to the thread from the operands of the instructions in the super-long instruction word to be executed obtained by the second multiplexer and the operands of the instructions in the superscalar instruction word. Thus, by setting a plurality of third multiplexers, the network processor can support the super-long instruction word scheduling mode and the superscalar scheduling mode at the same time, and the hardware cost is low.

[0013] In a possible design, the network processor further includes a storage module, and the storage module is used to store multiple instructions. If the storage address of the instruction in the storage module is within the first address range, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode; if the storage address of the instruction in the storage module is within the second address range, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode. Thus, the storage module can store multiple instructions of different scheduling modes.

[0014] In one possible design, if the first indication information is a first value, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode; if the first indication information is a second value, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

[0015] In a second aspect, the present application provides a compiler, which includes a compiling module and a sending module. The compiling module is used to compile instructions based on the compilation requirements corresponding to the instructions, and obtain the compiled instructions and first indication information, the first indication information is used to indicate the scheduling mode of the compiled instructions. The sending module is used to send the compiled instructions and the first indication information to the network processor.

[0016] Therefore, the compiler provided in this application can realize mixed compilation of superscalar and very long instruction words, which helps to improve the execution efficiency of instructions.

[0017] In one possible design, the compilation requirement includes a compilation mode, the compilation mode includes a superscalar compilation mode and a very long instruction word compilation mode, the scheduling mode includes a superscalar scheduling mode and a very long instruction word scheduling mode, and if the compilation mode of the instruction is the superscalar compilation mode, the first indication information indicates that the scheduling mode of the instruction is the superscalar scheduling mode. If the compilation mode of the instruction is the very long instruction word compilation mode, the first indication information indicates that the scheduling mode of the instruction is the very long instruction word scheduling mode.

[0018] In one possible design, the compilation requirement is determined based on the business type corresponding to the instruction.

[0019] In a third aspect, the present application provides an instruction scheduling method, wherein a network processor comprises: a scheduler, a plurality of scheduling control modules and a plurality of cache queues, wherein the plurality of scheduling control modules correspond one to one with the plurality of cache queues. The method comprises: a plurality of scheduling control modules respectively obtain a first number of instructions from each cache queue in a plurality of non-empty cache queues, and generate a scheduling request based on the first indication information of the first number of instructions in each non-empty cache queue to obtain a plurality of scheduling requests, wherein the scheduling request corresponds to each non-empty cache queue, and the first indication information is used to indicate the scheduling mode of the first number of instructions. A plurality of scheduling control modules send a plurality of scheduling requests to the scheduler. The scheduler responds to the plurality of scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, wherein the scheduling response signal is used to indicate the target cache queue to be scheduled and the target scheduling mode of the first number of instructions. At least one scheduling control module responds to at least one scheduling response signal, and generates an instruction word to be executed based on the first number of instructions in the target cache queue and the target scheduling mode.

[0020] The beneficial effects of the third aspect can refer to the description of the first aspect.

[0021] In one possible design, the scheduling mode includes an extremely long instruction word scheduling mode. When the scheduling mode corresponding to multiple scheduling requests includes the extremely long instruction word scheduling mode, the scheduling request also includes instruction distribution information, and the instruction distribution information is used to indicate the distribution positions of valid instructions and empty instructions in a first number of instructions in a cache queue; the scheduling response signal includes an extremely long instruction word scheduling response signal, and the extremely long instruction word scheduling response signal is used to indicate that the target scheduling mode is the extremely long instruction word scheduling mode; the scheduler responds to multiple scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, including: the scheduler responds to multiple scheduling requests and sends an extremely long instruction word scheduling response signal to the scheduling control module corresponding to the scheduling request whose scheduling mode is the extremely long instruction word scheduling mode.

[0022] In one possible design, the instruction word includes an ultra-long instruction word, and when the first scheduling request corresponding to the first cache queue in the target cache queue indicates that the scheduling mode of the first cache queue is an ultra-long instruction word scheduling mode, the method further includes: when the instruction distribution information of the first scheduling request indicates that there is an empty instruction, the scheduler responds to the second scheduling request corresponding to the second cache queue in the target cache queue and sends a superscalar scheduling response signal to the scheduling control module corresponding to the second cache queue. The scheduling control module performs a shift operation and an OR operation on the instructions in the first cache queue and the instructions in the second cache queue to generate an ultra-long instruction word to be executed.

[0023] In one possible design, the scheduling mode includes a superscalar scheduling mode, the scheduling response signal includes a superscalar scheduling response signal, and the superscalar scheduling response signal is used to indicate that the target scheduling mode is the superscalar scheduling mode; when the scheduling modes corresponding to multiple scheduling requests are all superscalar scheduling modes, the scheduler responds to multiple scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, including: the scheduler responds to multiple scheduling requests and sends multiple superscalar scheduling response signals to multiple scheduling control modules.

[0024] In one possible design, the instruction word includes a superscalar instruction word, at least one scheduling control module responds to at least one scheduling response signal, and generates an instruction word to be executed based on a first number of instructions in a target cache queue and a target scheduling mode, including: the scheduling control module responds to multiple superscalar scheduling response signals, and generates a superscalar instruction word to be executed based on a first number of instructions in the target cache queue and a superscalar scheduling mode, the number of instructions in the superscalar instruction word is the same as the first number, the position of valid instructions in the superscalar instruction word corresponds to the identifier of the target cache queue, and the superscalar instruction word contains empty instructions except for valid instructions.

[0025] In one possible design, the method further includes: the multiple cache queues cache the received instructions to the target cache queue based on the received second indication information, and the second indication information is used to indicate an identifier of the target cache queue of the instruction.

[0026] In one possible design, the network processor also includes an execution module; the method also includes: the execution module executes the instruction word to be executed.

[0027] In a possible design, the execution module includes: a plurality of first multiplexers, a plurality of registers, a second multiplexer, and a plurality of third multiplexers. The plurality of first multiplexers correspond to the plurality of registers one-to-one, and the plurality of registers correspond to the plurality of third multiplexers one-to-one. The output end of each first multiplexer is coupled to the input end of the corresponding register, the output ends of the plurality of registers are respectively coupled to the plurality of input ends of the second multiplexer, the output end of each register is also coupled to the first input end of the corresponding third multiplexer, and the output end of the second multiplexer is also coupled to the second input end of the third multiplexer. The execution module executes the instruction word to be executed, including: controlling the second multiplexer to obtain the operand of the instruction in the super-long instruction word to be executed, and the third multiplexer determines the operand to be executed corresponding to the thread from the operand of the instruction in the super-long instruction word to be executed obtained by the second multiplexer and the operand of the instruction in the superscalar instruction word.

[0028] In one possible design, the network processor further includes a storage module, and the method further includes: controlling the storage module to store a plurality of instructions, and if the storage address of the instruction in the storage module is within a first address range, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode. If the storage address of the instruction in the storage module is within a second address range, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

[0029] In one possible design, if the first indication information is a first value, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode; if the first indication information is a second value, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

[0030] In a fourth aspect, the present application provides a compilation method, which is applied to a compiler, and the compiler includes a compilation module and a sending module. The method includes: compiling an instruction based on a compilation requirement corresponding to the instruction, obtaining a compiled instruction and a first indication information, and the first indication information is used to indicate a scheduling mode of the compiled instruction. The sending module sends the compiled instruction and the first indication information to a network processor.

[0031] In one possible design, the compilation requirement includes a compilation mode, the compilation mode includes a superscalar compilation mode and a very long instruction word compilation mode, the scheduling requirement includes a superscalar scheduling mode and a very long instruction word scheduling mode, and if the compilation mode of the instruction is the superscalar compilation mode, the first indication information indicates that the scheduling mode of the instruction is the superscalar scheduling mode. If the compilation mode of the instruction is the very long instruction word compilation mode, the first indication information indicates that the scheduling mode of the instruction is the very long instruction word scheduling mode.

[0032] In one possible design, the compilation requirement is determined based on the business type corresponding to the instruction.

[0033] The beneficial effects of the fourth aspect can refer to the description of the second aspect.

[0034] In a fifth aspect, the present application provides a chip, the chip comprising a network processor and a power supply circuit, wherein the power supply circuit is used to supply power to the network processor, and the network processor is used to implement the method of the third aspect.

[0035] In a sixth aspect, the present application provides a computer device, the computer device comprising a processor and a memory, the memory being used to store a set of computer instructions. When the processor executes the set of computer instructions, it is used to execute the method of the third aspect or the fourth aspect.

[0036] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the instruction scheduling method or compilation method in any of the above aspects and any possible implementation methods.

[0037] In an eighth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a computer or a processor, it enables the computer or the processor to execute the instruction scheduling method or the compilation method in any of the above aspects and any possible implementation methods.

[0038] It can be understood that any of the network processors, compilers, chips, computer devices, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0039] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of a network processor provided in an embodiment of the present application;

[0041] Figure 2A schematic diagram of the structure of a microcode processor provided in an embodiment of the present application;

[0042] Figure 3 A block diagram of a superscalar network processor 4 instruction concurrency architecture provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of an EP structure of a superscalar network processor provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the structure of a very long instruction word network processor provided in an embodiment of the present application;

[0045] Figure 6 A schematic diagram of the structure of a network processor provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of a scheduling process of a network processor provided in an embodiment of the present application;

[0047] Figure 8 A flowchart of a very long instruction word scheduling mode provided in an embodiment of the present application;

[0048] Fig. 9 A flowchart of another very long instruction word scheduling mode provided in an embodiment of the present application;

[0049] Fig.10 A schematic diagram of the structure of another network processor provided in an embodiment of the present application;

[0050] Fig.11 A schematic diagram of different modes of an execution module provided in an embodiment of the present application;

[0051] Fig.12 A schematic diagram of the structure of an execution module provided in an embodiment of the present application;

[0052] Fig.13 A storage schematic diagram of a storage module provided in an embodiment of the present application;

[0053] Fig.14 A schematic diagram of the structure of a compiler provided in an embodiment of the present application;

[0054] Fig.15 A flowchart of an instruction scheduling method provided in an embodiment of the present application;

[0055] Fig.16 A flowchart of a compilation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] For ease of understanding, some examples of concepts related to the embodiments of the present application are provided for reference, as shown below:

[0057] Instructions may include arithmetic and logical operation instructions, such as addition, subtraction, multiplication, division, AND, OR, NOT, XOR, etc.; shift operation instructions, such as arithmetic shift, logical shift and circular shift; data transfer instructions, such as transfer between general registers and transfer between different storage units of the main memory; input and output instructions, transfer between general registers and input and output devices; transfer instructions, such as instructions for changing the execution order in the program; and stack operation instructions.

[0058] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0059] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0060] like Figure 1 As shown, Figure 1 A schematic diagram of the structure of a network processor provided in an embodiment of the present application. The network processor may include a microcode processor, a coprocessor, and a crossbar, wherein the microcode processor and the crossbar communicate with each other through a bus, and the crossbar communicate with the coprocessor through a bus. The microcode processor is mainly responsible for processing input data packets, such as processing input message headers based on pre-compiled microcodes and outputting data packets, and other complex operations are processed by the coprocessor.

[0061] The structural diagram of the microcode processor is as follows Figure 2As shown, the microcode processor may include a matching unit, a branch unit, and an action unit. The matching unit extracts some fields from the full vector (FV) to form an input / output request (IO request), and sends the input / output request to the coprocessor, and returns an input / output response (IO response) after the coprocessor executes a table lookup or related algorithm. The branch unit performs branch acceleration according to the full vector and the input / output response to obtain the entry of the specified branch program. The action unit executes the program based on the entry of the specified branch program to complete the modification of the full vector and output the modified full vector, or terminates the program and outputs a message. It can be understood that the matching unit, the branch unit, and the action unit can all be implemented using a programmable processor.

[0062] In order to reduce the area and power consumption of network processors, a superscalar network processor has been proposed. The superscalar network processor adopts an architecture that implements a type of concurrent operations in a processor core that implements instruction-level concurrency. A superscalar network processor that adopts this architecture can achieve higher processing throughput at the same main frequency. There are generally multiple execution units (or functional units) in a processor core, such as an arithmetic logic unit and a displacement unit. When the network processor does not adopt a superscalar architecture, the network processor can only execute a single instruction in each clock cycle, so that only one execution unit is working, while the other execution units are idle. When the network processor adopts a superscalar architecture, multiple instructions can be dispatched to be executed in different execution units at the same time in one clock cycle, thereby achieving instruction parallelism.

[0063] like Figure 3 As shown, Figure 3 The block diagram of the architecture of the superscalar network processor 4 instruction concurrency is shown in FIG. The superscalar network processor may include a storage module, an instruction scheduling module, and an execution module, wherein the storage module may be a memory or a cache, and the storage module is used to store instructions. After the thread-based program counter (PC) obtains the instruction from the storage module, the instruction is cached in the instruction first input first output (I-FIFO) of the instruction scheduling module, and each I-FIFO is bound to a thread. Figure 3Four I-FIFOs, such as I-FIFO0, I-FIFO1, I-FIFO2 and I-FIFO3, and four threads, such as T0, T1, T2 and T3, are shown. When the I-FIFO is not empty, instructions are dispatched from the I-FIFO and distributed to the corresponding execution pipelines (EPs), such as EP0, EP1, EP2 and EP3. Each EP is bound to a fixed thread, for example, the instruction in I-FIFO0 is distributed to EP0, EP0 and T0 are bound, and T0 executes the instruction.

[0064] Among them, the EP structure of the superscalar network processor is as follows Figure 4 As shown, EP may include an instruction fetch (IF) operation, an instruction decode (ID) operation, a data select (DS) operation, an execute (EX) operation and a write back (WB) operation that are executed in sequence. The instruction fetch operation is to obtain an instruction from the storage module and store it in the instruction register. The instruction decode operation is to split and interpret the retrieved instruction according to the predetermined instruction format, identify and distinguish different instruction categories and various methods of obtaining operands. The data selection operation obtains the address of the operand in the storage module according to the instruction address code, and reads the operand from the storage module for calculation. The execution operation completes the various operations specified by the instruction and specifically implements the function of the instruction. The write back operation writes the running result data of the execution operation instruction back to the register so that it can be quickly accessed by subsequent instructions. Therefore, from the processing mode of the superscalar network processor for instructions, it can be seen that the superscalar network processor has a low dependency between instructions and a high execution efficiency of instructions.

[0065] However, the parallelism of instructions in superscalar network processors is low, the delay of instruction processing is large, and the execution pipeline independently obtains and schedules instructions, and its peripheral logic is complex.

[0066] In addition, a very long instruction word (VLIW) network processor has been proposed. The very long instruction word network processor architecture adopts an instruction level parallel (ILP) processor system. Compared with the superscalar network processor, the very long instruction word network processor adopts another way to realize the parallel operation of multiple instructions. Specifically, the scheduling of the very long instruction word network processor is a scheduling that has been determined and completed during the compilation stage of the program. When scheduling, the very long instruction word network processor can package instructions with low dependencies among multiple instructions to generate a very long instruction word.

[0067] like Figure 5 As shown, Figure 5 A structural diagram of a very long instruction word network processor provided for an embodiment of the present application. The very long instruction word network processor includes a storage module, an instruction scheduling module and an execution module, wherein the storage module can be a memory or a cache, and the storage module is used to store instructions. After the thread-based program counter obtains the instruction from the storage module, the instruction is cached in the I-FIFO of the instruction scheduling module. When the I-FIFO is not empty, the instruction is scheduled from the I-FIFO and distributed to the corresponding EP for execution. The EP supports multiple (for example, 4) threads, such as T0, T1, T2 and T3, but only one thread is executing instructions at the same time.

[0068] Since the work of determining out-of-order execution is done by the compiler, the VLIW network processor does not require complex scheduling hardware. Therefore, the VLIW network processor can provide stronger processing capabilities and reduce the complexity of hardware compared to the superscalar network processor. Among them, the VLIW architecture can be understood as a single instruction stream and multiple data streams. The architecture has a high degree of instruction-level parallelism and low processing latency. There is only one execution pipeline to obtain instructions, and the logic of instruction and data scheduling is simple.

[0069] However, the high dependency between instructions in a very long instruction word network processor will result in a low instruction packing rate and require complex network processor logic, which is prone to the risk of conflicts between instructions and increases the complexity of the network processor.

[0070] Therefore, the present application provides a network processor that can support multiple scheduling modes (for example, supporting both superscalar scheduling mode and very long instruction word scheduling mode) and flexibly select scheduling modes based on instructions. For example, for instructions with high inter-instruction dependency, a superscalar scheduling mode can be used to improve the execution efficiency of instructions. For instructions with low inter-instruction dependency, a very long instruction word scheduling mode can be used to package multiple instructions to reduce the delay in executing instructions. Therefore, the network processor provided by the present application can provide an adaptive scheduling mode for instructions, which can improve the execution efficiency of instructions and reduce the delay in the execution of instructions.

[0071] The network processor in the present application can be used in network devices such as switches, routers or modems.

[0072] The network processor proposed in this application is further described below.

[0073] like Figure 6 As shown, Figure 6A schematic diagram of the structure of a network processor provided by an embodiment of the present application. The network processor 60 includes a scheduler 61, a plurality of scheduling control modules 62 and a plurality of cache queues 63, wherein the plurality of scheduling control modules 62 and the plurality of cache queues 63 correspond one to one. Figure 6 , n scheduling control modules 62 are shown, such as scheduling control module (1), scheduling control module (2), ..., scheduling control module (n), and n cache queues 63 are shown, such as cache queue (1), cache queue (2), ..., cache queue (n), and scheduling control module (1) corresponds to cache queue (1), and so on. The output end of each cache queue 63 is coupled to the first input end of the corresponding scheduling control module 62, the output end of each scheduling control module 62 is coupled to the input end of the scheduler 61, and the output end of the scheduler 61 is coupled to the second input end of the scheduling control module 62.

[0074] Among them, the multiple scheduling control modules 62 are used to obtain the first number of instructions from each cache queue 63 in the multiple non-empty cache queues 63, and generate scheduling requests based on the first indication information of the first number of instructions in each non-empty cache queue 63 to obtain multiple scheduling requests. Each of the multiple scheduling requests corresponds to a non-empty cache queue 63, and the first indication information is used to indicate the scheduling mode of the first number of instructions. In addition, the multiple scheduling control modules 62 are also used to send the multiple scheduling requests to the scheduler 61.

[0075] Exemplarily, the cache queue 63 may be a first-in, first-out queue, which may be used to temporarily store instructions, and the cache queue 63 may also be referred to as an instruction first-in, first-out queue (I-FIFO). In the present application, if instructions are stored in the cache queue 63, the cache queue 63 is a non-empty cache queue.

[0076] Exemplarily, the first number may be the number of packed instructions corresponding to the very long instruction word scheduling mode. In one possible example, the first number may be 4, that is, when running in the very long instruction word scheduling mode, the network processor 60 packs 4 instructions into 1 very long instruction word.

[0077] Exemplarily, the first indication information is used to indicate a scheduling mode of a first number of instructions, wherein the scheduling mode of the first number of instructions may include a superscalar scheduling mode and a very long instruction word scheduling mode. In one possible example, if the first indication information is a first value (e.g., 0), the scheduling mode of the first number of instructions is a superscalar scheduling mode, and if the first indication information is a second value (e.g., 1), the scheduling mode of the first number of instructions is a very long instruction word scheduling mode. The first indication information may also be referred to as in-path control information. When the network processor 60 receives an instruction, it will also receive the first indication information of the instruction at the same time.

[0078] Exemplarily, when instructions are stored in the cache queue 63, the scheduling control module 62 reads a first number of instructions from the cache queue 63, then parses the first number of instructions, and sends a scheduling request to the scheduler 61 according to the first indication information of the first number of instructions. The scheduling request may include a superscalar scheduling request and a very long instruction word scheduling request. If the first indication information indicates that the scheduling mode of the first number of instructions is a superscalar scheduling mode, the scheduling control module 62 generates a superscalar scheduling request. If the first indication information indicates that the scheduling mode of the first number of instructions is a very long instruction word scheduling mode, the scheduling control module 62 generates a very long instruction word scheduling request.

[0079] The scheduler 61 is used to respond to multiple scheduling requests and send at least one scheduling response signal to at least one scheduling control module 62, and the scheduling response signal is used to indicate the target cache queue to be scheduled and the target scheduling mode of the first number of instructions.

[0080] Exemplarily, if the scheduler 61 receives multiple superscalar scheduling requests from multiple scheduling control modules 62, the scheduler 61 may send a scheduling response signal to each scheduling control module 62 that initiates the superscalar scheduling request, and the scheduling response signal is used to instruct the multiple scheduling control modules 62 that initiate the superscalar scheduling request to schedule the instruction according to the superscalar scheduling mode. That is to say, the cache queues 63 corresponding to the multiple scheduling control modules 62 that initiate the superscalar scheduling request are all target cache queues, and the target scheduling mode is the superscalar scheduling mode. If the scheduler 61 receives multiple superscalar scheduling requests and multiple very long instruction word scheduling requests from multiple scheduling control modules 62 at the same time, the scheduler 61 may send a scheduling response signal to one of the scheduling control modules 62 that initiates the very long instruction word scheduling request, and the scheduling response signal is used to instruct the scheduling control module 62 to schedule the instruction according to the very long instruction word scheduling mode. That is to say, the cache queue 63 corresponding to one of the scheduling control modules 62 that initiates the very long instruction word scheduling request is the target cache queue, and the target scheduling mode is the very long instruction word scheduling mode. Therefore, by the scheduler 61 responding to the scheduling requests sent by the multiple scheduling control modules 62, a high-efficiency scheduling mode can be provided, thereby improving the execution efficiency of instructions.

[0081] The at least one scheduling control module 62 is further configured to respond to at least one scheduling response signal and generate instruction words to be executed based on the first number of instructions in the target cache queue and the target scheduling mode.

[0082] Exemplarily, the instruction word may include a superscalar instruction word and a very long instruction word. If the target scheduling mode is a superscalar scheduling mode, the plurality of scheduling control modules 62 may generate superscalar instruction words to be executed based on the first number of instructions and the superscalar scheduling mode. If the target scheduling mode is a very long instruction word scheduling mode, the plurality of scheduling control modules 62 may generate very long instruction words to be executed based on the first number of instructions and the very long instruction word scheduling mode.

[0083] Optionally, the scheduling mode includes a superscalar scheduling mode, the scheduling response signal includes a superscalar scheduling response signal, and the superscalar scheduling response signal is used to indicate that the target scheduling mode is the superscalar scheduling mode. When the scheduling modes corresponding to the multiple scheduling requests are all superscalar scheduling modes, the scheduler 61 is specifically used to respond to the multiple scheduling requests and send the multiple superscalar scheduling response signals to the multiple scheduling control modules 62.

[0084] Exemplarily, the scheduling response signal can be expressed as GNT=(v, m). Wherein, if v=1, it means that the scheduling control module 62 that initiates the scheduling request is scheduled, and if v=0, it means that the scheduling control module 62 that initiates the scheduling request is not scheduled. If m=1, it means that the scheduling mode is the very long instruction word scheduling mode, and if m=0, it means that the scheduling mode is the superscalar scheduling mode. In a possible example, the superscalar scheduling response signal can be expressed as GNT=2'b10, which means that the superscalar scheduling response signal consists of two bits (bit, b), where v is 1 and m is 0.

[0085] Exemplarily, if multiple scheduling control modules 62 initiate multiple scheduling requests, and the scheduling modes corresponding to the multiple scheduling requests are superscalar scheduling modes, the scheduler 61 responds to the multiple scheduling requests of the multiple scheduling control modules 62 at the same time, and sends superscalar scheduling response signals to the multiple scheduling control modules 62.

[0086] Optionally, the instruction word includes a superscalar instruction word, and the scheduling control module 62 is specifically used to respond to multiple superscalar scheduling response signals, and generate a superscalar instruction word to be executed based on the first number of instructions in the target cache queue and the superscalar scheduling mode. The number of instructions in the superscalar instruction word is the same as the first number, the position of the valid instruction in the superscalar instruction word corresponds to the identifier of the target cache queue, and the superscalar instruction word contains empty instructions except for the valid instructions.

[0087] Exemplarily, it is assumed that the cache queue 63 includes 4 I-FIFOs, namely I-FIFO0, I-FIFO1, I-FIFO2 and I-FIFO3. The superscalar instruction word includes 4 instructions, namely {instruction0, instruction1, instruction2, instruction3}, wherein the position of instruction0 corresponds to the identifier of I-FIFO0, the position of instruction1 corresponds to the identifier of I-FIFO1, the position of instruction2 corresponds to the identifier of I-FIFO2, and the position of instruction3 corresponds to the identifier of I-FIFO3.

[0088] Assuming that I-FIFO0 is the target cache queue, the scheduling control module 62 corresponding to I-FIFO0 responds to the superscalar scheduling response signal GNT=2'b10 and outputs a superscalar instruction word, then the superscalar instruction word includes 4 instructions, the position of the first instruction among the 4 instructions is a valid instruction, and the positions of the second instruction, the third instruction and the fourth instruction among the 4 instructions are all empty instructions. Among them, the empty instruction is also a no operation (NO Operation, NOP) instruction, and the empty instruction can also be represented by 0. That is, the instruction output by the scheduling control module 62 corresponding to I-FIFO0 is {instruction, 0, 0, 0}.

[0089] Optionally, the scheduling mode includes a very long instruction word scheduling mode. When the scheduling mode corresponding to multiple scheduling requests includes the very long instruction word scheduling mode, the scheduling request also includes instruction distribution information, and the instruction distribution information is used to indicate the distribution positions of valid instructions and empty instructions in the first number of instructions in the cache queue.

[0090] Exemplarily, if the scheduling mode corresponding to the multiple scheduling requests includes a very long instruction word scheduling mode, the scheduling control module 62 continues to identify the distribution positions of the valid instructions and the empty instructions in the first number of instructions, and generates instruction distribution information. In the embodiment of the present application, "p" represents the instruction distribution information. In one possible example, if the instruction is a NOP instruction, p=1; if the instruction is a non-NOP instruction, P=0. In another possible example, if the instruction is a NOP instruction, p=0; if the instruction is a non-NOP instruction, p=1. Take 4 instructions {M1, N1, N2, M2} as an example, where N1 and N2 are NOP instructions, M1 and M2 are non-NOP instructions, and the value of the NOP instruction is 1, and the value of the non-NOP instruction is 0, then p=4'b0110, which means that the instruction distribution information consists of 4 bits, indicating that from left to right the first instruction is a non-NOP instruction, the second instruction is a NOP instruction, the third instruction is a NOP instruction, and the fourth instruction is a non-NOP instruction.

[0091] The scheduling response signal includes a LVW scheduling response signal, which is used to indicate that the target scheduling mode is a LVW scheduling mode. The scheduler 61 is specifically used to respond to the scheduling request and send the LVW scheduling response signal to the scheduling control module 62.

[0092] Exemplarily, the scheduling request can be expressed as request = (d, p), where d is the scheduling mode and p is the instruction distribution information. If d = 1, the scheduling mode is the very long instruction word scheduling mode, and if d = 0, the scheduling mode is the superscalar scheduling mode. Optionally, the cache queue 63 can also send cache queue indication information to the scheduling control module 62. If the cache queue indication information is a first value (for example, 0), it indicates that the cache queue 63 is an empty cache queue. If the cache queue indication information is a second value (for example, 1), it indicates that the cache queue 63 is a non-empty cache queue.

[0093] In a possible example, the very long instruction word scheduling response signal can be expressed as GNT=2'b11, which means that the very long instruction word scheduling response signal consists of two bits, wherein v takes a value of 1 and m takes a value of 1.

[0094] Optionally, if multiple scheduling control modules 62 initiate multiple scheduling requests, and the scheduling modes corresponding to the multiple scheduling requests include both superscalar scheduling mode and very long instruction word scheduling mode, the scheduler 61 preferentially responds to the scheduling request initiated by the scheduling control module 62 that sends the very long instruction word scheduling mode. That is, the execution of instructions that satisfy the very long instruction word scheduling mode is preferentially executed, and the instruction level parallelism is high and the processing delay is low.

[0095] Optionally, the instruction word includes an ultra-long instruction word. When the first scheduling request corresponding to the first cache queue in the target cache queue indicates that the scheduling mode of the first cache queue is an ultra-long instruction word scheduling mode, the scheduler 61 is further configured to respond to the second scheduling request corresponding to the second cache queue in the target cache queue and send a superscalar scheduling response signal to the scheduling control module 62 corresponding to the second cache queue when the instruction distribution information of the first scheduling request indicates that there is an empty instruction. The scheduling control module 62 is further configured to perform a shift operation and an or operation on the instructions in the first cache queue and the instructions in the second cache queue to generate an ultra-long instruction word to be executed.

[0096] Exemplarily, both the first cache queue and the second cache queue are non-empty cache queues, and the scheduling mode corresponding to the first number of instructions stored in the first cache queue is the very long instruction word scheduling mode, and the scheduling mode corresponding to the first number of instructions stored in the second cache queue is the superscalar scheduling mode, then the scheduler 61 responds to the scheduling request issued by the scheduling control module 62 corresponding to the first cache queue. Among them, the scheduler 61 sends a very long instruction word scheduling signal to the scheduling control module 62 corresponding to the first cache queue. When there are empty instructions among the instructions stored in the first cache queue, in order to improve the execution efficiency of the instructions, the scheduler 61 can respond to the scheduling request issued by the scheduling control module 62 corresponding to the second cache queue. Among them, the scheduler 61 sends a superscalar scheduling response signal to the scheduling control module 62 corresponding to the second cache queue.

[0097] For example, Figure 7 As shown, Figure 7A flowchart of a scheduling of a network processor provided in an embodiment of the present application. Taking four cache queues 63 and four scheduling control modules 62 as an example, the I-FIFO receives instructions from the previous module. Assuming that I-FIFO0 is the first cache queue and I-FIFO1 is the second cache queue, the scheduling mode of the instructions stored in I-FIFO0 is the very long instruction word scheduling mode, and the scheduling mode of the instructions stored in I-FIFO1 can be the very long instruction word scheduling mode or the superscalar scheduling mode. The scheduling control module 62 corresponding to I-FIFO0 reads 4 instructions from I-FIFO0, and then parses the 4 instructions, and can obtain the instruction distribution information of the 4 instructions as p=4'b0110, and sends a scheduling request request=5'b10110 to the scheduler 61 according to the first indication information, which indicates that the scheduling request consists of 5 bits, wherein the value of d is 1, that is, the scheduling mode corresponding to the scheduling request is the super long instruction word scheduling mode, and the value of p is 0110, that is, from left to right, the first instruction is a non-NOP instruction, the second instruction is a NOP instruction, the third instruction is a NOP instruction, and the fourth instruction is a non-NOP instruction. After receiving the scheduling request, the scheduler 61 sends a super long instruction word scheduling response signal to the scheduling control module 62, and the super long instruction word scheduling response signal is GNT=2'b11, and the scheduling control module corresponding to I-FIFO0 outputs a super long instruction word, and at this time, the super long instruction word includes 4 instructions. If there is an empty instruction among the four instructions, in order to improve the execution efficiency of the instructions, the scheduler 61 can also send a superscalar scheduling response signal to the scheduling control module corresponding to I-FIFO1, and the scheduling control module corresponding to I-FIFO1 outputs a superscalar instruction word. The scheduling control module 62 can shift the superscalar instruction word according to the instruction distribution information, and then perform or operation on the super-long instruction word and the superscalar instruction word to obtain a super-long instruction word in which all instructions are valid instructions, and send the super-long instruction word in which all instructions are valid instructions to the threads corresponding to I-FIFO0 and I-FIFO1 for execution.

[0098] At the same time, the scheduling control module 62 also sends a thread identification (identity, ID) to the thread, wherein each instruction corresponds to a thread identification, and the thread can determine the instruction to be processed by it based on the thread identification. Taking four threads (T0, T1, T2 and T3) as an example, the thread identification can be represented by two bits, for example, if the thread identification of the instruction is 2'b00, the instruction is sent to T0; if the thread identification of the instruction is 2'b01, the instruction is sent to T1; if the thread identification of the instruction is 2'b10, the instruction is sent to T2; and if the thread identification of the instruction is 2'b11, the instruction is sent to T3.

[0099] Specifically, take 4 cache queues (I-FIFO0, I-FIFO1, I-FIFO2 and I-FIFO3) and 4 threads (T0, T1, T2 and T3) as an example, where I-FIFO0 corresponds to T0, I-FIFO1 corresponds to T1, I-FIFO2 corresponds to T2, and I-FIFO3 corresponds to T3. Figure 8 As shown, Figure 8 A flowchart of a very long instruction word scheduling mode provided in an embodiment of the present application. Figure 8 7 very long instruction words stored in I-FIFO0, I-FIFO1, I-FIFO2 and I-FIFO3 are shown respectively, wherein each very long instruction word includes 4 instructions. The 7 very long instruction words need to be scheduled 4 times. Among them, the first scheduling includes: scheduling the instructions in I-FIFO0, scheduling the instructions in I-FIFO0 according to the very long instruction word mode, and the very long instruction word obtained based on the instructions in I-FIFO0 is {instructionA, instructionB,0, instructionC}. Since the instruction at the position corresponding to I-FIFO2 in the super-long instruction word obtained based on the instruction in I-FIFO0 is an empty instruction, the scheduler 61 sends a superscalar scheduling response signal to the scheduling control module corresponding to I-FIFO2, and the superscalar instruction word obtained based on the instruction in I-FIFO2 is {0, 0, instructionD, 0}, thereby executing or operating the superscalar instruction word obtained based on the instruction in I-FIFO2 and the super-long instruction word obtained based on the instruction in I-FIFO0 to obtain the super-long instruction word to be executed, that is, {instructionA, instructionB, instructionD, instructionC}, wherein all instructions in the super-long instruction word are valid instructions. The scheduling control module 62 sends the super-long instruction word to T0 and T2 for execution respectively, wherein T0 executes instructionA, instructionB and instructionC, and T2 executes instructionD.

[0100] The second scheduling may include: scheduling the instructions in I-FIFO0. Since the instructions in I-FIFO0 only include one valid instruction, the instructions in I-FIFO0 are scheduled according to the superscalar scheduling mode, and the superscalar instruction word obtained based on the instructions in I-FIFO0 is {instructionE, 0, 0, 0}. Since the instructions corresponding to the positions of I-FIFO1, I-FIFO2 and I-FIFO3 in the superscalar instruction word obtained based on the instructions in I-FIFO0 are all empty instructions, the scheduler 61 sends superscalar scheduling response signals to the scheduling control modules corresponding to I-FIFO1, I-FIFO2 and I-FIFO3 respectively, wherein the superscalar instruction word obtained based on the instructions in I-FIFO1 is {0, 0, 0, instructionF}, the superscalar instruction word obtained based on the instructions in I-FIFO2 is {0, 0, 0, instructionG}, and the superscalar instruction word obtained based on the instructions in I-FIFO3 is {instructionH, 0, 0, 0}. Therefore, by performing shift operations on the superscalar instruction words obtained based on the instructions in I-FIFO1, the superscalar instruction words obtained based on the instructions in I-FIFO2, and the superscalar instruction words obtained based on the instructions in I-FIFO3, respectively, it can be obtained that the superscalar instruction words obtained based on the instructions in I-FIFO1 are {0, instructionF, 0, 0}, the superscalar instruction words obtained based on the instructions in I-FIFO2 are {0, 0, instructionG, 0}, and the superscalar instruction words obtained based on the instructions in I-FIFO3 are {0, 0, 0, instructionH}. Then, the superscalar instruction word obtained based on the instruction in I-FIFO0, the superscalar instruction word obtained based on the instruction in I-FIFO1, the superscalar instruction word obtained based on the instruction in I-FIFO2, and the superscalar instruction word obtained based on the instruction in I-FIFO3 are ORed to obtain the super-long instruction word to be executed, i.e., {instructionE, instructionF, instructionG, instructionH}, wherein all instructions in the super-long instruction word are valid instructions. The scheduling control module 62 sends the super-long instruction word to T0, T1, T2, and T3 for execution respectively, wherein T0 executes instructionE, T1 executes instructionF, T2 executes instructionG, and T3 executes instructionH.

[0101] The third scheduling may include: scheduling the instructions in I-FIFO2, scheduling the instructions in I-FIFO2 according to the super long instruction word scheduling mode, and the super long instruction word obtained based on the instruction in I-FIFO2 is {instructionI, instructionJ, instructionK, 0}. Since the instruction at the position corresponding to I-FIFO3 in the super long instruction word obtained based on the instruction in I-FIFO2 is an empty instruction, the scheduler 61 sends a super scalar scheduling response signal to the scheduling control module corresponding to I-FIFO3, and the super scalar instruction word obtained based on the instruction in I-FIFO3 is {0, 0, instructionL, 0}. Therefore, a shift operation is performed on the super scalar instruction word obtained based on the instruction in I-FIFO3, and the super scalar instruction word obtained based on the instruction in I-FIFO3 is {0, 0, 0, instructionL}. Then, the super long instruction word obtained based on the instruction in I-FIFO2 and the super scalar instruction word obtained based on the instruction in I-FIFO3 are executed or operated to obtain the super long instruction word to be executed, namely {instructionI, instructionJ, instructionK, instructionL}, wherein all instructions in the super long instruction word are valid instructions. The scheduling control module 62 sends the super long instruction word to T2 and T3 for execution respectively, wherein T2 executes instructionI, instructionJ and instructionK, and T3 executes instructionL.

[0102] The fourth scheduling may include: scheduling the instructions in I-FIFO1, scheduling the instructions in I-FIFO1 according to the super long instruction word scheduling mode, and the super long instruction word obtained based on the instruction in I-FIFO1 is {instructionM, instructionN, 0, 0}. Since the position corresponding to I-FIFO3 in the super long instruction word obtained based on the instruction in I-FIFO1 is an empty instruction, the scheduler 61 sends a super scalar scheduling response signal to the scheduling control module corresponding to I-FIFO3, and the super scalar instruction word obtained based on the instruction in I-FIFO3 is {0, 0, 0, instructionO}. Thus, the super long instruction word obtained based on the instruction in I-FIFO1 and the super scalar instruction word obtained based on the instruction in I-FIFO3 are executed or operated to obtain the super long instruction word to be executed, that is, {instructionM, instructionN, 0, instructionO}. The scheduling control module 62 sends the very long instruction words to T1 and T3 for execution respectively, wherein T1 executes instructionM and instructionN, and T3 executes instructionO. Thus, the scheduling of 7 very long instruction words can be completed based on 4 schedulings.

[0103] It is understandable that the present application does not impose any specific restrictions on the scheduling order of instructions in I-FIFO0, I-FIFO1, I-FIFO2 and I-FIFO3. In a possible example, Fig. 9 As shown, Fig. 9A flowchart of another very long instruction word scheduling mode provided for an embodiment of the present application. Among them, the first scheduling and the second scheduling can be the same, and no further description is given here. The third scheduling can be to schedule the instructions in I-FIFO1, and the instructions in I-FIFO1 are scheduled according to the very long instruction word scheduling mode, and the very long instruction word obtained based on the instruction in I-FIFO1 is {instructionM, instructionN, 0, 0}. Since the instructions at the disposal of I-FIFO2 and I-FIFO3 corresponding to the very long instruction word obtained based on the instruction in I-FIFO1 are empty instructions, the scheduler 61 sends a superscalar scheduling response signal to the scheduling control modules corresponding to I-FIFO2 and I-FIFO3 respectively, and the superscalar instruction word obtained based on the instruction in I-FIFO2 is {instructionI, 0, 0, 0}, and the superscalar instruction word obtained based on the instruction in I-FIFO3 is {0, 0, instructionL, 0}. Thus, the superscalar instruction word obtained based on the instruction in I-FIFO2 and the superscalar instruction word obtained based on the instruction in I-FIFO3 are shifted, and the superscalar instruction word obtained based on the instruction in I-FIFO2 is {0, 0, instructionI, 0}, and the superscalar instruction word obtained based on the instruction in I-FIFO3 is {0, 0, 0, instructionL}. Then, the super-long instruction word obtained based on the instruction in I-FIFO1, the superscalar instruction word obtained based on the instruction in I-FIFO2, and the superscalar instruction word obtained based on the instruction in I-FIFO3 are or-operated to obtain the super-long instruction word to be executed, that is, {instructionM, instructionN, instructionI, instructionL}, wherein all instructions in the super-long instruction word are valid instructions. The scheduling control module 62 sends the super-long instruction word to T1, T2, and T3 for execution, wherein T1 executes instructionM and instructionN, T2 executes instructionI, and T3 executes instructionL.

[0104] Correspondingly, the fourth scheduling may include: scheduling the instructions in I-FIFO2, scheduling the instructions in I-FIFO2 according to the super-long instruction word scheduling mode, and the super-long instruction word obtained based on the instruction in I-FIFO2 is {0, instructionJ, instructionK, 0}. Since the instruction at the position corresponding to I-FIFO3 in the super-long instruction word obtained based on the instruction in I-FIFO2 is an empty instruction, the scheduler 61 sends a superscalar scheduling response signal to the scheduling control module corresponding to I-FIFO3, and the superscalar instruction word obtained based on the instruction in I-FIFO3 is {0, 0, 0, instructionO}. Thus, the super-long instruction word obtained based on the instruction in I-FIFO2 and the superscalar instruction word obtained based on the instruction in I-FIFO3 are executed or operated to obtain the super-long instruction word to be executed, that is, {0, instructionJ, instructionK, instructionO}. The scheduling control module 62 sends the very long instruction words to T2 and T3 for execution respectively, wherein T2 executes instruction J and instruction K, and T3 executes instruction O. Thus, the scheduling of 7 very long instruction words can be completed based on 4 schedulings.

[0105] Therefore, for 7 VLIWs, if a VLIW network processor is used, 7 beats are required to execute the instruction, while the network processor provided by the embodiment of the present application only needs 4 beats to execute the instruction, thereby greatly improving the execution efficiency of the instruction.

[0106] Optionally, the plurality of cache queues 63 are used to cache the received instruction to a target queue based on the received second indication information, wherein the second indication information is used to indicate an identifier of a target cache queue of the instruction.

[0107] Exemplarily, the identifiers of the target cache queues may be I-FIFO0, I-FIFO1, I-FIFO2, and I-FIFO3. The second indication information may also be in-path control information. When the network processor 60 receives the instruction, it also receives the second indication information of the instruction at the same time. In one possible example, the second indication information may be represented by two bits. For example, if the second indication information is 2'b00, the instruction is stored in I-FIFO0; if the second indication information is 2'b01, the instruction is stored in I-FIFO1; if the second indication information is 2'b10, the instruction is stored in I-FIFO2; and if the second indication information is 2'b11, the instruction is stored in I-FIFO3.

[0108] Optional, such as Fig.10 As shown, Fig.10The network processor 60 may further include an execution module 64, wherein the execution module 64 is used to execute the instruction word to be executed. The instruction word to be executed may be Figure 8 or Fig. 9 The input end of the execution module 64 is coupled to the output end of the scheduling control module 62. Fig.10 , EP1, EP2, ..., EPn, and n threads are shown, T1, T2, ..., Tn, wherein each EP corresponds to each thread one by one.

[0109] The execution module 64 can support multiple modes, such as Fig.11 As shown, Fig.11 A schematic diagram of different modes of an execution module provided in an embodiment of the present application. Taking the execution module 64 including 4 execution pipelines (EP0, EP1, EP2 and EP3) as an example, each execution pipeline corresponds to a thread, that is, 4 execution pipelines correspond to 4 threads (T0, T1, T2 and T3). The scheduling mode may include: a superscalar scheduling mode, a very long instruction word scheduling mode and a hybrid scheduling mode, wherein the hybrid scheduling mode includes both a superscalar scheduling mode and a very long instruction word scheduling mode. Fig.11 (a) in the figure shows a superscalar scheduling mode, i.e., 4*EP(S), where "S" represents the superscalar scheduling mode, wherein instructions in EP0, EP1, EP2, and EP3 are assigned to corresponding T0, T1, T2, and T3 for execution according to the superscalar scheduling mode. Fig.11 (b) in the figure shows a hybrid scheduling mode, namely 2*EP(S)+1*EP(V=2), where "V" represents a very long instruction word scheduling mode, wherein the instructions in EP0 and EP1 are assigned to the corresponding T0 and T1 for execution according to the superscalar scheduling mode, and the instructions in EP2 and EP3 are packaged to generate a very long instruction word including 2 instructions, which is assigned to the corresponding T2 and T3 for execution. Fig.11 (c) in the figure shows another hybrid scheduling mode, namely 1*EP(S)+1*EP(V=3), wherein the instructions in EP0, EP1 and EP2 are packaged to generate a very long instruction word including 3 instructions, which is assigned to a corresponding thread in T0, T1 and T2 for execution, and the instructions in EP3 are assigned to the corresponding T3 for execution according to the superscalar scheduling mode. Fig.11 (d) in the figure shows the very long instruction word scheduling mode, i.e. 1*EP (V=4), in which the instructions in EP0, EP1, EP2 and EP3 are packaged to generate a very long instruction word including 4 instructions, which is assigned to one of the corresponding threads T0, T1, T2 and T3 for execution.

[0110] Optionally, the execution module 64 includes a plurality of first multiplexers (MUX), a plurality of registers, a second multiplexer and a plurality of third multiplexers. The plurality of first multiplexers correspond to the plurality of registers one-to-one, and the plurality of registers correspond to the plurality of third multiplexers one-to-one. The output end of each first multiplexer is coupled to the input end of the corresponding register, the output ends of the plurality of registers are coupled to the input end of the second multiplexer respectively, the output end of each register is also coupled to the first input end of the corresponding third multiplexer, and the output end of the second multiplexer is also coupled to the second input end of the third multiplexer. The second multiplexer is used to obtain the operands of the instructions in the super-long instruction word to be executed, and the third multiplexer is used to determine the operands to be executed corresponding to the thread from the operands of the instructions in the super-long instruction word to be executed obtained by the second multiplexer and the operands of the instructions in the superscalar instruction word.

[0111] like Fig.12 As shown, Fig.12 A schematic diagram of the structure of an execution module provided in an embodiment of the present application. Fig.12 4 first multiplexers 641, 4 registers 642, a second multiplexer 643 and 4 third multiplexers 644 are shown in the figure. The 4 registers 642 are T0R, T1R, T2R and T3R respectively. Each first multiplexer 641 includes a plurality of input terminals. For example, the first multiplexer 641 includes 5 input terminals, wherein the 5 input terminals respectively input the data stored in the register, source operand 1, source operand 2, source operand 3 and source operand 4. The first multiplexer 641 is used to determine the source operand to be written into the register 642 from the data stored in the register and the plurality of source operands. The register 642 is used to temporarily store the source operand.

[0112] The second multiplexer 643 may include 4 input terminals, and the third multiplexer 644 may include a first input terminal and a second input terminal. In one possible example, if any thread in the execution module executes an instruction, the second multiplexer 643 determines the source operand corresponding to the thread from the 4 registers 642 based on the thread identifier of the instruction, and the third multiplexer 644 determines that the source operand inputted at the second input terminal is the source operand to be executed by the corresponding thread. In another possible example, if any thread in the execution module executes an instruction, the third multiplexer 644 determines that the source operand inputted at the first input terminal is the source operand to be executed by the corresponding thread based on the thread identifier of the instruction. In one possible example, if the instruction to be executed by T0 is an addition instruction, the addition instruction includes the address of the source operand 1 and the address of the source operand 2 to be executed for the addition operation, and the scheduling mode of the addition instruction is a superscalar scheduling mode, then T0 can find the source operand 1 from the register based on the address of the source operand 1, and find the source operand 2 from the register based on the address of the source operand 2. After T0 performs the addition operation on source operand 1 and source operand 2, it generates a destination operand and writes the destination operand into the storage module.

[0113] Continue to view Fig.10 The network processor 60 may further include a storage module 65, and the storage module 65 is used to store multiple instructions. The cache queue 63 receives instructions from the storage module 65. For example, the cache queue 63 receives 4 instructions from the storage module in each clock cycle.

[0114] Optionally, if the storage address of the instruction in the storage module 65 is within the first address range, the scheduling mode of the instruction indicated by the first indication information is the superscalar scheduling mode. If the storage address of the instruction in the storage module 65 is within the second address range, the scheduling mode of the instruction indicated by the first indication information is the very long instruction word scheduling mode.

[0115] like Fig.13 As shown, Fig.13 A storage schematic diagram of a storage module provided for the present application. Among them, the first indication information can be the address information of the instruction, and the storage address can also be understood as the physical address of the storage module 65. Assuming that the storage module 65 includes a space for instructions in a superscalar scheduling mode and a space for instructions in a very long instruction word scheduling mode, the address range of the storage module 65 is X~N-1, wherein the first address range can be X~M-1, and the second address range can be M~N-1. That is, the address range of the space for instructions in the superscalar scheduling mode is X~M-1, and the address range of the space for instructions in the very long instruction word scheduling mode is M~N-1.

[0116] Optionally, if the first indication information is a first value, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode. If the first indication information is a second value, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

[0117] Exemplarily, the first indication information may be tag information of the instruction. In one example, the first value may be 0, and the second value may be 1. That is, if the first indication information is 0, the scheduling mode of the first number of instructions is a superscalar scheduling mode, and if the first indication information is 1, the scheduling mode of the first number of instructions is a very long instruction word scheduling mode. In another example, the first value may be 1, and the second value may be 0. That is, if the first indication information is 1, the scheduling mode of the first number of instructions is a superscalar scheduling mode, and if the first indication information is 0, the scheduling mode of the first number of instructions is a very long instruction word scheduling mode.

[0118] The compiler that generates the first indication information is introduced below.

[0119] like Fig.14 As shown, Fig.14 A schematic diagram of the structure of a compiler provided in an embodiment of the present application. Compiler 1400 may include a compiling module 1401 and a sending module 1402. Compiling module 1401 is used to compile instructions based on the compilation requirements corresponding to the instructions to obtain compiled instructions and first indication information. The first indication information is used to indicate the scheduling mode of the compiled instructions. Sending module 1402 is used to send the compiled instructions and the first indication information to a network processor. For example, sending to a storage module of a network processor to store the compiled instructions in the storage module of the network processor.

[0120] Optionally, the compilation requirement may be a compilation mode, and the compilation mode includes a superscalar compilation mode and a very long instruction word compilation mode. If the compilation requirement of the instruction is the superscalar compilation mode, the first indication information indicates that the scheduling mode of the instruction is the superscalar scheduling mode. If the compilation requirement of the instruction is the very long instruction word compilation mode, the first indication information indicates that the scheduling mode of the instruction is the very long instruction word scheduling mode. The compiler sends the compiled instruction and the first indication information to a storage module in the network processor, wherein the storage module includes a space for instructions in the superscalar scheduling mode and a space for instructions in the very long instruction word scheduling mode. Specifically, the space for instructions in the superscalar scheduling mode is used to store instructions whose compilation requirement is the superscalar scheduling mode, and the space for instructions in the very long instruction word scheduling mode is used to store instructions whose compilation requirement is the very long instruction word scheduling mode.

[0121] Optionally, the compilation requirement can be determined based on the service type corresponding to the instruction. In a possible example, if the service requires a large amount of traffic, such as a download service, the instruction corresponding to the service can be compiled according to the very long instruction word compilation mode. If the service requires a small amount of traffic, such as a monitoring service, the instruction corresponding to the service can be compiled according to the superscalar compilation mode.

[0122] The software can mark the instructions, and the compilation module 1401 can compile the instructions based on the compilation requirements of the instructions marked by the software, wherein the compilation requirements of the instructions can also be understood as performance paths and non-performance paths, or the compilation requirements can be determined based on the performance requirements of the instructions, and the performance path is that the execution of the instructions requires a larger flow, and the non-performance path is that the execution of the instructions requires a smaller flow. For the performance path, the instructions can be compiled according to the very long instruction word compilation mode, and for the non-performance path, the instructions can be compiled according to the superscalar compilation mode. Thus, the compiler provided in the embodiment of the present application can realize the mixed compilation of superscalar and very long instruction words, which helps to improve the execution efficiency of the instructions.

[0123] It should be noted that the compilation module 1401 compiles the instruction as one of the compilation methods based on the compilation mode corresponding to the instruction. The compilation module 1401 can also compile the instruction in other ways, which is not limited in this embodiment of the present application.

[0124] Applied to the above network processor, the present application embodiment also provides an instruction scheduling method. Fig.15 As shown, Fig.15 A flowchart of an instruction scheduling method provided in an embodiment of the present application. The instruction scheduling method includes:

[0125] S1501, multiple scheduling control modules respectively obtain a first number of instructions from each of a plurality of non-empty cache queues, and generate a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue to obtain multiple scheduling requests. The scheduling request corresponds to each non-empty cache queue, and the first indication information is used to indicate a scheduling mode of the first number of instructions.

[0126] S1502. Multiple scheduling control modules send multiple scheduling requests to a scheduler.

[0127] Exemplarily, for each non-empty cache queue, the corresponding scheduling control module obtains a first number of instructions from the non-empty cache queue and generates a scheduling request based on the first indication information. The first indication information can indicate that the scheduling mode of the instruction is a superscalar scheduling mode, and the first indication information can also indicate that the scheduling mode of the instruction is a very long instruction word scheduling mode. The network processor adopts a hybrid technology of the superscalar scheduling mode and the very long instruction word scheduling mode, which can improve the execution efficiency of the instruction and improve the problems of large circuit area and high power consumption. The specific implementation methods of S1501 and S1502 can refer to the above description of the scheduling control module.

[0128] S1503: The scheduler responds to the multiple scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, wherein the scheduling response signal is used to indicate the target cache queue to be scheduled and the target scheduling mode of the first number of instructions.

[0129] Exemplarily, for different scheduling requests, the scheduler will respond to different scheduling response signals. If the scheduler receives superscalar scheduling requests sent by multiple scheduling control modules, the scheduler can send a scheduling response signal to each scheduling control module that initiates the superscalar scheduling request. If the scheduler simultaneously receives multiple superscalar scheduling requests and multiple very long instruction word scheduling requests from multiple scheduling control modules, the scheduler can send a scheduling response signal to one of the scheduling control modules that initiates the very long instruction word scheduling request. The specific implementation method of S1503 can refer to the above description of the scheduler.

[0130] S1504. At least one scheduling control module responds to at least one scheduling response signal and generates instruction words to be executed based on a first number of instructions in the target cache queue and a target scheduling mode.

[0131] Exemplarily, the instruction word may include a superscalar instruction word and a very long instruction word. If the target scheduling mode is a superscalar scheduling mode, the plurality of scheduling control modules may generate superscalar instruction words to be executed based on the first number of instructions and the superscalar scheduling mode. If the target scheduling mode is a very long instruction word scheduling mode, the plurality of scheduling control modules may generate very long instruction words to be executed based on the first number of instructions and the very long instruction word scheduling mode.

[0132] Optionally, for the very long instruction word scheduling mode, S1503 may include: the scheduler responds to the scheduling request and sends a very long instruction word scheduling response signal to the scheduling control module corresponding to the scheduling request whose scheduling mode is the very long instruction word scheduling mode.

[0133] In addition, when the instruction distribution information of the first scheduling request indicates that there is an empty instruction, the scheduler responds to the second scheduling request corresponding to the second cache queue in the target cache queue and sends a superscalar scheduling response signal to the scheduling control module corresponding to the second cache queue, and the scheduling control module performs shift operations and OR operations on the instructions in the first cache queue and the instructions in the second cache queue to generate a super long instruction word to be executed.

[0134] Optionally, for the superscalar scheduling mode, S1503 may include: the scheduler responds to multiple scheduling requests and sends multiple superscalar scheduling response signals to multiple scheduling control modules. S1504 may include: the scheduling control module responds to multiple superscalar scheduling response signals and generates superscalar instruction words to be executed based on the first number of instructions in the target cache queue and the superscalar scheduling mode.

[0135] Optionally, before S1501, the method may further include: multiple cache queues cache the received instructions into the target cache queue based on the received second indication information.

[0136] Optionally, after S1504, the method may further include: an execution module executing the instruction word to be executed.

[0137] Applied to the above compiler, the compilation method provided by this application is introduced below. Fig.16 As shown, Fig.16 A flowchart of a compilation method provided in this application. The method includes the following process.

[0138] S1601: A compiling module compiles an instruction based on a compiling requirement corresponding to the instruction to obtain the compiled instruction and first indication information. The first indication information is used to indicate a scheduling mode of the compiled instruction.

[0139] S1602. The sending module sends the compiled instruction and the first indication information to the network processor.

[0140] The present application also provides a chip, which includes a network processor and a power supply circuit, wherein the power supply circuit is used to supply power to the network processor, and the network processor is used to implement the instruction scheduling method.

[0141] The present application also provides a computer device, which includes a processor and a memory, wherein the memory is used to store a set of computer instructions. When the processor executes the set of computer instructions, it is used to execute the above instruction scheduling method or compilation method.

[0142] The embodiment of the present application also provides an electronic device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program codes, and the computer program codes include computer instructions. When the one or more processors execute the computer instructions, the electronic device executes the above-mentioned related method steps to implement the instruction scheduling method or compilation method in the above-mentioned embodiment.

[0143] An embodiment of the present application also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the instruction scheduling method or compilation method in the above-mentioned embodiment.

[0144] The embodiments of the present application also provide a computer program product. When the computer program product is run on a computer, the computer executes the above-mentioned related steps to implement the instruction scheduling method or compilation method executed by the electronic device in the above-mentioned embodiments.

[0145] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor can execute the computer execution instructions stored in the memory so that the chip executes the instruction scheduling method or compilation method executed by the electronic device in the above-mentioned method embodiments.

[0146] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here.

[0147] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0148] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0150] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0151] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0152] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A network processor, characterized in that: include: A scheduler, a plurality of scheduling control modules and a plurality of cache queues, wherein the plurality of scheduling control modules correspond to the plurality of cache queues one by one; The multiple scheduling control modules are used to obtain a first number of instructions from each cache queue in a plurality of non-empty cache queues, respectively, and generate a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue to obtain multiple scheduling requests, each scheduling request corresponds to each non-empty cache queue, and the first indication information is used to indicate a scheduling mode of the first number of instructions; The multiple scheduling control modules are further used to send the multiple scheduling requests to the scheduler; The scheduler is used to respond to the multiple scheduling requests and send at least one scheduling response signal to at least one scheduling control module, wherein the scheduling response signal is used to indicate a target cache queue to be scheduled and a target scheduling mode of the first number of instructions; The at least one scheduling control module is further configured to respond to the at least one scheduling response signal and generate instruction words to be executed based on the first number of instructions in the target cache queue and the target scheduling mode.

2. The network processor according to claim 1, characterized in that: The scheduling mode includes a very long instruction word scheduling mode, and when the scheduling modes corresponding to the multiple scheduling requests include the very long instruction word scheduling mode, the scheduling request further includes instruction distribution information, and the instruction distribution information is used to indicate the distribution positions of valid instructions and empty instructions in the first number of instructions in the cache queue; The scheduling response signal comprises a very long instruction word scheduling response signal, and the very long instruction word scheduling response signal is used to indicate that the target scheduling mode is the very long instruction word scheduling mode; The scheduler is specifically used to respond to the multiple scheduling requests and send the very long instruction word scheduling response signal to the scheduling control module corresponding to the scheduling request whose scheduling mode is the very long instruction word scheduling mode.

3. The network processor according to claim 2, characterized in that: The instruction word includes an extra-long instruction word, and when a first scheduling request corresponding to a first cache queue in the target cache queue indicates that the scheduling mode of the first cache queue is the extra-long instruction word scheduling mode, The scheduler is further configured to respond to a second scheduling request corresponding to a second cache queue in the target cache queue and send a superscalar scheduling response signal to the scheduling control module corresponding to the second cache queue when the instruction distribution information of the first scheduling request indicates that there is an empty instruction; The scheduling control module is further used to perform shift operations and OR operations on the instructions in the first cache queue and the instructions in the second cache queue to generate the very long instruction word to be executed.

4. The network processor according to claim 1, characterized in that: The scheduling mode includes a superscalar scheduling mode, the scheduling response signal includes a superscalar scheduling response signal, and the superscalar scheduling response signal is used to indicate that the target scheduling mode is the superscalar scheduling mode; When the scheduling modes corresponding to the multiple scheduling requests are all the superscalar scheduling modes, the scheduler is specifically configured to respond to the multiple scheduling requests and send the multiple superscalar scheduling response signals to the multiple scheduling control modules.

5. The network processor according to claim 4, characterized in that: The instruction words include superscalar instruction words, and the scheduling control module is specifically used to respond to the multiple superscalar scheduling response signals and generate a superscalar instruction word to be executed based on a first number of instructions in the target cache queue and the superscalar scheduling mode. The number of instructions in the superscalar instruction word is the same as the first number, the position of the valid instructions in the superscalar instruction word corresponds to the identifier of the target cache queue, and the superscalar instruction word contains empty instructions except the valid instructions.

6. The network processor according to any one of claims 1 to 5, characterized in that: The multiple cache queues are used to cache the received instructions to the target cache queue based on the received second indication information, and the second indication information is used to indicate the identifier of the target cache queue of the instruction.

7. The network processor according to any one of claims 1 to 6, characterized in that: The network processor also includes an execution module; The execution module is used to execute the instruction word to be executed.

8. The network processor according to claim 7, characterized in that: The execution module includes: a plurality of first multiplexers, a plurality of registers, a second multiplexer, and a plurality of third multiplexers; the plurality of first multiplexers correspond to the plurality of registers one-to-one, and the plurality of registers correspond to the plurality of third multiplexers one-to-one; The output end of each first multiplexer is coupled to the input end of the corresponding register, the output ends of the multiple registers are respectively coupled to the multiple input ends of the second multiplexer, the output end of each register is also coupled to the first input end of the corresponding third multiplexer, and the output end of the second multiplexer is also coupled to the second input end of the third multiplexer; The second multiplexer is used to obtain the operand of the instruction in the very long instruction word to be executed; The third multiplexer is used to determine the operand to be executed corresponding to the thread from the operands of the instructions in the to-be-executed very long instruction word and the operands of the instructions in the superscalar instruction word obtained by the second multiplexer.

9. The network processor according to any one of claims 1 to 8, characterized in that: The network processor also includes a storage module, and the storage module is used to store a plurality of instructions; If the storage address of the instruction in the storage module is within the first address range, the scheduling mode of the instruction indicated by the first indication information is the superscalar scheduling mode; if the storage address of the instruction in the storage module is within the second address range, the scheduling mode of the instruction indicated by the first indication information is the very long instruction word scheduling mode.

10. The network processor according to any one of claims 1 to 8, characterized in that: If the first indication information is a first value, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode; if the first indication information is a second value, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

11. A compiler, characterized in that include: Compile modules and send modules; The compiling module is used to compile the instruction based on the compilation requirements corresponding to the instruction to obtain the compiled instruction and first indication information, wherein the first indication information is used to indicate the scheduling mode of the compiled instruction; The sending module is used to send the compiled instruction and the first indication information to the network processor.

12. The compiler according to claim 11, characterized in that The compilation requirement includes a compilation mode, the compilation mode includes a superscalar compilation mode and a very long instruction word compilation mode, the scheduling mode includes a superscalar scheduling mode and a very long instruction word scheduling mode, and if the compilation mode of the instruction is the superscalar compilation mode, the first indication information indicates that the scheduling mode of the instruction is the superscalar scheduling mode; If the compilation mode of the instruction is the very long instruction word compilation mode, the first indication information indicates that the scheduling mode of the instruction is the very long instruction word scheduling mode.

13. The compiler according to claim 11 or 12, characterized in that: The compilation requirement is determined based on a business type corresponding to the instruction or a performance requirement of the instruction.

14. An instruction scheduling method, characterized in that: Applied to a network processor, the network processor includes a scheduler, multiple scheduling control modules and multiple cache queues, the multiple scheduling control modules and the multiple cache queues correspond one to one; the method includes: The multiple scheduling control modules respectively obtain a first number of instructions from each cache queue in a plurality of non-empty cache queues, and generate a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue to obtain a plurality of scheduling requests, each scheduling request corresponds to each non-empty cache queue, and the first indication information is used to indicate a scheduling mode of the first number of instructions; The multiple scheduling control modules send the multiple scheduling requests to the scheduler; The scheduler responds to the multiple scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, wherein the scheduling response signal is used to indicate a target cache queue to be scheduled and a target scheduling mode of the first number of instructions; The at least one scheduling control module is responsive to the at least one scheduling response signal and generates instruction words to be executed based on the first number of instructions in the target cache queue and the target scheduling mode.

15. The method according to claim 14, characterized in that The scheduling mode includes a very long instruction word scheduling mode. When the scheduling modes corresponding to the multiple scheduling requests include the very long instruction word scheduling mode, the scheduling request also includes instruction distribution information, and the instruction distribution information is used to indicate the distribution positions of valid instructions and empty instructions in the first number of instructions in the cache queue; the scheduling response signal includes a very long instruction word scheduling response signal, and the very long instruction word scheduling response signal is used to indicate that the target scheduling mode is the very long instruction word scheduling mode; The scheduler responds to the multiple scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, including: The scheduler responds to the multiple scheduling requests and sends the very long instruction word scheduling response signal to the scheduling control module corresponding to the scheduling request whose scheduling mode is the very long instruction word scheduling mode.

16. The method according to claim 15, characterized in that The instruction word includes an extremely long instruction word, and when a first scheduling request corresponding to a first cache queue in the target cache queue indicates that a scheduling mode of the first cache queue is the extremely long instruction word scheduling mode, the method further includes: When the instruction distribution information of the first scheduling request indicates that there is an empty instruction, the scheduler responds to a second scheduling request corresponding to a second cache queue in the target cache queue and sends a superscalar scheduling response signal to the scheduling control module corresponding to the second cache queue; The scheduling control module performs a shift operation and an OR operation on the instructions in the first cache queue and the instructions in the second cache queue to generate the very long instruction word to be executed.

17. The method according to claim 14, characterized in that The scheduling mode includes a superscalar scheduling mode, the scheduling response signal includes a superscalar scheduling response signal, and the superscalar scheduling response signal is used to indicate that the target scheduling mode is the superscalar scheduling mode; When the scheduling modes corresponding to the multiple scheduling requests are all the superscalar scheduling mode, the scheduler responds to the multiple scheduling requests and sends at least one scheduling response signal to at least one scheduling control module, including: The scheduler responds to the plurality of scheduling requests and sends a plurality of the superscalar scheduling response signals to the plurality of scheduling control modules.

18. The method according to claim 17, characterized in that The instruction word includes a superscalar instruction word, the at least one scheduling control module responds to the at least one scheduling response signal, and generates an instruction word to be executed based on the first number of instructions in the target cache queue and the target scheduling mode, including: The scheduling control module responds to the multiple superscalar scheduling response signals, and generates a superscalar instruction word to be executed based on a first number of instructions in the target cache queue and the superscalar scheduling mode, the number of instructions in the superscalar instruction word is the same as the first number, the position of the valid instructions in the superscalar instruction word corresponds to the identifier of the target cache queue, and the superscalar instruction word contains empty instructions except the valid instructions.

19. The method according to any one of claims 14 to 18, characterized in that The method further comprises: The multiple cache queues cache the received instructions to the target cache queue based on the received second indication information, where the second indication information is used to indicate an identifier of the target cache queue of the instruction.

20. The method according to any one of claims 14 to 19, characterized in that The network processor further includes an execution module; the method further includes: The execution module executes the instruction word to be executed.

21. The method according to claim 20, characterized in that The execution module includes: a plurality of first multiplexers, a plurality of registers, a second multiplexer and a plurality of third multiplexers; the plurality of first multiplexers correspond to the plurality of registers one-to-one, and the plurality of registers correspond to the plurality of third multiplexers one-to-one; the output end of each first multiplexer is coupled to the input end of the corresponding register, the output ends of the plurality of registers are respectively coupled to the plurality of input ends of the second multiplexer, the output end of each register is also coupled to the first input end of the corresponding third multiplexer, and the output end of the second multiplexer is also coupled to the second input end of the third multiplexer; the execution module executes the instruction word to be executed, including: The second multiplexer obtains the operand of the instruction in the very long instruction word to be executed; The third multiplexer determines the operands to be executed corresponding to the thread from the operands of the instructions in the to-be-executed very long instruction word and the operands of the instructions in the superscalar instruction word obtained by the second multiplexer.

22. The method according to any one of claims 14 to 21, characterized in that The network processor further includes a storage module, and the method further includes: The storage module stores multiple instructions. If the storage address of the instruction in the storage module is within a first address range, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode; if the storage address of the instruction in the storage module is within a second address range, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

23. The method according to any one of claims 14 to 21, characterized in that If the first indication information is a first value, the scheduling mode of the instruction indicated by the first indication information is a superscalar scheduling mode; if the first indication information is a second value, the scheduling mode of the instruction indicated by the first indication information is a very long instruction word scheduling mode.

24. A compiling method, characterized in that: The compiling method is applied to a compiler, the compiler comprising: a compiling module and a sending module; the method comprises: The compiling module compiles the instruction based on the compiling requirement corresponding to the instruction to obtain the compiled instruction and first indication information, where the first indication information is used to indicate the scheduling mode of the compiled instruction; The sending module sends the compiled instruction and the first indication information to the network processor.

25. The method according to claim 24, characterized in that The compilation requirement includes a compilation mode, the compilation mode includes a superscalar compilation mode and a very long instruction word compilation mode, the scheduling mode includes a superscalar scheduling mode and a very long instruction word scheduling mode, and if the compilation mode of the instruction is the superscalar compilation mode, the first indication information indicates that the scheduling mode of the instruction is the superscalar scheduling mode; If the compilation mode of the instruction is the very long instruction word compilation mode, the first indication information indicates that the scheduling mode of the instruction is the very long instruction word scheduling mode.

26. The method according to claim 24 or 25, characterized in that The compilation requirement is determined based on a business type corresponding to the instruction or a performance requirement of the instruction.

27. A chip, characterized in that: The chip comprises: a network processor and a power supply circuit; wherein the power supply circuit is used to supply power to the network processor; and the network processor is used to implement the method described in any one of claims 14-23.

28. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, it is used to execute the method of any one of claims 14-23 or any one of claims 24-26.

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