Monoclinic analog-to-digital converter

Abstract

The invention discloses a monoclinic analog-to-digital converter, which belongs to the field of image sensors and is characterized in that after a reset voltage of a to-be-processed pixel signal is quantized for the first time through a counting module, when the to-be-processed pixel signal is not greater than a preset voltage threshold (namely, the to-be-processed pixel signal is generated under weak light), the to-be-processed pixel signal is quantized; and controlling the counting module to quantize the to-be-processed pixel signal for the second time on the basis of the first counting parameter, and when the to-be-processed pixel signal is greater than a preset voltage threshold (namely, the to-be-processed pixel signal is generated under strong light), outputting the to-be-processed pixel signal. On the basis of a second counting parameter (the counting frequency is halved and the counting bit is subtracted by one), the counting module is controlled to carry out second quantization on the to-be-processed pixel signal, that is, when the to-be-processed pixel signal corresponding to the strong light is processed, the power consumption of the counting module is reduced in a mode of sacrificing the analog-to-digital conversion precision; therefore, the power consumption of the monoclinic analog-to-digital converter is reduced, and the power consumption of the CMOS image sensor is finally reduced.

Description

Technical Field

[0001] The invention relates to the field of image sensors, and in particular to a single-slope analog-to-digital converter. Background Art

[0002] As an important component of CMOS (Complementary Metal Oxide Semiconductor) image sensors, the power consumption of analog-to-digital converters also affects the overall power consumption of CMOS image sensors. However, the related technology lacks a mature single-slope analog-to-digital converter, resulting in high power consumption of related analog-to-digital converters, thereby making the power consumption of CMOS image sensors remain high.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the invention

[0004] The object of the present invention is to provide a single slope analog-to-digital converter, which controls the counting module to perform a second quantization on the pixel signal to be processed based on an original first counting parameter after the reset voltage of the pixel signal to be processed is quantized for the first time through a counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (that is, the pixel signal to be processed is generated under weak light), and controls the counting module to perform a second quantization on the pixel signal to be processed based on a second counting parameter (the counting frequency is halved and the counting bit is reduced by one) when the pixel signal to be processed is greater than the preset voltage threshold (that is, the pixel signal to be processed is generated under strong light), that is, by reducing the power consumption of the counting module by sacrificing the analog-to-digital conversion accuracy when processing the pixel signal to be processed corresponding to strong light, thereby reducing the power consumption of the single slope analog-to-digital converter, which is beneficial to ultimately reducing the power consumption of the CMOS image sensor.

[0005] In order to solve the above technical problems, the present invention provides a single slope analog-to-digital converter, comprising:

[0006] A comparator, used to reset both its first input terminal and second input terminal to a reset voltage when reset, wherein the first input terminal is used to input a pixel signal to be processed, and the second input terminal is used to input a ramp signal;

[0007] A counting module is used to perform a first quantization on the reset voltage of the first input terminal of the comparator when the comparator is reset; and is also used to perform a second quantization on the pixel signal to be processed based on a first counting parameter after the first quantization is completed, if the voltage value of the pixel signal to be processed is not greater than a preset voltage threshold, wherein the voltage value of the pixel signal to be processed is: the voltage difference of the pixel signal to be processed relative to the reset voltage, and the first counting parameter is: the counting frequency is the first frequency, and the counting weight is 1; if the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, the pixel signal to be processed is second quantized based on a second counting parameter, so as to subtract the difference between the result of the second quantization and the result of the first quantization as the pixel digital signal corresponding to the pixel signal to be processed, wherein the second counting parameter is: the counting frequency is the second frequency, the first frequency is twice the second frequency, and the counting weight is 2.

[0008] On the other hand, the counting module includes a clock control device and N cascaded sub-counters;

[0009] Among the N cascaded sub-counters, the output end of the previous sub-counter is connected to the clock end of the next sub-counter, and the clock control device is respectively connected to the clock end of the first sub-counter, the output end of the first sub-counter, and the clock end of the second sub-counter;

[0010] The clock control device is used to transmit a first counting clock signal to a clock terminal of the first-stage sub-counter when the comparator outputs a first digital signal, and transmit a second counting clock signal to a clock terminal of the second-stage sub-counter when the comparator outputs a second digital signal, wherein the frequency of the first counting clock signal is a first frequency, the frequency of the second counting clock signal is a second frequency, and the first frequency is twice the second frequency;

[0011] Any of the sub-counters is used to count under the drive of a counting clock signal, wherein the counting clock signal includes a first counting clock signal and a second counting clock signal.

[0012] On the other hand, the clock control device includes a clock control module and a switch module;

[0013] The switch module is arranged between the output terminal of the first-stage sub-counter and the clock terminal of the second-stage sub-counter;

[0014] The clock control module is used to realize the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module when the comparator outputs the first digital signal, and transmit the first counting clock signal to the clock end of the first-stage sub-counter; when the comparator outputs the second digital signal, disconnect the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module, and transmit the second counting clock signal to the clock end of the second-stage sub-counter through the switch module.

[0015] On the other hand, the switch module includes a first switch and a second switch;

[0016] The first switch is arranged between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter, the clock control module is respectively connected to the first end of the first switch, the control end of the first switch and the control end of the second switch, and the second end of the second switch is connected to the clock end of the second-stage sub-counter;

[0017] The clock control module is specifically used to control the first switch to be turned on and the second switch to be turned off when the comparator outputs a first digital signal, and to transmit a first counting clock signal to the clock end of the first-stage sub-counter; when the comparator outputs a second digital signal, control the first switch to be turned off and the second switch to be turned on, and to transmit a second counting clock signal to the input end of the second switch.

[0018] On the other hand, the clock control module includes a signal generation module and a clock selection module;

[0019] The clock selection module is respectively connected to the clock end of the first-stage sub-counter and the first end of the second switch, and the output end of the signal generation module is respectively connected to the control end of the first switch and the control end of the second switch;

[0020] The signal generating module is used to controllably output a first switch control signal or a second switch control signal, wherein the first switch control signal is used to control the first switch to be turned on, and the second switch control signal is used to control the second switch to be turned on;

[0021] The clock selection module is used to output a first counting clock signal under a first constraint condition and to output a second counting clock signal under a second constraint condition, wherein the first constraint condition includes the comparator outputting a first digital signal and the signal generating module outputting a first switch control signal, and the second constraint condition includes the comparator outputting a second digital signal and the signal generating module outputting a second switch control signal.

[0022] On the other hand, the first constraint condition further includes that a counting enable signal is valid, and the second constraint condition further includes that a counting enable signal is valid.

[0023] On the other hand, the clock selection module includes a first AND gate and a second AND gate;

[0024] The input ends of the first AND gate are respectively connected to the first counting clock signal, the counting enable signal, the output end of the comparator and the first switch control signal output end of the signal generating module, the output end of the first AND gate is connected to the clock end of the first-stage sub-counter, the input ends of the second AND gate are respectively connected to the second counting clock signal, the counting enable signal, the output end of the comparator and the second switch control signal output end of the signal generating module, and the output end of the second AND gate is connected to the first end of the second switch.

[0025] On the other hand, the sub-counter includes an OR gate, a first NAND gate, a second NAND gate, a first inverter, a second inverter, a CMOS switch, a first signal inverting device, a second signal inverting device, and a third signal inverting device;

[0026] The input end of the OR gate is connected to the latch signal and the clock signal respectively, the output end of the OR gate is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the switching signal, the output end of the first NAND gate is connected to the enable end of the CMOS switch, the input end of the first inverter, and the enable end of the second signal inversion device respectively, the output end of the first inverter is connected to the enable end of the first signal inversion device and the enable end of the third signal inversion device respectively, the input end of the first signal inversion device, the output end of the second inverter and the input end of the third signal inversion device are jointly used as the output end of the sub-counter, the output end of the first signal inversion device is connected to the second input end of the second NAND gate and the output end of the second signal inversion device respectively, the first input end of the second NAND gate is used as the reset port of the sub-counter, the output end of the second NAND gate is connected to the input end of the second signal inversion device and the first end of the CMOS switch respectively, and the second end of the CMOS switch is connected to the input end of the second inverter and the output end of the third signal inversion device respectively;

[0027] The switching signal is used to cooperate with the latch signal to negate the sub-counter.

[0028] On the other hand, the sub-counter is also used for:

[0029] After completing the first quantization, the controlled device inverts its own count value;

[0030] The count value after the second quantization is completed by the counting module is used as the pixel digital signal corresponding to the pixel signal to be processed.

[0031] Beneficial effect: The present invention provides a single-slope analog-to-digital converter. Considering that (1) the power of the analog-to-digital converter can be reduced by reducing the counting frequency and counting bit of the counting module, and (2) the quantization noise introduced by a small decrease in the counting bit is negligible relative to the photon shot noise of the pixel signal to be processed itself generated under strong light, the present invention can control the counting module to perform a second quantization on the reset voltage of the pixel signal to be processed based on the original first counting parameter when the pixel signal to be processed is not greater than the preset voltage threshold (that is, the pixel signal to be processed is generated under weak light) and control the counting module to perform a second quantization on the pixel signal to be processed based on the second counting parameter (the counting frequency is halved and the counting bit is reduced by one) when the pixel signal to be processed is greater than the preset voltage threshold (that is, the pixel signal to be processed is generated under strong light). That is, when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced by sacrificing the analog-to-digital conversion accuracy, thereby reducing the power consumption of the single-slope analog-to-digital converter, which is beneficial to ultimately reducing the power consumption of the CMOS image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic diagram of the structure of a single-slope analog-to-digital converter provided by the present invention;

[0034] Figure 2 A structural schematic diagram of a signal generating module provided by the present invention;

[0035] Figure 3 A schematic diagram of the structure of a clock selection module provided by the present invention;

[0036] Figure 4 A schematic diagram of the structure of an N-stage cascaded sub-counter provided by the present invention;

[0037] Figure 5 A schematic diagram of the structure of a sub-counter provided by the present invention;

[0038] Figure 6 An analog-to-digital conversion timing diagram of a weak-light pixel signal provided by the present invention;

[0039] Figure 7 This is a timing diagram of analog-to-digital conversion of a strong light pixel signal provided by the present invention. DETAILED DESCRIPTION

[0040] The core of the present invention is to provide a single slope analog-to-digital converter. After the reset voltage of a pixel signal to be processed is quantized for the first time through a counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (that is, the pixel signal to be processed is generated under weak light), the counting module is controlled based on an original first counting parameter to perform a second quantization on the pixel signal to be processed. When the pixel signal to be processed is greater than the preset voltage threshold (that is, the pixel signal to be processed is generated under strong light), the counting module is controlled based on a second counting parameter (the counting frequency is halved and the counting bit is reduced by one) to perform a second quantization on the pixel signal to be processed. That is, when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced by sacrificing the analog-to-digital conversion accuracy, thereby reducing the power consumption of the single slope analog-to-digital converter, which is beneficial to ultimately reducing the power consumption of the CMOS image sensor.

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Please refer to Figure 1 , Figure 1 A schematic structural diagram of a single slope analog-to-digital converter provided by the present invention comprises:

[0043] A comparator, used to reset both its first input terminal and second input terminal to a reset voltage when reset, wherein the first input terminal is used to input a pixel signal to be processed, and the second input terminal is used to input a ramp signal;

[0044] A counting module is used to perform a first quantization on the reset voltage of the first input terminal of the comparator when the comparator is reset; and is also used to perform a second quantization on the pixel signal to be processed based on a first counting parameter after the first quantization is completed, if the voltage value of the pixel signal to be processed is not greater than a preset voltage threshold, wherein the voltage value of the pixel signal to be processed is: the voltage difference of the pixel signal to be processed relative to the reset voltage, and the first counting parameter is: the counting frequency is the first frequency, and the counting weight is 1; if the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, the pixel signal to be processed is second quantized based on a second counting parameter, so as to subtract the difference between the result of the second quantization and the result of the first quantization as the pixel digital signal corresponding to the pixel signal to be processed, wherein the second counting parameter is: the counting frequency is the second frequency, the first frequency is twice the second frequency, and the counting weight is 2.

[0045] Specifically, in Figure 2 In, V RAMP : The ramp signal of the ramp generator output, V PIEXL : pixel output signal, RST: comparator reset voltage signal, high level enable, comparator reset, Comp_out: comparator output signal, V IN+ >V IN- When the comparator output is high level, otherwise it is low level. CLK[0]: the first counting clock signal, the frequency is FCLK[0]. CLK[1]: the second counting clock signal, the frequency FCLK[1]=FCLK[0] / 2, where the dual-frequency optional N-bit counter is the above-mentioned counting module, N is a positive integer, C N With C P are coupling capacitors, used to couple the corresponding signal to the input terminal of the comparator, wherein the first coupling capacitor C N The lower electrode is connected to the pixel signal to be processed V PIXEL , the upper plate is connected to the inverting input of the comparator, and the second coupling capacitor C P The lower plate is connected to the ramp voltage signal V RAMP , the upper plate is connected to the non-inverting input of the comparator.

[0046] Specifically, considering the technical problems in the above background technology, and considering that (1) the power of the analog-to-digital converter can be reduced by reducing the counting frequency and counting bits of the counting module, and (2) the quantization noise introduced by a small decrease in the counting bits is negligible compared to the photon shot noise of the pixel signal to be processed generated under strong light, the counting module in the single-slope analog-to-digital converter in the embodiment of the present invention is controlled to count at a low frequency and with one less counting bit when quantizing the "pixel signal to be processed based on strong light", thereby reducing the power consumption of the counting module when quantizing the "pixel signal to be processed based on strong light". Therefore, in the embodiment of the present invention, the single-slope analog-to-digital converter is first controlled to perform a reset quantization stage, that is, after the comparator in the single-slope analog-to-digital converter is reset, the reset voltage of the first input terminal of the comparator is quantized for the first time by the counting module in the single-slope analog-to-digital converter.

[0047] Specifically, since the pixel digital signal can be regarded as: the difference between the result of the second quantization of the pixel signal to be processed by the counting module and the result of the first quantization of the reset voltage of the pixel signal to be processed, the second quantization action can be carried out in the embodiment of the present invention. Taking the above ideas into consideration, the embodiment of the present invention first determines whether the pixel signal to be processed is generated based on "strong light or weak light" through a preset voltage threshold, that is, when the voltage value of the pixel signal to be processed is not greater than the preset voltage threshold, it indicates that the pixel signal to be processed is generated based on weak light. At this time, the counting module can be controlled based on the first counting parameter to perform a second quantization on the pixel signal to be processed. The first counting parameter here can be considered as the original counting parameter, that is, the counting parameter that has not been changed, and has a first frequency and a counting weight of 1.

[0048] Specifically, when the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, it indicates that the pixel signal to be processed is generated based on strong light. At this time, the counting module can be controlled based on the second counting parameter to perform a second quantization on the pixel signal to be processed. Due to the above considerations, in the embodiment of the present invention, it is intended to sacrifice counting bits when quantizing the "pixel signal to be processed based on strong light". Therefore, the counting weight in the second counting parameter in the embodiment of the present invention is 2, and the two quantization results are in the same dimension, reducing the counting frequency by half.

[0049] Specifically, in the embodiment of the present invention, based on the idea of ​​DCDS (Digital Correlated Double Sampling), the difference between the result of the second quantization and the result of the first quantization is taken as the pixel digital signal corresponding to the pixel signal to be processed.

[0050] Specifically, the embodiments of the present invention can be applied to the design fields of CCD (Charge-coupled Device Image Sensor) and CIS (CMOS Image Sensor) and related applications.

[0051] In addition, considering that the comparator in the single-slope analog-to-digital converter itself can realize the voltage value grading of the pixel signal to be processed by setting the voltage of the ramp signal, in the embodiment of the present invention, the voltage value of the ramp voltage signal received by the second input terminal of the comparator can be controlled to be a preset voltage threshold in the pre-comparison stage. Then, the level level output by the comparator at this time can represent the comparison result between the pixel signal to be processed and the preset voltage threshold. That is, if the comparator outputs the first digital signal in the pre-comparison stage, it is determined that the voltage value of the pixel signal to be processed is not greater than the preset voltage threshold. If the comparator outputs the second digital signal in the pre-comparison stage, it is determined that the voltage value of the pixel signal to be processed is greater than the preset voltage threshold. In the embodiment of the present invention, the "comparison between the pixel signal to be processed and the preset voltage threshold" can be realized based on the original comparator in the single-slope analog-to-digital converter, without the need for additional devices or calculation actions, further saving costs and reducing power consumption.

[0052] The preset voltage threshold may be set to a voltage value corresponding to an MSB (Most Significant Bit), which is not limited in the embodiment of the present invention.

[0053] The present invention provides a single slope analog-to-digital converter. Considering that (1) the power of the analog-to-digital converter can be reduced by reducing the counting frequency and counting bit of a counting module, and (2) the quantization noise introduced by a small decrease in the counting bit is negligible relative to the photon shot noise of the pixel signal to be processed itself generated under strong light, the present invention can control the counting module to perform a second quantization on the pixel signal to be processed based on the original first counting parameter after the reset voltage of the pixel signal to be processed is performed for the first time by the counting module, when the pixel signal to be processed is not greater than a preset voltage threshold (that is, the pixel signal to be processed is generated under weak light), and when the pixel signal to be processed is greater than the preset voltage threshold (that is, the pixel signal to be processed is generated under strong light), control the counting module to perform a second quantization on the pixel signal to be processed based on the second counting parameter (the counting frequency is halved and the counting bit is reduced by one). That is, when processing the pixel signal to be processed corresponding to strong light, the power consumption of the counting module is reduced by sacrificing the analog-to-digital conversion accuracy, thereby reducing the power consumption of the single slope analog-to-digital converter, which is beneficial to ultimately reducing the power consumption of the CMOS image sensor.

[0054] Based on the above embodiments:

[0055] As an optional embodiment, the counting module includes a clock control device and N cascaded sub-counters;

[0056] Among the N cascaded sub-counters, the output end of the previous sub-counter is connected to the clock end of the next sub-counter, and the clock control device is respectively connected to the clock end of the first sub-counter, the output end of the first sub-counter, and the clock end of the second sub-counter;

[0057] A clock control device, used for transmitting a first counting clock signal to a clock terminal of the first-stage sub-counter when the comparator outputs a first digital signal, and transmitting a second counting clock signal to a clock terminal of the second-stage sub-counter when the comparator outputs a second digital signal, wherein a frequency of the first counting clock signal is a first frequency, a frequency of the second counting clock signal is a second frequency, and the first frequency is twice the second frequency;

[0058] Any sub-counter is used for counting under the drive of a counting clock signal, wherein the counting clock signal includes a first counting clock signal and a second counting clock signal.

[0059] Specifically, in the embodiment of the present invention, considering that "transmitting a first counting clock signal to the clock end of the first-stage sub-counter" is equivalent to realizing the first counting parameter, and "transmitting a second counting clock signal to the clock end of the second-stage sub-counter" is equivalent to realizing the second counting parameter, the counting module in the embodiment of the present invention includes a clock control device and N cascaded sub-counters. The counting parameter can be switched by the clock control device according to the different output levels of the comparator, so that the counting module in the embodiment of the present invention has a simple structure and low cost.

[0060] Of course, in addition to this specific structure, the counting module may also be of other types, which is not limited in the embodiment of the present invention.

[0061] As an optional embodiment, the clock control device includes a clock control module and a switch module;

[0062] The switch module is arranged between the output terminal of the first-stage sub-counter and the clock terminal of the second-stage sub-counter;

[0063] A clock control module is used to realize the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module when the comparator outputs the first digital signal, and transmit the first counting clock signal to the clock end of the first-stage sub-counter; when the comparator outputs the second digital signal, disconnect the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module, and transmit the second counting clock signal to the clock end of the second-stage sub-counter through the switch module.

[0064] Specifically, considering that when implementing the second counting parameter (the counting frequency is the second frequency, the first frequency is twice the second frequency, and the counting weight is 2), the clock signal of the first-level sub-counter is not allowed to be transmitted to the second-level sub-counter, and the output end of the first-level sub-counter and the clock end of the second-level sub-counter can be reliably cut off through the switch module, the clock control device in the embodiment of the present invention includes a clock control module and a switch module, so that through the cooperation of the clock control module and the switch module, reliable switching of the counting parameters can be achieved, which is beneficial to improving the reliability of the single-slope analog-to-digital converter.

[0065] Of course, in addition to this specific structure, the clock control device can also be of many other types, which is not limited in the embodiment of the present invention.

[0066] As an optional embodiment, the switch module includes a first switch and a second switch;

[0067] The first switch is arranged between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter, the clock control module is respectively connected to the first end of the first switch, the control end of the first switch and the control end of the second switch, and the second end of the second switch is connected to the clock end of the second-stage sub-counter;

[0068] The clock control module is specifically used to control the first switch to be turned on and the second switch to be turned off when the comparator outputs the first digital signal, and to transmit the first counting clock signal to the clock end of the first-stage sub-counter; when the comparator outputs the second digital signal, control the first switch to be turned off and the second switch to be turned on, and to transmit the second counting clock signal to the input end of the second switch.

[0069] Specifically, considering that when implementing the first counting parameter, the second counting clock signal is also not allowed to be input into the clock end of the second-stage sub-counter, and the signal path can be cut off by the switch, the switch module in the embodiment of the present invention includes a first switch and a second switch. Through the cooperation of the two switches, it is possible to prevent interference from another technical parameter that may exist when implementing any counting parameter.

[0070] Of course, in addition to this specific form, the switch module may also be of other types, which is not limited in the embodiment of the present invention.

[0071] As an optional embodiment, the clock control module includes a signal generation module and a clock selection module;

[0072] The clock selection module is connected to the clock end of the first-stage sub-counter and the first end of the second switch respectively, and the output end of the signal generation module is connected to the control end of the first switch and the control end of the second switch respectively;

[0073] A signal generating module, configured to controllably output a first switch control signal or a second switch control signal, wherein the first switch control signal is used to control the first switch to be turned on, and the second switch control signal is used to control the second switch to be turned on;

[0074] A clock selection module is used to output a first counting clock signal under a first constraint condition and to output a second counting clock signal under a second constraint condition, wherein the first constraint condition includes the comparator outputting a first digital signal and the signal generating module outputting a first switch control signal, and the second constraint condition includes the comparator outputting a second digital signal and the signal generating module outputting a second switch control signal.

[0075] Specifically, in order to better illustrate the embodiments of the present invention, please refer to Figures 2 to 4 , Figure 2 A structural diagram of a signal generating module provided by the present invention, Figure 3 A schematic diagram of the structure of a clock selection module provided by the present invention, Figure 4 A schematic diagram of the structure of an N-stage cascaded sub-counter provided by the present invention, wherein the N-bit counter is composed of N cascaded sub-counters. AND4: Four-input AND gate structure. DRST: Sub-counter reset signal, high level enables, resets the output of the N-bit counter. EN_RAMP: Count enable signal, low level makes the counting module not count. Ψ0: The output signal of the D flip-flop, controls the K0 switch to be turned on or off, thereby controlling whether the CLK[0] counting signal works normally. 0: The inverted output signal of the D flip-flop, which controls the K1 switch to turn on or off, thereby controlling whether the CLK[1] counting signal works normally. LOCK_EN: Latch signal. In the pre-comparison stage, the falling edge sampling comparator output result is used to select the frequency used by the counting module in the signal quantization stage, and the SWITCH_EN signal is used to negate the output result of each bit of the counting module. SWITCH_EN and the LOCK_EN signal are used to negate the output result of each bit of the counter. Q <0> , Q <1> , Q <2> , Q <3> , Q <n-1>: The output results of the 0th, 1st, 2nd, 3rd, and N-1th bit sub-counters.

[0076] Specifically, in the embodiment of the present invention, based on N stages of cascaded sub-counters, an N-bit counter with optional dual frequencies (i.e., the first frequency and the second frequency) can be realized through a signal generation module, a clock selection module and two switches, without excessively increasing the size and cost of the single-slope analog-to-digital converter.

[0077] Of course, in addition to this specific form, the counting module may also be in many other forms, which is not limited in the embodiment of the present invention.

[0078] As an optional embodiment, the first constraint condition further includes that the counting enable signal is valid, and the second constraint condition further includes that the counting enable signal is valid.

[0079] Specifically, considering that the user may have a control demand for whether the single-slope analog-to-digital converter counts or not, in order to meet the user's needs, the first constraint condition and the second constraint condition of the clock selection module in the embodiment of the present invention both include that the counting enable signal is valid, that is, the clock selection module can only output the counting clock signal when the counting enable signal is valid, so that the user can control whether the single-slope analog-to-digital converter counts or not by controlling the counting enable signal, thereby improving the user experience.

[0080] As an optional embodiment, the clock selection module includes a first AND gate and a second AND gate;

[0081] The input ends of the first AND gate are respectively connected to the first counting clock signal, the counting enable signal, the output end of the comparator and the first switch control signal output end of the signal generating module, the output end of the first AND gate is connected to the clock end of the first-stage sub-counter, the input ends of the second AND gate are respectively connected to the second counting clock signal, the counting enable signal, the output end of the comparator and the second switch control signal output end of the signal generating module, and the output end of the second AND gate is connected to the first end of the second switch.

[0082] For details, please refer to Figure 3 , two AND gates can selectively output the first counting clock signal and the second counting clock signal respectively, and the cost and volume of the AND gates are relatively small, which can further reduce the cost and volume of the counting module.

[0083] Of course, in addition to this specific form, the clock selection module can also be of many other types, which is not limited in the embodiment of the present invention.

[0084] As an optional embodiment, the sub-counter includes an OR gate, a first NAND gate, a second NAND gate, a first inverter, a second inverter, a CMOS switch, a first signal inverting device, a second signal inverting device, and a third signal inverting device;

[0085] The input end of the OR gate is respectively connected to the latch signal and the clock signal, the output end of the OR gate is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the switching signal, the output end of the first NAND gate is respectively connected to the enable end of the CMOS switch, the input end of the first inverter, and the enable end of the second signal inversion device, the output end of the first inverter is respectively connected to the enable end of the first signal inversion device and the enable end of the third signal inversion device, the input end of the first signal inversion device, the output end of the second inverter, and the input end of the third signal inversion device are collectively used as the output end of the sub-counter, the output end of the first signal inversion device is respectively connected to the second input end of the second NAND gate and the output end of the second signal inversion device, the first input end of the second NAND gate is used as the reset port of the sub-counter, the output end of the second NAND gate is respectively connected to the input end of the second signal inversion device and the first end of the CMOS switch, and the second end of the CMOS switch is respectively connected to the input end of the second inverter and the output end of the third signal inversion device;

[0086] The switching signal is used to cooperate with the latch signal to negate the sub-counter.

[0087] Specifically, in order to better illustrate the embodiments of the present invention, please refer to Figure 5 , Figure 5 A schematic diagram of the structure of a sub-counter provided by the present invention, OR: OR gate. NAND: NAND gate. INV: inverter. TG: CMOS switch, high level enable, turned on in enabled state, turned off in non-enabled state (EN is the enable terminal of TG). ENINV: high level enable, inverts the input signal and outputs it. When LOCK_EN is low level and SWITCH is high level, the rising edge of CLK reversely transmits the data of the output terminal Q of the sub-counter to the D terminal of the sub-counter, and the falling edge of CLK transmits the data of the D terminal of the sub-counter to the output terminal Q of the sub-counter. Therefore, every time the falling edge of CLK passes, the signal output by Q is inverted once, and by cascading N sub-counters, a binary counter can be realized.

[0088] Of course, in addition to this specific form, the sub-counter can also be of many other types, which is not limited in the embodiment of the present invention.

[0089] As an optional embodiment, the sub-counter is further used for:

[0090] After completing the first quantization, the controlled device inverts its own count value;

[0091] The count value after the second quantization is completed by the counting module is used as the pixel digital signal corresponding to the pixel signal to be processed.

[0092] Specifically, in order to obtain the difference between the result of the second quantization and the result of the first quantization, it is considered that the counting module itself can be negated, which is equivalent to obtaining the negative number of the result of the first quantization, and then the second quantization is counted normally through the counting module. The output result of the counting module after the second quantization is equivalent to the difference between the result of the second quantization and the result of the first quantization. Therefore, in the embodiment of the present invention, after the first quantization is completed, the count value of each sub-counter in the counting module can be negated. Based on this, the count value of the counting module after the second quantization is completed can be used as the pixel digital signal corresponding to the pixel signal to be processed, which can avoid adding additional devices or calculation processes for difference calculation, reduce costs and further reduce power consumption.

[0093] Specifically, as described in the aforementioned embodiment, the sub-counter in the embodiment of the present invention can be controlled to invert its own count value, that is, the count value of the sub-counter can be inverted under the control of the aforementioned SWITCH_EN and LOCK_EN signals. Therefore, in the embodiment of the present invention, the sub-counter can be used to implement the work of "inverting the count value of each sub-counter in the counting module after completing the first quantization", avoiding the increase of cost and volume caused by adding devices.

[0094] Specifically, in order to better introduce the analog-to-digital conversion process in the embodiment of the present invention, please refer to Figure 6 and Figure 7 , Figure 6 An analog-to-digital conversion timing diagram of a weak-light pixel signal provided by the present invention; Figure 6 The present invention provides a timing diagram for analog-to-digital conversion of a strong light pixel signal. Figure 6 The process in is introduced as follows:

[0095] (1) The reset quantization phase begins. The RST and DRST signals are high, resetting the comparator and counter. In the reset quantization phase, Ψ0 is always high, and switch K0 is turned on. When V RAMP When the ramp voltage signal (generated by the ramp generator) starts to change, the changing voltage will be (the second coupling capacitor C P ) is coupled to the non-inverting input terminal V IN+ (solid line) and the inverting input voltage V IN- (dotted line) for comparison, when V IN+ > V IN- When the comparison result Comp_out is high, and the EN_RAMP signal is high, the counter starts counting from bit 0. IN+ < V IN- When the comparison result Comp_out is low level, the counting stops and the counting result is recorded as:

[0096] ;

[0097] F CLK[0] is the clock frequency when the 0th bit counter starts counting, S is the slope of the ramp voltage signal, V PEAK When the voltage of the ramp voltage signal reaches its maximum value, V IN+ Coupling voltage value, V RST V corresponding to the ramp voltage signal during reset IN+ Coupling voltage value and pixel voltage corresponding to V IN- Coupling voltage value, D out1 The Q output of the N-bit counter in the reset quantization stage <n-1:0>The corresponding decimal result.

[0098] (2) Pre-comparison stage, V IN+ The voltage is always V REF , when the pixel voltage is transmitted, the comparator inverting input terminal V IN- The value is V SIG , the actual pixel difference voltage is (V RST – V SIG ). At this time, the comparator non-inverting input signal V REF The inverting input signal V SIG For comparison, Figure 7 In the example, V SIG Greater than V REF (preset voltage threshold), the comparator output is low level, judging that (V RST – V SIG ) signal is a low-light pixel signal, and Ψ0 is always high. At the same time, in order to realize the subtraction operation of DCDS, each bit of the sub-counter is inverted by controlling the LOCK_EN and SWITCH_EN signals to obtain (2 N -D out1 -1) output result.

[0099] (3) Signal quantization stage, when V RAMP When the voltage starts to change, the changing voltage will be coupled to the comparator's non-inverting input terminal V IN+ (solid line) and the inverting input voltage V IN- (dotted line) for comparison, when V IN+ > V IN- When the comparison result Comp_out is high, and the EN_RAMP signal is high, the counter starts counting. IN+ < V IN- When the comparison result Comp_out is low level, the counting stops and the counting result is recorded as:

[0100] ;

[0101] Ignore overflow 2 N Count value, the pixel difference voltage (V RST – V SIG ) The corresponding quantization result is:

[0102] ;

[0103] Specifically, Figure 7 The process in is:

[0104] At the beginning of the reset quantization phase, the RST and DRST signals are high, resetting the comparator and counter. In the reset quantization phase, Ψ0 is always high, and the switch K0 is turned on. When V RAMP When the voltage starts to change, the changing voltage will be coupled to the comparator's non-inverting input terminal V IN+ (solid line) and the pixel signal voltage V to be processed at the inverting input terminal IN- (dotted line) for comparison, when V IN+ > V IN- When the comparison result Comp_out is high, and the EN_RAMP signal is high, the counter starts counting from bit 0. IN+ < V IN- When the comparison result Comp_out is low level, the counting stops and the counting result is recorded as:

[0105] ;

[0106] F CLK[0] is the clock frequency when the 0th bit counter starts counting, S is the slope of the ramp voltage signal, V PEAK When the voltage of the ramp voltage signal reaches its maximum value, V IN+ Coupling voltage value, V RST V corresponding to the ramp voltage signal during reset IN+ Coupling voltage value and pixel voltage corresponding to V IN- Coupling voltage value, D out1 The Q output of the N-bit counter in the reset quantization stage <n-1:0>The corresponding decimal result.

[0107] Pre-comparison stage, V IN+ The voltage is always V REF , when the pixel voltage is transmitted, the comparator inverting input terminal V IN- The value is V SIG , the actual pixel difference voltage is (V RST –V SIG ). At this time, the comparator non-inverting input signal V REF The inverting input signal V SIG For comparison, Figure 7 In the example, V SIG Less than V REF , the comparator output becomes high level in the pre-comparison stage, judging that (V RST –V SIG ) signal is a strong light pixel signal, Ψ0 becomes a low level in the pre-comparison stage, and the counter will start counting from the first bit in the signal quantization stage, the counting weight is recorded as 2, and the counting frequency becomes half of the reset quantization stage. At the same time, in order to realize the subtraction operation of DCDS, the LOCK_EN and SWITCH_EN signals are used to control each bit of the sub-counter to obtain (2 N -D out1 -1) output.

[0108] Signal quantization stage when V RAMP When the voltage starts to change, the changing voltage will be coupled to the comparator's non-inverting input terminal V IN+ (solid line) and the inverting input voltage V IN- (dotted line) for comparison, when V IN+ > V IN- When the comparison result Comp_out is high, and the EN_RAMP signal is high, the counter starts counting from the 1st bit. IN+ < V IN- When the comparison result Comp_out is low level, the counting stops and the counting result is recorded as:

[0109] ;

[0110] Because F CLK[1] The frequency value is F CLK[0] half of , and the count weight is 2, so this value is always an even number, which is the same as using F CLK[0] The result of the count differs by 1, 0, or -1, ignoring overflow. N Count value, the pixel difference voltage (V RST – V SIG ) The corresponding quantization result is:

[0111] ;

[0112] According to the dynamic power consumption formula of each stage counter circuit:

[0113] P=c i V DD 2 E i ;

[0114] c i is the total load capacitance of each logic module inside the i-th level counter, V DD is the power supply voltage of the counter, E i is the switching characteristic of the i-th level counter, representing the number of jumps in the output of the i-th level counter per unit time, E i It is related to the counting clock frequency. When quantizing the high-light pixel signal, the dynamic power consumption of the counter in the signal quantization stage can be halved by increasing the weight and halving the counting clock frequency. However, under the high-light pixel signal, the counting accuracy of the SS ADC also changes from N bits to (N-1) bits.

[0115] According to the quantization noise formula:

[0116] ;

[0117] V RANGE is the quantization range of SS ADC, and N is the quantization accuracy of SS ADC. Therefore, under weak light pixel signals and strong light pixel signals, the quantization noise values ​​brought by DCDS are:

[0118] ;

[0119] ;

[0120] (V RST – V REF ) is generally set to 1 / 2V RANGE , then for the strong light pixel signal, the minimum photon shot noise value is:

[0121] ;

[0122] CG is the conversion gain of the pixel in the image sensor. For the image sensor, v shot1 The value is much larger than v readnoise2 Therefore, reducing the accuracy of quantizing the strong light pixel signal will not affect the linearity of the SS ADC, which proves the feasibility of reducing the power consumption of the SS ADC by reducing the dynamic power consumption of the counter.

[0123] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the element.

[0124] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A single slope analog-to-digital converter, characterized in that include: A comparator, used to reset both its first input terminal and second input terminal to a reset voltage when reset, wherein the first input terminal is used to input a pixel signal to be processed, and the second input terminal is used to input a ramp signal; A counting module is used to perform a first quantization on the reset voltage of the first input terminal of the comparator when the comparator is reset; and is also used to perform a second quantization on the pixel signal to be processed based on a first counting parameter after the first quantization is completed, if the voltage value of the pixel signal to be processed is not greater than a preset voltage threshold, wherein the voltage value of the pixel signal to be processed is: the voltage difference of the pixel signal to be processed relative to the reset voltage, and the first counting parameter is: the counting frequency is the first frequency, and the counting weight is 1; if the voltage value of the pixel signal to be processed is greater than the preset voltage threshold, the pixel signal to be processed is second quantized based on a second counting parameter, so as to subtract the difference between the result of the second quantization and the result of the first quantization as the pixel digital signal corresponding to the pixel signal to be processed, wherein the second counting parameter is: the counting frequency is the second frequency, the first frequency is twice the second frequency, and the counting weight is 2.

2. The single slope analog-to-digital converter according to claim 1, characterized in that: The counting module includes a clock control device and N cascaded sub-counters; Among the N cascaded sub-counters, the output end of the previous sub-counter is connected to the clock end of the next sub-counter, and the clock control device is respectively connected to the clock end of the first sub-counter, the output end of the first sub-counter, and the clock end of the second sub-counter; The clock control device is used to transmit a first counting clock signal to a clock terminal of the first-stage sub-counter when the comparator outputs a first digital signal, and transmit a second counting clock signal to a clock terminal of the second-stage sub-counter when the comparator outputs a second digital signal, wherein the frequency of the first counting clock signal is a first frequency, the frequency of the second counting clock signal is a second frequency, and the first frequency is twice the second frequency; Any of the sub-counters is used to count under the drive of a counting clock signal, wherein the counting clock signal includes a first counting clock signal and a second counting clock signal.

3. The single slope analog-to-digital converter according to claim 2, characterized in that: The clock control device comprises a clock control module and a switch module; The switch module is arranged between the output terminal of the first-stage sub-counter and the clock terminal of the second-stage sub-counter; The clock control module is used to realize the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module when the comparator outputs the first digital signal, and transmit the first counting clock signal to the clock end of the first-stage sub-counter; when the comparator outputs the second digital signal, disconnect the electrical connection between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter through the switch module, and transmit the second counting clock signal to the clock end of the second-stage sub-counter through the switch module.

4. The single slope analog-to-digital converter according to claim 3, characterized in that: The switch module includes a first switch and a second switch; The first switch is arranged between the output end of the first-stage sub-counter and the clock end of the second-stage sub-counter, the clock control module is respectively connected to the first end of the first switch, the control end of the first switch and the control end of the second switch, and the second end of the second switch is connected to the clock end of the second-stage sub-counter; The clock control module is specifically used to control the first switch to be turned on and the second switch to be turned off when the comparator outputs a first digital signal, and to transmit a first counting clock signal to the clock end of the first-stage sub-counter; when the comparator outputs a second digital signal, control the first switch to be turned off and the second switch to be turned on, and to transmit a second counting clock signal to the input end of the second switch.

5. The single slope analog-to-digital converter according to claim 4, characterized in that: The clock control module includes a signal generation module and a clock selection module; The clock selection module is respectively connected to the clock end of the first-stage sub-counter and the first end of the second switch, and the output end of the signal generation module is respectively connected to the control end of the first switch and the control end of the second switch; The signal generating module is used to controllably output a first switch control signal or a second switch control signal, wherein the first switch control signal is used to control the first switch to be turned on, and the second switch control signal is used to control the second switch to be turned on; The clock selection module is used to output a first counting clock signal under a first constraint condition and to output a second counting clock signal under a second constraint condition, wherein the first constraint condition includes the comparator outputting a first digital signal and the signal generating module outputting a first switch control signal, and the second constraint condition includes the comparator outputting a second digital signal and the signal generating module outputting a second switch control signal.

6. The single slope analog-to-digital converter according to claim 5, characterized in that: The first constraint condition further includes that a count enable signal is valid, and the second constraint condition further includes that a count enable signal is valid.

7. The single slope analog-to-digital converter according to claim 5, characterized in that: The clock selection module includes a first AND gate and a second AND gate; The input ends of the first AND gate are respectively connected to the first counting clock signal, the counting enable signal, the output end of the comparator and the first switch control signal output end of the signal generating module, the output end of the first AND gate is connected to the clock end of the first-stage sub-counter, the input ends of the second AND gate are respectively connected to the second counting clock signal, the counting enable signal, the output end of the comparator and the second switch control signal output end of the signal generating module, and the output end of the second AND gate is connected to the first end of the second switch.

8. The single slope analog-to-digital converter according to claim 2, characterized in that: The sub-counter includes an OR gate, a first NAND gate, a second NAND gate, a first inverter, a second inverter, a CMOS switch, a first signal inverting device, a second signal inverting device, and a third signal inverting device; The input end of the OR gate is connected to the latch signal and the clock signal respectively, the output end of the OR gate is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the switching signal, the output end of the first NAND gate is connected to the enable end of the CMOS switch, the input end of the first inverter, and the enable end of the second signal inversion device respectively, the output end of the first inverter is connected to the enable end of the first signal inversion device and the enable end of the third signal inversion device respectively, the input end of the first signal inversion device, the output end of the second inverter and the input end of the third signal inversion device are jointly used as the output end of the sub-counter, the output end of the first signal inversion device is connected to the second input end of the second NAND gate and the output end of the second signal inversion device respectively, the first input end of the second NAND gate is used as the reset port of the sub-counter, the output end of the second NAND gate is connected to the input end of the second signal inversion device and the first end of the CMOS switch respectively, and the second end of the CMOS switch is connected to the input end of the second inverter and the output end of the third signal inversion device respectively; The switching signal is used to cooperate with the latch signal to negate the sub-counter.

9. The single-slope analog-to-digital converter according to any one of claims 2 to 8, characterized in that: The sub-counter is also used for: After completing the first quantization, the controlled device inverts its own count value; The count value after the second quantization is completed by the counting module is used as the pixel digital signal corresponding to the pixel signal to be processed.

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