HEMT transistor

Abstract

The present disclosure generally provides a high electron mobility transistor or HEMT. An example HEMT includes: a first semiconductor layer; a gate electrode disposed on a first surface of the first semiconductor layer; a first passivation layer comprising at least a sub-layer of a first dielectric material on a side of the gate, the first passivation layer further extending over a first portion of a surface of the first semiconductor layer; and a second passivation layer different from the first passivation layer, the second passivation layer comprising at least a sub-layer of the same first dielectric material on a second portion of the surface of the first semiconductor layer alongside the first passivation layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. FR2310687, filed on October 5, 2023, and entitled “Transistor HEMT”, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to the field of transistors and, more particularly, to the field of high electron mobility transistors, also referred to as HEMTs. Background Art

[0004] HEMT transistors rely on a heterojunction with a two-dimensional electron gas (also known as 2DEG) formed at its surface.

[0005] There exists a need for improved HEMT transistors and methods of making the same. Summary of the invention

[0006] To achieve this, one embodiment provides:

[0007] A HEMT transistor, comprising:

[0008] - a first semiconductor layer;

[0009] - a gate arranged on the first surface of the first semiconductor layer;

[0010] a first passivation layer comprising at least a sublayer made of a first dielectric material on the side of the gate, the first passivation layer also extending over a first part of the surface of the first semiconductor layer; and

[0011] A second passivation layer, different from the first passivation layer, comprising at least a sublayer made of the same first dielectric material on a second portion of the surface of the first semiconductor layer beside the first passivation layer.

[0012] According to an embodiment, the first dielectric material is aluminum nitride.

[0013] According to an embodiment, the first semiconductor layer is based on gallium nitride, for example made of aluminum-gallium nitride.

[0014] According to an embodiment, the transistor comprises a source contact metallization and a drain contact metallization respectively arranged on either side of the gate.

[0015] According to an embodiment, the first passivation layer extends laterally from the gate towards the drain contact metallization and only on a portion of the surface between the gate and the drain contact metallization the first passivation layer also extends laterally from the gate to the source contact metallization.

[0016] According to an embodiment, the second passivation layer extends laterally from an edge of the first passivation layer between the gate and drain contact metallization to the drain contact metallization.

[0017] According to an embodiment, the first passivation layer is covered with an insulating layer and the second passivation layer covers a side of the insulating layer between the gate and drain contact metallization and extends over a portion of the insulating layer towards the gate.

[0018] According to an embodiment, the first passivation layer includes a first sublayer and a second sublayer, the first sublayer is made of a first dielectric material, the second sublayer is made of a second dielectric material different from the first dielectric material, and the second sublayer covers the first sublayer.

[0019] According to an embodiment, the second dielectric material is aluminum oxide.

[0020] According to an embodiment, the first dielectric material of the first passivation layer and the first dielectric material of the second passivation layer have different physical properties.

[0021] Another embodiment provides a method of forming a HEMT transistor, comprising the following consecutive steps:

[0022] a) forming a first semiconductor layer;

[0023] b) forming a gate on the first surface of the first semiconductor layer;

[0024] c) Formation:

[0025] a first passivation layer comprising at least a sublayer made of a first dielectric material on the sides of the gate, the first passivation layer also extending over a first portion of the surface of the first semiconductor layer, and

[0026] A second passivation layer, different from the first passivation layer, comprises at least a sublayer made of the same first dielectric material on a second portion of the surface of the first semiconductor layer beside the first passivation layer.

[0027] According to an embodiment, during step c), a first passivation layer is formed before the second passivation layer, step c) comprising:

[0028] - a step of depositing a first passivation layer;

[0029] - a step of depositing an insulating layer;

[0030] - a step of partially etching the first passivation layer and the insulating layer; and

[0031] - A step of depositing a second passivation layer on the upper surface of the insulating layer and the first semiconductor layer.

[0032] According to one embodiment:

[0033] The first passivation layer comprises a first sublayer and a second sublayer, the first sublayer is made of a first dielectric material, the second sublayer is made of a second dielectric material different from the first dielectric material, and the second sublayer covers the first sublayer, and step c) comprises:

[0034] - a step of depositing a first sub-layer;

[0035] - a step of depositing a second sub-layer;

[0036] - a step of depositing an insulating layer;

[0037] - a step of partially etching the first passivation layer and the insulating layer; and

[0038] - A step of depositing a second passivation layer on the upper side of the insulating layer and the first semiconductor layer.

[0039] According to one embodiment, during step c), the first passivation layer and the second passivation layer are applied during one deposition step, step c) being preceded by a step of locally heat treatment.

[0040] According to an embodiment, step c) comprises successively a step of depositing a first passivation layer and a step of depositing a second passivation layer, the second passivation layer being deposited by a deposition process different from the deposition process used for the first passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above features and advantages, and others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0042] Figure 1 is a partially simplified cross-sectional view of an example of a HEMT transistor according to a first embodiment;

[0043] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I and Figure 2J It is a diagram showing the manufacturing Figure 1 A cross-sectional view of an example step of a method of making a HEMT transistor as shown in;

[0044] Figure 3 is a partially simplified cross-sectional view of an example of a HEMT transistor according to a second embodiment;

[0045] Figure 4is a partially simplified cross-sectional view of an example of a HEMT transistor according to a third embodiment; and

[0046] Figure 5A , Figure 5B and Figure 5C It is a diagram showing the manufacturing Figure 4 A cross-sectional view of an example of steps of a method for a HEMT transistor is shown. DETAILED DESCRIPTION

[0047] In the various drawings, the same features are represented by the same reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals, and may be provided with the same structure, size, and material properties.

[0048] For the sake of clarity, only operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, the applications that the described HEMT transistors may have are not described in detail, and the embodiments are compatible with the usual applications of HEMT transistors. The field of HEMT transistors capable of withstanding relatively high voltages (e.g., voltages on the order of 100 to 650 volts) in the off state is more specifically considered herein.

[0049] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct electrical connection without any intervening elements other than electrical conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0050] In the following disclosure, unless otherwise specified, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or when referring to direction qualifiers, such as "horizontal", "vertical", etc., it refers to the direction shown in the figure.

[0051] Unless otherwise stated, the expressions "about," "approximately," "substantially," and "on the order of" mean within 10%, and preferably within 5%.

[0052] For the purposes of the present invention, the expression "same material" means that two materials have a corresponding chemical composition (or stoichiometry) that substantially contains the same main chemical element (or component). The expression "main chemical element" means that the element has a stoichiometric percentage greater than 40% in the chemical composition. Typically, the stoichiometric percentage of each main chemical element in the two materials may be (nominal) different. For example, the actual stoichiometric percentage of the main chemical element may vary from the nominal value within the range of +3% / -3%, preferably within the range of +2% / -2% (for example, in AlN, the nominal stoichiometric percentage of both Al and N is 50%, while the actual stoichiometric percentage may be in the range of 47%-53%). In addition, two identical materials may contain different traces of impurity elements (such as carbon, hydrogen and oxygen). For the purposes of the present invention, "impurity element" means an element present in the chemical composition with a stoichiometric percentage less than or equal to 2%, preferably less than or equal to 1%. Typically, the total stoichiometric percentage of impurity elements in the material is less than or equal to 5%, preferably less than or equal to 3%.

[0053] Figure 1 is a partial simplified cross-sectional view of an example of a HEMT transistor 110 according to an embodiment.

[0054] The HEMT transistor 110 includes a first semiconductor layer 13 arranged on a second conductive layer 23. The semiconductor layer 13 is in contact with the upper surface of the conductive layer 23, for example, through its lower surface. As an example, a stack including the semiconductor layer 13 and the semiconductor layer 23 is located on a substrate 21. The semiconductor layer 23 is in contact with the upper surface of the substrate 21, for example, through its lower surface. The interface between the first semiconductor layer 13 and the second semiconductor layer 23 defines a heterojunction, at the surface of which a two-dimensional electron gas 2DEG (also referred to as an electron channel) is formed.

[0055] The semiconductor layers 13 and 23 are made of, for example, III-V semiconductor materials, for example based on gallium nitride (GaN). The semiconductor layer 13 is made of, for example, aluminum gallium nitride (AlGaN). The semiconductor layer 23 is made of, for example, gallium nitride.

[0056] As an example, the substrate 21 comprises a semiconductor material. The substrate 21 is made of silicon or silicon carbide, for example. As a variation, the substrate 21 is made of aluminum nitride. For example, the substrate 21 comprises a buffer layer (not shown in detail in the figure) made of gallium nitride, for example, on its upper surface side. The buffer layer is in contact with the lower surface of the semiconductor layer 23, for example, through its upper surface. The substrate 21 can be a complex composition of different semiconductors and isolation materials to ensure the good quality of the layer 23. The substrate 21 can be a convenient sequence of silicon or different substrates (sapphire or SiC) plus AlN, AlGaN and GaN layers to obtain a suitable layer 23 in terms of defects, stress, and isolation from the semiconductor wafer.

[0057] The HEMT transistor 110 includes a gate 15 on the upper surface of the semiconductor layer 13. The gate 15 is in contact with the upper surface of the semiconductor layer 13, for example, through its lower surface.

[0058] The gate 15 is made of, for example, a semiconductor material, such as a III-V semiconductor material, such as gallium nitride, and is, for example, P-type doped.

[0059] As an example, the HEMT transistor 110 further includes a source contact metallization 29 and a drain contact metallization 31. As an example, the contact metallizations 29 and 31 are based on titanium, titanium nitride and / or an alloy of aluminum and copper. For example, the source contact metallization 29 and the drain contact metallization 31 each define an ohmic contact with the semiconductor layer 23 or the semiconductor layer 13, the contact metallizations 29 and 31 are located on top of the semiconductor layer 23 and in contact with the semiconductor layer 23, for example on either side of the gate 15. Alternatively, the contact metallizations 29 and 31 are located on top of the semiconductor layer 13 and in contact with the semiconductor layer 13, for example on either side of the gate 15.

[0060] The HEMT transistor 110 further includes a first passivation layer 17 made of a first dielectric material (eg, aluminum nitride) so as to cover the side surfaces of the gate 15 and also extend over a portion of the upper surface of the first semiconductor layer 13. Figure 1 In the example of , the passivation layer 17 also partially covers the upper surface of the gate 15 in the peripheral portion of the gate 15 (close to the side of the gate 15). As an example, the passivation layer 17 is in contact with the upper surface of the semiconductor layer 13 through its lower surface. Figure 1 In an embodiment of the present invention, the passivation layer 17 covers only a portion of the upper surface of the semiconductor layer 13, located next to the gate 15, for example at the periphery of the gate 15. More specifically, in this example, the passivation layer 17 extends laterally from the gate 15 towards the drain contact metallization 31, on a portion of the surface that is only between the gate 15 and the drain contact metallization 31. In other words, the passivation layer 17 does not extend all the way to the drain contact metallization 31. In this example, the passivation layer 17 extends laterally from the gate 15 towards the source contact metallization 29, on a portion of the surface that is only between the gate 15 and the source contact metallization 29. In other words, the passivation layer 17 does not extend all the way to the source contact metallization 29. As a variation (not shown), the passivation layer 17 extends laterally from the gate 15 to the source contact metallization 29.

[0061] The HEMT transistor 110 further includes a second passivation layer 19 which is different from the first passivation layer 17 and is made of, for example, the same first dielectric material as the first passivation layer 17 , such as aluminum nitride.

[0062] Alternatively, the first passivation layer and the second passivation layer may be made of other nitride materials or oxide materials. In an alternative, not shown embodiment, the first passivation layer and the second passivation layer may be made of aluminum oxide, hafnium oxide and / or nitride-based aluminum oxide.

[0063] For example, the aluminum nitride of the first passivation layer 17 and the second passivation layer 19 both have a chemical composition comprising a stoichiometric percentage of aluminum equal to 50% and a stoichiometric percentage of nitrogen equal to 50%.

[0064] Alternatively, the aluminum nitride of the first passivation layer and the aluminum nitride of the second passivation layer may have a chemical composition including a stoichiometric percentage of aluminum between 47% and 53% and a complementary stoichiometric percentage of nitrogen. For example, the aluminum nitride of the first passivation layer has a chemical composition of 47% aluminum and 53% nitriding, while the aluminum nitride of the second passivation layer has a chemical composition of 51% aluminum and 49% nitriding.

[0065] In one (not shown) embodiment, the chemical composition of the aluminum nitride of one or both of the first passivation layer and the second passivation layer may include a stoichiometric percentage of an impurity element (eg, hydrogen), for example equal to 1%.

[0066] The second passivation layer 19 is arranged on another part of the upper surface of the semiconductor layer 13. By way of example, the passivation layer 19 is in contact with the upper surface of the first semiconductor layer 13, more precisely, the passivation layer 19 is formed next to the passivation layer 17 and covers the part of the semiconductor layer 13 not covered by the passivation layer 17, the passivation layers 17 and 19 being in contact, for example, through their sides. In the example shown, the passivation layer 19 extends laterally from the edge of the passivation layer 17 between the gate 15 and the drain contact metallization 31, up to the drain contact metallization 31. In the example shown, the passivation layer 19 also extends laterally from the edge of the passivation layer 17 between the gate 15 and the source contact metallization 29, up to the source contact metallization 29 on top of the layer 13 and in contact with the layer 13.

[0067] The passivation layers 17 and 19 each have a thickness in the range of 2 nm to 20 nm, for example, a thickness in the range of 5 nm to 10 nm. The passivation layers 17 and 19 have substantially the same thickness, for example. Alternatively, the passivation layers 17 and 19 have different thicknesses based on application requirements.

[0068] In an embodiment not shown, the top of the gate has an optional intermediate conductive layer made of a metal-containing material, for example based on titanium nitride. The intermediate metal layer is, for example, in contact with the gate. The intermediate metal layer, for example, extends only over the central part of the upper surface of the gate, so that the peripheral part of the upper surface of the gate is not covered by the metal layer. The passivation layer 17, for example, extends laterally all the way to the intermediate metal layer. As a variation, the intermediate metal layer completely covers the top surface of the gate.

[0069] The gate 15 has a gate contact metallization 27 on top, for example, and is in direct contact with it. As an example, the gate contact metallization 27 is based on titanium nitride and / or on an alloy of aluminum and copper. When an intermediate metal layer (not shown) is present, the gate contact metallization is in direct contact with the intermediate metal layer, for example.

[0070] The HEMT transistor 110 , for example, includes a multi-layer insulating layer having metallization formed inside and on top thereof.

[0071] As an example, the HEMT transistor 110 includes a first insulating layer 33 on top of and in contact with the upper surface of the passivation layer 17. As an example, the insulating layer 33 covers the entire surface of the passivation layer 17 without covering the passivation layer 19. The insulating layer 33 is, for example, self-aligned with the passivation layer 17. The insulating layer 33 is, for example, opened in front of the central portion of the gate 15 to be passed through by the gate contact metallization 27. The insulating layer 33 is, for example, made of a dielectric material, for example, made of an oxide, for example, made of silicon dioxide (SiO2).

[0072] As an example, the passivation layer 19 covers a side of the insulating layer 33 between the gate 15 and the drain contact metallization 31 and also extends over a portion of the insulating layer 33 towards the gate 15. Thus, starting from the drain contact metallization 31, the passivation layer 19 covers a portion of the upper surface of the semiconductor layer 13 between the drain contact metallization 31 and the passivation layer 17 and then also extends over the insulating layer 33, so that a portion of the passivation layer 19 is in front of the passivation layer 17 and is separated therefrom by the insulating layer 33, and in the example shown, the passivation layer 19 also covers a side of the insulating layer 33 between the gate 15 and the source contact metallization 29 and also extends towards the gate 15 over a portion of the insulating layer 33. Thus, starting from the source contact metallization 29, the passivation layer 19 covers a portion of the upper surface of the semiconductor layer 13 between the source contact metallization 29 and the passivation layer 17 and then also extends over the insulating layer 33, so that a portion of the passivation layer 19 is in front of the passivation layer 17 and is separated therefrom by the insulating layer 33. As an example, insulating layer 19 is deposited and patterned in self-alignment with insulating layer 35 (as described below).

[0073] As an example, the HEMT transistor 110 includes a second insulating layer 35 on top of and in contact with the upper surface of the passivation layer 19. As an example, the insulating layer 35 has a side in contact with the drain contact metallization 31 and extends toward the source contact metallization 29. As an example, the insulating layer 35, for example, covers only the entire surface of the passivation layer 19. Thus, the insulating layer 35, for example, extends over a portion of the upper surface of the semiconductor layer 13 that is not covered by the insulating layer 33 and over a peripheral portion of the insulating layer 33, and the insulating layer 35, for example, is made of a dielectric material, for example, silicon nitride (SiN) or an oxide, for example, silicon dioxide (SiO2).

[0074] For example, the HEMT transistor 110 includes a third insulating layer 39 covering the second insulating layer 35 and the source contact metallization 29 and the drain contact metallization 31. The third insulating layer 39 is made of the same material as the insulating layer 33 and / or 35, for example.

[0075] As an example, the HEMT transistor 110 comprises a metal region 37 which extends simultaneously over a portion of the surface of the first insulating layer 33 which is not covered by the second insulating layer 35 and over a portion of the surface of the third insulating layer 39. The metal region 37 is thus arranged on two different insulating layer levels. As an example, the metal region 37 is based on titanium nitride and / or on an alloy of aluminum and copper. The metal region 37 is made, for example, of the same material as the gate contact metallization 27.

[0076] For example, metal region 37 has a gate-drain-side edge ( Figure 1 The metal region 37 is a function of the distribution of the electric field at the right edge of the gate electrode in the gate electrode, and reduces the peak of the critical electric field, thereby increasing the avalanche voltage. For example, the metal region 37 is called a field plate.

[0077] exist Figure 1 In a transistor of , the 2DEG channel is, for example, normally closed, i.e., it is blocked under the gate 15, which prevents current from flowing between the source and drain of the transistor. The transistor will then be in an off state. The channel can be restored (i.e., made conductive) by biasing the gate 15. In this case, current can flow between the source and drain of the transistor. The transistor will then be in an on or conductive state. The described embodiments can also be applied to normally-on transistors.

[0078] The presence of the passivation layers 17 and 19 allows the upper surface of the semiconductor layer 13 to be protected, on which dangling bonds and Ga-O bonds may exist, thereby introducing negative charges that may cause degradation of 2DEG mobility, generate leakage current and / or reduce the breakdown voltage of the transistor. The passivation layers 17 and 19 fill these bonds to make the surface of the semiconductor layer 13 electrically inactive.

[0079] The passivation layers 17 and 19 also make it possible to protect the semiconductor layer 13 from oxidation and to improve its state conditions, to which the 2DEG channel is sensitive.

[0080] The passivation layers 17 and 19 may reduce the interface state density and increase the 2DEG carrier density and drift mobility by suppressing the trapping effect.

[0081] The first passivation layer 17, and more specifically the portion of the passivation layer 17 situated on the sides of the gate 15, makes it possible to increase the resistivity of the 2DEG channel under and around the gate, which results in a reduction of the electric field formed at the corners of the gate 15 and therefore a reduction of the leakage current. On the other hand, the passivation effect of the portion of the layer 17 present on the side walls of the gate is also important, always with the aim of reducing the leakage current (reducing conduction by trapping mechanisms at the sides of the gate 15).

[0082] The second passivation layer 19 enables the introduction of positive charges at the interface between the passivation layer and the first semiconductor layer 13, which locally increases the electron density in the 2DEG channel and thus locally reduces the resistivity of the 2DEG channel and improves the RON value across the device.

[0083] The use of double passivation enables a compromise to be reached between leakage current reduction and resistivity reduction of the 2DEG channel.

[0084] In this embodiment, the passivation layers 17 and 19 are both made of aluminum nitride, but can be deposited under different deposition conditions to obtain the corresponding sought effects of locally increasing the resistivity of the 2DEG channel below and around the gate (passivation layer 17) and locally increasing the electron density in the 2DEG channel (passivation layer 19). Alternatively, or in a complementary manner, before depositing the passivation layers 17 and 19, the surface of the semiconductor layer 13 can undergo different processes relative to the deposition area of ​​the passivation layer 17 and the deposition area of ​​the passivation layer 19, respectively, to obtain the corresponding sought effects of locally increasing the resistivity of the 2DEG channel (passivation layer 17) and locally increasing the electron density in the 2DEG channel (passivation layer 19).

[0085] The first passivation layer 17 and the second passivation layer 19 may have different physical structures. For example, the first passivation layer 17 and the second passivation layer 19 have different crystal properties. For example, the first passivation layer 17 and the second passivation layer 19 have different properties at the interface with the semiconductor layer 13.

[0086] As an example, using an AlN material more similar to layer 13 (AlGaN) can restore the original properties of the AlGaN layer, thereby restoring the intrinsic 2DEG low resistivity damaged by the processes required to pattern and remove the gate layer 15. In general, the same material (layers 17 and 19) may be deposited independently with different deposition conditions to modulate the effect on gate leakage and 2DEG resistivity, modulating impurities within the film (such as carbon, hydrogen and oxygen) or changing the film density to obtain layers with different permeabilities to H. This will protect the electrical properties of layer 15 used, for example, in the gate.

[0087] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I and Figure 2J It is a diagram showing the manufacturing Figure 1 sectional views of successive steps of an example of a method for a HEMT transistor are shown in FIG.

[0088] Figure 2A The diagram shows an initial structure, which includes a substrate 21, a second semiconductor layer, and a first semiconductor layer 13 in order from the bottom surface of the structure. The initial structure also includes a gate layer 15. Figure 2A In the initial structure shown, layers 23 , 13 and 15 extend continuously and have a substantially uniform thickness across the entire upper surface of substrate 21 .

[0089] Figure 2B The structure obtained at the end of the step of partial etching of the gate layer 15 is shown, so that only the layers forming the gate layer 15 remain. Figure 1 The gate of a transistor is part of each layer of the stack.

[0090] During this step, the gate 15 is etched, for example, by a plasma etching method, for example by a chlorine-based plasma etching method, for example by boron trichloride (BCl 3 ) and oxygen (O 2 ) plasma etching.

[0091] This etching step is followed, for example, by a step of cleaning the upper surface of the structure to remove, for example, residues originating from the etching mask(s) and impurities resulting from the etching of the gate 15. The cleaning of the structure comprises, for example, a step of stripping by oxygen and nitrogen (N2) plasma. The cleaning of the structure may also comprise a step of removing organic residues by means of a solvent.

[0092] Figure 2C The diagram shows Figure 2B The structure shown is obtained at the end of the step of forming the passivation layer 17 and the insulating layer 33 on the upper surface of the structure.

[0093] During this step, the passivation layer 17 is first produced in a continuous manner so that it covers Figure 2B The entire upper surface of the structure shown in .

[0094] The passivation layer 17 is formed, for example, to be in contact with the upper surface of the semiconductor layer 13 and the side surfaces and upper surface of the gate 15 .

[0095] The passivation layer 17 is formed, for example, by a thin layer deposition method, such as atomic layer deposition, also known as ALD method, for example by heat or plasma using a convenient precursor of an Al source. As an example, the method of deposition of the passivation layer 17 is plasma-enhanced ALD or thermally-enhanced ALD. At the end of this step, the passivation layer 17 has a thickness, for example, in the range from 1 nm to 15 nm, for example in the range from 3 nm to 10 nm, for example on the order of 6 nm.

[0096] Then, in this example, an insulating layer 33 is formed in a continuous manner so that it covers the entire upper surface of the passivation layer 17. The insulating layer 33 is formed, for example, in contact with the passivation layer 17. The insulating layer 33 is formed, for example, by plasma enhanced chemical vapor deposition or PECVD or LPCVD or different CVD techniques. At the end of this step, the insulating layer 33 has a thickness, for example, in the range from 10 nm to 200 nm, for example, in the range from 30 nm to 150 nm, for example, on the order of 70 nm.

[0097] As an example, before the step of depositing the passivation layer 17 and the insulating layer 33, preparation Figure 2B One or more steps of the surface of the structure shown. Figure 2B Preparation of the surface of the structure shown in may include cleaning, for example including chemical cleaning by an acid such as hydrogen chloride (HCl) or hydrogen fluoride (HF) or by an alkaline solution such as ammonia (NH 3 ) . Figure 2B The preparation of the surface of the structure shown in may also include cleaning including surface oxidation, for example. A passivation layer 17 will thus be formed in contact with the oxide film, which itself is formed in contact with the upper surface of layer 13 .

[0098] Figure 2D The structure obtained at the end of the step of etching the passivation layer 17 and the insulating layer 33 is illustrated.

[0099] More specifically, during this step, the passivation layer 17 and the insulating layer 33 are removed in front of a portion of the semiconductor layer 13. As an example, the layers 17 and 33 are kept next to the gate 15, and the layers 17 and 33 are removed outside the periphery of the gate 15, here in the portions situated to the right and to the left of the gate 15.

[0100] As an example, the removal of layers 17 and 33 is performed by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4).

[0101] The etching of layers 17 and 33 is, for example, selective and does not etch semiconductor layer 13. The etching of layers 17 and 33 is then stopped, wherein the upper surface of layer 13 is exposed.

[0102] These etching steps are followed, for example, by a step of cleaning the upper surface of the structure, for example similar to that described with respect to Figure 2B as described.

[0103] Figure 2E The diagram shows Figure 2D The structure obtained at the end of the step of forming the passivation layer 19 and the insulating layer 35 on the upper surface of the structure shown in FIG.

[0104] During this step, the passivation layer 19 is first formed in a continuous manner so that it covers Figure 2D The entire upper surface of the structure shown in .

[0105] The passivation layer 19 is, for example, formed in contact with the upper surface of the insulating layer 33 and the portion of the semiconductor layer 13 not covered by the passivation layer 17. As an example, the passivation layer 19 also covers the etched sides of the layers 17 and 33.

[0106] The passivation layer 19 is formed, for example, by a thin layer deposition method, such as atomic layer deposition (ALD method). As an example, the method of depositing the passivation layer 19 is plasma enhanced ALD or thermal ALD. At the end of this step, the passivation layer 19 has a thickness, for example, in the range from 1 nm to 10 nm, for example, in the range from 2 nm to 8 nm, for example, on the order of 5 nm.

[0107] Then, in this example, the insulating layer 35 is formed in a continuous manner so that it covers the entire upper surface of the passivation layer 19. The insulating layer 35 is formed, for example, in contact with the passivation layer 19. Figure 2C The insulating layer 35 is formed in a similar manner to one of the possible methods described for forming the layer 33. At the end of this step, the insulating layer 35 has a thickness, for example, in the range from 50 nm to 200 nm, for example on the order of 80 or 100 nm.

[0108] As an example, before the step of depositing the passivation layer 19 and the insulating layer 35, similar to what has been described above, Figure 2C As described, Figure 2D One or more steps of preparation of the surface of the structure shown.

[0109] Figure 2FThe structure obtained at the end of the step of forming openings intended to receive ohmic contacts and more specifically a source contact metallization 29 and a drain contact metallization 31 is illustrated.

[0110] Figure 2G The structure obtained at the end of the step of forming the ohmic contacts, and more specifically the source contact metallization 29 and the drain contact metallization 31 is illustrated.

[0111] First, openings are created in layers 35 and 19 intended to receive source contact metallization 29 and drain contact metallization 31 ( Figure 2F ). The openings are formed, for example, by a plasma etching method, for example based on fluorine, for example based on carbon tetrafluoride (CF4). In this example, the etching extends through the semiconductor layer 13 and occurs on or in the semiconductor layer 23. The step of forming the openings intended to receive the contact metallizations 29 and 31 is followed, for example, by a step of cleaning the upper surface of the structure, for example similar to that already described with reference to Figure 2B as described.

[0112] As an example, a step of preparing the surface of the upper side of layer 23 in the opening may be provided. This step comprises, for example, chemical cleaning by means of an acid, such as hydrogen chloride (HCl).

[0113] Then( Figure 2G ), for example, forming a source contact metallization 29 and a drain contact metallization 31 in the previously formed openings. The metallizations 29, 31 are formed, for example, by depositing one or more layers of metal-containing material followed by an etching step.

[0114] In the example shown, the source and drain metallizations extend at the bottom and sides of the openings and also extend on top of the passivation layer 35 beside the sides of the openings.

[0115] Figure 2H The diagram shows Figure 2G The structure obtained at the end of a step of forming an insulating layer 39 on the upper surface of the structure shown in , followed by a step of forming openings in layers 39, 35 and 19 in the central part of the structure.

[0116] For example, the insulating layer 39 is first formed in a continuous manner so that it covers Figure 2G The insulating layer 39 is formed by contacting the entire upper surface of the structure shown in FIG. Figure 2C The method described for forming layer 33 is the same as that for forming layer 33. At the end of this step, insulating layer 39 has a thickness, for example, in the range from 150 nm to 400 nm, for example in the range from 200 nm to 350 nm, for example, on the order of 300 nm.

[0117] An opening is then formed in the central part of the structure, which passes vertically through the layers 39, 35 and 19 and emerges on the upper surface of the layer 33. This opening extends in front of the gate 15 and in front of a portion of the area between the gate 15 and the drain contact metallization 31.

[0118] Fig.2I The diagram shows Figure 2H The structure obtained at the end of the step of forming a metallization 37 on the upper surface of the structure shown in .

[0119] As an example, during this step, a region 37 is formed on a portion of the surface of the first insulating layer 33 and Figure 2H Region 37 extends on one side of the opening formed in the step of etch and extends over the top of insulating layer 39 beside the side of the opening. Region 37 is formed, for example, by depositing one or more layers made of a metal-containing material followed by an etching step.

[0120] Figure 2J The diagram shows Fig.2I The structure shown in FIG. 1 is obtained at the end of the step of opening the layers 33 and 17 in front of the gate 15 and the subsequent step of forming the gate metallization 27 in the opening.

[0121] More specifically, during this step, layers 33 and 17 are removed in front of the central portion of the upper surface of gate 15 .

[0122] By way of example, the removal of layers 33 and 17 is performed by plasma etching, for example based on fluorine, for example based on carbon tetrafluoride (CF4) or an equivalent chemistry capable of etching dielectrics made of silicon dioxide or silicon nitride.

[0123] The presence of layers 17 and 19 below layers 33 and 35 is also useful from an integration point of view, since it is possible to have an etching step that can stop on layers 17 and 19 before reaching layers 15 and 13, respectively, in this way protecting the impact on the thickness and surface quality of layers 13 and 15 in order to maintain their electrical properties. The removal of layers 17 and 19 can be performed in a gentle manner using a wet etching chemistry or a soft dry etching process that can maintain the characteristics of layers 17 and 19 (thickness, surface quality).

[0124] On layer 17 Figure 2J The etching step is, for example, selective or partially selective, and can then be removed by a wet process or soft dry etching. For example, after partially removing layers 33 and 17, there is, for example, a step of cleaning the upper surface of the structure, for example similar to that described with respect to Figure 2B as described.

[0125] The gate contact metallization 27 is formed in the opening formed in the layers 33 and 17 in front of the central portion of the gate 15. As an example, the gate contact metallization 27 is formed on top of the gate layer 15 and in contact with the gate layer 15, or in contact with an intermediate metal layer (not shown) covering the gate layer. The gate contact metallization 27 is formed, for example, by depositing one or more layers made of a metal-containing material, followed by an etching step.

[0126] As an example, the step of forming the gate contact metallization 27 is preceded by a step of preparing the surface of the structure, for example comprising chemical cleaning by an acid, such as hydrogen chloride (HCl).

[0127] Figure 3 is a partially simplified cross-sectional view of an example of a HEMT transistor 114 according to a third embodiment.

[0128] Figure 3 Illustration of Figure 1 The transistor 114 is similar to the transistor 110 shown, with the difference that the passivation layer 17 corresponds to a stack of a first sublayer 171 made of a first dielectric material, preferably aluminum nitride, and a second sublayer 173 made of a second dielectric material different from the first material, preferably aluminum oxide (Al2O3). The second passivation layer 19 is made of the first dielectric material or the second dielectric material. Preferably, the second passivation layer 19 is made of aluminum nitride.

[0129] In this embodiment, the first sub-layer 171 and the second sub-layer 173 are in contact with each other, and the second sub-layer 173 is coated on the upper surface of the first sub-layer 171 .

[0130] The manufacturing process of transistor 114 is similar to that of Figures 2A to 2J The manufacturing process of the transistor 110 described above is described. The first sublayer 171 and the second sublayer 173 are manufactured in a continuous manner so that they cover the upper surface of the semiconductor layer 13 and the side and upper surface of the gate 15. Then, for example, the insulating layer 33 is formed in a continuous manner so that it covers the entire upper surface of the passivation layer 17. Then, as described above with reference to Figure 2D As explained, the passivation layer 17 (formed of two sub-layers) and the insulating layer 33 are removed.

[0131] As a variant (not shown), the second passivation layer corresponds to a portion of the first sublayer above which the second sublayer has been removed. In this case, the second passivation layer does not overlap the first insulating layer. The manufacturing process of such a transistor is, for example, similar to that already described in detail. Figures 2A to 2J The fabrication process of transistor 110 is described except that Figure 2DThe etching step of is stopped on the upper surface of the first sublayer. Therefore, the first sublayer is not removed and grows continuously upward to the drain contact metallization. In other words, the second passivation layer is formed by the first sublayer. In this embodiment, no steps are performed with respect to Figure 2E The step of depositing a second passivation layer is disclosed.

[0132] For example, the second sub-layer 173 is made of aluminum oxide (Al 2 O 3 ).

[0133] As a variation, sublayer 171 is made of aluminum oxide (Al 2 O 3 ) and sublayer 173 is made of AlN with different deposition conditions.

[0134] With respect to the passivation properties of passivation layer 19, the addition of sublayer 173 to passivation layer 17 advantageously changes the passivation properties of passivation layer 17, further increasing the resistivity of the 2DEG channel beneath and around the gate while maintaining low resistivity in the remainder of the 2DEG channel.

[0135] Figure 4 is a partially simplified cross-sectional view of an example of a HEMT transistor 116 according to a fourth embodiment.

[0136] Figure 4 Illustration of Figure 1 The transistor 110 shown is similar to the transistor 116, with the difference that the passivation layer 19 does not extend over the sides and part of the upper surface of the layer 33, in other words, the second passivation layer 19 is formed by a portion of the first passivation layer that extends (continuously) up to the drain contact metallization 31. In this embodiment, the first passivation layer 17 and the second passivation layer 19 are a single piece ( Figure 4 and Figure 5C The dividing line between the passivation layers 17 and 19 in FIG. 1 is for illustrative purposes only).

[0137] For example, the passivation layer 17 is made of aluminum oxide, and the passivation layer 19 is made of AlN.

[0138] Figure 5A , Figure 5B and Figure 5C It is a diagram showing the manufacturing Figure 4 0046] A cross-sectional view of an example step of a method of making a HEMT transistor 116 is shown in FIG.

[0139] For manufacturing Figure 4 The process of transistor 116 shown in FIG. 1 includes, for example, FIG. 2A to FIG. 2C The steps are similar to those shown in FIG. 1 , with the difference that the passivation layer 17 is made of aluminum oxide. Starting from forming layers 17 and 33, such as combined Figure 2C Shown and Figure 5AAs reproduced in FIG. 1 , in this embodiment, part of the aluminum oxide layer 17 is converted by chemical reaction into an aluminum nitride layer which forms the passivation layer 19 .

[0140] Figure 5B The diagram shows the etching Figure 5A The structure shown in the figure is obtained after the step of forming the insulating layer 33. Figure 2D Compared with the steps of manufacturing transistor 110 shown in Figure 5B In this embodiment, the etching of layer 33 stops on the upper surface of layer 17 so that layer 17 remains even outside the plumb line of layer 33 .

[0141] Figure 5C The step of converting the parts of the aluminium oxide passivation layer 17 not covered by the layer 33 into aluminium nitride to form the passivation layer 19 is illustrated.

[0142] For example, by annealing under ammonia Figure 5B The conversion step is carried out using the structure shown in . During this step, oxygen is outgassed from layer 19 and replaced by nitrogen.

[0143] Or, in regard to Figure 5B At the end of the steps shown, a conversion step is performed by depositing a nitride layer on the top surface of the structure, so as to cover the top surfaces of the passivation layer 17 and the insulating layer 33 before applying a thermal process to the entire structure.

[0144] At the end of this step, except for Figure 2E Except that the passivation layer 19 is not deposited during the steps shown in FIG. , the manufacturing process of the transistor 116 is similar to that of FIG. Figure 2E to Figure 2J Same as described.

[0145] exist Figure 4 and Figures 5A to 5C In the embodiment shown in , the trade-off between the on-state resistance and off-state leakage current of the transistor is advantageously improved by using two passivation layers 17 and 19 of different chemistries between the gate and drain of the transistor with a single deposition of the passivation material.

[0146] To achieve this, one embodiment provides a method of forming a HEMT transistor, comprising the following consecutive steps:

[0147] a) forming a first semiconductor layer 13;

[0148] b) forming a gate 15 on the first surface of the first semiconductor layer 13;

[0149] c) depositing a first dielectric material on the side of the gate 15 and over the surface of the first semiconductor layer 13;

[0150] d) forming an insulating layer 33 over a first portion of the first dielectric material, which is located on the side of the gate 15 and in the vicinity of the grid;

[0151] e) processing the first dielectric material in the second portion adjacent to the first portion to transform the first dielectric material into the second dielectric material.

[0152] According to an embodiment, the first dielectric material is aluminum oxide.

[0153] According to an embodiment, the second dielectric material is aluminum nitride.

[0154] According to an embodiment, the first semiconductor layer 13 is based on gallium nitride, for example made of aluminum-gallium nitride.

[0155] According to one embodiment, the first semiconductor layer 13 contacts the second semiconductor layer 23 via a second surface opposite to the first surface.

[0156] According to one embodiment, the second semiconductor layer 23 is made of gallium nitride.

[0157] According to an embodiment, the method includes forming a source contact metallization 29 and a drain contact metallization 31 .

[0158] According to one embodiment, step e) comprises annealing under ammonia.

[0159] According to an embodiment, step e) comprises a step of forming a nitride layer on top of the insulating layer, followed by a step of a thermal process.

[0160] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0161] In particular, it may be provided that the ohmic contact metallization, for example the source contact metallization and the drain contact metallization, may be formed before forming the gate contact metallization.

[0162] Further, although the first embodiment has been described with the aluminum nitride passivation layer 17, the passivation layer 17 may be made of a first sublayer and a second sublayer, the first sublayer being made of aluminum nitride and the second sublayer being made of, for example, aluminum oxide, the first sublayer and the second sublayer being in contact with each other, and the first sublayer of aluminum nitride covering the upper surface of the second sublayer. In this variation, Figure 2D The etching step shown in comprises etching of the layer 33 and of the stack of the first sub-layer and the second sub-layer in order to expose a portion of the top surface of the semiconductor layer 13 for the subsequent deposition of the passivation layer 19 and the insulating layer 33 .

[0163] Further, although an example of an embodiment in which the transistor gate 15 is in contact with the upper surface of the upper semiconductor layer 13 has been described above, as a variation, the gate 15 may be separated from the semiconductor layer 13 by a gate insulator layer.

[0164] Finally, actual implementation of the embodiments and variations described herein are within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. A HEMT transistor, comprising: a first semiconductor layer; a gate disposed on the first surface of the first semiconductor layer and having a side surface; a first passivation layer comprising at least a sublayer made of a first dielectric material on the sides of the gate, the first passivation layer also extending over a first portion of the surface of the first semiconductor layer; as well as A second passivation layer, which is different from the first passivation layer, comprises at least a sublayer made of the same first dielectric material on a second portion of the surface of the first semiconductor layer beside the first passivation layer.

2. The HEMT transistor according to claim 1, wherein: The first dielectric material is aluminum nitride.

3. The HEMT transistor according to claim 1, wherein: The first semiconductor layer is based on gallium nitride, for example made of aluminum-gallium nitride.

4. The HEMT transistor of claim 1, comprising source and drain contact metallizations respectively arranged on either side of the gate.

5. The HEMT transistor according to claim 4, wherein: The first passivation layer extends laterally from the gate towards the drain contact metallization and, only over a portion of the surface between the gate and the drain contact metallization, also extends laterally from the gate to the source contact metallization.

6. The HEMT transistor according to claim 4, wherein: The second passivation layer extends laterally from an edge of the first passivation layer between the gate and the drain contact metallization to the drain contact metallization.

7. The HEMT transistor according to claim 1, wherein: The first passivation layer is covered with an insulating layer, and the second passivation layer covers a side of the insulating layer between the gate and drain contact metallization and extends over a portion of the insulating layer towards the gate.

8. The HEMT transistor according to claim 1, wherein: The first passivation layer includes a first sublayer and a second sublayer, the first sublayer is made of the first dielectric material, the second sublayer is made of a second dielectric material different from the first dielectric material, and the second sublayer covers the first sublayer.

9. The HEMT transistor according to claim 8, wherein: The second dielectric material is aluminum oxide.

10. The HEMT transistor according to claim 1, wherein: The first passivation layer and the second passivation layer each have a thickness in a range from 2 nm to 20 nm.

11. A method for forming a HEMT transistor, comprising: a) forming a first semiconductor layer; b) forming a gate on the first surface of the first semiconductor layer, wherein the gate has a side surface; c) Formation: a first passivation layer comprising at least a sublayer made of a first dielectric material on the sides of the gate, the first passivation layer also extending over a first portion of the surface of the first semiconductor layer, and A second passivation layer, which is different from the first passivation layer, comprises at least a sublayer made of the same first dielectric material on a second portion of the surface of the first semiconductor layer beside the first passivation layer.

12. The method of claim 11, wherein during step c), the first passivation layer is formed before the second passivation layer, the step c) comprising: a step of depositing the first passivation layer; a step of depositing an insulating layer; A step of partially etching the first passivation layer and the insulating layer; as well as The step of depositing the second passivation layer on the upper surface of the insulating layer and the first semiconductor layer.

13. The method according to claim 11, wherein the first passivation layer comprises a first sublayer and a second sublayer, the first sublayer is made of the first dielectric material, the second sublayer is made of a second dielectric material different from the first dielectric material, and the second sublayer covers the first sublayer, and step c) comprises: a step of depositing the first sub-layer; a step of depositing the second sub-layer; a step of depositing an insulating layer; A step of partially etching the first passivation layer and the insulating layer; as well as The step of depositing the second passivation layer on the upper surfaces of the insulating layer and the first semiconductor layer.

14. The method according to claim 11, wherein during step c), the first passivation layer and the second passivation layer are applied during one deposition step, step c) being preceded by a step of locally heat treatment.

15. The method of claim 11, wherein step c) comprises, in sequence, the steps of depositing the first passivation layer and depositing the second passivation layer, the second passivation layer being deposited by a deposition process different from that used for the first passivation layer. 16 . The HEMT transistor of claim 1 , further comprising a first insulating layer covering an upper surface of the first passivation layer and a second insulating layer covering an upper surface of the second passivation layer.

17. The HEMT transistor according to claim 16, wherein: A portion of the second passivation layer overlaps a top surface of the first insulating layer, the portion of the second passivation layer being interposed between the first insulating layer and the second insulating layer.

18. The HEMT transistor according to claim 1, wherein: The first passivation layer partially covers an upper surface of the gate in a peripheral portion of the gate.

19. A HEMT transistor comprising: a first semiconductor layer; a gate disposed on the first surface of the first semiconductor layer and having a side surface; a first passivation layer comprising at least a sublayer made of a first dielectric material on the sides of the gate, the first passivation layer also extending over a first portion of the surface of the first semiconductor layer; as well as A second passivation layer being a single piece with the first passivation layer, the second passivation layer comprising at least a sublayer made of a second dielectric material on a second portion of the surface of the first semiconductor layer beside the first passivation layer, wherein the second dielectric material is different from the first dielectric material.

20. The HEMT transistor according to claim 19, wherein: The second dielectric material of the second passivation layer is formed from the first dielectric material by a chemical reaction.

Images