Driving backboard and display panel

Abstract

The invention provides a driving backboard and a display panel, the driving backboard comprises a plurality of sub-pixels arranged in a display area in an array mode, and each sub-pixel comprises a polycrystalline silicon transistor, an oxide transistor and a storage capacitor. The driving backboard further comprises a substrate, a first semiconductor layer, a first conducting layer, a second semiconductor layer and a second conducting layer, the first semiconductor layer, the first conducting layer, the second semiconductor layer and the second conducting layer are arranged on the substrate, the first semiconductor layer forms an active portion of the polycrystalline silicon transistor, and the first conducting layer forms a grid electrode of the polycrystalline silicon transistor. The second semiconductor layer forms an active part of the oxide transistor and a first pole plate of the storage capacitor, and the second conductive layer forms a grid electrode of the oxide transistor, so that the first pole plate of the storage capacitor and the active part of the oxide transistor are arranged on the same layer, and the conductive layer between the second semiconductor layer and the first conductive layer can be removed; therefore, the film layer of the driving backboard can be simplified, the preparation process is simplified, the preparation efficiency is improved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a display panel. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements for the resolution, power consumption and picture quality of display products. In order to meet these requirements, low-temperature polycrystalline oxide (LTPO) technology is often used to make pixel driving circuits in the driving backplane of display products. Low-temperature polysilicon oxide technology combines the high mobility of low-temperature polysilicon (LTPS) and the low leakage current advantages of oxide semiconductors such as indium gallium zinc oxide (IGZO). It has the advantages of high resolution, high response speed, high brightness, high aperture ratio, low power consumption and supports refresh rates of 1Hz to 120Hz.

[0003] However, two thin film transistor (TFT) devices need to be prepared in the low-temperature polycrystalline oxide driving backplane, and there are many film layers, which leads to complex processes, low preparation efficiency, and high production costs. Summary of the invention

[0004] The present application provides a driving backplane and a display panel to alleviate the technical problems of a low-temperature polycrystalline oxide driving backplane having a large number of film layers, a complex process, low preparation efficiency, and high manufacturing cost.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The embodiment of the present application provides a driving backplane, which includes a display area and a non-display area located on one side of the display area, wherein a plurality of sub-pixels arranged in an array are arranged in the display area, and each of the sub-pixels includes a polysilicon transistor, an oxide transistor, and a storage capacitor; the driving backplane also includes:

[0007] substrate;

[0008] A first semiconductor layer, disposed on one side of the substrate, wherein the first semiconductor layer includes an active portion of the polysilicon transistor;

[0009] A first conductive layer, disposed on a side of the first semiconductor layer away from the substrate, the first conductive layer comprising a gate of the polysilicon transistor;

[0010] a second semiconductor layer, disposed on a side of the first conductive layer away from the substrate, the second semiconductor layer comprising a first plate of a storage capacitor and an active portion of the oxide transistor, the first plate of the storage capacitor being disposed correspondingly to a gate of the polysilicon transistor;

[0011] A second conductive layer, disposed on a side of the second semiconductor layer away from the substrate, the second conductive layer comprising a gate of the oxide transistor;

[0012] a third conductive layer, the third conductive layer being disposed on a side of the second conductive layer away from the substrate, the third conductive layer comprising a source and a drain of the polysilicon transistor and a source and a drain of the oxide transistor;

[0013] The non-display area includes a fan-out area arranged close to the display area, and a first fan-out routing and a second fan-out routing arranged alternately are arranged in the fan-out area, the first fan-out routing is located in at least one of the first conductive layer and the second conductive layer, the second fan-out routing is located in at least one of the second conductive layer and the third conductive layer, the first fan-out routing and the second fan-out routing are located in different layers, and the impedance of the first fan-out routing and the second fan-out routing are the same.

[0014] In the driving backplane provided in an embodiment of the present application, the first fan-out routing is located in the first conductive layer, the second fan-out routing is located in the second conductive layer, the ratio of the length of the first fan-out routing to its cross-sectional area is a first ratio, the ratio of the length of the second fan-out routing to its cross-sectional area is a second ratio, and the second ratio is equal to the first ratio.

[0015] In the driving backplane provided in the embodiment of the present application, the second fan-out routing includes a blocking portion and a conductive portion located on a side of the blocking portion away from the substrate, and a thickness of the conductive portion is the same as a thickness of the first fan-out routing.

[0016] In the driving backplane provided in the embodiment of the present application, the material of the conductive part includes molybdenum, the material of the blocking part includes titanium, and the material of the first fan-out wiring is the same as that of the conductive part.

[0017] In the driving backplane provided in an embodiment of the present application, the first fan-out routing includes a first sub-routing located in the first conductive layer and a second sub-routing located in the second conductive layer, the first sub-routing and the second sub-routing are connected in parallel, and the second fan-out routing is located in the third conductive layer.

[0018] In the driving backplane provided in the embodiment of the present application, the orthographic projection of the first sub-line on the substrate overlaps with the orthographic projection of the second sub-line on the substrate.

[0019] In the driving backplane provided in the embodiment of the present application, the orthographic projection of the first fan-out routing on the substrate at least partially overlaps with the orthographic projection of the second fan-out routing on the substrate.

[0020] In the driving backplane provided in the embodiment of the present application, the driving backplane also includes a fourth conductive layer arranged between the substrate and the first semiconductor layer, and the fourth conductive layer includes a first light shielding portion arranged corresponding to the active portion, and a second light shielding portion arranged corresponding to the active portion.

[0021] In the driving backplane provided in the embodiment of the present application, the second light shielding portion is electrically connected to the gate of the oxide transistor.

[0022] In the driving backplane provided in the embodiment of the present application, the first fan-out routing and the second fan-out routing both extend along a first direction, and the first fan-out routing and the second fan-out routing are arranged alternately in the first direction; the driving backplane further includes a hole-digging area arranged in the display area, the first conductive layer further includes a first winding located in the display area, the second conductive layer further includes a second winding located in the display area, and the first winding and the second winding both extend along the first direction;

[0023] The driving backplane also includes a first winding group and a second winding group, the first winding group is configured to cooperate with the second winding group to surround the hole area, the first winding group and the second winding group each include a plurality of the first windings and the second windings alternately arranged in a second direction, wherein the first direction and the second direction are different, and an angle between the second direction and the first direction is greater than 0 degrees and less than or equal to 90 degrees.

[0024] In the driving backplane provided in the embodiment of the present application, there is a gap between the orthographic projection of the first winding on the substrate and the orthographic projection of the second winding on the substrate.

[0025] In the driving backplane provided in the embodiment of the present application, each of the sub-pixels further includes:

[0026] a switching transistor, wherein a gate of the switching transistor is connected to the first scanning signal line, and a first electrode of the switching transistor is connected to the data line;

[0027] a driving transistor, wherein a first electrode of the driving transistor and a second electrode of the switching transistor are connected to a first node;

[0028] a compensation transistor, wherein a gate of the compensation transistor is connected to the second scanning signal line, a first electrode of the compensation transistor and the gate of the driving transistor are connected to a second node, and a second electrode of the compensation transistor is connected to a second electrode of the driving transistor;

[0029] a first initialization transistor, wherein a gate of the first initialization transistor is connected to a third scanning signal line, a first electrode of the first initialization transistor is connected to a first initialization signal line, and a second electrode of the first initialization transistor and a gate of the driving transistor are connected to a second node;

[0030] a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode of the first light emission control transistor is connected to a high potential power line, and a second electrode of the first light emission control transistor and a first electrode of the driving transistor are connected to a first node;

[0031] a second light emission control transistor, wherein a gate of the second light emission control transistor is connected to the light emission control signal line, and a first electrode of the second light emission control transistor and a second electrode of the driving transistor are connected to a third node;

[0032] a second initialization transistor, wherein a gate of the second initialization transistor is connected to a fourth scanning signal line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emission control transistor are connected to a fourth node;

[0033] a third initialization transistor, wherein a gate of the third initialization transistor is connected to the fourth scanning signal line, a first electrode of the third initialization transistor is connected to the third initialization signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor at a first node;

[0034] a first capacitor, wherein one plate of the first capacitor is connected to the high potential power line, and the other plate of the first capacitor is connected to the gate of the driving transistor at a second node;

[0035] a second capacitor, wherein one plate of the second capacitor is connected to the first scanning signal line, and the other plate of the second capacitor is connected to the second electrode of the first initialization transistor;

[0036] Among them, the polysilicon transistor includes the switching transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor, and the third initialization transistor; the oxide transistor includes the compensation transistor and the first initialization transistor; the first capacitor is the storage capacitor, and the second capacitor is a boost capacitor.

[0037] In the driving backplane provided in the embodiment of the present application, the first winding and the second winding can be at least one of the first scanning signal line, the second scanning signal line, the third scanning signal line, the fourth scanning signal line, the light-emitting control signal line, the first initialization signal line, the second initialization signal line, and the third initialization signal line.

[0038] In the driving backplane provided in the embodiment of the present application, the first electrode plate of the storage capacitor is arranged corresponding to the gate of the driving transistor.

[0039] An embodiment of the present application further provides a display panel, which includes a light-emitting device and a driving backplane as described in one of the above embodiments, wherein the light-emitting device is arranged on the driving backplane.

[0040] The beneficial effects of the present application are as follows: in the driving backplane and display panel provided by the present application, the driving backplane includes a plurality of sub-pixels arranged in an array in a display area, each of the sub-pixels includes a polysilicon transistor, an oxide transistor and a storage capacitor, the driving backplane also includes a substrate and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer and a third conductive layer arranged on the substrate, the first semiconductor layer forms an active portion of the polysilicon transistor, the first conductive layer forms a gate of the polysilicon transistor, the second semiconductor layer forms an active portion of the oxide transistor and a first electrode plate of the storage capacitor, the second conductive layer forms the gate of the oxide transistor, and the third conductive layer forms a polysilicon crystal. The source and drain of the body tube, the source and drain of the oxide transistor, by arranging the first electrode plate of the storage capacitor and the active part of the oxide transistor in the same layer, the conductive layer between the second semiconductor layer and the first conductive layer can be removed, thereby simplifying the film layer of the driving backplane, simplifying the preparation process, improving the preparation efficiency, and reducing the production cost; in addition, at least one of the first conductive layer and the second conductive layer is further formed with a first fan-out wiring, and at least one of the second conductive layer and the third conductive layer is further formed with a second fan-out wiring, the first fan-out wiring and the second fan-out wiring are located in different layers, and the first fan-out wiring and the second fan-out wiring have the same impedance to improve display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A schematic diagram of the planar structure of a driving backplane provided in an embodiment of the present application.

[0043] Figure 2 A schematic diagram of a partial film layer structure of a driving backplane provided in an embodiment of the present application.

[0044] Figure 3 for Figure 1 Detailed structural diagram of the fan-out area.

[0045] Figure 4 for Figure 3 A schematic diagram of a cross-sectional structure along the M-M' direction.

[0046] Figure 5 for Figure 3 Schematic diagram of another cross-sectional structure along the M-M' direction.

[0047] Figure 6 Another schematic diagram of the planar structure of the driving backplane provided in an embodiment of the present application.

[0048] Figure 7 for Figure 6 Detailed structural diagram of the edge routing in the middle hole area.

[0049] Figure 8 A schematic diagram of a circuit of a sub-pixel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0051] Please refer to Figures 1 to 5 , Figure 1 A schematic diagram of a planar structure of a driving backplane provided in an embodiment of the present application, Figure 2 A schematic diagram of a partial film structure of a driver backplane provided in an embodiment of the present application, Figure 3 for Figure 1 Detailed structural diagram of the fan-out area. Figure 4 for Figure 3 A schematic diagram of a cross-sectional structure along the M-M' direction, Figure 5 for Figure 3 Another cross-sectional structure diagram along the M-M' direction. Figure 1 and Figure 2The driving backplane 100 includes a display area AA and a non-display area BA located on one side of the display area AA. A plurality of sub-pixels SP arranged in an array are arranged in the display area AA. For example, the plurality of sub-pixels SP are arranged in sequence in a first direction X and in sequence in a second direction Y. The first direction X is different from the second direction Y. The angle between the first direction X and the second direction Y is greater than 0 degrees and less than or equal to 90 degrees. For example, the first direction X is perpendicular to the second direction Y, that is, the first direction X is a row direction, and the second direction Y is a column direction. Each sub-pixel SP includes a polysilicon transistor 1, an oxide transistor 2, and a storage capacitor C1. The non-display area BA includes a fan-out area SA arranged near the display area AA. The fan-out area SA is used to fan out various signal lines in the display area AA.

[0052] The driving backplane 100 also includes a substrate 10 and a first semiconductor layer 20, a first conductive layer 30, a second semiconductor layer 40 and a second conductive layer 50 arranged on the substrate 10. The first semiconductor layer 20 is arranged on one side of the substrate 10, and the first semiconductor layer 20 includes an active portion 21 of the polysilicon transistor 1. The first conductive layer 30 is arranged on a side of the first semiconductor layer 20 away from the substrate 10, and the first conductive layer 30 includes a gate 31 of the polysilicon transistor 1, and the gate 31 of the polysilicon transistor 1 is arranged corresponding to the active portion 21 of the polysilicon transistor 1. The second semiconductor layer 40 is arranged on a side of the first conductive layer 30 away from the substrate 10, and the second semiconductor layer 40 includes a first plate 42 of the storage capacitor C1 and an active portion 41 of the oxide transistor 2, and the first plate 42 of the storage capacitor C1 is arranged corresponding to the gate 31 of the polysilicon transistor 1. The second conductive layer 50 is disposed on a side of the second semiconductor layer 40 away from the substrate 10, and the second conductive layer 50 includes a gate 51 of the oxide transistor 2, and the gate 51 of the oxide transistor 2 is disposed corresponding to the active portion 41 of the oxide transistor 2. In this way, by disposing the first electrode 42 of the storage capacitor C1 and the active portion 41 of the oxide transistor 2 in the same layer, the conductive layer between the second semiconductor layer 40 and the first conductive layer 30 can be removed, thereby simplifying the film layer of the driving backplane 100, simplifying the manufacturing process, improving the manufacturing efficiency, and reducing the manufacturing cost.

[0053] Specifically, the driving backplane 100 further includes a third conductive layer 60 and a fourth conductive layer 70. The third conductive layer 60 is disposed on a side of the second conductive layer 50 away from the substrate 10. The third conductive layer 60 includes a source 61 and a drain 62 of the polysilicon transistor 1 and a source 64 and a drain 63 of the oxide transistor 2. The fourth conductive layer 70 is disposed between the substrate 10 and the first semiconductor layer 20. The fourth conductive layer 70 includes a first light shielding portion 71 and a second light shielding portion 72, wherein the first light shielding portion 71 is disposed corresponding to the active portion 21 of the polysilicon transistor 1, and the second light shielding portion 72 is disposed corresponding to the active portion 41 of the oxide transistor 2. Of course, the driving backplane 100 further includes an insulating layer located between each conductive layer and semiconductor layer.

[0054] Specifically, refer to Figure 2 , the fourth conductive layer 70 is arranged on one side of the substrate 10, and the first buffer layer 11 and the second buffer layer 12 are arranged between the fourth conductive layer 70 and the first semiconductor layer 20. The first buffer layer 11 covers the fourth conductive layer 70 and the substrate 10, and the second buffer layer 12 covers the first buffer layer 11. Optionally, the substrate 10 can be a substrate of inorganic material or a substrate of organic material. For example, in one embodiment of the present application, the material of the substrate 10 can be a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present application, the substrate 10 can also be a flexible substrate substrate, for example, the material of the substrate 10 can be polyimide (PI). The substrate 10 can also be a composite of multiple layers of materials. The first buffer layer 11 and the second buffer layer 12 can be inorganic films, such as SiNx, SiOx or a composite layer thereof. The material of the fourth conductive layer 70 includes a metal material with light-shielding properties.

[0055] The first semiconductor layer 20 is disposed on the second buffer layer 12. The material of the first semiconductor layer 20 includes semiconductor materials such as polysilicon. The active portion 21 of the polysilicon transistor 1 formed by the first semiconductor layer 20 includes a first channel portion 211 and a first source contact portion 212 and a first drain contact portion 213 located on opposite sides of the first channel portion 211. The first light shielding portion 71 is at least disposed corresponding to the first channel portion 211 to shield the first channel portion 211 from light.

[0056] A first insulating layer 13 is disposed between the first semiconductor layer 20 and the first conductive layer 30. The material of the first insulating layer 13 includes inorganic materials such as SiNx and SiOx. The material of the first conductive layer 30 includes a metal material with conductive properties, such as molybdenum. The gate 31 formed by the first conductive layer 30 is disposed corresponding to the first channel portion 211.

[0057] A second insulating layer 14 is provided between the first conductive layer 30 and the second semiconductor layer 40. The material of the second insulating layer 14 includes inorganic materials such as SiNx and SiOx. The material of the second semiconductor layer 40 includes a metal oxide semiconductor material, such as Indium Gallium Zinc Oxide (IGZO). The second semiconductor layer 40 is formed with an active portion 41 of the oxide transistor 2 and a first plate 42 of the storage capacitor C1. The active portion 41 of the oxide transistor 2 includes a second channel portion 411 and a second source contact portion 412 and a second drain contact portion 413 located on opposite sides of the second channel portion 411. The second light shielding portion 72 is provided at least corresponding to the second channel portion 411 to shield the second channel portion 411. The first plate 42 of the storage capacitor C1 is provided corresponding to the gate 31 of the polysilicon transistor 1 to form the storage capacitor C1. Of course, in some embodiments, the second light shielding portion 72 can also be electrically connected to the gate 51 of the oxide transistor 2 to serve as the bottom gate of the oxide transistor 2.

[0058] A third insulating layer 15 is disposed between the second semiconductor layer 40 and the second conductive layer 50. The material of the third insulating layer 15 includes inorganic materials such as SiNx and SiOx. The material of the second conductive layer 50 includes a metal material having conductive properties, such as molybdenum, titanium, etc., that is, the second conductive layer 50 can be formed by two metal layers, a titanium layer and a molybdenum layer, the molybdenum layer is located on the side of the titanium layer away from the substrate 10, and the titanium layer is used to block the hydrogen in the upper layer to avoid affecting the active portion 41.

[0059] A fourth insulating layer 16 is provided between the second conductive layer 50 and the third conductive layer 60. The material of the fourth insulating layer 16 includes inorganic materials such as SiNx and SiOx. An opening 161 is formed on the fourth insulating layer 16. The material of the third conductive layer 60 includes conductive metals such as titanium, aluminum, and copper. The third conductive layer 60 is formed with a source 61 and a drain 62 of the polysilicon transistor 1, and a source 64 and a drain 63 of the oxide transistor 2. The source 61 of the polysilicon transistor 1 is connected to the first source contact 212, the drain 62 of the polysilicon transistor 1 is connected to the first drain contact 213, the source 64 of the oxide transistor 2 is connected to the second source contact 412, and the drain 63 of the oxide transistor 2 is connected to the second drain contact 413.

[0060] The driving backplane 100 further includes a fifth conductive layer 80 and a sixth conductive layer 90, wherein the fifth conductive layer 80 is located on a side of the third conductive layer 60 away from the substrate 10, and the sixth conductive layer 90 is located on a side of the fifth conductive layer 80 away from the substrate 10. A first flat layer 17 is disposed between the third conductive layer 60 and the fifth conductive layer 80. The material of the first flat layer 17 includes an organic material, and the first flat layer 17 is filled in the opening 161. The material of the fifth conductive layer 80 is the same as that of the third conductive layer 60. The fifth conductive layer 80 forms a transfer electrode 81, and the transfer electrode 81 is connected to the drain 62 of the polysilicon transistor 1.

[0061] A second planar layer 18 is disposed between the fifth conductive layer 80 and the sixth conductive layer 90. The material of the second planar layer 18 includes an organic material. The material of the sixth conductive layer 90 includes a transparent conductive material such as indium tin oxide. The sixth conductive layer 90 is formed with a first electrode 91, and the first electrode 91 is connected to the switching electrode 81.

[0062] The driving backplane 100 further includes a third flat layer 19 and a retaining wall 92. The material of the third flat layer 19 includes an organic material. The third flat layer 19 covers the sixth conductive layer 90 and the second flat layer 18, and the third flat layer 19 is provided with an opening 191 at a position corresponding to the first electrode 91, and the opening 191 exposes a portion of the first electrode 91. The retaining wall 92 is provided on the third flat layer 19 and is located around the opening 191.

[0063] Reference Figure 3 The fan-out area SA is provided with alternately arranged first fan-out traces 32 and second fan-out traces 52, the first fan-out traces 32 are located in at least one of the first conductive layer 30 and the second conductive layer 50, the second fan-out traces 52 are located in at least one of the second conductive layer 50 and the third conductive layer 60, and the first fan-out traces 32 and the second fan-out traces 52 are located in different layers, and the impedances of the first fan-out traces 32 and the second fan-out traces 52 are the same to improve display uniformity.

[0064] In one embodiment, the first fan-out routing 32 is located in the first conductive layer 30, and the second fan-out routing 52 is located in the second conductive layer 50, that is, the first conductive layer 30 also includes the first fan-out routing 32 located in the fan-out area SA, and the second conductive layer 50 also includes the second fan-out routing 52 located in the fan-out area SA. The first fan-out routing 32 and the second fan-out routing 52 are alternately arranged in the first direction X, and the impedance of the first fan-out routing 32 and the second fan-out routing 52 are the same to improve display uniformity.

[0065] The ratio of the length of the first fan-out trace 32 to its cross-sectional area is a first ratio, and the ratio of the length of the second fan-out trace 52 to its cross-sectional area is a second ratio, and the second ratio is equal to the first ratio, so that the impedances of the first fan-out trace 32 and the second fan-out trace 52 are the same. Moreover, the fan-out area SA includes a plurality of first fan-out traces 32 and a plurality of second fan-out traces 52, and the impedances of the first fan-out traces 32 and the second fan-out traces 52 are the same.

[0066] Optionally, refer to Figure 4 , the width of the first fan-out trace 32 is the same as the width of the second fan-out trace 52. The second fan-out trace 52 includes a blocking portion 522 and a conductive portion 521 located on a side of the blocking portion 522 away from the substrate 10, and a thickness H2 of the conductive portion 521 is the same as a thickness H1 of the first fan-out trace 32. The material of the conductive portion 521 includes molybdenum, the material of the blocking portion 522 includes titanium, and the material of the first fan-out trace 32 is the same as the material of the conductive portion 521.

[0067] The orthographic projection of the first fan-out routing 32 on the substrate 10 is separated from the orthographic projection of the second fan-out routing 52 on the substrate 10, that is, there is no overlapping part between the orthographic projection of the first fan-out routing 32 on the substrate 10 and the orthographic projection of the second fan-out routing 52 on the substrate 10, so as to reduce the parasitic capacitance between the first fan-out routing 32 and the second fan-out routing 52. In addition, the present application forms the first fan-out routing 32 with the first conductive layer 30, forms the second fan-out routing 52 with the second conductive layer 50, and the first conductive layer 30 and the second conductive layer 50 are separated by two insulating layers, namely, the second insulating layer 14 and the third insulating layer 15, and the second semiconductor layer 40, so as to increase the distance between the first fan-out routing 32 and the second fan-out routing 52, thereby further reducing the parasitic capacitance between the first fan-out routing 32 and the second fan-out routing 52 and improving the display uniformity.

[0068] In some other embodiments, the orthographic projection of the first fan-out trace 32 on the substrate 10 is at least partially overlapped with the orthographic projection of the second fan-out trace 52 on the substrate 10 to reduce the area of ​​the non-display area BA occupied by the fan-out area SA, thereby improving the screen-to-body ratio.

[0069] In another embodiment, referring to Figure 5, the first fan-out routing 32 includes a first sub-routing 321 located in the first conductive layer 30 and a second sub-routing 322 located in the second conductive layer 50, the first sub-routing 321 and the second sub-routing 322 are connected in parallel, and the second fan-out routing 52 is located in the third conductive layer 60. That is, the first conductive layer 30 also includes the first sub-routing 321 located in the fan-out area SA, the second conductive layer 50 also includes the second sub-routing 322 located in the fan-out area SA, and the third conductive layer 60 also includes the second fan-out routing 52 located in the fan-out area SA. The second sub-routing 322 is connected to the first sub-routing 321 through a plurality of contact holes on the third insulating layer 15, so as to realize the parallel connection between the first sub-routing 321 and the second sub-routing 322, so as to reduce the impedance of the first fan-out routing 32.

[0070] Optionally, the orthographic projection of the first sub-route 321 on the substrate 10 overlaps with the orthographic projection of the second sub-route 322 on the substrate 10 to reduce the area occupied by the first fan-out route 32 in the fan-out area SA.

[0071] Of course, in some other embodiments, the first fan-out routing 32 may also be located in the first conductive layer 30, and the second fan-out routing 52 may be located in the second conductive layer 50 and the third conductive layer 60; or, the first fan-out routing 32 may also be located in the first conductive layer 30, and the second fan-out routing 52 may be located in the third conductive layer 60; or, the first fan-out routing 32 may also be located in the second conductive layer 50, and the second fan-out routing 52 may be located in the third conductive layer 60.

[0072] In one embodiment, referring to Figures 1 to 8 , Figure 6 Another schematic diagram of the planar structure of the driving backplane 100 provided in the embodiment of the present application is shown in FIG. Figure 7 for Figure 6 Detailed structural diagram of the HA edge routing in the middle hole area. Figure 8 This is a schematic circuit diagram of a sub-pixel SP provided in an embodiment of the present application. Figure 6 Different from the above embodiment, the driving backplane 100 also includes a hole area HA arranged in the display area AA. The hole area HA is formed by digging a hole in the driving backplane 100. Functional components such as a camera can be arranged under the hole area HA. ​​The hole area HA is used to transmit light to improve the lighting effect of functional components such as the camera.

[0073] Reference Figure 7, the first conductive layer 30 further includes a first winding 33 located in the display area AA, and the second conductive layer 50 further includes a second winding 53 located in the display area AA. The first winding 33 and the second winding 53 both extend along the first direction X. The driving backplane 100 further includes a first winding group 331 and a second winding group 332, the first winding group 331 is configured to cooperate with the second winding group 332 to surround the hole area HA, and the first winding group 331 and the second winding group 332 both include a plurality of first windings 33 and second windings 53 alternately arranged in the second direction Y. The first winding group 331 and the second winding group 332 are symmetrically arranged about the hole area HA.

[0074] Optionally, there is a gap between the orthographic projection of the first winding 33 on the substrate 10 and the orthographic projection of the second winding 53 on the substrate 10, that is, the orthographic projection of the first winding 33 on the substrate 10 and the orthographic projection of the second winding 53 on the substrate 10 do not overlap, so as to reduce the parasitic capacitance between the first winding 33 and the second winding 53. In addition, the present application forms the first winding 33 by using the first conductive layer 30, forms the second winding 53 by the second conductive layer 50, and the first conductive layer 30 and the second conductive layer 50 are separated by two insulating layers of the second insulating layer 14 and the third insulating layer 15 and the second semiconductor layer 40, so as to increase the distance between the first winding 33 and the second winding 53, thereby further reducing the parasitic capacitance between the first winding 33 and the second winding 53 and improving the display uniformity.

[0075] The first winding 33 and the second winding 53 may be various control signal lines or scanning lines on the driving backplane 100. Figure 8 , taking the example that each sub-pixel SP includes 8 transistors and 2 capacitors, the 8 transistors are respectively a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second initialization transistor T7, and a third initialization transistor T8. The 2 capacitors are respectively a first capacitor Cst and a second capacitor Cboost.

[0076] Specifically, a gate of the switch transistor T2 is connected to the first scan signal line Pscan, and a first electrode of the switch transistor T2 is connected to the data line DATA.

[0077] A first node A is connected to a first electrode of the driving transistor T1 and a second electrode of the switching transistor T2 .

[0078] The gate of the compensation transistor T3 is connected to the second scan signal line Nscan1 , the first electrode of the compensation transistor T3 and the gate of the driving transistor T1 are connected to the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1 .

[0079] The gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2 , the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 and the gate of the driving transistor T1 are connected to the second node Q.

[0080] The gate of the first light emission control transistor T5 is connected to the light emission control signal line EM, the first electrode of the first light emission control transistor T5 is connected to the high potential power line VDD, and the second electrode of the first light emission control transistor T5 is connected to the first node A with the first electrode of the driving transistor T1.

[0081] A gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B.

[0082] The gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan2, the first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and the second electrode of the second initialization transistor T7 and the second electrode of the second light emission control transistor T6 are connected to the fourth node C.

[0083] A gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2 , a first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3 , and a second electrode of the third initialization transistor T8 is connected to the first node A with the first electrode of the driving transistor T1 .

[0084] One plate of the first capacitor Cst is connected to the high potential power line VDD, and the other plate of the first capacitor Cst is connected to the gate of the driving transistor T1 at the second node Q.

[0085] One plate of the second capacitor Cboost is connected to the first scan signal line Pscan, and the other plate of the second capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0086] The polysilicon transistor 1 includes a switch transistor T2, a driving transistor T1, a first light emission control transistor T5, a second light emission control transistor T6, a second initialization transistor T7, and a third initialization transistor T8; the oxide transistor 2 includes a compensation transistor T3 and a first initialization transistor T4; the first capacitor Cst is a storage capacitor C1, and the second capacitor Cboost is a boost capacitor. The first winding 33 and the second winding 53 can be at least one of the first scanning signal line Pscan, the second scanning signal line Nscan1, the third scanning signal line Nscan2, the fourth scanning signal line Pscan2, the light emission control signal line EM, the first initialization signal line VI-G, the second initialization signal line VI-ANO, and the third initialization signal line VI3.

[0087] Optionally, the first electrode 42 of the storage capacitor C1 is disposed corresponding to the gate of the driving transistor T1 .

[0088] It should be noted that the first electrode of the transistor in the above embodiment is the source and the second electrode is the drain; or the first electrode of the transistor in the above embodiment is the drain and the second electrode is the source. The first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2 and the light emitting control signal line EM can be connected to different gate drive circuits respectively. Specifically, five groups of gate drive circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2 and the light emitting control signal line EM respectively, wherein the gate drive circuit connected to the first scan signal line Pscan can adopt bilateral drive, and other gate drive circuits adopt unilateral drive.

[0089] Based on the same inventive concept, the present application also provides a display panel, which includes a light-emitting device and a driving backplane 100 of one of the aforementioned embodiments, wherein the light-emitting device is disposed on the driving backplane 100, and the driving backplane 100 is used to drive the light-emitting device to emit light.

[0090] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving backplane, characterized in that: The invention comprises a display area and a non-display area located on one side of the display area, wherein a plurality of sub-pixels are arranged in the display area, each of the sub-pixels comprises a polysilicon transistor, an oxide transistor and a storage capacitor, one electrode plate of the storage capacitor and a gate of the polysilicon transistor are both located on a first conductive layer, the other electrode plate of the storage capacitor and an active portion of the oxide transistor are both located on a second semiconductor layer, the gate of the oxide transistor is located on the second conductive layer, and the second conductive layer is located on a side of the second semiconductor layer away from the first conductive layer; Among them, the driving backplane also includes a hole area arranged in the display area, the first conductive layer also includes a first winding located in the display area, and the second conductive layer also includes a second winding located in the display area, and the first winding and the second winding extend in the same direction.

2. The driving backplane according to claim 1, characterized in that: The driving back plate also includes a first winding group and a second winding group, the first winding group is configured to cooperate with the second winding group to surround the hole area, the first winding group and the second winding group each include a plurality of the first windings and the second windings extending in a first direction and alternately arranged in a second direction, wherein the first direction and the second direction are different, and an angle between the second direction and the first direction is greater than 0 degrees and less than or equal to 90 degrees.

3. The driving backplane according to claim 2, characterized in that: There is a gap between an orthographic projection of the first winding on the substrate of the driving backplane and an orthographic projection of the second winding on the substrate of the driving backplane.

4. The driving backplane according to claim 1, characterized in that: Each of the sub-pixels further comprises: a switching transistor, wherein a gate of the switching transistor is connected to the first scanning signal line, and a first electrode of the switching transistor is connected to the data line; a driving transistor, wherein a first electrode of the driving transistor and a second electrode of the switching transistor are connected to a first node; a compensation transistor, wherein a gate of the compensation transistor is connected to the second scanning signal line, a first electrode of the compensation transistor and the gate of the driving transistor are connected to a second node, and a second electrode of the compensation transistor is connected to a second electrode of the driving transistor; a first initialization transistor, wherein a gate of the first initialization transistor is connected to a third scanning signal line, a first electrode of the first initialization transistor is connected to a first initialization signal line, and a second electrode of the first initialization transistor and a gate of the driving transistor are connected to a second node; a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode of the first light emission control transistor is connected to a high potential power line, and a second electrode of the first light emission control transistor and a first electrode of the driving transistor are connected to a first node; a second light emission control transistor, wherein a gate of the second light emission control transistor is connected to the light emission control signal line, and a first electrode of the second light emission control transistor and a second electrode of the driving transistor are connected to a third node; a second initialization transistor, wherein a gate of the second initialization transistor is connected to a fourth scanning signal line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emission control transistor are connected to a fourth node; a third initialization transistor, wherein a gate of the third initialization transistor is connected to the fourth scanning signal line, a first electrode of the third initialization transistor is connected to the third initialization signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor at a first node; a first capacitor, wherein one plate of the first capacitor is connected to the high potential power line, and the other plate of the first capacitor is connected to the gate of the driving transistor at a second node; a second capacitor, wherein one plate of the second capacitor is connected to the first scanning signal line, and the other plate of the second capacitor is connected to the second electrode of the first initialization transistor; Among them, the polysilicon transistor includes the switching transistor, the driving transistor, the first light-emitting control transistor, the second light-emitting control transistor, the second initialization transistor, and the third initialization transistor; the oxide transistor includes the compensation transistor and the first initialization transistor; the first capacitor is the storage capacitor, and the second capacitor is a boost capacitor.

5. The driving backplane according to claim 4, characterized in that: The first winding and the second winding can be at least one of the first scanning signal line, the second scanning signal line, the third scanning signal line, the fourth scanning signal line, the light emitting control signal line, the first initialization signal line, the second initialization signal line, and the third initialization signal line, respectively.

6. The driving backplane according to any one of claims 1 to 5, characterized in that: The driving backplane further comprises a third conductive layer disposed on a side of the second conductive layer away from the second semiconductor layer, the third conductive layer comprising a source and a drain of the polysilicon transistor and a source and a drain of the oxide transistor; The non-display area includes a fan-out area arranged close to the display area, wherein first fan-out routing and second fan-out routing are alternately arranged, the first fan-out routing is located in at least one of the first conductive layer and the second conductive layer, the second fan-out routing is located in at least one of the second conductive layer and the third conductive layer, the first fan-out routing and the second fan-out routing are located in different layers, and the first fan-out routing and the second fan-out routing have the same impedance.

7. The driving backplane according to claim 6, characterized in that: The first fan-out routing is located in the first conductive layer, the second fan-out routing is located in the second conductive layer, a ratio of a length of the first fan-out routing to its cross-sectional area is a first ratio, a ratio of a length of the second fan-out routing to its cross-sectional area is a second ratio, and the second ratio is equal to the first ratio.

8. The driving backplane according to claim 7, characterized in that: The second fan-out routing includes a blocking portion and a conductive portion located on a side of the blocking portion away from the second semiconductor layer, and a thickness of the conductive portion is the same as a thickness of the first fan-out routing.

9. The driving backplane according to claim 8, characterized in that: The material of the conductive portion includes molybdenum, the material of the blocking portion includes titanium, and the material of the first fan-out wiring is the same as that of the conductive portion.

10. The driving backplane according to claim 6, characterized in that: The first fan-out routing includes a first sub-routing located in the first conductive layer and a second sub-routing located in the second conductive layer, the first sub-routing and the second sub-routing are connected in parallel, and the second fan-out routing is located in the third conductive layer.

11. The driving backplane according to claim 10, characterized in that: An orthographic projection of the first sub-line on the substrate of the driving backplane overlaps with an orthographic projection of the second sub-line on the substrate of the driving backplane.

12. The driving backplane according to claim 6, characterized in that: An orthographic projection of the first fan-out trace on the substrate of the driving backplane at least partially overlaps with an orthographic projection of the second fan-out trace on the substrate of the driving backplane.

13. The driving backplane according to claim 6, characterized in that: The driving backplane also includes: A first semiconductor layer, disposed on one side of the substrate of the driving backplane, wherein the first semiconductor layer includes an active portion of the polysilicon transistor; The fourth conductive layer is disposed between the substrate of the driving backplane and the first semiconductor layer, and includes a first light shielding portion disposed corresponding to the active portion of the polysilicon transistor and a second light shielding portion disposed corresponding to the active portion of the oxide transistor.

14. The driving backplane according to claim 13, characterized in that: The second light shielding portion is electrically connected to a gate of the oxide transistor.

15. A display panel, characterized in that: It comprises a light emitting device and a driving backplane as claimed in any one of claims 1 to 14, wherein the light emitting device is arranged on the driving backplane.

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