Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, which comprise a display area. The display area of the array substrate comprises a substrate, a first transparent electrode layer, a first metal layer, a gate insulating layer, a semiconductor layer, a second transparent electrode layer and a second metal layer. The first transparent electrode layer is arranged on the substrate and comprises a common electrode. The first metal layer is arranged on a surface of the first transparent electrode layer away from the substrate and comprises a gate electrode. The gate insulating layer is arranged on the substrate and covers the common electrode and the gate electrode. The semiconductor layer is arranged on a surface of the gate insulating layer away from the substrate. The second transparent electrode layer is arranged on a surface of the gate insulating layer away from the substrate and comprises a pixel electrode. The second metal layer is arranged on a surface of the second transparent electrode layer away from the substrate and comprises a source electrode and a drain electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Fringe Field Switching (FFS) is a widely used LCD display technology, offering advantages such as high transmittance, wide viewing angles, and minimal color shift. Conventional FFS array substrates require a high number of masking steps, increasing their production costs. Summary of the Invention

[0003] Embodiments of the present application provide an array substrate and a display panel to improve the problem of increased manufacturing costs due to a large number of masking operations for the array substrate.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, comprising a display area, wherein the display area of ​​the array substrate comprises:

[0005] substrate;

[0006] a first transparent electrode layer, the first transparent electrode layer being disposed on the substrate, and the first transparent electrode layer comprising a common electrode;

[0007] a first metal layer, the first metal layer being disposed on a surface of the first transparent electrode layer away from the substrate, the first metal layer comprising a gate;

[0008] a gate insulating layer, the gate insulating layer being disposed on the substrate and covering the common electrode and the gate;

[0009] a semiconductor layer, the semiconductor layer being disposed on a surface of the gate insulating layer away from the substrate;

[0010] a second transparent electrode layer, the second transparent electrode layer being disposed on a surface of the gate insulating layer away from the substrate, the second transparent electrode layer including a pixel electrode surface;

[0011] The second metal layer is disposed on a surface of the second transparent electrode layer away from the substrate, and the second metal layer includes a source electrode and a drain electrode.

[0012] Furthermore, the second transparent electrode layer further includes a first auxiliary electrode, the first auxiliary electrode is located between the semiconductor layer and the second metal layer, and the first auxiliary electrode is electrically connected to the pixel electrode and the drain electrode.

[0013] Furthermore, the first auxiliary electrode includes a first horizontal portion, a vertical portion, and a second horizontal portion, the first horizontal portion is connected to the second horizontal portion through the vertical portion, the second horizontal portion is electrically connected to the pixel electrode, and the drain electrode covers the first horizontal portion, the vertical portion, and the second horizontal portion;

[0014] Wherein, the top surface of the second horizontal portion is lower than the top surface of the first horizontal portion.

[0015] Furthermore, the display area of ​​the array substrate further includes a passivation layer, the passivation layer is provided on a side of the source electrode and the drain electrode away from the substrate, and the passivation layer covers the pixel electrode.

[0016] Furthermore, the passivation layer includes a first horizontal passivation portion, a vertical passivation portion, and a second horizontal passivation portion, the first horizontal passivation portion is connected to the second horizontal passivation portion through the vertical passivation portion, and a top surface of the first horizontal passivation portion is higher than a top surface of the second horizontal passivation portion;

[0017] In a top view of the array substrate, a portion of the first horizontal passivation portion overlaps with the first auxiliary electrode, and a portion of the second horizontal passivation portion overlaps with the pixel electrode.

[0018] Furthermore, the display area of ​​the array substrate further includes a scan line, a first support column, and a second support column, wherein the scan line is provided on the substrate, the first support column is provided on a surface of the passivation layer away from the substrate, and the second support column is provided on a surface of the passivation layer away from the substrate;

[0019] Wherein, in a top view of the array substrate, the first supporting pillars cover the semiconductor layer, and the second supporting pillars overlap with the scanning lines.

[0020] Furthermore, the top surface of the second support column is higher than the bottom surface of the first support column, and the top surface of the second support column is lower than the top surface of the first support column.

[0021] Furthermore, the first transparent electrode layer further includes a second auxiliary electrode, which is provided in the same layer as the common electrode, wherein the gate is located on a surface of the second auxiliary electrode away from the substrate.

[0022] Furthermore, the array substrate further includes a non-display area, the non-display area is located outside the display area, the non-display area includes a GOA area, and the GOA area of ​​the array substrate includes:

[0023] a first signal line, the first signal line being in the same layer as the common electrode;

[0024] a second signal line, the second signal line being located on a surface of the first signal line away from the substrate, and the second signal line being in the same layer as the gate;

[0025] a third signal line, the third signal line being located on a surface of the gate insulating layer away from the substrate, and the third signal line being in the same layer as the pixel electrode;

[0026] a fourth signal line, the fourth signal line being located on a surface of the third signal line away from the substrate, and the fourth signal line being in the same layer as the source and the drain;

[0027] The gate insulating layer is provided with a first via hole, and the third signal line is electrically connected to the second signal line through the first via hole.

[0028] In a second aspect, an embodiment of the present application provides a display panel, which includes the array substrate.

[0029] Beneficial effects of this application:

[0030] The present application provides an array substrate and a display panel, wherein a first transparent electrode layer is provided on the substrate, the first transparent electrode layer includes a common electrode, and a first metal layer is provided on a surface of the first transparent electrode layer away from the substrate, the first metal layer includes a gate, the semiconductor layer is provided on a surface of the gate insulating layer away from the substrate, the second transparent electrode layer is provided on a surface of the gate insulating layer away from the substrate, the second transparent electrode layer includes a pixel electrode, and the second metal layer is provided on a surface of the second transparent electrode layer away from the substrate, the second metal layer includes a source electrode and a drain electrode. When preparing the array substrate, the common electrode and the gate can be prepared using a common photomask, and the pixel electrode, the source electrode, and the drain can be prepared using a common photomask. There is no need to use separate photomasks to prepare the gate and the common electrode, nor is there a need to use separate photomasks to prepare the pixel electrode, the source electrode, and the drain. This saves the number of photomasks used in preparing the array substrate and reduces the production cost of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a top view of the array substrate of the present application;

[0032] Figure 2 yes Figure 1 A schematic diagram of the AA′ position of the first array substrate is shown;

[0033] Figure 3 yes Figure 1 The AA of the second array substrate shown ′ Schematic diagram of the location;

[0034] Figure 4a-4g is a flow chart of a preparation process of the array substrate of the present application.

[0035] 10 - array substrate; 100 - substrate; 200 - first transparent electrode layer, 210 - common electrode, 220 - second auxiliary electrode; 300 - first metal layer, 310 - gate, 320 - fourth auxiliary electrode; 400 - gate insulating layer, 410 - first via hole; 500 - semiconductor layer; 600 - second transparent electrode layer, 610 - pixel electrode, 620 - first auxiliary electrode, 621 - first horizontal part, 622 - vertical part, 623 - second horizontal part, 630 - third auxiliary electrode; 700 - second metal layer, 710 - source, 720 - drain; 800 - passivation layer, 810 - first horizontal passivation part, 820 - vertical passivation part, 830 - second horizontal passivation part, 840 - second via hole; 900 - spacer layer, 910 - first support column, 920 - second support column; 1000 - first signal line; 1100 - second signal line; 1200 - third signal line; 1300 - fourth signal line. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in combination with the accompanying drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the ideas of the present application, and should not be regarded as limiting the protection scope of the present application.

[0037] In addition, the terms "first", "second" and similar words do not represent any order, number or importance, but are only used to distinguish different technical features. The term "a plurality of" and similar words represent two or more, unless otherwise explicitly limited.

[0038] The first embodiment of the present application provides an array substrate 10, referring to Figure 1-Figure 3 The array substrate 10 includes a display area AA, and the display area AA of the array substrate 10 includes a substrate 100, a first transparent electrode layer 200, a first metal layer 300, a gate insulating layer 400, a semiconductor layer 500, a second transparent electrode layer 600 and a second metal layer 700.

[0039] Specifically, the first transparent electrode layer 200 is disposed on the substrate 100, and the first transparent electrode layer 200 includes a common electrode 210; the first metal layer 300 is disposed on a surface of the first transparent electrode layer 200 away from the substrate 100, and the first metal layer 300 includes a gate 310; the gate insulating layer 400 is disposed on the substrate 100, and the gate insulating layer 400 covers the common electrode 210 and the gate 310; the semiconductor layer 500 is disposed on a surface of the gate insulating layer 400 away from the substrate 100; the second transparent electrode layer 600 is disposed on a surface of the gate insulating layer 400 away from the substrate 100, and the second transparent electrode layer 600 includes a pixel electrode 610; the second metal layer 700 is disposed on a surface of the second transparent electrode layer 600 away from the substrate 100, and the second metal layer 700 includes a source 710 and a drain 720.

[0040] When preparing a 4-mask array substrate of a conventional solution, the pixel electrode is located on the side of the passivation layer away from the substrate, and the pixel electrode is electrically connected to the drain through a via. Therefore, the via and the pixel electrode need to use separate masks, resulting in an excessive number of masks for the array substrate. Therefore, the technical solution of the present application is to arrange the first transparent electrode layer 200 on the substrate 100, the first transparent electrode layer 200 includes a common electrode 210, and the first metal layer 300 is arranged on a surface of the first transparent electrode layer 200 away from the substrate 100, the first metal layer 300 includes a gate 310, the semiconductor layer 500 is arranged on a surface of the gate insulating layer 400 away from the substrate 100, the second transparent electrode layer 600 is arranged on a surface of the gate insulating layer 400 away from the substrate 100, the second transparent electrode layer 600 includes a pixel electrode 610, the second metal layer 300 includes a gate electrode 310, the semiconductor layer 500 is arranged on a surface of the gate insulating layer 400 away from the substrate 100, Layer 700 is provided on a surface of the second transparent electrode layer 600 away from the substrate 100. The second metal layer 700 includes a source electrode 710 and a drain electrode 720. When preparing the array substrate 10, the common electrode 210 and the gate electrode 310 can be prepared using a common photomask, and the pixel electrode 610, the source electrode 710, and the drain electrode 720 can be prepared using a common photomask. There is no need to use a photomask to prepare the gate electrode 310 and the common electrode 210 separately, nor is there a need to use a photomask to prepare the pixel electrode 610, the source electrode 710, and the drain electrode 720 separately. This can save the number of photomasks used in the preparation of the array substrate 10 and reduce the production cost of the array substrate 10.

[0041] In this embodiment, the array substrate 10 is applied to a liquid crystal display panel.

[0042] In this embodiment, reference Figure 2The pixel electrode 610 is located on a surface of the gate insulating layer 400 away from the substrate 100; the common electrode 210 is located on the substrate 100; wherein, in a top view of the array substrate 10, the pixel electrode 610 overlaps with the common electrode 210. The second transparent electrode layer 600 includes a pixel electrode 610, which is located on a surface of the gate insulating layer 400 away from the substrate 100; the first transparent electrode layer 200 includes a common electrode 210, which is located on the substrate 100; in a top view of the array substrate 10, the pixel electrode 610 overlaps with the common electrode 210, so that only one insulating layer is separated from the second transparent electrode layer 600 and the first transparent electrode layer 200. This can reduce the distance between the second transparent electrode layer 600 and the first transparent electrode layer 200, thereby increasing the storage capacitance formed by the second transparent electrode layer 600 and the first transparent electrode layer 200, ensuring that each pixel of the display panel can store more charge and maintain it for a longer time, thereby reducing the refresh frequency requirement of the display panel.

[0043] In this embodiment, reference Figure 2 The second transparent electrode layer 600 further includes a first auxiliary electrode 620 , which is located between the semiconductor layer 500 and the second metal layer 700 , and is electrically connected to the pixel electrode 610 and the drain electrode 720 . By setting the second transparent electrode layer 600 to also include a first auxiliary electrode 620, the first auxiliary electrode 620 is located between the semiconductor layer 500 and the second metal layer 700, and the first auxiliary electrode 620 is electrically connected to the pixel electrode 610 and the drain 720, so that the pixel electrode 610 can be electrically connected to the second metal layer 700 through the first auxiliary electrode 620. Compared with the conventional solution of setting the pixel electrode 610 in the second metal layer 700 away from the substrate 100, the pixel electrode 610 prepared using the same mask as the source 710 and the drain 720 of the second metal layer 700 does not need to use an additional mask to make the first via 410 to electrically connect the pixel electrode 610 and the drain 720, thereby saving the number of masks and reducing the complexity and cost of preparing the array substrate 10.

[0044] In this embodiment, the second transparent electrode layer 600 further includes a third auxiliary electrode 630 . The third auxiliary electrode 630 is located between the semiconductor layer 500 and the source electrode 710 .

[0045] In this embodiment, reference Figure 2 In the top view of the array substrate 10 , the gate 310 overlaps with the semiconductor layer 500 .

[0046] In this embodiment, the first auxiliary electrode 620 includes a first horizontal portion 621, a vertical portion 622 and a second horizontal portion 623, the first horizontal portion 621 is connected to the second horizontal portion 623 through the vertical portion 622, the second horizontal portion 623 is electrically connected to the pixel electrode 610, and the second metal layer 700 covers the first horizontal portion 621, the vertical portion 622 and the second horizontal portion 623; wherein the top surface of the second horizontal portion 623 is lower than the top surface of the first horizontal portion 621. By setting the first auxiliary electrode 620 to include a first horizontal portion 621, a vertical portion 622 and a second horizontal portion 623, the first horizontal portion 621 is connected to the second horizontal portion 623 through the vertical portion 622, and the second horizontal portion 623 is electrically connected to the pixel electrode 610, and the second metal layer 700 covers the first horizontal portion 621, the vertical portion 622 and the second horizontal portion 623; wherein the top surface of the second horizontal portion 623 is lower than the top surface of the first horizontal portion 621, which can increase the contact area between the first auxiliary electrode 620 and the pixel electrode, thereby reducing the impedance of the connection between the pixel electrode 610 and the drain, and improving the stability of the array substrate 10.

[0047] In this embodiment, reference Figure 2 and Figure 3 The display area AA of the array substrate 10 further includes a passivation layer 800. The passivation layer 800 is disposed on the side of the source electrode 710 and the drain electrode 720 away from the substrate 100, and the passivation layer 800 covers the pixel electrode 610. By configuring the display area AA of the array substrate 10 to further include the passivation layer 800, the passivation layer 800 is disposed on the side of the source electrode 710 and the drain electrode 720 away from the substrate 100, and the passivation layer 800 covers the pixel electrode 610, the passivation layer 800 can protect the pixel electrode 610 and improve the uniformity of the electric field of the array substrate 10, thereby facilitating the control of the liquid crystal of the display device corresponding to the array substrate 10. At the same time, the thickness of the pixel electrode 610 can be reduced, thereby improving the light transmittance of the corresponding display device.

[0048] In this embodiment, reference Figure 3 The passivation layer 800 includes a first horizontal passivation portion 810, a vertical passivation portion 820 and a second horizontal passivation portion 830, wherein the first horizontal passivation portion 810 is connected to the second horizontal passivation portion 830 through the vertical passivation portion 820, and the top surface of the first horizontal passivation portion 810 is higher than the top surface of the second horizontal passivation portion 830; wherein, in the top view of the array substrate 10, a portion of the first horizontal passivation portion 810 overlaps with the first auxiliary electrode 620, and a portion of the second horizontal passivation portion 830 overlaps with the pixel electrode 610.

[0049] In this embodiment, reference Figure 2 The display area AA of the array substrate 10 further includes a first support column 910. The first support column 910 is disposed on a surface of the passivation layer 800 away from the substrate 100. In a top view of the array substrate 10, the first support column 910 covers the semiconductor layer 500. The display area AA of the array substrate 10 further includes the first support column 910. The first support column 910 is disposed on a surface of the passivation layer 800 away from the substrate 100. In a top view of the array substrate 10, the first support column 910 covers the semiconductor layer 500. The provision of the first support column 910 allows the first support column 910 to support the counter substrate 100 of the display panel, thereby improving the structural stability of the display panel.

[0050] In this embodiment, reference Figure 3 The display area AA of the array substrate 10 also includes a scan line and a second support column 920. The second support column 920 is arranged on a surface of the passivation layer 800 away from the substrate 100. In the top view of the array substrate 10, the second support column overlaps with the scan line.

[0051] In this embodiment, the top surface of the second support column 920 is higher than the bottom surface of the first support column 910, and the top surface of the second support column 920 is lower than the top surface of the first support column 910. By providing the second support column 920, and setting the top surface of the second support column 920 higher than the bottom surface of the first support column 910, and the top surface of the second support column 920 lower than the top surface of the first support column 910, when the display panel corresponding to the array substrate 10 is subjected to external force and the first support column 910 is subjected to pressure, the second support column 920 can act as a buffer, thereby improving the stability of the display panel corresponding to the array substrate 10.

[0052] In this embodiment, reference Figure 2 and Figure 3The array substrate 10 further includes a non-display area BB, the non-display area BB being located at the periphery of the display area AA, the non-display area BB including a GOA area CC, the GOA area CC including a first signal line 1000, a second signal line 1100, a third signal line 1200, and a fourth signal line 1300; the first signal line 1000 and the common electrode 210 are in the same layer; the second signal line 1100 is located on a surface of the first signal line 100 away from the substrate 100, and the second signal line 1100 is connected to the gate 310. the same layer; the third signal line 1200 is located on a surface of the gate insulating layer 400 away from the substrate 100, and the third signal line 1200 is on the same layer as the pixel electrode 610; the fourth signal line 1300 is located on a surface of the third signal line 1200 away from the substrate 100, and the fourth signal line 1300 is on the same layer as the source 710 and the drain 720; wherein the gate insulating layer 400 is provided with a first via hole 410, and the third signal line 1200 is electrically connected to the second signal line through the first via hole 410. The GOA region CC is provided to include a first signal line 1000, a second signal line 1100, a third signal line 1200 and a fourth signal line 1300; the first signal line 1000 is in the same layer as the common electrode 210; the second signal line 1100 is located on a surface of the first signal line 100 away from the substrate 100, and the second signal line 1100 is in the same layer as the gate 310; the third signal line 1200 is located on a surface of the gate insulating layer 400 away from the substrate 100, and the third signal line 1200 is in the same layer as the pixel electrode 610; the fourth signal line 1300 is located on a surface of the third signal line 1200 away from the substrate 100, and the fourth signal line 1300 is in the same layer as the source 710 and the drain 720; a first via 410 is provided in the gate insulating layer 400, The third signal line 1200 is electrically connected to the second signal line through the first via 410, so that the first and second metal lines can be fabricated using a common photomask along with the common electrode 210 and the gate 310. The first via 410 can be fabricated using a common photomask along with the semiconductor layer 500. The third signal line 1200 and the fourth signal line 1300 can be fabricated using a common photomask along with the pixel electrode 610, the source electrode 710, and the drain electrode 720. Compared to conventional solutions that require an additional photomask to fabricate the first via 410 and electrically connect the fourth metal line to the third metal line through the first via 410 fabricated using an additional photomask, this solution can reduce the number of photomasks required for fabricating the array substrate 10, thereby reducing the manufacturing cost of the array substrate 10. Furthermore, since the fourth metal line is in direct contact with the third metal line and the third metal line is in direct contact with the second metal line, impedance can be reduced, thereby reducing power consumption of the array substrate 10.

[0053] In this embodiment, reference Figure 2 and Figure 3 The first transparent electrode layer 200 includes a second auxiliary electrode 220, which is arranged on the substrate 100. The second auxiliary electrode 220 is arranged on the same layer as the common electrode, wherein the gate 310 is arranged on a surface of the second auxiliary electrode 220 away from the substrate 100, and in the top view of the array substrate 10, the gate 310 overlaps with the second auxiliary electrode 220.

[0054] In this embodiment, the first metal layer 300 further includes a fourth auxiliary electrode 320, which is disposed on a surface of the first transparent electrode layer 200 away from the substrate. The array substrate further includes a common electrode line disposed on the substrate and electrically connected to the fourth auxiliary electrode 320. In a top view of the array substrate, the fourth auxiliary electrode 320 overlaps with a portion of the common electrode 210. By providing the first metal layer 300 with the fourth auxiliary electrode 320, the fourth auxiliary electrode 320 being disposed on a surface of the first transparent electrode layer 200 away from the substrate 100, and the common electrode line being electrically connected to the fourth auxiliary electrode 320, the contact resistance between the common electrode 210 and the common electrode line can be reduced, thereby improving the operational stability of the array substrate.

[0055] A second embodiment of the present application provides a display panel, which includes the array substrate.

[0056] The third embodiment of the present application also provides a method for preparing the array substrate 10, referring to Figure 4a-4g , the preparation method comprises the following steps:

[0057] S100: forming a first transparent electrode layer 200 and a first metal layer 300 in sequence on a substrate 100;

[0058] S200: etching the first transparent electrode layer 200 and the first metal layer 300 into a common electrode 210 and a gate 310 using a first photomask process;

[0059] S300: forming a gate insulating layer 400 on the substrate 100 , wherein the gate insulating layer 400 covers the gate 310 and the common electrode 210 ;

[0060] S400: forming a semiconductor layer 500 on the gate insulating layer 400, and etching the semiconductor layer 500 into a semiconductor pattern using a second photomask process;

[0061] S500: forming a second transparent electrode layer 600 and a first transparent electrode layer 200 in sequence on the semiconductor layer 500;

[0062] S600 : using a third photomask process to etch the second transparent electrode layer 600 and the first transparent electrode layer 200 into a pixel electrode 610 , a source electrode 710 and a drain electrode 720 .

[0063] The method for preparing the array substrate 10 of the technical solution of the present application uses a first photomask process to etch the first transparent electrode layer 200 and the first metal layer 300 into a common electrode 210 and a gate electrode 310, forms a semiconductor layer 500 on the gate insulating layer 400, and uses a second photomask process to etch the semiconductor layer 500 into a semiconductor pattern. Then, a third photomask process is used to etch the second transparent electrode layer 600 and the first transparent electrode layer 200 into a pixel electrode 610, a source electrode 710, and a drain electrode 720. There is no need to use a photomask to prepare the gate electrode 310 and the common electrode 210 separately, nor is there a need to use a photomask to prepare the pixel electrode 610, the source electrode 710, and the drain electrode 720 separately. This can save the number of photomasks required for preparing the array substrate 10 and reduce the production cost of the array substrate 10.

[0064] In this embodiment, the mask used in the first mask process is a semi-transparent mask, the mask used in the second mask process is a semi-transparent mask, and the mask used in the third mask process is a semi-transparent mask.

[0065] In this embodiment, the preparation method includes the following steps:

[0066] S700: Forming a passivation layer 800 on the gate insulating layer 400, and allowing the passivation layer 800 to cover the pixel electrode 610 and the second metal layer 700. By forming the passivation layer 800 on the gate insulating layer 400 and allowing the passivation layer 800 to cover the pixel electrode 610 and the second metal layer 700, the passivation layer 800 can protect the pixel electrode 610 and improve the uniformity of the electric field of the array substrate 10, thereby being more conducive to controlling the liquid crystal of the display device corresponding to the array substrate 10; at the same time, the thickness of the pixel electrode 610 can be reduced, thereby improving the light transmittance of the corresponding display device.

[0067] In this embodiment, the array substrate 10 further includes a non-display area BB, which is located outside the display area AA. The non-display area BB includes a GOA area CC. Step S200 further includes: etching a portion of the first transparent electrode layer 200 and the first metal layer 300 located in the GOA area CC into a first signal line 1000 and a second signal line 1100 using a first photomask process;

[0068] Step S400 also includes:

[0069] A first via hole 410 is etched on the gate insulating layer 400 using a second photomask process, wherein the first via hole 410 is located in the GOA region CC;

[0070] Step S600 further includes: etching the second transparent electrode layer 600 and the first transparent electrode layer 200 into a third signal line 1200 and a fourth signal line 1300 using a third photomask process.

[0071] By setting the step S200 to further include: using a first mask process to etch the first transparent electrode layer 200 and a portion of the first metal layer 300 located in the GOA area CC into a first signal line 1000 and a second signal line 1100; step S400 also includes: step S600 also includes: using a third mask process to etch the second transparent electrode layer 600 and the first transparent electrode layer 200 into a third signal line 1200 and a fourth signal line 1300; so that the first metal line and the second metal line can share a common electrode 210 and the gate 310. The first via 410 can be prepared using a common photomask with the semiconductor layer 500, and the third signal line 1200 and the fourth signal line 1300 can be prepared using a common photomask with the pixel electrode 610 and the source 710 and the drain 720. Compared with the conventional solution that requires an additional photomask to make the first via 410 and electrically connects the fourth metal wire to the third metal wire through the first via 410 made using an additional photomask, the number of photomasks prepared for the array substrate 10 can be saved, thereby reducing the production cost of the array substrate 10.

[0072] In this embodiment, the preparation method includes the following steps:

[0073] S800: forming a spacer layer 900 on the passivation layer 800;

[0074] S900 : using a fourth photomask process to form the spacer layer 900 into a first support column 910 , wherein, in a top view of the array substrate 10 , the first support column 910 covers the semiconductor layer 500 .

[0075] In this embodiment, the mask used in the fourth mask process is a semi-transparent mask.

[0076] In this embodiment, step S900 further includes:

[0077] A fourth photomask process is used to etch a second via hole 840 on the passivation layer 800 . The second via hole 840 is located in the GOA region CC. In a top view of the array substrate 10 , an edge of the via hole overlaps with the fourth signal line 1300 .

[0078] Setting step S900 also includes: etching a second via 840 on the passivation layer 800 using a fourth photomask process, wherein the second via 840 is located in the GOA region CC, and in the top view of the array substrate 10, the edge of the opening overlaps with the fourth signal line 1300; so that the first support column 910 and the second via 840 can be prepared simultaneously using one photomask, thereby saving the number of masks for preparing the array substrate 10 and reducing the production cost of the array substrate 10.

[0079] In this embodiment, step S900 further includes:

[0080] The spacer layer 900 is formed into a second support column 920 using a fourth photomask process. The second support column 920 does not overlap with the semiconductor layer 500, nor does it overlap with the second transparent electrode layer 600. The top surface of the second support column 920 is higher than the bottom surface of the first support column 910, and the top surface of the second support column 920 is lower than the top surface of the first support column 910. By providing the second support column 920, and setting the top surface of the second support column 920 higher than the bottom surface of the first support column 910, and the top surface of the second support column 920 lower than the top surface of the first support column 910, when the display panel corresponding to the array substrate 10 is subjected to external force and the first support column 910 is subjected to pressure, the second support column 920 can act as a buffer, thereby improving the stability of the display panel corresponding to the array substrate 10.

[0081] The third embodiment of the present application further provides a display panel, which includes the array substrate 10 . The display panel also includes an opposing substrate 100 . The opposing substrate 100 is disposed on the array substrate 10 .

[0082] The above describes in detail the specific embodiments of the present application. The above embodiments disclosed in this application are merely preferred embodiments of the present application. Those skilled in the art will appreciate that many variations and improvements can be made without departing from the spirit of the present application. These variations and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. An array substrate, characterized in that: The display area of ​​the array substrate includes: substrate; a first transparent electrode layer, the first transparent electrode layer being disposed on the substrate, and the first transparent electrode layer comprising a common electrode; a first metal layer, the first metal layer being disposed on a surface of the first transparent electrode layer away from the substrate, the first metal layer comprising a gate; a gate insulating layer, the gate insulating layer being disposed on the substrate and covering the common electrode and the gate; a semiconductor layer, the semiconductor layer being disposed on a surface of the gate insulating layer away from the substrate; a second transparent electrode layer, the second transparent electrode layer being disposed on a surface of the gate insulating layer away from the substrate, the second transparent electrode layer comprising a pixel electrode; a second metal layer, the second metal layer being disposed on a surface of the second transparent electrode layer away from the substrate, the second metal layer comprising a source electrode and a drain electrode; The second transparent electrode layer further includes a first auxiliary electrode, the first auxiliary electrode is located between the semiconductor layer and the second metal layer, and the first auxiliary electrode is electrically connected to the pixel electrode and the drain electrode; The display area of ​​the array substrate further includes a passivation layer, the passivation layer is provided on a side of the source electrode and the drain electrode away from the substrate, and the passivation layer covers the pixel electrode; The passivation layer includes a first horizontal passivation portion, a vertical passivation portion, and a second horizontal passivation portion, wherein the first horizontal passivation portion is connected to the second horizontal passivation portion through the vertical passivation portion, and a top surface of the first horizontal passivation portion is higher than a top surface of the second horizontal passivation portion; Wherein, in a top view of the array substrate, a portion of the first horizontal passivation portion overlaps with the first auxiliary electrode, and a portion of the second horizontal passivation portion overlaps with the pixel electrode; The display area of ​​the array substrate further includes a scan line, a first support column, and a second support column, wherein the scan line is provided on the substrate, the first support column is provided on a surface of the passivation layer away from the substrate, and the second support column is provided on a surface of the passivation layer away from the substrate; Wherein, in a top view of the array substrate, the first supporting pillars cover the semiconductor layer, and the second supporting pillars overlap with the scanning lines.

2. The array substrate according to claim 1, wherein: The first auxiliary electrode includes a first horizontal portion, a vertical portion, and a second horizontal portion, the first horizontal portion is connected to the second horizontal portion through the vertical portion, the second horizontal portion is electrically connected to the pixel electrode, and the drain electrode covers the first horizontal portion, the vertical portion, and the second horizontal portion; Wherein, the top surface of the second horizontal portion is lower than the top surface of the first horizontal portion.

3. The array substrate according to claim 1, wherein: The top surface of the second supporting column is higher than the bottom surface of the first supporting column, and the top surface of the second supporting column is lower than the top surface of the first supporting column.

4. The array substrate according to claim 1, wherein: The first transparent electrode layer further includes a second auxiliary electrode, which is disposed in the same layer as the common electrode. The gate is located on a surface of the second auxiliary electrode away from the substrate.

5. The array substrate according to claim 1, wherein: The array substrate further includes a non-display area, the non-display area being located at the periphery of the display area, the non-display area including a GOA area, and the GOA area of ​​the array substrate includes: a first signal line, the first signal line being in the same layer as the common electrode; a second signal line, the second signal line being located on a surface of the first signal line away from the substrate, and the second signal line being in the same layer as the gate; a third signal line, the third signal line being located on a surface of the gate insulating layer away from the substrate, and the third signal line being in the same layer as the pixel electrode; a fourth signal line, the fourth signal line being located on a surface of the third signal line away from the substrate, and the fourth signal line being in the same layer as the source and the drain; The gate insulating layer is provided with a first via hole, and the third signal line is electrically connected to the second signal line through the first via hole.

6. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 5.

Images