Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a first chip including a first memory cell and a second memory cell, a second chip including a third memory cell and a fourth memory cell, and a third chip including a row decoder. In a first program operation of the first memory cell, the row decoder applies a first program voltage to the first word line. In a first program operation of the second memory cell, the row decoder applies a second program voltage higher than the first program voltage to the first word line. In the first program operation of the third memory cell, the row decoder applies a third program voltage to the first word line. In the first program operation of the fourth memory cell, the row decoder applies a fourth program voltage higher than the third program voltage to the first word line.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0002] As a semiconductor storage device, a NAND flash memory is known.

[0003] Background Art Literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent No. 10811393

[0006] Patent Document 2: U.S. Patent No. 10797028

[0007] Patent Document 3: U.S. Patent No. 8584061

[0008] Patent Document 4: Japanese Patent Application Publication No. 2012-238363 Summary of the invention

[0009] [Problems to be solved by the invention]

[0010] In one embodiment of the present invention, a semiconductor memory device capable of improving processing capability is provided.

[0011] [Technical means to solve the problem]

[0012] A semiconductor memory device of an embodiment includes: a first chip including a first column including a first memory cell and a second column including a second memory cell; a second chip including a third column including a third memory cell and a fourth column including a fourth memory cell; and a third chip including a row decoder and a controller, wherein the row decoder is connected to a first word line connected to each gate of the first to fourth memory cells, and the controller is configured to perform a write operation of repeating a programming loop including a programming operation and a programming verification operation. In a first programming operation of a write operation of the first memory cell, the row decoder applies a first programming voltage to the first word line. In a first programming operation of a write operation of the second memory cell, the row decoder applies a second programming voltage higher than the first programming voltage to the first word line. In a first programming operation of a write operation of the third memory cell, the row decoder applies a third programming voltage to the first word line. In a first programming operation of a write operation of the fourth memory cell, the row decoder applies a fourth programming voltage higher than the third programming voltage to the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a block diagram showing the overall configuration of a memory system including the semiconductor memory device according to the first embodiment.

[0014] Figure 2 It is a plan view showing a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0015] Figure 3 It is a perspective view showing a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0016] Figure 4 This is a circuit diagram of a row decoder included in the semiconductor memory device according to the first embodiment.

[0017] Figure 5 It is a cross-sectional view showing the arrangement of an array chip and a circuit chip included in the semiconductor memory device according to the first embodiment.

[0018] Figure 6 It is a perspective view showing the arrangement of an array chip and a circuit chip included in the semiconductor memory device according to the first embodiment.

[0019] Figure 7 It is a cross-sectional view of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0020] Figure 8 It is along Figure 7 A cross-sectional view of the memory pillars along line II and line II-II.

[0021] Fig. 9 It is a diagram showing a threshold voltage distribution and data allocation of a TLC (Triple Level Cell) in the semiconductor memory device according to the first embodiment.

[0022] Fig.10 This is a diagram showing the relationship between the first programming mode and the second programming mode in the write operation in the semiconductor memory device according to the first embodiment.

[0023] Fig.11 This is a graph showing the relationship between the threshold voltage and the programming voltage of the memory cell transistor in the semiconductor memory device according to the first embodiment.

[0024] Fig.12 This is a timing chart showing the voltages of the respective wirings during the writing operation in the semiconductor memory device according to the first embodiment.

[0025] Fig.13 This is a command sequence for a write operation in the semiconductor memory device according to the first embodiment.

[0026] Fig.14 This is a diagram showing the structure of a memory address in the semiconductor memory device according to the first embodiment.

[0027] Fig.15 Is based on Fig.14 A diagram showing the order in which data is written to memory addresses.

[0028] Fig.16 This is a diagram showing an example of selection of an operation mode in a memory cell array included in the semiconductor memory device according to the first embodiment.

[0029] Fig.17 This is a flowchart of a write operation in the semiconductor memory device according to the first embodiment.

[0030] Fig.18 It is a plan view showing a circuit configuration of a memory cell array included in a semiconductor memory device according to a first variation of the first embodiment.

[0031] Fig.19 It is a perspective view showing a circuit configuration of a memory cell array included in a semiconductor memory device according to a first variation of the first embodiment.

[0032] Fig. 20 A diagram showing an example of selection of an operation mode in a memory cell array included in a semiconductor memory device according to a first modification of the first embodiment.

[0033] Fig.21 It is a cross-sectional view showing the arrangement of an array chip and a circuit chip included in a semiconductor memory device according to a second modification of the first embodiment.

[0034] Fig. 22 It is a perspective view showing a circuit configuration of a memory cell array included in a semiconductor memory device according to a second variation of the first embodiment.

[0035] Fig.23 A diagram showing an example of selection of an operation mode in a memory cell array included in a semiconductor memory device according to a second variation of the first embodiment.

[0036] Fig.24 A diagram showing an example of selection of an operation mode in a memory cell array included in the semiconductor memory device according to the second embodiment.

[0037] Fig.25 A diagram showing an example of selection of an operation mode in a memory cell array included in the semiconductor memory device according to the second embodiment.

[0038] Fig.26 This is a flowchart of a write operation in the semiconductor memory device according to the second embodiment.

[0039] Fig. 27A diagram showing an example of selection of an operation mode in a memory cell array included in a semiconductor memory device according to a modification of the second embodiment.

[0040] Fig.28 A diagram showing an example of selection of an operation mode in a memory cell array included in a semiconductor memory device according to a modification of the second embodiment.

[0041] Fig.29 A diagram showing an example of selection of an operation mode in a memory cell array included in a semiconductor memory device according to a modification of the third embodiment.

[0042] Fig.30 This is a flowchart of a write operation in the semiconductor memory device according to the third embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, in the following description, the same symbols are marked for the components having substantially the same function and structure. In the case where repeated description is not necessary, it is sometimes omitted. In addition, each embodiment shown below illustrates a device or method for embodying the technical idea of ​​the embodiment. The technical idea of ​​the embodiment does not specify the material, shape, structure, configuration, etc. of the constituent parts as follows. Various changes can be made to the technical idea of ​​the embodiment without departing from the scope of the invention. These embodiments or their variations are included in the invention described in the claims and their equivalents.

[0044] 1. First Implementation Method

[0045] A semiconductor memory device according to the first embodiment will be described.

[0046] 1.1 Composition

[0047] 1.1.1 Overall Structure of a Semiconductor Memory Device

[0048] First, refer to Figure 1 , an example of the overall structure of the semiconductor storage device 1 is described. Figure 1 1 is a block diagram showing the overall structure of a memory system including the semiconductor memory device 1. Figure 1 In the example of FIG. 1 , a part of the connection between each component is indicated by an arrow line, but the connection between the components is not limited to this.

[0049] like Figure 1 As shown, the memory system includes a semiconductor memory device 1 and a memory controller 2 .

[0050] The semiconductor memory device 1 is, for example, a three-dimensional stacked NAND flash memory, which includes a plurality of nonvolatile memory cell transistors three-dimensionally arranged on a semiconductor substrate.

[0051] The memory controller 2 instructs the semiconductor memory device 1 to perform a read operation, a write operation, an erase operation, etc. based on a request from a host device (not shown). In addition, the memory controller 2 manages the memory space of the semiconductor memory device 1 .

[0052] The semiconductor memory device 1 includes a plurality of external connection terminals PD. The semiconductor memory device 1 is connected to the memory controller 2 via the external connection terminals PD. In addition, the semiconductor memory device 1 is supplied with a power supply voltage from the outside via the external connection terminals PD.

[0053] The semiconductor memory device 1 is configured to be controllable by the memory controller 2. For example, the semiconductor memory device 1 transmits and receives a signal DQ and timing signals DQS and DQSn with the memory controller 2. The signal DQ is, for example, data DT, a memory address ADD, or a command CMD. The memory address ADD is information indicating the position of a memory cell transistor in the memory cell array 100. For example, the command CMD includes a command for executing a read operation, a write operation, an erase operation, etc. The timing signals DQS and DQSn are timing signals used when the data DT is input and output. The timing signal DQSn is an inversion signal of the timing signal DQS.

[0054] In addition, the semiconductor memory device 1 receives various control signals from the memory controller 2. For example, the control signals include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn.

[0055] The chip enable signal CEn is a signal for starting the semiconductor memory device 1. The instruction latch enable signal CLE is a signal indicating that the signal DQ is an instruction. The address latch enable signal ALE is a signal indicating that the signal DQ is an address. When the signal DQ is an instruction CMD or a memory address ADD, the write enable signal WEn is a signal for capturing the signal DQ. Each time the signal WEn is switched, the instruction CMD or the memory address ADD is captured into the semiconductor memory device 1. The read enable signal REn is a signal for enabling the memory controller 2 to read data from the semiconductor memory device 1. For example, when the semiconductor memory device 1 outputs data, the signals DQS and DQSn are generated based on the signal REn.

[0056] Semiconductor storage device 1 transmits ready busy signal RBn to memory controller 2. Ready busy signal RBn is a signal indicating whether semiconductor storage device 1 is in a state where it cannot receive command CMD from memory controller 2 (busy state) or can receive command CMD (ready state).

[0057] Next, the internal structure of semiconductor memory device 1 will be described.

[0058] The semiconductor memory device 1 includes a plurality of array chips 3 and a circuit chip 4. Figure 1 In the example shown, the semiconductor memory device 1 includes two array chips 3a and 3b. The number of array chips 3 is not limited to two.

[0059] The array chip 3 is a chip on which an array of nonvolatile memory cell transistors is provided.

[0060] The circuit chip 4 is a chip provided with a circuit for controlling the array chip 3. For example, the semiconductor memory device 1 has a structure in which a plurality of array chips 3 and circuit chips 4 are bonded together (hereinafter, also referred to as a "bonded structure"). In the following, when neither the array chip 3 nor the circuit chip 4 is limited, it is simply referred to as a "chip".

[0061] The semiconductor memory device 1 includes a memory cell array 100. The memory cell array 100 is a region where nonvolatile memory cell transistors are arranged three-dimensionally. The memory cell array 100 is provided in array chips 3a and 3b. Hereinafter, a portion of the memory cell array 100 provided in the array chip 3a is referred to as "memory cell array 100a". A portion of the memory cell array 100 provided in the array chip 3b is referred to as "memory cell array 100b". That is, the memory cell array 100 includes the memory cell arrays 100a and 100b.

[0062] The memory cell array 100 includes a plurality of blocks BLK. Figure 1 In the example, the memory cell array 100 includes two blocks BLK0 and BLK1. The block BLK is, for example, a collection of multiple memory cell transistors that erase data together. In the present embodiment, one block BLK is set in an area where a portion of the memory cell array 100a and a portion of the memory cell array 100b are merged. That is, the block BLK includes multiple memory cell transistors set in the memory cell array 100a and multiple memory cell transistors set in the memory cell array 100b. The multiple memory cell transistors in the block BLK are associated with rows and columns.

[0063] The block BLK includes a plurality of string units SU. The string unit SU is, for example, a collection of a plurality of NAND strings NS selected together when performing a write operation or a read operation. Figure 1In the example of , each block BLK includes four string components SU0, SU1, SU2, and SU3. For example, the memory cell array 100a (array chip 3a) includes string components SU0 and SU1 of each block BLK. The memory cell array 100b (array chip 3b) includes string components SU2 and string components SU3 of each block. In addition, the configuration of the string components SU included in the array chips 3a and 3b is arbitrary.

[0064] The string unit SU includes a plurality of NAND strings NS. The NAND string NS includes a set of a plurality of memory cell transistors connected in series.

[0065] The number of blocks BLK in the memory cell array 100 and the number of string units SU in the block BLK are arbitrary. The circuit configuration of the memory cell array 100 will be described below.

[0066] Next, the circuit chip 4 will be described. The circuit chip 4 includes a row decoder 20 , a sense amplifier 30 , an input / output circuit 40 , and a peripheral circuit unit 50 .

[0067] The row decoder 20 is a decoding circuit for the row address RA (block address BA). The row decoder 20 is connected to the input / output circuit 40, the address register 51, the row driver 55, and the memory cell array 100. The row decoder 20 selects any block BLK in the memory cell array 100 based on the decoding result of the row address RA (block address BA). The row decoder 20 applies a voltage to the row-direction wiring (the word line and the selection gate line described below) of the selected block BLK.

[0068] The sense amplifier 30 is a circuit for writing and reading data DT. The sense amplifier 30 is connected to the input / output circuit 40, the address register 51, the column driver 56, and the memory cell array 100. The sense amplifier 30 reads data DT from the memory cell array 100 during a read operation. In addition, the sense amplifier 30 supplies a voltage based on the write data DT to the memory cell array 100 during a write operation. The sense amplifier 30 can apply a voltage to a wiring in the column direction (a bit line described below).

[0069] The input / output circuit 40 is a circuit for inputting and outputting the signal DQ and various control signals. The input / output circuit 40 is connected to the memory controller 2 via the external connection terminal PD. In addition, the input / output circuit 40 is connected to the address register 51, the instruction register 52, the sequencer 53, and the sense amplifier 30.

[0070] When the input signal DQ is data DT (write data), the input-output circuit 40 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input-output circuit 40 sends the data DT to the sense amplifier 30. In addition, the input-output circuit 40 outputs the data DT (read data) to the memory controller 2 together with the timing signals DQS and DQSn.

[0071] When the input signal DQ is the memory address ADD, the input / output circuit 40 sends the memory address ADD to the address register 51. When the input signal DQ is the command CMD, the input / output circuit 40 sends the command CMD to the command register 52.

[0072] The input / output circuit 40 transmits various control signals received from the memory controller 2 to the sequencer 53 .

[0073] The input / output circuit 40 transmits the ready busy signal RBn received from the sequencer 53 to the memory controller 2 .

[0074] The peripheral circuit unit 50 controls the operation in the memory cell array 100. The peripheral circuit unit 50 includes an address register 51, a command register 52, a sequencer 53, a voltage generating circuit 54, a row driver 55, and a column driver 56.

[0075] The address register 51 is a register for temporarily storing the memory address ADD. The address register 51 is connected to the input-output circuit 40, the row driver 55, the row decoder 20, and the sense amplifier 30. The address register 51 receives the memory address ADD from the input-output circuit 40. For example, the memory address ADD includes a row address RA and a column address CA. The row address RA is an address that specifies the wiring in the row direction of the memory cell array 100. The column address CA is an address that specifies the wiring in the column direction of the memory cell array 100. For example, the row address RA includes a block address BA and a page address PA. For example, the block address BA is used to select a block BLK. Hereinafter, the selected block BLK is expressed as a "selected block BLK". In addition, the unselected block BLK is expressed as a "non-selected block BLK". The page address PA is used to select the wiring in the row direction (word line and selection gate line). The column address CA is used to select the wiring in the column direction (bit line). For example, the address register 51 sends the page address PA to the row driver 55. The address register 51 sends the block address BA to the row decoder 20. The address register 51 transmits a column address CA to the sense amplifier 30 .

[0076] The command register 52 is a register for temporarily storing the command CMD. The command register 52 is connected to the input / output circuit 40 and the sequencer 53. The command register 52 transmits the command CMD to the sequencer 53.

[0077] The sequencer 53 is a circuit that controls the overall operation of the semiconductor memory device 1. The sequencer 53 can function as a controller of the semiconductor memory device 1. For example, the sequencer 53 is connected to the input / output circuit 40, the command register 52, the voltage generating circuit 54, the row driver 55, the column driver 56, the row decoder 20, and the sense amplifier 30. For example, the sequencer 53 controls the voltage generating circuit 54, the row driver 55, the column driver 56, the row decoder 20, and the sense amplifier 30. For example, the sequencer 53 performs a write operation, a read operation, an erase operation, etc. based on the command CMD.

[0078] The voltage generating circuit 54 generates voltages for writing, reading, and erasing operations based on the control of the sequencer 53. The voltage generating circuit 54 is connected to the sequencer 53, the row driver 55, and the column driver 56. The voltage generating circuit 54 supplies voltages to the row driver 55 and the column driver 56.

[0079] The row driver 55 is a driver that supplies voltage to the row decoder 20. The row driver 55 is connected to the sequencer 53, the voltage generating circuit 54, and the row decoder 20. For example, the row driver 55 supplies voltage to the row decoder 20 based on the row address RA (page address PA).

[0080] The column driver 56 is a driver that supplies a voltage to the sense amplifier 30. The column driver 56 is connected to the sequencer 53, the voltage generating circuit 54, and the sense amplifier 30. For example, the column driver 56 supplies a voltage to the sense amplifier 30.

[0081] 1.1.2 Circuit structure of memory cell array

[0082] Next, refer to Figure 2 and Figure 3 , an example of the circuit structure of the memory cell array 100 is described. Figure 2 1 is a plan view showing the circuit configuration of the memory cell array 100 . Figure 3 is a perspective view showing the circuit configuration of the memory cell array 100. In addition, Figure 2 and Figure 3 The example of FIG. 1 shows the circuit configuration of block BLK0, but the same is true for other blocks BLK. Hereinafter, the direction in which the word lines WL in each array chip 3 extend is expressed as the X direction. The direction intersecting the X direction and in which the bit lines BL extend is expressed as the Y direction. The direction intersecting the X direction and the Y direction and in which the array chips 3a and 3b and the circuit chip 4 are stacked is expressed as the Z direction.

[0083] like Figure 2As shown, for example, the block BLK0 includes four string units SU0-SU3. More specifically, the memory cell array 100a includes string units SU0 and SU1 of the block BLK0. The memory cell array 100b includes string units SU2 and SU3 of the block BLK0.

[0084] Each string unit SU includes a plurality of NAND strings NS.

[0085] The NAND string NS includes a plurality of memory cell transistors MC and selection transistors ST1 and ST2 . Figure 2 In the example of , the NAND string NS includes 128 memory cell transistors MC0 to MC127. In addition, the number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0086] The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC can be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or a FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductor for the charge storage layer. The following describes the case where the memory cell transistor MC is a MONOS type.

[0087] The selection transistors ST1 and ST2 are used to select the string component SU during various operations. Hereinafter, the selected string component SU is referred to as "selected string component SU". In addition, the unselected string component SU is referred to as "non-selected string component SU". The number of the selection transistors ST1 and ST2 is arbitrary. It is sufficient that one or more selection transistors ST1 and ST2 are included in the NAND string NS.

[0088] The current paths of the memory cell transistors MC and the selection transistors ST1 and ST2 in each NAND string NS are connected in series. Figure 2 In the example of , from the bottom to the top of the paper, the current paths are connected in series in the order of the selection transistor ST1, the memory cell transistors MC0 to MC127, and the selection transistor ST2. That is, from the bit line BL to the source line SL, the selection transistor ST1, the memory cell transistors MC0 to MC127, and the selection transistor ST2 are connected in sequence. The drain of the selection transistor ST1 is connected to any bit line BL. The source of the selection transistor ST2 is connected to the source line SL.

[0089] The control gates of the plurality of memory cell transistors MC0 to MC127 in the block BLK are connected in common to the word lines WL0 to WL127, respectively. Each word line WL is connected in common to the memory cell transistor MC of the memory cell array 100a and the memory cell transistor MC of the memory cell array 100b. That is, the memory cell array 100a (array chip 3a) and the memory cell array 100b (array chip 3b) share the word line WL.

[0090] Figure 2 In the example, the memory cell transistor MC0 of the block BLK0 of the memory cell arrays 100a and 100b is commonly connected to the word line WL0. The other memory cell transistors MC1 to MC127 are similarly connected to the corresponding word lines WL1 to WL127. In other words, the memory cell array 100a (array chip 3a) and the memory cell array 100b (array chip 3b) share the word lines WL0 to WL127.

[0091] In each block BLK, gates of a plurality of selection transistors ST1 in the string unit SU are connected in common to one selection gate line SGD. Figure 2 In the example, the gates of the multiple selection transistors ST1 in the string component SU0 are connected in common to the selection gate line SGD0. Similarly, the gates of the multiple selection transistors ST1 in the string component SU1 are connected in common to the selection gate line SGD1. The gates of the multiple selection transistors ST1 in the string component SU2 are connected in common to the selection gate line SGD2. The gates of the multiple selection transistors ST1 in the string component SU3 are connected in common to the selection gate line SGD3.

[0092] In each block BLK, the gates of multiple selection transistors ST2 in multiple string components SU of the memory cell array 100a (array chip 3a) are connected in common to one selection gate line SGS. Similarly, the gates of multiple selection transistors ST2 in multiple string components SU of the memory cell array 100b (array chip 3b) are connected in common to one selection gate line SGS. Hereinafter, the selection gate line SGS connected to the selection transistor ST2 of the memory cell array 100a and not connected to the selection transistor ST2 of the memory cell array 100b will be expressed as "selection gate line SGSa". The selection gate line SGS connected to the selection transistor ST2 of the memory cell array 100b and not connected to the selection transistor ST2 of the memory cell array 100a will be expressed as "selection gate line SGSb". Figure 2In the example, the gates of the multiple selection transistors ST2 in the string components SU0 and SU1 are commonly connected to the selection gate line SGSa. Similarly, the gates of the multiple selection transistors ST2 in the string components SU2 and SU3 are commonly connected to the selection gate line SGSb. That is, the memory cell array 100a and the memory cell array 100b do not share the selection gate line SGS. In addition, the memory cell array 100a and the memory cell array 100b may not share the selection gate line SGS. Alternatively, the selection gate line SGS may be set for each string component SU in the same manner as the selection gate line SGD.

[0093] The word line WL and the select gate lines SGD and SGS are connected to the row decoder 20 , respectively.

[0094] The drains of the multiple selection transistors ST1 in the string component SU are respectively connected to different bit lines BL. In other words, the bit line BL is commonly connected to one NAND string NS in each string component SU of each block BLK. In other words, the memory cell array 100a and the memory cell array 100b share the bit line BL. The same column address CA is assigned to the multiple NAND strings NS connected to one bit line BL. Figure 2 In the example, each string component SU includes n+1 (n is an integer greater than 0) NAND strings NS. That is, the string component SU includes n+1 selection transistors ST1. The drains of the n+1 selection transistors ST1 in the string component SU are respectively connected to n+1 bit lines BL0 to BLn. The bit lines BL0 to BLn are respectively connected to the sense amplifier 30.

[0095] The multiple string components SU of the multiple blocks BLK of the memory cell array 100a (array chip 3a) are connected in common to one source line SL. That is, the sources of the multiple selection transistors ST2 in the memory cell array 100a are connected in common to one source line SL. Similarly, the multiple string components SU of the multiple blocks BLK of the memory cell array 100b (array chip 3b) are connected in common to one source line SL. That is, the sources of the multiple selection transistors ST2 in the memory cell array 100b are connected in common to one source line SL. Hereinafter, in the case of limiting the source line SL connected to the selection transistor ST2 of the memory cell array 100a and not connected to the selection transistor ST2 of the memory cell array 100b, it is expressed as "source line SLa". In the case of limiting the source line SL connected to the selection transistor ST2 of the memory cell array 100b and not connected to the selection transistor ST2 of the memory cell array 100a, it is expressed as "source line SLb". Furthermore, the memory cell array 100 a and the memory cell array 100 b may share the source line SL.

[0096] Hereinafter, a set of multiple memory cell transistors MC connected to one word line WL in one string unit SU is referred to as a "unit unit CU". For example, when the memory cell transistor MC stores 1 bit of data, the storage capacity of the unit unit CU is defined as "1 page of data". Based on the number of bits of data stored in the memory cell transistor MC, the unit unit CU can have a storage capacity of more than 2 pages of data.

[0097] like Figure 3 As shown, the array area (string components SU2 and SU3) of the block BLK0 of the memory cell array 100b is arranged above the array area (string components SU0 and SU1) of the block BLK0 of the memory cell array 100a. In other words, the array area of ​​the block BLK0 of the array chip 3b and the array area of ​​the block BLK0 of the array chip 3a are arranged in the Z direction. That is, the NAND string NS of the memory cell array 100a and the NAND string NS of the memory cell array 100b arranged above the NAND string NS are included in the same block BLK. Figure 3 In the example of , in each memory cell array 100a and 100b, a plurality of memory cell transistors MC arranged along the X direction and the Y direction are connected in common to one word line WL. In each memory cell array 100a and 100b, a NAND string NS arranged along the Y direction is connected in common to a bit line BL. Furthermore, a NAND string NS of the memory cell array 100a and a NAND string NS of the memory cell array 100b arranged along the Z direction are connected in common to one bit line BL.

[0098] 1.1.3 Line Decoder Circuit Configuration

[0099] Next, refer to Figure 4 The circuit configuration of the row decoder 20 will be described. Figure 4 is a circuit diagram of the row decoder 20. In the following description, when the source and drain of a transistor are not defined, either the source or drain of the transistor is referred to as “one end of the transistor”, and either the source or drain of the transistor is referred to as “the other end of the transistor”.

[0100] like Figure 4 As shown, the row decoder 20 includes a plurality of row decoder components 200 provided for each block BLK. In addition, Figure 4 The example shows the row decoder component 200 corresponding to the block BLK0, but the row decoder components 200 corresponding to other blocks BLK also have the same structure.

[0101] The row decoder element 200 includes a block decoder 201, a level shifter 202, a WL switch circuit group WLSW, a SGD switch circuit group SGDSW, and a SGS switch circuit group SGSSW.

[0102] The block decoder 201 decodes the block address BA. The block decoder 201 is connected to the level shifter 202. In addition, the block decoder 201 is connected to a plurality of switch circuits (transistor T2) of the SGD switch circuit group SGDSW via the signal line RDECn. In addition, the SGD switch circuit group SGDSW can also be connected to the level shifter 202 via the signal line RDECn. The block decoder 201 sends the decoding result (signal) of the block address BA to the level shifter 202 and the SGD switch circuit group SGDSW. When the block address BA is the address of the corresponding block BLK, the block decoder 201 sends a high ("H") level signal to the level shifter 202 and sends a low ("L") level signal to the SGD switch circuit group SGDSW. On the other hand, when the block address BA is not the address of the corresponding block BLK, the block decoder 201 sends an "L" level signal to the level shifter 202 and sends an "H" level signal to the SGD switch circuit group SGDSW.

[0103] The level shifter 202 performs level conversion on the potential of the signal received from the block decoder 201. For example, the level shifter 202 performs level conversion on the voltage (potential) of the "H" level signal received from the block decoder 201 to the voltage VRDEC. The level shifter 202 is connected to the plurality of switch circuits (transistors T3) of the WL switch circuit group WLSW, the plurality of switch circuits (transistors T1) of the SGD switch circuit group SGDSW, and the plurality of switch circuits (transistors T4) of the SGS switch circuit group SGSSW via the signal line TG.

[0104] The SGD switch circuit group SGDSW is a collection of multiple switch circuits that control the connection between the row driver 55 and the multiple selection gate lines SGD. The SGD switch circuit group SGDSW includes multiple high-voltage n-channel MOS transistors T1 and multiple high-voltage n-channel MOS transistors T2. The transistors T1 and T2 function as switch circuits that control the connection between the row driver 55 and the selection gate line SGD. The transistor T1 is controlled based on the voltage of the signal applied via the signal line TG. In addition, the transistor T2 is controlled based on the voltage of the signal applied via the signal line RDECn. Figure 4 In the example of , the SGD switch circuit group SGDSW includes transistors T1_0 to T1_3 and T2_0 to T2_3. In addition, the number and arrangement of transistors T1 and T2 are designed based on the configuration of the selection gate line SGD.

[0105] One end of the transistor T1_0 is connected to the selection gate line SGD0. The other end of the transistor T1_0 is connected to the row driver 55 via the wiring SGD0_SEL. The gate of the transistor T1_0 is connected to the signal line TG.

[0106] One end of the transistor T2_0 is connected to the selection gate line SGD0. The other end of the transistor T2_0 is connected to the row driver 55 via the wiring SGD0_USEL. The gate of the transistor T2_0 is connected to the signal line RDECn.

[0107] One end of the transistor T1_1 is connected to the selection gate line SGD1. The other end of the transistor T1_1 is connected to the row driver 55 via the wiring SGD1_SEL. The gate of the transistor T1_1 is connected to the signal line TG.

[0108] One end of the transistor T2_1 is connected to the selection gate line SGD1. The other end of the transistor T2_1 is connected to the row driver 55 via the wiring SGD1_USEL. The gate of the transistor T2_1 is connected to the signal line RDECn.

[0109] One end of the transistor T1_2 is connected to the selection gate line SGD2. The other end of the transistor T1_2 is connected to the row driver 55 via the wiring SGD2_SEL. The gate of the transistor T1_2 is connected to the signal line TG.

[0110] One end of the transistor T2_2 is connected to the selection gate line SGD2. The other end of the transistor T2_2 is connected to the row driver 55 via the wiring SGD2_USEL. The gate of the transistor T2_2 is connected to the signal line RDECn.

[0111] One end of the transistor T1_3 is connected to the selection gate line SGD3. The other end of the transistor T1_3 is connected to the row driver 55 via the wiring SGD3_SEL. The gate of the transistor T1_3 is connected to the signal line TG.

[0112] One end of the transistor T2_3 is connected to the selection gate line SGD3. The other end of the transistor T2_3 is connected to the row driver 55 via the wiring SGD3_USEL. The gate of the transistor T2_3 is connected to the signal line RDECn.

[0113] The row driver 55 applies a voltage corresponding to the selected block BLK to the wirings SGD0_SEL to SGD3_SEL, and applies a voltage corresponding to the non-selected block BLK to the wirings SGD0_USEL to SGD3_USEL.

[0114] The WL switch circuit group WLSW is a set of multiple switch circuits that control the connection between the row driver 55 and the multiple word lines WL. The WL switch circuit group WLSW includes multiple high-voltage n-channel MOS transistors T3. The transistor T3 functions as a switch circuit that controls the connection between the row driver 55 and the selection gate line SGD. The transistor T3 is controlled based on the voltage of the signal applied via the signal line TG. Figure 4In the example of , the WL switch circuit group WLSW includes transistors T3_0 to T3_127. In addition, the number and arrangement of the transistors T3 are designed based on the configuration of the word line WL.

[0115] One end of the transistor T3_0 is connected to the word line WL0. The other end of the transistor T3_0 is connected to the row driver 55 via the wiring CG0. The gate of the transistor T3_0 is connected to the signal line TG.

[0116] The transistors T3_1 to T3_127 are connected in the same manner. For example, one end of the transistor T3_1 is connected to the word line WL1. The other end of the transistor T3_1 is connected to the row driver 55 via the wiring CG1. The gate of the transistor T3_1 is connected to the signal line TG.

[0117] The row driver 55 applies a voltage corresponding to the selected block BLK to the wirings CG0 to CG127 .

[0118] The SGS switch circuit group SGSSW is a set of multiple switch circuits that control the connection between the row driver 55 and the multiple selection gate lines SGS. The SGS switch circuit group SGSSW includes multiple high-voltage n-channel MOS transistors T4. The transistor T4 functions as a switch circuit that controls the connection between the row driver 55 and the selection gate line SGS. The transistor T4 is controlled based on the voltage of the signal applied via the signal line TG. Figure 4 In the example of , the SGS switch circuit group SGSSW includes two high withstand voltage n-channel MOS transistors T4_a and T4_b. In addition, the number and arrangement of the transistors T4 are designed based on the configuration of the select gate line SGS.

[0119] One end of the transistor T4_a is connected to the selection gate line SGSa. The other end of the transistor T4_a is connected to the row driver 55 via the wiring GSGSa. The gate of the transistor T4_a is connected to the signal line TG.

[0120] One end of the transistor T4_b is connected to the selection gate line SGSb. The other end of the transistor T4_b is connected to the row driver 55 via the wiring GSGSb. The gate of the transistor T4_b is connected to the signal line TG.

[0121] The row driver 55 applies a voltage corresponding to the selected block BLK to the wirings GSGSa and GSGSb.

[0122] For example, in a write operation, a read operation, or an erase operation, when the block address BA is consistent with the corresponding block BLK0, the block decoder 201 sends a signal of "H" level to the level shifter 202, and applies a voltage of "L" level (for example, ground voltage Vss) to the signal line RDECn. Thus, the level shifter 202 applies a voltage VRDEC which is a voltage of "H" level to the signal line TG. In addition, when the block address BA is inconsistent with the corresponding block BLK0, the block decoder 201 sends a signal of "L" level to the level shifter 202, and applies a voltage of "H" level to the signal line RDECn. Thus, the level shifter 202 applies a voltage of "L" level to the signal line TG. When the voltage of "H" level is applied to the signal line TG, the transistors T1, T3, and T4 are turned on. In addition, when the voltage of "H" level is applied to the signal line RDECn, the transistor T2 is turned on. Furthermore, the “H” level voltage applied to the signal line RDECn is lower than the “H” level voltage (voltage VRDEC) applied to the signal line TG.

[0123] 1.1.4 Chip Configuration

[0124] Next, refer to Figure 5 , an example of the configuration of each chip is described. Figure 5 3 is a cross-sectional view showing the arrangement of the array chips 3a and 3b and the circuit chip 4. Figure 5 In the example of FIG. 1 , one word line WL and one bit line BL are shown respectively for simplicity of description. Also, the selection gate lines SGD and SGS and the source line SL are omitted.

[0125] Hereinafter, when the Z direction is defined, the direction from the array chip 3 toward the circuit chip 4 is expressed as a Z1 direction, and the direction opposite to the Z1 direction is expressed as a Z2 direction.

[0126] like Figure 5 As shown, the array chip 3a is attached to the circuit chip 4 in the Z2 direction. Furthermore, the array chip 3b is attached to the array chip 3a. In other words, the circuit chip 4 is attached to the surface of the array chip 3a facing the Z1 direction. Furthermore, the array chip 3b is attached to the surface of the array chip 3a facing the Z2 direction. In other words, the circuit chip 4, the array chip 3a, and the array chip 3b are stacked in order in the Z2 direction.

[0127] The row decoder 20 and the sense amplifier 30 are provided on the semiconductor substrate 400 of the circuit chip 4 .

[0128] Memory cell arrays 100a and 100b are provided in array chips 3a and 3b, respectively.

[0129] A block BLK is formed by a part of the memory cell array 100a and a part of the memory cell array 100b arranged in the Z direction. The word line WL is shared by the memory cell array 100a and the memory cell array 100b. The bit line BL is shared by the memory cell array 100a and the memory cell array 100b.

[0130] 1.1.5 Configuration of storage cell array

[0131] Next, refer to Figure 6 , an example of the configuration of the memory cell array 100 is described. Figure 6 3 is a perspective view showing the arrangement of array chips 3a and 3b and circuit chip 4. Figure 6 In the example of FIG. 1 , one word line WL, one bit line BL, and one signal line (eg, a signal line for transmitting a signal DQ) are each shown for simplicity of description. In addition, the selection gate lines SGD and SGD and the source line SL are omitted.

[0132] like Figure 6 As shown, the array chip 3a includes a memory cell array 100a, a WL connection portion 110a, a BL connection portion 120a, and a signal connection portion 130a. Similarly, the array chip 3b includes a memory cell array 100b, a WL connection portion 110b, a BL connection portion 120b, and a signal connection portion 130b.

[0133] The WL connecting portions 110 a and 110 b are regions where contact plugs, wirings, and the like are provided to connect the word lines WL and the select gate lines SGD and SGS to the row decoder 20 .

[0134] Figure 6 In the example, the WL connection portion 110a is arranged adjacent to the memory cell array 100a in the X direction. The word line WL provided in the memory cell array 100a is led out to the WL connection portion 110a. The word line WL provided in the memory cell array 100a is connected to the contact plug electrically connected to the row decoder 20 at the WL connection portion 110a. In addition, the configuration of the WL connection portion 110a is arbitrary. For example, a plurality of WL connection portions 110a may be provided. In addition, the WL connection portion 110a may also be provided within the memory cell array 100a.

[0135] Similarly, the WL connection portion 110b is arranged adjacent to the memory cell array 100b in the X direction. Furthermore, the WL connection portion 110b is arranged above the WL connection portion 110a. The word line WL provided in the memory cell array 100b is led out to the WL connection portion 110b. The word line WL provided in the memory cell array 100b is connected to the contact plug electrically connected to the row decoder 20 at the WL connection portion 110b. In addition, the configuration of the WL connection portion 110b is arbitrary. For example, a plurality of WL connection portions 110b may be provided. In addition, the WL connection portion 110b may also be provided within the memory cell array 100b.

[0136] For example, the word line WL is connected to the row decoder 20 via WL connecting portions 110a and 110b. For example, the word line WL provided in the memory cell array 100a and the word line WL provided in the memory cell array 100b are electrically connected at the WL connecting portion 110a.

[0137] The BL connecting portions 120 a and 120 b are regions where contact plugs, wirings, and the like that connect the bit lines BL and the sense amplifiers 30 are provided.

[0138] Figure 6 In the example, the BL connection portion 120a is arranged adjacent to the memory cell array 100a in the Y direction. The bit line BL provided in the memory cell array 100a is led out to the BL connection portion 120a. The bit line BL provided in the memory cell array 100a is connected to the contact plug electrically connected to the sense amplifier 30 at the BL connection portion 120a. In addition, the configuration of the BL connection portion 120a is arbitrary. For example, a plurality of BL connection portions 120a may be provided.

[0139] Similarly, the BL connection portion 120b is arranged adjacent to the memory cell array 100b in the Y direction. Furthermore, the BL connection portion 120b is arranged above the BL connection portion 120a. The bit line BL provided in the memory cell array 100b is led out to the BL connection portion 120b. The bit line BL provided in the memory cell array 100b is connected to the contact plug electrically connected to the sense amplifier 30 at the BL connection portion 120b. In addition, the configuration of the BL connection portion 120b is arbitrary. For example, a plurality of BL connection portions 120b may be provided.

[0140] The bit line BL is connected to the sense amplifier 30 via the BL connecting portions 120a and 120b. For example, the bit line BL of the memory cell array 100a and the bit line BL of the memory cell array 100b are electrically connected at the BL connecting portion 120a.

[0141] The signal connection portions 130 a and 130 b are regions where signal lines (contact plugs, wirings, etc.) are provided to connect the external connection terminals PD and the input / output circuit 40 . Figure 6In the example, the signal connection part 130a is arranged at the end of the array chip 3a in the Y direction. Similarly, the signal connection part 130b is arranged at the end of the array chip 3b in the Y direction. For example, the input-output circuit 40 and the signal connection parts 130a and 130b are arranged along the Z direction. In addition, the configuration of the signal connection parts 130a and 130b is arbitrary. For example, a plurality of signal connection parts 130a and 130b can be respectively provided.

[0142] The signal connection portion 130b is provided with an external connection terminal PD. For example, the external connection terminal PD is connected to the input / output circuit 40 via a signal line provided in the signal connection portions 130a and 130b. The signal line is not electrically connected to the memory cell arrays 100a and 100b.

[0143] The circuit chip 4 includes, for example, a WL connection portion 21 and a BL connection portion 31 .

[0144] The WL connection portion 21 is a region where contact plugs and wirings are provided to connect the row decoder 20 to the word lines WL and the select gate lines SGD and SGS. The word lines WL and the select gate lines SGD and SGS are connected to the row decoder 20 via the WL connection portion 21. The WL connection portion 21 and the WL connection portions 110a and 110b are arranged along the Z direction. In addition, the row decoder 20 is arranged adjacent to the WL connection portion 21. For example, a row decoder 20 may be arranged adjacent to the WL connection portion 21. Figure 4 The row decoder 20 illustrated includes a WL switch circuit group WLSW, a SGD switch circuit group SGDSW, and a SGS switch circuit group SGSSW.

[0145] The BL connection portion 31 is a region where contact plugs and wirings are provided to connect the sense amplifier 30 to the bit line BL. The bit line BL is connected to the sense amplifier 30 via the BL connection portion 31. The BL connection portion 31 and the BL connection portions 120a and 120b are arranged along the Z direction. In addition, the sense amplifier 30 is arranged adjacent to the BL connection portion 31.

[0146] 1.1.6 Cross-sectional structure of memory cell array

[0147] Next, refer to Figure 7 , an example of the cross-sectional structure of the memory cell array 100 is described. Figure 7 is a cross-sectional view of the memory cell array 100 .

[0148] like Figure 7 As shown, the semiconductor memory device 1 has a bonding structure in which an array chip 3a, an array chip 3b and a circuit chip 4 are bonded together. The chips are electrically connected to each other via electrodes provided on the chips.

[0149] First, the internal structure of the array chip 3a will be described.

[0150] The array chip 3a includes a memory cell array 100a and various wiring layers for connecting with other chips.

[0151] The array chip 3 a includes insulating layers 301 , 305 , 310 , and 313 , wiring layers 302 , 304 , and 308 , a semiconductor layer 303 , and conductors 306 , 307 , 309 , 311 , 312 , and 314 .

[0152] In the memory cell array 100 a , a plurality of insulating layers 301 and a plurality of wiring layers 302 are alternately stacked layer by layer. Figure 7 In the example of FIG. 1 , the selection gate line SGD, the word lines WL0 to WL127 , and the 130 wiring layers 302 functioning as the selection gate line SGS are sequentially stacked toward the Z2 direction.

[0153] The insulating layer 301 may contain silicon oxide (SiO), for example. The wiring layer 302 contains a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor. As the conductive material of the wiring layer 302, for example, a laminated structure of titanium nitride (TiN) and tungsten (W) may be used. In this case, TiN is formed in a manner covering W. In addition, the wiring layer 302 may contain a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed in a manner covering the conductive material.

[0154] For example, the plurality of wiring layers 302 are separated for each block BLK by a component SLT extending in the X direction. The component SLT includes an insulating layer 305. The insulating layer 305 may contain SiO. In addition, the component SLT may include a conductor that is electrically connected to the semiconductor layer 303 and is not electrically connected to the wiring layer 302. In this case, the insulating layer 305 is formed so as to surround the side surface of the component SLT. Moreover, the conductor is embedded in the inside of the insulating layer 305.

[0155] In the Z2 direction, a semiconductor layer 303 is provided above the wiring layer 302 that functions as a selection gate line SGS. An insulating layer 301 is provided between the wiring layer 302 and the semiconductor layer 303. The semiconductor layer 303 functions as a source line SL. In the Z2 direction, a wiring layer 304 is provided above the semiconductor layer 303. The wiring layer 304 is used as a wiring layer for electrically connecting the semiconductor layer 303 to other chips. The wiring layer 304 includes a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor. For example, the wiring layer 304 includes aluminum (Al).

[0156] A plurality of memory columns MP are provided in the memory cell array 100a. For example, the memory column MP has a substantially cylindrical shape extending in the Z direction. One memory column MP corresponds to one NAND string NS. The memory column MP penetrates (passes through) a plurality of wiring layers 302. The end of the memory column MP in the Z2 direction is connected to the semiconductor layer 303. That is, one end of the memory column MP is connected to the source line SL.

[0157] In the Z1 direction, a conductor 306 is provided on the end of the memory column MP. For example, the conductor 306 has a substantially cylindrical shape. The conductor 306 functions as a contact plug. A conductor 307 is provided on the conductor 306. For example, the conductor 307 has a substantially cylindrical shape. The conductor 307 functions as a contact plug. In the Z1 direction, a plurality of wiring layers 308 are provided above the memory column MP. The wiring layer 308 extends in the Y direction. The plurality of wiring layers 308 are arranged along the X direction. The wiring layer 308 functions as a bit line BL. The wiring layer 308 is electrically connected to any memory column MP via the conductors 306 and 307. That is, the other end of the memory column MP is connected to the bit line BL. The conductors 306 and 307 and the wiring layer 308 may contain metal materials such as W, Al, or copper (Cu).

[0158] In the Z1 direction, the conductor 309 is provided on the wiring layer 308. In other words, the wiring layer 308 (bit line BL) is connected to the conductor 309 at the BL connection portion 120a. For example, the conductor 309 has a substantially cylindrical shape. The conductor 309 functions as a contact plug. The conductor 309 may contain a metal material such as W, Al, or Cu.

[0159] In the Z1 direction, an insulating layer 310 is provided on the insulating layer 301. The insulating layer 310 may contain SiO.

[0160] A plurality of conductors 311 are provided in the same layer as the insulating layer 310. The conductors 311 function as electrodes for electrically connecting to other chips. The conductors 311 may contain Cu.

[0161] In the Z1 direction, the conductor 311 is provided on the conductor 309 .

[0162] Furthermore, a plurality of wiring layers may be provided between the conductor 311 and the wiring layer 308 .

[0163] In the Z2 direction, the conductor 312 is provided on the wiring layer 308. In other words, the wiring layer 308 (bit line BL) is connected to the conductor 312 at the BL connection portion 120a. For example, the conductor 312 has a substantially cylindrical shape. The conductor 312 functions as a contact plug. The conductor 312 may contain a metal material such as W, Al, or Cu.

[0164] In the Z2 direction, an insulating layer 313 is provided on the wiring layer 304 and the insulating layer 301. The insulating layer 313 may contain SiO.

[0165] A plurality of conductors 314 are provided in the same layer as the insulating layer 313. The conductors 314 function as electrodes for electrically connecting to other chips. The conductors 314 may contain Cu.

[0166] In the Z2 direction, the conductor 314 is provided on the conductor 312 .

[0167] Next, the internal structure of the array chip 3b will be described. The following description will focus on the differences from the array chip 3a.

[0168] In the array chip 3b, the conductors 312 and 314 described in the configuration of the array chip 3a are removed. The other configurations are the same as those of the array chip 3a. The wiring layer 308 of the array chip 3b is electrically connected to the wiring layer 308 of the array chip 3a via the conductors 309 and 311 of the array chip 3b and the conductors 312 and 314 of the array chip 3a.

[0169] Next, the circuit chip 4 will be described.

[0170] The circuit chip 4 includes a plurality of transistors Tr and various wiring layers. The plurality of transistors Tr are used for the row decoder 20 and the sense amplifier 30, and the like.

[0171] More specifically, the circuit chip 4 includes a semiconductor substrate 400 , insulating layers 401 , 402 , and 410 , a gate insulating film 403 , a gate electrode 404 , conductors 405 , 407 , 409 , and 411 , and wiring layers 406 and 408 .

[0172] An element isolation region is provided near the surface of the semiconductor substrate 400. The element isolation region electrically isolates, for example, an n-type well region and a p-type well region provided near the surface of the semiconductor substrate 400. An insulating layer 401 is embedded in the element isolation region. The insulating layer 401 may contain SiO.

[0173] An insulating layer 402 is provided over the semiconductor substrate 400. The insulating layer 402 may contain SiO.

[0174] The transistor Tr includes: a gate insulating film 403 provided on a semiconductor substrate 400, a gate electrode 404 provided on the gate insulating film 403, and a source and a drain (not shown) formed on the semiconductor substrate 400. The source and the drain are electrically connected to a wiring layer 406 via a conductor 405. The conductor 405 extends in the Z2 direction. The conductor 405 functions as a contact plug. A conductor 407 is provided on the wiring layer 406. The conductor 407 extends in the Z2 direction. The conductor 407 functions as a contact plug. A wiring layer 408 is provided on the conductor 407. A conductor 409 is provided on the wiring layer 408. The conductor 409 extends in the Z2 direction. The conductor 409 functions as a contact plug. The wiring layers 406 and 408 include conductive materials. The conductors 405, 407, and 409, and the wiring layers 406 and 408 may include a metal material, a p-type semiconductor, or an n-type semiconductor. The number of wiring layers provided in the circuit chip 4 is arbitrary.

[0175] In the Z2 direction, an insulating layer 410 is provided on the insulating layer 402. The insulating layer 410 may contain SiO.

[0176] A plurality of conductors 411 are provided in the same layer as the insulating layer 410. The conductors 411 function as electrodes for electrically connecting to other chips. For example, one conductor 411 is provided on one conductor 409. The conductor 411 may contain Cu. The conductor 411 of the circuit chip 4 is in contact with (electrically connected to) the conductor 311 of the array chip 3a.

[0177] Next, the internal structure of the memory column MP will be described.

[0178] The memory pillar MP includes a blocking insulating film 320 , a charge storage layer 321 , a tunnel insulating film 322 , a semiconductor layer 323 , a core layer 324 , and a cap layer 325 .

[0179] More specifically, a memory hole MH is provided that penetrates (passes through) a plurality of wiring layers 302. The memory hole MH corresponds to the memory pillar MP. The end of the memory hole MH in the Z2 direction reaches the semiconductor layer 303. On the side of the memory hole MH, a blocking insulating film 320, a charge accumulation layer 321, and a tunnel insulating film 322 are stacked in order from the outside. For example, when the memory hole MH is cylindrical, the blocking insulating film 320, the charge accumulation layer 321, and the tunnel insulating film 322 each have a cylindrical shape. The semiconductor layer 323 is provided in contact with the side of the tunnel insulating film 322. The end of the semiconductor layer 323 in the Z2 direction is in contact with the semiconductor layer 303. The semiconductor layer 323 is a region where the channels of the memory cell transistor MC and the selection transistors ST1 and ST2 are formed. Therefore, the semiconductor layer 323 functions as a signal line that connects the current path of the selection transistor ST2, the memory cell transistors MC0 to MC127, and the selection transistor ST1. That is, the memory pillar MP includes a semiconductor layer 323 extending in the Z direction through the interior of the plurality of wiring layers 302. The core layer 324 is embedded in the interior of the semiconductor layer 323. On the ends of the semiconductor layer 323 and the core layer 324 in the Z1 direction, a cap layer 325 is provided whose side surface is in contact with the tunnel insulating film 322.

[0180] The blocking insulating film 320, the tunnel insulating film 322, and the core layer 324 may contain SiO. The charge storage layer 321 may contain silicon nitride (SiN). The semiconductor layer 323 and the cap layer 325 may contain, for example, polysilicon.

[0181] The memory column MP is combined with the wiring layer 302 that functions as the word lines WL0 to WL127, respectively, to form the memory cell transistors MC0 to MC127. Similarly, the memory column MP is combined with the wiring layer 302 that functions as the selection gate line SGD to form the selection transistor ST1. The memory column MP is combined with the wiring layer 302 that functions as the selection gate line SGS to form the selection transistor ST2. In other words, the memory column MP has the memory cell transistor MC and the selection transistors ST1 and ST2.

[0182] Reference Figure 8 , an example of the cross-sectional structure of the memory pillar MP along the XY plane will be described. Figure 8 is along Figure 7 More specifically, Figure 8 The cross-sectional structure of the memory pillar MP in the layer including the wiring layer 302 functioning as the word line WL127 and the cross-sectional structure of the memory pillar MP in the layer including the wiring layer 302 functioning as the word line WL0 are shown.

[0183] like Figure 8 As shown, the core layer 324 is provided, for example, in the center of the memory pillar MP. The semiconductor layer 323 surrounds the side of the core layer 324. The tunnel insulating film 322 surrounds the side of the semiconductor layer 323. The charge storage layer 321 surrounds the side of the tunnel insulating film 322. The blocking insulating film 320 surrounds the side of the charge storage layer 321. The wiring layer 302 surrounds the side of the blocking insulating film 320.

[0184] For example, in the manufacturing step of the array chip 3a, the memory hole MH is processed from the bit line BL side toward the source line SL side. In other words, when forming the memory hole MH, the laminate including multiple wiring layers 302 and multiple insulating layers 301 is processed toward the semiconductor layer 303. At this time, depending on the processing characteristics of dry etching, the memory hole MH sometimes becomes an inclined shape. That is, the diameter of the memory hole MH (memory column MP) becomes smaller toward the source line SL (Z2 direction). In other words, the cell size (diameter) of the memory cell transistor MC becomes smaller from the bit line BL side toward the source line SL side.

[0185] For example, the diameter of the memory column MP corresponding to the wiring layer 302 that functions as the word line WL127, that is, the diameter of the memory cell transistor MC127 is set to D1. The diameter of the memory column MP in the layer including the wiring layer 302 that functions as the word line WL0, that is, the diameter of the memory cell transistor MC0 is set to D2. In the case where the memory hole MH has an inclined shape, the diameter D1 and the diameter D2 are in a relationship of D1<D2. In this way, if the cell size (diameter) of the memory cell transistor MC is different for each word line WL, then in the same memory column MP, the write characteristics of the memory cell transistors MC0~MC127 will be biased.

[0186] The multiple memory columns MP in the array chip 3 are manufactured together. Therefore, the deviation of the shapes of the multiple memory columns MP in the same array chip 3 is relatively small. Therefore, the deviation of the cell size of the multiple memory cell transistors MC connected to the same word line WL in the array chip 3 is smaller than the deviation of the cell size of the memory cell transistors MC0 to MC127. In other words, the deviation of the write characteristics of the multiple string components SU (unit components CU) in the array chip 3 connected to the same word line WL is relatively small.

[0187] Array chips 3a and 3b are manufactured separately. Therefore, for example, the deviation in shape of the memory column MP of array chip 3a and the memory column MP of array chip 3b may be greater than the deviation in shape of multiple memory columns MP in the same array chip 3. That is, the deviation in write characteristics of string components SU of multiple array chips 3 may be greater than the deviation in write characteristics of multiple string components SU located in the same array chip 3. In the case where the memory hole MH is an inclined shape whose diameter becomes smaller toward the source line SL side, the deviation in shape of the memory cell transistors MC of multiple array chips 3 may be more significant in the memory cell transistors MC on the source line SL side (for example, memory cell transistor MC127).

[0188] 1.2 Threshold voltage distribution of memory cell transistors

[0189] Next, refer to Fig. 9 , an example of a threshold voltage distribution that may be adopted by the memory cell transistor MC is described. Fig. 9 It is a diagram showing the threshold voltage distribution and data allocation when the memory cell transistor MC is a TLC (Triple Level Cell) capable of storing 3 bits (8 values) of data. In addition, the number of bits of data that the memory cell transistor MC can store is arbitrary. For example, the memory cell transistor MC can be an SLC (Single Level Cell) capable of storing 1 bit (2 values) of data, an MLC (Multi Level Cell) capable of storing 2 bits (4 values) of data, a QLC (Quad Level Cell) capable of storing 4 bits (16 values) of data, or a PLC (Penta Level Cell) capable of storing 5 bits (32 values) of data.

[0190] like Fig. 9 As shown, the threshold voltage of each memory cell transistor MC adopts a discrete value included in any one of eight distributions, for example. The eight distributions are described below in order of threshold voltage from low to high as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state.

[0191] The "S0" state is, for example, equivalent to the erased state of data. Moreover, the "S1" to "S7" states are equivalent to the state in which charge is injected into the charge storage layer and data is written. In the write operation, the verification voltage corresponding to each threshold voltage distribution is set to V1 to V7. The voltages V1 to V7 are in the relationship of V1<V2<V3<V4<V5<V6<V7<Vread. The voltage Vread is the voltage applied to the unselected word line WL (hereinafter referred to as "non-selected word line WL") during the read operation. If the voltage Vread is applied to the gate, the memory cell transistor MC becomes conductive regardless of the stored data.

[0192] More specifically, the threshold voltage included in the "S0" state is less than voltage V1. The threshold voltage included in the "S1" state is greater than voltage V1 and less than voltage V2. The threshold voltage included in the "S2" state is greater than voltage V2 and less than voltage V3. The threshold voltage included in the "S3" state is greater than voltage V3 and less than voltage V4. The threshold voltage included in the "S4" state is greater than voltage V4 and less than voltage V5. The threshold voltage included in the "S5" state is greater than voltage V5 and less than voltage V6. The threshold voltage included in the "S6" state is greater than voltage V6 and less than voltage V7. Moreover, the threshold voltage included in the "S7" state is greater than voltage V7 and less than voltage Vread.

[0193] The setting value of the read voltage corresponding to each state may be the same as or different from the setting value of the verification voltage. In order to simplify the description, the following description is based on the case where the verification voltage and the read voltage are set to the same value.

[0194] Hereinafter, the read operations corresponding to the "S1" to "S7" states are respectively expressed as R1 read operation, R2 read operation, R3 read operation, R4 read operation, R5 read operation, R6 read operation, and R7 read operation. The R1 read operation determines whether the threshold voltage of the memory cell transistor MC is less than the voltage V1. The R2 read operation determines whether the threshold voltage of the memory cell transistor MC is less than the voltage V2. The R3 read operation determines whether the threshold voltage of the memory cell transistor MC is less than the voltage V3. The same is true for the following.

[0195] As described above, each memory cell transistor MC can obtain 8 states by having any one of 8 threshold voltage distributions. By assigning these states to "000" to "111" in binary representation, each memory cell transistor MC can store 3 bits of data. Below, the 3 bits of data are respectively expressed as a lower bit, a middle bit, and an upper bit. In addition, the set of lower bits that are written (or read) together in the unit component CU is expressed as a lower page. Similarly, the set of middle bits is expressed as a middle page. In addition, the set of high bits is expressed as a high page.

[0196] Fig. 9 In the example of , as shown below, “upper bit / middle bit / lower bit” are allocated to the memory cell transistors MC included in each threshold voltage distribution.

[0197] "S0" state: "111" data

[0198] "S1" state: "110" data

[0199] "S2" state: "100" data

[0200] "S3" state: "000" data

[0201] "S4" state: "010" data

[0202] "S5" state: "011" data

[0203] "S6" state: "001" data

[0204] "S7" status: "101" data

[0205] When reading the data allocated in this way, the low-order bit is determined by the R1 read action and the R5 read action. The middle-order bit is determined by the R2 read action, the R4 read action, and the R6 read action. The high-order bit is determined by the R3 read action and the R7 read action. In other words, the values ​​of the low-order bit, the middle-order bit, and the high-order bit are determined by the 2nd, 3rd, and 2nd read actions, respectively. Hereinafter, this data allocation is expressed as a "2-3-2 code". In addition, the data allocation for the "S0" to "S7" states is not limited to the 2-3-2 code.

[0206] 1.3 Write Action

[0207] Next, the programming operation is described. The programming operation includes a programming operation and a programming verification operation.

[0208] The programming action is an action of increasing the threshold voltage of the memory cell transistor MC by injecting electrons into the charge storage layer (or maintaining the threshold voltage by hardly injecting electrons into the charge storage layer). Hereinafter, the memory cell transistor MC that increases the threshold voltage will be referred to as "the memory cell transistor MC as the programming object". In addition, the memory cell transistor MC that does not increase the threshold voltage will be referred to as "the memory cell transistor MC prohibited from programming". In the programming action, each memory cell transistor MC is set as a programming object or prohibited from programming based on the write data stored in the sense amplifier 30. For example, when the write data is "0", the memory cell transistor MC is set as the programming object. In addition, when the write data is "1", the memory cell transistor MC is set to prohibit programming.

[0209] The programming verification action is an action that reads data from the memory cell transistor MC after the programming action and determines whether the threshold voltage of the memory cell transistor MC reaches the target level (write target state) as the target. The following description of the present embodiment focuses on the adjustment method of the optimal write voltage that does not cause over-programming. Therefore, regarding the pass / fail of the verification, the memory cell transistor MC that writes the fastest among the multiple string components SU that are written at the same time is considered. The result of the programming verification action is that the memory cell transistor MC whose threshold voltage has not reached the write target state is set as the memory cell transistor MC to be programmed. In addition, the memory cell transistor MC whose threshold voltage has reached the write target state is set as the memory cell transistor MC that is prohibited from programming.

[0210] In the writing operation, a combination of a programming operation and a programming verification operation is repeated (hereinafter referred to as a "programming loop"). The programming voltage applied to the word line WL selected during the programming operation (hereinafter referred to as a "selected word line WL") increases each time the programming loop is repeated. By repeating the programming loop, the threshold voltage of the memory cell transistor MC gradually increases to the target level. As described above, the writing operation of repeating the programming loop while increasing the programming voltage is also referred to as an "incremental voltage-boosting writing operation".

[0211] For example, when the memory cell transistor MC is a TLC, three pages of data (low page, middle page, and high page) can be written together through a write operation. Hereinafter, the operation of writing a plurality of pages of data corresponding to one cell unit CU together is also described as a "full sequence write operation". For example, in a full sequence write operation, by repeating a programming cycle, writing is performed sequentially starting from a state with a lower threshold voltage.

[0212] 1.3.1 Action Mode in Write Action

[0213] Next, refer to Fig.10, an example of the action mode of the write action is described. Fig.10 This is a diagram showing the relationship between the first programming mode and the second programming mode in a write operation. Fig.10 The example of is a simplified representation of the voltage value applied to the selected word line WL. In addition, the details of the voltage of each wiring in the write operation will be described below. In addition, in order to simplify the description, Fig.10 The example is limited to a write action corresponding to 1 state. Fig.10 The example is represented by a plurality of memory cell transistors MC in a string unit SU that are simultaneously being written, and shows the memory cell transistor MC with the fastest writing progress.

[0214] like Fig.10 As shown, the write operation includes a first programming mode and a second programming mode as operation modes.

[0215] The first program mode is an operation mode in which a preset voltage Vpgm1 is applied as a program voltage Vpgm to the selected word line WL in a program operation PG of the first program loop.

[0216] The second programming mode is an operation mode in which a voltage higher than the voltage Vpgm1 is applied to the selected word line WL in the programming action PG of the first programming loop. For example, in the second programming mode, as the programming voltage Vpgm in the programming action PG of the first programming loop, a voltage (Vpgm1+dV) is applied. The offset voltage dV is a positive voltage value set based on the result of the programming verification action of the first programming mode. The offset voltage dV is set to a value at which over-programming does not occur in the first programming action PG. Over-programming is a state in which the threshold voltage of the memory cell transistor MC exceeds the state of the write target.

[0217] Hereinafter, when the programming voltage Vpgm of the first programming mode is limited, it is expressed as "programming voltage Vpgmf". Similarly, when the programming voltage of the second programming mode is limited, it is expressed as "programming voltage Vpgms". In addition, when the programming action PG of the first programming mode is limited, it is expressed as "programming action PG1". Furthermore, when the first programming action PG1 of the first programming mode is limited, it is expressed as "programming action PG1_1". Similarly, when the programming action PG of the second programming mode is limited, it is expressed as "programming action PG2". Furthermore, when the first programming action PG2 of the second programming mode is limited, it is expressed as "programming action PG2_1". The same is true for the programming actions PG of the programming loops after the second time. In addition, when the programming verification action PV of the first programming mode is limited, it is expressed as "programming verification action PV1". Furthermore, when the first programming verification action PV1 of the first programming mode is limited, it is expressed as "programming verification action PV1_1". Similarly, when the program verification action PV of the second programming mode is limited, it is expressed as "program verification action PV2". Furthermore, when the first program verification action PV2 of the second programming mode is limited, it is expressed as "program verification action PV2_1". The same applies to the program verification actions PV of the second and subsequent programming loops.

[0218] Next, a specific example of the first programming mode is described. The row decoder 20 applies a voltage Vpgm1 to the selected word line WL as the programming voltage Vpgmf of the first programming loop in the programming action PG1_1. Then, the row decoder 20 applies a verification voltage Vvfy based on the target level (the state of the write object) to the selected word line WL in the programming verification action PV1_1. For example, in the case of a programming verification action PV corresponding to a write action in the "S1" state, the voltage V1 is set as the verification voltage Vvfy. In addition, the verification voltage Vvfy is based on the target level. Therefore, the verification voltage Vvfy will not be boosted based on the repetition of the programming loop. Fig.10 In the example of FIG. 1 , in each program verification action PV, a verification voltage Vvfy having the same voltage value is applied to the selected word line WL.

[0219] The row decoder 20 boosts the programming voltage Vpgmf by the voltage dVpgm each time the programming action PG is repeated. The voltage dVpgm is a boosted voltage. In addition, the voltage dVpgm may also be a different voltage value for each programming loop or action mode. For example, in the programming action PG1_2, the row decoder 20 applies the voltage Vpgm2 (= Vpgm1 + dVpgm) to the selected word line WL as the programming voltage Vpgmf for the second programming loop. The voltage Vpgm2 is a voltage obtained by adding the voltage dVpgm to the voltage Vpgm1. The row decoder 20 applies the voltage Vpgm3 (= Vpgm1 + 2dVpgm) to the selected word line WL as the programming voltage Vpgmf for the third programming loop in the programming action PG1_3. The voltage Vpgm3 is a voltage obtained by adding the voltage dVpgm to the voltage Vpgm2. The row decoder 20 applies voltage Vpgm4 (=Vpgm1+3dVpgm) to the selected word line WL as the programming voltage Vpgmf of the fourth programming loop in the programming action PG1_4. Voltage Vpgm4 is a voltage obtained by adding voltage dVpgm to voltage Vpgm3. The row decoder 20 applies voltage Vpgm5 (=Vpgm1+4dVpgm) to the selected word line WL as the programming voltage Vpgmf of the fifth programming loop in the programming action PG1_5. Voltage Vpgm5 is a voltage obtained by adding voltage dVpgm to voltage Vpgm4. The row decoder 20 applies voltage Vpgm6 (=Vpgm1+5dVpgm) to the selected word line WL as the programming voltage Vpgmf of the sixth programming loop in the programming action PG1_6. Voltage Vpgm6 is a voltage obtained by adding voltage dVpgm to voltage Vpgm5. In this way, the row decoder 20 increases the programming voltage Vpgmf by the voltage dVpgm each time the programming action PG is repeated. Fig.10 In the example of , in the first programming mode, the verification is passed in the sixth programming loop. In this case, in the programming action PG1_6, the voltage Vpgm6 (= Vpgm1 + 5dVpgm) is applied to the selected word line WL.

[0220] Next, a specific example of the second programming mode is described. Based on the result of the first programming mode, the programming voltage Vpgms (= Vpgm1 + dV) in the programming action PG2_1 is set. For example, in order to avoid over-programming of the threshold voltage of the memory cell transistor MC, the programming voltage Vpgmf in the previous programming loop of the programming loop that has passed the verification is set as the programming voltage Vpgms of the programming action PG2_1. Fig.10In the example of , in the first programming mode, the memory cell transistor MC that is written the fastest among the multiple memory cell transistors MC that are written simultaneously passes the verification in the sixth programming loop. In this case, the voltage Vpgm5 (= Vpgm1 + 4dVpgm) of the programming action PG1_5 of the previous (fifth) programming loop is set as the programming voltage Vpgms of the programming action PG2_1. That is, the voltage 4dVpgm is set as the offset voltage dV. Then, the programming action PG2_1 is performed using the voltage Vpgm5. In other words, in the second programming mode, the writing action is performed starting from the fifth programming loop of the first programming mode. As in the first programming mode, the programming voltage Vpgms is boosted by the voltage dVpgm each time the programming action is repeated. For example, the row decoder 20 applies the voltage Vpgm6 (= Vpgm1 + 5dVpgm) to the selected word line WL in the programming action PG2_2 as the programming voltage Vpgms of the second programming loop. As a result, for example, in the second programming mode, the memory cell transistor MC with faster writing passes the second programming loop verification. Thus, in the second programming mode, the number of programming loops can be reduced by four times.

[0221] In addition, the offset voltage dV can be set arbitrarily. Fig.10 In the example of , as the programming voltage Vpgms of the programming action PG2_1, the voltage Vpgm4 (= Vpgm1 + 3dVpgm) of the programming action PG1_4 of the second (fourth) programming loop may be set. That is, as the offset voltage dV, the voltage 3dVpgm may be set. In addition, as the programming voltage Vpgms of the programming action PG2_1, the intermediate voltage between the voltage Vpgm4 (= Vpgm1 + 3dVpgm) of the programming action PG1_4 and the voltage Vpgm5 (= Vpgm1 + 4dVpgm) of the programming action PG1_5 may be set. That is, as the offset voltage dV, a voltage higher than the voltage 3dVpgm and lower than the voltage 4dVpgm may be set.

[0222] For example, a write operation is performed on the string components SU0 and SU1 connected to the selection word line WL0 of the array chip 3a. The deviation of the write characteristics of the string components SU0 and SU1 is relatively small. In this case, in the write operation of the string component SU0, the first programming mode is selected. And, in the write operation of the string component SU1, the second programming mode is selected.

[0223] 1.3.2 Variation in the write characteristics of memory cell transistors

[0224] Next, refer to Fig.11 , the deviation of the writing characteristics of the memory cell transistor MC is described. Fig.11: is a graph showing the relationship between the threshold voltage of the memory cell transistor MC and the programming voltage Vpgm. Fig.11 The example of φ represents a rise in the threshold voltage of the memory cell transistor MC in the write operation corresponding to the “ S1 ” state. Fig.11 In the example, cell A, cell B, and cell C respectively represent memory cell transistors MC having different write characteristics. As described above, the current focus is on optimizing the write voltage that does not cause over-programming, so these are the characteristics of the memory cell transistors MC with the fastest write characteristics of some string components SU. For example, the deviation of the write characteristics is affected by the difference in the unit size of the memory cell transistors MC caused by the different stacking positions of the word line WL, or the difference in the wiring length (wiring resistance and RC time constant) from the memory cell transistors MC of each array chip 3 to the word line WL of the row decoder 20.

[0225] in addition, Fig.11 In the example of FIG. 1 , the white circle of cell A, the white triangle of cell B, and the white square of cell C respectively represent a state where the number of repetitions of the cycle of the write action and the erase action (hereinafter referred to as "W / E times") is relatively small (for example, the state just after shipment). The black circle of cell A represents a state where the W / E times are relatively large (for example, the state close to the upper limit of the W / E times).

[0226] First, the explanation will focus on unit A. Fig.11 As shown, as the number of W / E increases, the threshold voltage of the memory cell transistor MC increases at a lower programming voltage Vpgm. Therefore, the voltage Vpgm1 is set to a voltage value such that over-programming does not occur in the programming operation PG of the first programming loop even when the number of W / E is close to the upper limit.

[0227] For example, in the case of cell A (white circle), by applying voltage Vpgm6 to the selected word line WL, the threshold voltage rises to the "S1" state. Therefore, when the first programming mode is selected, 6 programming loops are performed. The offset voltage dV corresponding to cell A is expressed as offset voltage dVa. When the second programming mode is selected, for example, a voltage of 4dVpgm is set as the offset voltage dVa. That is, in the programming action PG2_1, a voltage Vpgm5 (= Vpgm1 + 4dVpgm) is applied as the programming voltage Vpgms. Thus, when the second programming mode is selected, the write action is terminated by 2 programming loops.

[0228] For example, in the case of cell B, by applying voltage Vpgm7 to the selected word line WL, the threshold voltage rises to the "S1" state. Therefore, when the first programming mode is selected, 7 programming loops are performed. The offset voltage dV corresponding to cell B is expressed as offset voltage dVb. When the second programming mode is selected, for example, a voltage of 5dVpgm is set as the offset voltage dVb. That is, in the programming action PG2_1, a voltage Vpgm6 (= Vpgm1 + 5dVpgm) is applied as the programming voltage Vpgms. Thus, when the second programming mode is selected, the write action is completed by 2 programming loops.

[0229] For example, in the case of cell C, by applying voltage Vpgm9 to the selected word line WL, the threshold voltage rises to the "S1" state. Therefore, when the first programming mode is selected, 9 programming loops are performed. The offset voltage dV corresponding to cell C is expressed as offset voltage dVc. When the second programming mode is selected, for example, 7dVpgm is set as the offset voltage dVc. That is, in the programming action PG2_1, voltage Vpgm8 (= Vpgm1 + 7dVpgm) is applied as the programming voltage Vpgms. Thus, when the second programming mode is selected, the write action is completed by 2 programming loops.

[0230] That is, by setting different offset voltages dV for the groups including memory cell transistors MC with different fastest write characteristics, that is, for the pages of the string unit SU, it is possible to reduce the variation in the number of programming loops when the second programming mode is selected.

[0231] 1.3.3 Voltage of each wiring during writing operation

[0232] Next, refer to Fig.12 , the voltage of each wiring during the write operation is described. Fig.12 1 is a timing chart showing the voltage of each wiring during the writing operation. Fig.12 The example represents 1 programming loop. In the following description, the selected word line WL is expressed as "selected word line WL_sel". In the case of defining a non-selected word line WL in which data has been erased among the non-selected word lines WL, it is expressed as "non-selected word line WL_unsel_e". In the case of defining a non-selected word line WL in which data has been written among the non-selected word lines WL, it is expressed as "non-selected word line WL_unsel_p".

[0233] like Fig.12 As shown, first, the program operation PG at time T0 to T8 will be described.

[0234] In the programming operation PG, the period from time T0 to time T3 is a precharge period of the channel of the selected memory cell transistor MC (hereinafter referred to as “selected memory cell transistor MC”).

[0235] At time T0, the channel of each NAND string NS in the selection block BLK is precharged to prohibit writing. More specifically, the sense amplifier 30 applies the voltage Vddsa to the bit line BL. The voltage Vddsa is a positive voltage higher than the voltage Vss. The voltage Vsrc_p is applied to the source line SL (source lines SLa and SLb). The voltage Vsrc_p is a voltage for the purpose of precharging the channel and improving the cutoff characteristics of the selection transistor ST2. The voltage Vsrc_p is a positive voltage higher than the voltage Vss. In addition, the voltage Vsrc_p can be the same voltage value as the voltage Vddsa. The row decoder 20 applies the voltage Vsgd_p to the selection gate line SGD corresponding to the selection string component SU. The voltage Vsgd_p is a voltage higher than the threshold voltage of the selection transistor ST1. The selection transistor ST1 becomes conductive. Thus, the voltage of the bit line BL above the voltage Vss is applied to the channel of the NAND string NS in the selection string component SU. The row decoder 20 applies a voltage Vsg to the selection gate line SGS and the selection gate line SGD corresponding to the non-selected string component SU. The voltage Vsg is a voltage higher than the voltage Vddsa. Thus, a higher voltage within the voltage range applied to the bit line BL or the source line SL can be applied to the channel of the NAND string NS in the non-selected string component SU from the bit line BL or the source line SL. In addition, the row decoder 20 applies a voltage Vpre1 ​​to the non-selected word line WL_unsel_p. The voltage Vpre1 ​​is a voltage higher than the threshold voltage of the written memory cell transistor MC. Thus, the memory cell transistor MC to which data has been written becomes conductive. The row decoder 20 applies a voltage Vss to the non-selected word line WL_unsel_e. The threshold voltage of the memory cell transistor MC from which data has been erased is lower than the voltage Vss. Therefore, the threshold voltage of the memory cell transistor MC from which data has been erased becomes conductive. The row decoder 20 applies a voltage Vss to the selection word line WL_sel. The selected memory cell transistor MC becomes conductive because the data has been erased. In addition, the row decoder 20 may also apply a voltage Vpre_sel to the selected word line WL_sel. The voltage Vpre_sel is a voltage higher than the voltage Vss. Through these operations, the channels of each NAND string NS in the selected block BLK are precharged from the bit line BL or the source line SL.

[0236] At time T1, the row decoder 20 applies voltage Vss to the select gate line SGS and the select gate line SGD corresponding to the non-selected string unit SU. The select transistor ST2 and the select transistor ST1 corresponding to the non-selected string unit SU are turned off. As a result, the channels of each NAND string NS in the non-selected string unit SU are in a floating state.

[0237] In this state, the sense amplifier 30 applies voltage Vss to the bit line BL corresponding to the "0" data, that is, the bit line BL corresponding to the selected memory cell transistor MC as the programming object. As a result, voltage Vss is applied to the channel corresponding to the selected memory cell transistor MC as the programming object in the selection string component SU (the channel is discharged). On the other hand, the sense amplifier 30 continues to apply voltage Vddsa to the bit line BL corresponding to the "1" data, that is, the bit line BL corresponding to the selected memory cell transistor MC prohibited from programming. Therefore, the selection transistor ST1 corresponding to the selected memory cell transistor MC prohibited from programming becomes disconnected. As a result, the channel corresponding to the selected memory cell transistor MC prohibited from programming in the selection string component SU becomes a floating state. That is to say, each channel in the non-selection string component SU and the channel corresponding to the selected memory cell transistor MC prohibited from programming in the selection string component SU become a floating state.

[0238] At time T2 , the row decoder 20 applies the voltage Vss to the unselected word line WL_unsel_p.

[0239] The time period from T3 to T7 is a period during which the address pulse is applied.

[0240] At time T3, the row decoder 20 applies voltage Vpass_e to the selected word line WL_sel and the unselected word line WL_unsel_e. Voltage Vpass_e is a voltage applied to the memory cell transistor MC in the erased state. Voltage Vpass_e is a voltage that can be set regardless of the threshold voltage of the memory cell transistor MC in the written state. In addition, the row decoder 20 applies voltage Vpass_p to the unselected word line WL_unsel_p. Voltage Vpass_p is a voltage applied to the memory cell transistor MC in the written state. Voltage Vpass_p is a voltage that turns the memory cell transistor MC into the on state regardless of the threshold voltage of the memory cell transistor MC. In addition, voltage Vpass_p is a voltage higher than voltage Vpre1. In addition, the voltage values ​​of voltages Vpass_e and Vpass_p may also be different for each word line WL. For example, the row decoder 20 applies voltage Vpass_p to a plurality of unselected word lines WL_unsel_p, respectively.

[0241] Each channel in the non-selected string component SU and the channel corresponding to the selected memory cell transistor MC in the selected string component SU that prohibits programming are all in a floating state. As the potential of the word line WL rises, the potential of these channels will rise due to coupling (hereinafter referred to as "channel boosting"). Through channel boosting, the potential difference between the word line WL and the channel is limited to a range where writing (threshold voltage rise) will not occur.

[0242] In addition, you can also Fig.12 Unlike the illustrated example, during the period from time T2 to time T4 , the row decoder 20 continues to apply the voltage Vpre1 ​​to the unselected word line WL_unsel_p without applying the voltage Vss.

[0243] At time T4, the row decoder 20 applies a programming voltage Vpgm to the selection word line WL_sel. The voltage Vpgm is a high voltage used to inject electrons into the charge accumulation layer of the selection memory cell transistor MC as the programming object. For example, in the programming action PG1_1 of the first programming mode, the voltage Vpgm1 is set as the programming voltage Vpgm. The programming voltage Vpgm is a voltage higher than the voltage Vpass_e and the voltage Vpass_p. As a result, in the selection memory cell transistor MC as the programming object, the potential difference (Vpgm-Vss) between the selection word line WL_sel and the channel becomes larger. As a result, electrons are injected into the charge accumulation layer, and the threshold voltage of the selection memory cell transistor MC rises. On the other hand, in the selection memory cell transistor MC that is prohibited from programming, due to the channel boosting, the potential difference between the selection word line WL_sel and the channel is smaller than that of the memory cell transistor MC as the programming object. As a result, electrons are hardly injected into the charge accumulation layer, and the threshold voltage of the memory cell transistor MC is maintained (the threshold voltage does not change to the extent that the state of the write target changes to a higher distribution).

[0244] At time T5, the row decoder 20 applies the voltage Vpass_e to the selected word line WL_sel. That is, the program voltage Vpgm is discharged.

[0245] During the period from time T6 to time T8, the row decoder 20 discharges the voltage applied to the selected word line WL_sel, the unselected word line WL_unsel_e, and the unselected word line WL_unsel_p. For example, the potential of the selected word line WL_sel, the unselected word line WL_unsel_e, and the unselected word line WL_unsel_p is reduced to the voltage Vp2v. The voltage Vp2v is a voltage higher than the voltage Vss.

[0246] At time T7, the row decoder 20 applies the voltage Vss to the selection gate lines SGD and SGS, and also applies the voltage Vss to the source line SL. Thus, the programming operation is completed.

[0247] Next, the program verification operation PV between times T8 and T9 will be described.

[0248] At time T8, the row decoder 20 applies the verification voltage Vvfy to the selection word line WL_sel. The sequencer 53 determines whether the verification is passed or failed based on the result of comparing the threshold voltage of the memory cell transistor MC with the verification voltage Vvfy. The row decoder 20 applies the voltage Vread to the non-selected word line WL_unsel_e and the non-selected word line WL_unsel_p. As a result, the non-selected memory cell transistor MC becomes conductive. The row decoder 20 applies the voltage Vsg to the selection gate line SGS and the selection gate line SGD corresponding to the selection string component SU. In addition, the row decoder 20 applies the voltage Vss to the selection gate line SGD corresponding to the non-selected string component SU. As a result, in the selection string component SU, the selection transistor ST1 becomes conductive. In addition, in the non-selected string component SU, the selection transistor ST1 becomes disconnected. In addition, the row decoder 20 may also temporarily apply a voltage higher than the voltage Vss to the selection gate line SGD corresponding to the non-selected string component SU immediately after time T8, and then apply the voltage Vss. Thus, the selection transistor ST1 is temporarily turned on. By turning on the selection transistor ST1 of the unselected string unit SU temporarily, the channel of the NAND string NS of the unselected string unit SU is discharged.

[0249] The sense amplifier 30 applies a voltage Vbl_r to the bit line. The voltage Vbl_r is a positive voltage higher than the voltage Vss. The voltage Vsrc_r is applied to the source line SL. The voltage Vsrc_r is a voltage higher than the voltage Vss and lower than the voltage Vbl_r. During the period from time T8 to time T9, the sense amplifier 30 reads the data of the selected memory cell transistor MC.

[0250] At time T9, the row decoder 20 applies voltage Vss to the selected word line WL_sel, the unselected word line WL_unsel_e, the unselected word line WL_unsel_p, the selected gate lines SGD and SGS. The sense amplifier 30 applies voltage Vss to the bit line BL. The voltage Vss is applied to the source line SL. Thus, the program verification operation PV is terminated.

[0251] 1.3.4 Write Action Instruction Sequence

[0252] Next, refer to Fig.13 , an example of a command sequence for a write action is described. Fig.13 is the instruction sequence for writing actions. To simplify the explanation, Fig.13The example of is shown as signal DQ and signal RBn. Signals CEn, CLE, ALE, WEn, and REn are omitted. Hereinafter, in signal DQ, instructions are represented by a circle, memory addresses are represented by a square, and data are represented by a hexagonal frame.

[0253] like Fig.13 As shown, the memory controller 2 sends a command set of a write operation to the semiconductor memory device 1. The command set of the write operation includes a command "80h", a memory address ADD, data DT, and a command "10h".

[0254] The memory controller 2 first sends a command "80h" to the semiconductor storage device 1. The command "80h" is a command to notify that a write operation is to be performed.

[0255] Next, the memory controller 2 sends a memory address ADD, data DT, and a command “10h” to the semiconductor memory device 1 . The command “10h” is a command to instruct execution of a write operation. The memory address ADD can be sent in a plurality of cycles based on the configuration of the memory cell array 100 .

[0256] When receiving the command "10h", the sequencer 53 sets the ready busy signal RBn to "L" level to execute the write operation.

[0257] When the write operation is completed, the sequencer 53 sets the ready busy signal RBn to the "H" level.

[0258] 1.3.5 Memory Address

[0259] Next, refer to Fig.14 , an example of memory address ADD is explained. Fig.14 This is a diagram showing the structure of the memory address ADD.

[0260] like Fig.14 As shown, the memory address ADD includes a block address BA, a page address PA, and a column address CA. Fig.14 In the example of , the column address CA is set on the lower address side, and the block address BA is set on the upper address side.

[0261] The column address CA is a 16-bit binary representation area of ​​address CA0 to address CA15, for example. For example, the number of bits of the column address CA is arbitrarily set based on the number of bit lines BL (data length of one page of data).

[0262] The page address PA is, for example, a 10-bit binary representation area of ​​the address RA0 to the address RA9. The number of bits of the page address PA is arbitrarily set based on the configuration of the block BLK, for example.

[0263] The block address BA is, for example, a region represented by the address RA10 to the address RAi (i is an integer greater than 10). The number of bits of the block address BA is arbitrarily set based on the number of blocks BLK, for example.

[0264] Next, the structure of the page address PA will be described in detail.

[0265] Fig.14 In the example of , the page address PA includes a string unit (SU) address, an array address, and a word line (WL) address from the lower address side. For example, the selection order of the unit unit CU in the write operation or the read operation is based on the order of the addresses of the page address PA.

[0266] The string component address is address information for selecting a string component SU, that is, selecting a gate line SGD. For example, when one array chip 3 includes four string components SU, the string component address is represented by a 2-bit address RA0 and an address RA1. In addition, the number of bits of the string component address is arbitrarily set based on the number of string components SU included in one array chip 3, for example.

[0267] The array address is address information for selecting the array chip 3. For example, when the semiconductor memory device 1 includes two array chips 3a and 3b, that is, when the memory cell array 100 includes memory cell arrays 100a and 100b, the array address is represented by a 1-bit address RA2. In addition, the number of bits of the array address is arbitrarily set based on the number of array chips 3, for example.

[0268] The word line address is address information for selecting a word line WL. When one block BLK includes 128 word lines WL, the word line address is represented by 7-bit addresses RA3 to RA9. The number of bits of the word line address is arbitrarily set based on the number of word lines WL included in one block BLK, for example.

[0269] 1.3.6 Data writing order

[0270] Next, refer to Fig.15 , an example of the order of data writing is explained. Fig.15 Is based on Fig.14 A diagram showing the order in which data is written to the memory address ADD. Fig.15 The example of schematically shows the cross-sectional structure of the string component SU in the block BLK0. One block in each string component SU represents one unit component CU corresponding to one word line WL. In other words, one block corresponds to one write operation. In addition, Fig.15 The numbers in the blocks indicate the data writing order (selection order) of the unit components CU.

[0271] like Fig.15As shown, for example, block BLK0 includes eight string units SU0 to SU7. String units SU0 to SU3 are arranged in the memory cell array 100a (array chip 3a). String units SU4 to SU7 are arranged in the memory cell array 100b (array chip 3b).

[0272] For example, first, in the state where the word line WL0 and the array chip 3a (memory cell array 100a) are selected, the string component address of the lower address is incremented. That is, the string components SU0 to SU3 of the memory cell array 100a are selected in sequence (write order "1" to "4"). Next, the array address of the upper address is incremented, and the array chip 3b (memory cell array 100b) is selected. In this state, the string component address of the lower address is incremented. That is, the string components SU4 to SU7 of the memory cell array 100b are selected in sequence (write order "5" to "7"). Next, the word line address located in the upper position of the array address is incremented. Thus, the word line WL1 is selected. Similar to the case of the word line WL0, the string components SU0 to SU3 of the memory cell array 100a (write order "9" to "12"), and the string components SU4 to SU7 of the memory cell array 100b (write order "13" to "16") are selected in sequence. Thereafter, the word line WL, the array chip 3, and the string unit SU are selected in the same manner.

[0273] 1.3.7 Specific example of action mode selection

[0274] Next, refer to Fig.16 , a specific example of action mode selection is explained. Fig.16 This is a diagram showing an example of selection of an action mode in block BLK0. Fig.16 The example shows a case where the write operation of the string units SU0 to SU7 corresponding to the selected word line WL127 is performed sequentially. Fig.16 In the example, one circle represents one unit component CU. A black circle represents a state where data is written to the unit component CU (a state where valid data is stored). A white circle represents a state where data of the unit component CU is erased (a state where no valid data is stored). A double circle represents a selected unit component CU.

[0275] like Fig.16As shown, for example, block BLK0 includes 8 string components SU0~SU7. The memory cell array 100a (array chip 3a) includes string components SU0~SU3. The memory cell array 100b (array chip 3b) includes string components SU4~SU7. Therefore, the write action of the string components SU0~SU7 corresponding to the word line WL127 starts from the string component SU0 of the array chip 3a close to the circuit chip 4. The memory cell arrays 100a and 100b share the word lines WL0~WL127. More specifically, the memory cell arrays 100a and 100b are respectively provided with 128 word lines WL0~WL127 from the bit line BL side toward the source line SL side. That is, the word lines WL0~WL127 of each array chip 3 are arranged in sequence in the direction away from the circuit chip 4. Therefore, when the word lines WL0 to WL127 are selected in sequence, the word lines WL on the side closer to the circuit chip 4 are selected in sequence in each array chip 3 .

[0276] Multiple memory columns MP in the same array chip 3 are formed together. Therefore, the deviation of the write characteristics of multiple string components SU in the same array chip 3 is relatively small. That is, the deviation of the write characteristics of the string components SU0 to SU3 of the array chip 3a is relatively small. Similarly, the deviation of the write characteristics of the string components SU4 to SU7 of the array chip 3b is relatively small. In contrast, the array chip 3a and the array chip 3b are manufactured separately. Therefore, the deviation of the write characteristics of the string components SU of multiple array chips 3 may be greater than the deviation of the write characteristics of the multiple string components SU in the same array chip 3. Therefore, in this embodiment, when the write action of multiple string components SU (unit components CU) connected to one selection word line WL is performed sequentially, the first programming mode is selected in the write action of the first selected string component SU of each array chip 3. Moreover, the second programming mode is selected in the write action of other string components SU. In other words, when the selected string component SU of the write action is the first string component SU in the array chip 3, the first programming mode is selected. Furthermore, when the selected string component SU is not the first string component SU in the array chip 3, the second programming mode is selected. Furthermore, the offset voltage dV of the second programming mode is set for each array chip 3. That is, in each array chip 3, the offset voltage dV is set based on the result of the write operation of the first string component SU that selects the first programming mode.

[0277] Fig.16 (a) shows the state where the string component SU0 of the array chip 3a is selected. The string component SU0 is the first string component SU corresponding to the selected word line WL127 in the array chip 3a. Therefore, the first programming mode is selected in the write operation of the string component SU0. In this case, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0278] Fig.16 (b) shows the state where the string component SU1 of the array chip 3a is selected. The string component SU1 is not the first string component SU corresponding to the selected word line WL127 in the array chip 3a. Therefore, the second programming mode is selected in the write operation of the string component SU1. For example, in the programming operation PG2_1 of the first programming loop, a voltage (Vpgm1+dV1) is applied to the selected word line WL127. The offset voltage dV1 is set based on the result of the write operation of the string component SU0. The same is true for the string components SU2 and SU3.

[0279] Fig.16 (c) shows the state where the string component SU4 of the array chip 3b is selected. The string component SU4 is the first string component SU corresponding to the selected word line WL127 in the array chip 3b. Therefore, the first programming mode is selected in the write operation of the string component SU4. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0280] Fig.16 (d) indicates the state in which the string component SU5 of the array chip 3b is selected. The string component SU5 is not the first string component SU in the array chip 3b corresponding to the selected word line WL127. Therefore, the second programming mode is selected in the write action of the string component SU5. For example, in the programming action PG2_1 of the first programming loop, a voltage (Vpgm1+dV2) is applied to the selected word line WL127. The offset voltage dV2 is set based on the result of the write action of the string component SU4. In addition, the offset voltage dV2 may be the same as or different from the offset voltage dV1. The same is true for the string components SU6 and SU7.

[0281] 1.3.8 Write Action Process

[0282] Next, refer to Fig.17 , an example of the process of the write action is described. Fig.17 This is a flowchart of the write operation.

[0283] like Fig.17 As shown, the sequencer 53 receives a command set for a write operation from the memory controller 2 ( S1 ).

[0284] The sequencer 53 selects the block BLK, the word line WL, the array chip 3, and the string unit SU based on the memory address ADD (S2).

[0285] The sequencer 53 confirms whether the selected string component SU is the first string component SU corresponding to the selected word line WL in the array chip 3 (S3). In other words, the sequencer 53 confirms whether the write action to be performed is the first write action corresponding to the selected word line WL in the array chip 3. More specifically, for example, when the selected string component SU is the string component SU0 or SU4, the sequencer 53 determines that it is the first string component SU. On the other hand, for example, when the selected string component SU is any one of the string components SU1 to SU3 and SU5 to SU7, the sequencer 53 determines that it is not the first string component SU.

[0286] When the selected string unit SU is the first string unit SU (S3_Yes), the sequencer 53 selects the first program mode (S4). Then, the sequencer 53 sets the voltage Vpgm1 as the program voltage Vpgmf in the program action PG1_1 of the first program loop.

[0287] On the other hand, when the selected string component SU is not the first string component SU (S3_No), the sequencer 53 selects the second programming mode (S5). Then, the sequencer 53 sets the voltage (Vpgm1+dV) as the programming voltage Vpgms in the programming operation PG2_1 of the first programming loop. For example, the sequencer 53 stores the result of the write operation of the first string component SU of the array chip 3, that is, the number of programming loops in the first programming mode. Moreover, the sequencer 53 sets the offset voltage dV based on the result of the write operation of the first string component SU of the array chip 3.

[0288] The sequencer 53 performs a program operation PG based on the set program voltage Vpgm ( S6 ).

[0289] Next, the sequencer 53 executes a program verification operation PV ( S7 ).

[0290] When verification fails (S8_No), the sequencer 53 checks whether the number of programming loops has reached a preset upper limit (S9).

[0291] When the number of programming loops reaches the upper limit (S9_Yes), the sequencer 53 ends the writing operation. The semiconductor memory device 1 has a status register for storing the status of the writing operation or the erasing operation. Thus, when the verification fails at the predetermined maximum number of loops, the failure information is stored in the status register.

[0292] If the number of program loops has not reached the upper limit (S9_No), the sequencer 53 increases the program voltage Vpgm (S10). Next, the sequencer 53 proceeds to S6 to execute the program operation PG of the next program loop.

[0293] When the verification is successful (S8_Yes), the sequencer 53 ends the writing operation. When the verification is successfully completed, the successful information is stored in the status register. The status can be confirmed by reading the status through the memory controller.

[0294] 1.4 Effects of this Implementation

[0295] According to the configuration of this embodiment, it is possible to improve the processing capability of the semiconductor memory device 1. This effect will be described in detail.

[0296] In the write operation, the threshold voltage of the memory cell transistor MC is raised to the state of the write target by repeating the programming cycle. At this time, the programming voltage in the first programming operation is set to a relatively low voltage so as not to cause over-programming. However, if the programming voltage in the first programming operation is set to a low voltage, the number of programming cycles tends to increase. In other words, the processing time of the write operation tends to increase.

[0297] In this regard, if the configuration of this embodiment is adopted, then when performing a write action, either the first programming mode or the second programming mode can be selected. In the first programming mode, the voltage Vpgm1 can be set as the programming voltage Vpgmf of the first programming action PG1_1. Moreover, in the second programming mode, the voltage (Vpgm1+dV) can be set as the programming voltage Vpgms of the first programming action PG2_1. The offset voltage dV is set based on the result of the write action in which the first programming mode is selected. The voltage (Vpgm1+dV) is a voltage higher than the voltage Vpgm1. That is, in the second programming mode, the programming loop can be started with a programming voltage higher than that of the first programming mode. Thus, when the second programming mode is selected, the number of programming loops can be reduced compared to the first programming mode. That is, the processing time of the write action can be reduced. Therefore, the processing capability of the semiconductor storage device 1 can be improved.

[0298] Furthermore, according to the configuration of this embodiment, the word lines WL can be shared by a plurality of array chips 3 stacked on the circuit chip 4. This can suppress an increase in the circuit scale of the row decoder 20. Therefore, an increase in the chip area of ​​the semiconductor memory device 1 can be suppressed.

[0299] Furthermore, if the configuration of this embodiment is adopted, then when the write operation of multiple string components SU connected to one selected word line WL is sequentially performed, the first programming mode can be applied to the write operation of the first selected string component SU of each array chip 3. Moreover, the second programming mode can be applied to the write operation of other string components SU. Therefore, even when the deviation of the write characteristics of multiple array chips 3 is relatively large, the optimal offset voltage dV can be set for each array chip 3. Thus, over-programming can be suppressed and the reliability of the write operation can be improved. Therefore, the reliability of the semiconductor storage device 1 can be improved. Furthermore, since the optimal offset voltage dV can be set for each array chip 3, the increase in the number of programming loops can be suppressed. In other words, the increase in the processing time of the write operation can be suppressed. Therefore, the processing capacity of the semiconductor storage device 1 can be improved.

[0300] 1.5 Variations

[0301] Next, two modified examples will be described with respect to the first embodiment. The following description will focus on the differences from the first embodiment.

[0302] 1.5.1 Variation 1

[0303] First, a first variation of the first embodiment will be described. In the first variation, a case where a write operation is performed sequentially from the word lines WL (memory cell transistors MC) on the source line SL side will be described.

[0304] 1.5.1.1 Circuit Configuration of Memory Cell Array

[0305] First, refer to Fig.18 and Fig.19 , an example of the circuit structure of the memory cell array 100 is described. Fig.18 1 is a plan view showing the circuit configuration of the memory cell array 100 . Fig.19 is a perspective view showing the circuit configuration of the memory cell array 100. In addition, Fig.18 and Fig.19 The example shows the circuit configuration of the block BLK0, but the same is true for other blocks BLK.

[0306] like Fig.18 and Fig.19 As shown, in this example, each current path is connected in series in the order of the selection transistor ST2, the memory cell transistors MC0 to MC127, and the selection transistor ST1. That is, the selection transistor ST2, the memory cell transistors MC0 to MC127, and the selection transistor ST1 are connected in order from the source line SL to the bit line BL. In other words, the word lines WL0 to WL127 are arranged in order from the source line SL side to the bit line BL side. The other configurations are the same as those of the first embodiment. Figure 2 and Figure 3 same.

[0307] 1.5.1.2 Specific example of action mode selection

[0308] Next, refer to Fig. 20 A specific example of the operation mode selection will be described. Fig. 20 This is a diagram showing an example of selection of an action mode in block BLK0. Fig. 20 The example of exemplifies a case where the writing operation of the string units SU0 to SU7 corresponding to the selected word line WL0 is sequentially performed.

[0309] In this example, similarly to the first embodiment, when the selected string unit SU for the write operation is the first string unit SU in the array chip 3, the first programming mode is selected. When the selected string unit SU is not the first string unit SU in the array chip 3, the second programming mode is selected.

[0310] like Fig. 20 As shown, in the memory cell arrays 100a and 100b, 128 word lines WL0 to WL127 are respectively provided from the source line SL side toward the bit line BL side. That is, the word lines WL0 to WL127 are sequentially arranged toward the circuit chip 4. In other words, the word lines WL0 to WL127 of each array chip 3 are sequentially arranged toward the circuit chip 4. Therefore, when the word lines WL0 to WL127 are sequentially selected, the word lines WL on the side farther from the circuit chip 4 are sequentially selected in each array chip 3.

[0311] Fig. 20 (a) shows the state where the string component SU0 of the array chip 3a is selected. Fig.16 Similarly to the description of (a), the first programming mode is selected in the write operation of the string unit SU0. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL0.

[0312] Fig. 20 (b) shows the state where the string component SU1 of the array chip 3a is selected. Fig.16 Similarly to the description of (b), the second programming mode is selected in the write operation of the string unit SU1. For example, in the programming operation PG2_1 of the first programming loop, the voltage (Vpgm1+dV1) is applied to the selected word line WL0. The same is true for the string units SU2 and SU3.

[0313] Fig. 20 (c) shows the state where the string component SU4 of the array chip 3b is selected. Fig.16Similarly to the description of (c), the first programming mode is selected in the write operation of the string unit SU4. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL0.

[0314] Fig. 20 (d) shows the state where the string component SU5 of the array chip 3b is selected. Fig.16 Similarly, in the writing operation of the string unit SU5, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, the voltage (Vpgm1+dV2) is applied to the selected word line WL0. The same is true for the string units SU6 and SU7.

[0315] 1.5.2 Example 2

[0316] Next, a second modification of the first embodiment will be described. In the second modification, a case where the arrangement of the array chips 3a and 3b is different from that of the first embodiment will be described.

[0317] 1.5.2.1 Chip Configuration

[0318] First, refer to Fig.21 , an example of the configuration of each chip is described. Fig.21 3 is a cross-sectional view showing the arrangement of the array chips 3a and 3b and the circuit chip 4. Fig.21 In the example of FIG. 1 , one word line WL and one bit line BL are shown respectively for simplicity of description. Also, the selection gate lines SGD and SGS and the source line SL are omitted.

[0319] like Fig.21 As shown, the array chip 3b is bonded on the circuit chip 4 toward the Z2 direction. Furthermore, the array chip 3a is bonded on the array chip 3b. In other words, the circuit chip 4 is bonded on the surface of the array chip 3b facing the Z1 direction. Furthermore, the array chip 3a is bonded on the surface of the array chip 3b facing the Z2 direction. In other words, the circuit chip 4, the array chip 3b, and the array chip 3a are stacked in this order toward the Z2 direction. Other structures are similar to those of the first embodiment. Figure 5 same.

[0320] 1.5.2.2 Circuit Structure of Memory Cell Array

[0321] Next, refer to Fig. 22 An example of the circuit configuration of the memory cell array 100 will be described. Fig. 22 is a perspective view showing the circuit configuration of the memory cell array 100. Fig. 22 The example shows the circuit configuration of the block BLK0, but the same is true for other blocks BLK.

[0322] like Fig. 22 As shown, the array area (string components SU0 and SU1) of the block BLK0 of the memory cell array 100a is arranged above the array area (string components SU2 and SU3) of the block BLK0 of the memory cell array 100b. In other words, the array area of ​​the block BLK0 of the array chip 3a and the array area of ​​the block BLK0 of the array chip 3b are arranged in the Z direction. That is, the NAND string NS of the memory cell array 100b and the NAND string NS of the memory cell array 100a arranged above the NAND string NS are included in the same block BLK. Other configurations are similar to those of the first embodiment. Figure 3 same.

[0323] 1.5.2.3 Specific example of action mode selection

[0324] Next, refer to Fig.23 , a specific example of action mode selection is explained. Fig.23 This is a diagram showing an example of selection of an action mode in block BLK0. Fig.23 The example shows a case where the write operation of the string units SU0 to SU7 corresponding to the selected word line WL127 is performed sequentially.

[0325] In this example, similarly to the first embodiment, when the selected string unit SU for the write operation is the first string unit SU in the array chip 3, the first programming mode is selected. When the selected string unit SU is not the first string unit SU in the array chip 3, the second programming mode is selected.

[0326] like Fig.23 As shown in FIG. 1 , the array chip 3b (memory cell array 100b) is arranged on the side close to the circuit chip 4, and the array chip 3a (memory cell array 100a) is arranged on the side away from the circuit chip 4. The configuration of the memory cell arrays 100a and 100b is similar to that of the first embodiment. Fig.16 In this example, the first selected one is the string assembly SU0 of the array chip 3a located on the side away from the circuit chip 4.

[0327] Fig.23 (a) shows the state where the string component SU0 of the array chip 3a is selected. Fig.16 Similarly to the description of (a), the first programming mode is selected in the write operation of the string unit SU0. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0328] Fig.23 (b) shows the state where the string component SU1 of the array chip 3a is selected. Fig.16Similarly, in the writing operation of the string unit SU1, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, the voltage (Vpgm1+dV1) is applied to the selected word line WL127. The same is true for the string units SU2 and SU3.

[0329] Fig.23 (c) shows the state where the string component SU4 of the array chip 3b is selected. Fig.16 Similarly to the description of (c), in the write operation of the string unit SU4, the first programming mode is selected. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0330] Fig.23 (d) shows the state where the string component SU5 of the array chip 3b is selected. Fig.16 Similarly, in the writing operation of the string unit SU5, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, the voltage (Vpgm1+dV2) is applied to the selected word line WL127. The same is true for the string units SU6 and SU7.

[0331] 1.5.3 Effects of Variations of the First Implementation Example

[0332] As long as the first modification and the second modification of the first embodiment are configured, the same effects as those of the first embodiment can be obtained. In addition, the first modification and the second modification may be combined.

[0333] 2. Second Implementation Method

[0334] Next, the second embodiment will be described. In the second embodiment, a method of selecting an operation mode that is different from the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0335] 2.1 Specific example of action mode selection

[0336] First, refer to Fig.24 and Fig.25 , a specific example of action mode selection is explained. Fig.24 and Fig.25 This is a diagram showing an example of selection of an action mode in block BLK0. Fig.24 The example of φ represents a case where the word line WL0 is selected. Fig.25 The example of represents a case where word line WL127 is selected.

[0337] like Fig.24 and Fig.25 As shown, the structure of block BLK0 is similar to that of the first embodiment. Fig.16 same.

[0338] In this embodiment, the method of selecting the operation mode of the write operation is different according to the word line WL. The method of selecting the operation mode includes a first selection method and a second selection method.

[0339] For example, depending on the position of the word line WL relative to the memory column MP, the size of the deviation of the shape (write characteristic) of the memory cell transistor MC of the plurality of array chips 3 is different. Based on the position of the word line WL, that is, the size of the deviation of the write characteristic of the plurality of array chips 3, either the first selection method or the second selection method is applied.

[0340] The first selection method is applied to the case where the deviation of the write characteristics is relatively small. More specifically, for example, when the selected word line WL of the write action is a word line WL configured on the side of the bit line BL, the first selection method is applied. In the first selection method, when the selected string component SU of the write action is the first string component SU of the first array chip 3 corresponding to the selected word line WL, the first programming mode is selected. Moreover, when the selected string component SU is another string component SU, the second programming mode is selected. Therefore, when the array chip 3 (hereinafter referred to as "selected array chip") including the selected string component SU is the array chip 3 selected after the second, the first programming mode is not selected. In other words, when the selected string component SU of the write action is the string component SU0, the first programming mode is selected. Moreover, when the selected string component SU is another string component SU, the second programming mode is selected. Moreover, regardless of the array chip 3, the offset voltage dV of the second programming mode is set to the same value.

[0341] The second selection method is applied to a case where the deviation of the write characteristics is relatively large. More specifically, for example, when the selected word line WL for the write action is a word line WL configured on the source line SL side, the second selection method is applied. In the second selection method, similarly to the first embodiment, when the selected string component SU for the write action is the first string component SU in the array chip 3, the first programming mode is selected. Moreover, when the selected string component SU is not the first string component SU in the array chip 3, the second programming mode is selected.

[0342] In addition, the allocation of the selection method of the action mode in each word line WL can be set arbitrarily. For example, the lower limit number of the word line WL to which the second selection method is applied is set to m (m is an integer greater than 1). It is also possible to apply the first selection method when the word line WL selected is any one of the word lines WL0 to WL(m-1), and apply the second selection method when the word line WL selected is any one of the word lines WLm to WL127. In addition, the selection method of the action mode applied may be different for each word line WL.

[0343] First, refer to Fig.24 , a specific example of the first selection method is described. In this example, the case where the selected word line WL0 (that is, the memory cell transistor MC0) is used as the selected word line WL on the bit line BL side is described. In other words, the write operation corresponding to the selected word line WL0 is described. When the selected word line WL is the word line WL0, the first selection method is applied.

[0344] Fig.24 (a) shows the state where the string component SU0 of the array chip 3a is selected. The string component SU0 is the first string component SU of the first array chip 3 corresponding to the selected word line WL0. Therefore, in the write operation of the string component SU0, the first programming mode is selected. For example, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL0.

[0345] Fig.24 (b) indicates the state in which the string component SU1 of the array chip 3a is selected. The string component SU1 is not the first string component SU (that is, the string component SU0) of the first array chip 3 corresponding to the selected word line WL0. Therefore, in the write operation of the string component SU1, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, a voltage (Vpgm1+dV3) is applied to the selected word line WL0. The offset voltage dV3 is set based on the result of the write operation of the string component SU0. The same is true for the string components SU2 and SU3.

[0346] Fig.24 (c) shows the state where the string component SU4 of the array chip 3b is selected. The string component SU4 is not the first string component SU (that is, the string component SU0) corresponding to the selected word line WL0. Therefore, in the write operation of the string component SU4, the second programming mode is selected. Similar to the string components SU1 to SU3 (the string components SU in which the second programming mode is selected in the array chip 3a), in the programming operation PG2_1 of the first programming loop, the voltage (Vpgm1+dV3) is applied to the selected word line WL0.

[0347] Fig.24(d) shows the state where the string component SU5 of the array chip 3b is selected. Similar to the string component SU4, in the write operation of the string component SU5, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, the voltage (Vpgm1+dV3) is applied to the selected word line WL0. The same is true for the string components SU6 and SU7.

[0348] Next, refer to Fig.25 , a specific example of the second selection method is described. In this example, the case where the selected word line WL127 (that is, the memory cell transistor MC127) is the selected word line WL on the source line SL side is described. In other words, the write operation corresponding to the selected word line WL127 (memory cell transistor MC127) is described. When the selected word line WL is the word line WL127, the second selection method is applied.

[0349] Fig.25 (e) indicates the state where the string component SU0 of the array chip 3a is selected. The string component SU0 is the first string component SU in the array chip 3a corresponding to the selected word line WL127. Therefore, in the write operation of the string component SU0, the first programming mode is selected. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0350] Fig.25 (f) indicates the state in which the string component SU1 of the array chip 3a is selected. The string component SU1 is not the first string component SU corresponding to the selected word line WL127 in the array chip 3a. Therefore, in the write operation of the string component SU1, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, a voltage (Vpgm1+dV4) is applied to the selected word line WL127. The offset voltage dV4 is set based on the result of the write operation of the string component SU0. The same is true for the string components SU2 and SU3.

[0351] Fig.25 (g) indicates a state where the string component SU4 of the array chip 3b is selected. The string component SU4 is the first string component SU corresponding to the selected word line WL127 in the array chip 3b. Therefore, in the write operation of the string component SU4, the first programming mode is selected. Therefore, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0352] Fig.25(h) indicates the state in which the string component SU5 of the array chip 3b is selected. The string component SU5 is not the first string component SU in the array chip 3b corresponding to the selected word line WL127. Therefore, the second programming mode is selected in the write action of the string component SU5. For example, in the programming action PG2_1 of the first programming loop, a voltage (Vpgm1+dV5) is applied to the selected word line WL127. The offset voltage dV5 is set based on the result of the write action of the string component SU4. In addition, the offset voltage dV5 may be the same as or different from the offset voltage dV4. The same is true for string components SU6 and SU7.

[0353] 2.2 Write action flow

[0354] Next, refer to Fig.26 , an example of the process of the write action is described. Fig.26 This is a flowchart of the write operation.

[0355] like Fig.26 As shown, the sequencer 53 receives a command set for a write operation from the memory controller 2 ( S1 ).

[0356] The sequencer 53 selects the block BLK, the word line WL, the array chip 3, and the string unit SU based on the memory address ADD (S2). The sequencer 53 selects either the first selection method or the second selection method based on the selected word line WL.

[0357] When the first selection method is selected (S21_Yes), the sequencer 53 checks whether the selected string unit SU is the string unit SU0 (S22). That is, the sequencer 53 checks whether the selected string unit SU is the first string unit SU of the first array chip 3 corresponding to the selected word line WL.

[0358] When the selected string unit SU is the string unit SU0 (S22_Yes), the sequencer 53 selects the first programming mode (S4). On the other hand, when the selected string unit SU is not the string unit SU0 (S22_No), the sequencer 53 selects the first programming mode (S5).

[0359] When the second selection method is selected, that is, when the first selection method is not selected ( S21_No), the sequencer 53 confirms whether the selected string unit SU is the first string unit SU corresponding to the selected word line WL in the array chip 3 ( S3 ).

[0360] When the selected string unit SU is the first string unit SU (S3_Yes), the sequencer 53 selects the first programming mode (S4). On the other hand, when the selected string unit SU is not the first string unit SU (S3_No), the sequencer 53 selects the second programming mode (S5).

[0361] The process after S6 is the same as Fig.17 same.

[0362] 2.3 Effects of this Implementation

[0363] As long as the configuration of this embodiment is adopted, the same effects as those of the first embodiment can be obtained.

[0364] Furthermore, as long as the configuration of this embodiment is adopted, when the deviation of the write characteristics of the array chip 3 is relatively small, the first programming mode can be applied to the write operation of the first string component SU of the first array chip 3, and the second programming mode can be applied to the write operation of other string components SU. Thus, the number of string components SU to which the first programming mode is applied can be suppressed. Therefore, the processing capacity of the write operation can be improved. In other words, the processing capacity of the semiconductor storage device 1 can be improved.

[0365] 2.4 Variations

[0366] Next, a variation of the second embodiment is described. In this example, similarly to the first variation of the first embodiment, a case where a write operation is sequentially performed on the word lines WL (memory cell transistors MC) on the source line SL side is described. The following description will focus on the differences from the second embodiment.

[0367] Reference Fig. 27 and Fig.28 , a specific example of action mode selection is explained. Fig. 27 and Fig.28 This is a diagram showing an example of selection of an action mode in block BLK0. Fig. 27 The example of φ represents a case where the word line WL0 is selected. Fig.28 The example of represents a case where word line WL127 is selected.

[0368] In this example, similarly to the second embodiment, the method of selecting the action mode of the write action is different depending on the word line WL. More specifically, for example, when the selected word line WL for the write action is the word line WL configured on the bit line BL side, the first selection method is applied. On the other hand, for example, when the selected word line WL for the write action is the word line WL configured on the source line SL side, the second selection method is applied.

[0369] like Fig. 27 and Fig.28 As shown, the structure of the block BLK0 is similar to that of the first variation of the first embodiment. Fig. 20In each of the memory cell arrays 100a and 100b, 128 word lines WL0 to WL127 are provided from the source line SL side toward the bit line BL side. In other words, the word lines WL0 to WL127 of each array chip 3 are arranged in order toward the circuit chip 4.

[0370] First, refer to Fig. 27 A specific example of the second selection method will be described. In this example, the word line WL0 is arranged on the source line SL side. Therefore, when the selected word line WL is the word line WL0, the second selection method is applied.

[0371] Fig. 27 The writing operation in (a) to (d) of the second embodiment is similar to that of the second embodiment. Fig.25 The writing operation in (e) to (h) is the same. When the selected string unit SU is the string unit SU0 or SU4, the first programming mode is selected. On the other hand, when the selected string unit SU is any one of the string units SU1 to SU3 or SU5 to SU7, the second programming mode is selected.

[0372] Next, refer to Fig.28 , a specific example of the first selection method is described. In this example, the word line WL127 is arranged on the side of the bit line BL. Therefore, when the selected word line WL is the word line WL127, the second selection method is applied.

[0373] Fig.28 The writing operation in (e) to (h) of the second embodiment is similar to that of the second embodiment. Fig.24 The writing operation in (a) to (d) is the same. When the selected string unit SU is the string unit SU0, the first programming mode is selected. On the other hand, when the selected string unit SU is any one of the string units SU1 to SU7, the second programming mode is selected.

[0374] 2.5 Effects of Variations of the Second Embodiment

[0375] As long as the configuration is that of the modified example of the second embodiment, the same effects as those of the second embodiment can be obtained.

[0376] 3. Third Implementation Method

[0377] Next, a third embodiment will be described. In the third embodiment, a method of setting the offset voltage dV which is different from the first and second embodiments will be described. Hereinafter, the differences from the first and second embodiments will be mainly described.

[0378] 3.1 Specific example of action mode selection

[0379] First, refer to Fig.29 , a specific example of action mode selection is explained. Fig.29 This is a diagram showing an example of selection of an action mode in block BLK0. Fig.29 The example of represents a case where word line WL127 is selected.

[0380] In this embodiment, similarly to the first selection method described in the second embodiment, when the selected string component SU of the write action is the first string component SU of the first array chip 3 corresponding to the selected word line WL, the first programming mode is selected. Furthermore, when the selected string component SU is another string component SU, the second programming mode is selected. That is, when the selected string component SU is the string component SU0, the first programming mode is selected. On the other hand, when the selected string component SU is another string component SU, the second programming mode is selected.

[0381] The offset voltage of the second programming mode is different for each array chip 3. For example, when the selected string component SU is included in the first array chip 3, the offset voltage dV is set based on the result of the write action of the first string component SU in which the first programming mode is selected, as in the first embodiment. That is, the voltage (Vpgm1+dV) is set as the programming voltage Vpgms of the programming action PG2_1. More specifically, for example, when the selected string component SU is any one of the string components SU1 to SU3 of the array chip 3a, the offset voltage dV is set. The offset voltage dV is based on the result of the write action of the string component SU0. In addition, when the selected string component SU is the first string component SU of the array chip 3 selected after the second, the voltage (dV-α) is set as the offset voltage. The correction value α is a pre-set positive voltage value smaller than the voltage dV. The voltage dV and the voltage (dV-α) are in the relationship of dV>(dV-α)>0. That is, the voltage (Vpgm1+dV-α) is set as the programming voltage Vpgms of the programming action PG2_1. The voltage Vpgm1, the voltage (Vpgm1+dV), and the voltage (Vpgm1+dV-α) are in the relationship of Vpgm1<(Vpgm1+dV-α)<(Vpgm1+dV). More specifically, for example, when the selected string component SU is the string component SU4 of the array chip 3b, the offset voltage (dV-α) is set. When the selected string component SU is included in the array chip 3 selected after the second one and is not the first string component SU, the voltage dV' is set as the offset voltage. The offset voltage dV' is based on the result of the write operation of the first string component SU of the array chip 3 selected after the second one. That is, the voltage (Vpgm1+dV') is set as the programming voltage Vpgms of the programming operation PG2_1. More specifically, for example, when the selected string component SU is any one of the string components SU5 to SU7 of the array chip 3b, the voltage dV' is set as the offset voltage. The offset voltage dV' is based on the result of the write operation of the string component SU4.

[0382] like Fig.29 As shown, the structure of block BLK0 is similar to that of the first embodiment. Fig.16 same.

[0383] Fig.29 (a) indicates a state where the string component SU0 of the array chip 3a is selected. The string component SU0 is the first string component SU of the first array chip 3 corresponding to the selected word line WL127. Therefore, the first programming mode is selected in the write operation of the string component SU0. For example, in the programming operation PG1_1 of the first programming loop, the voltage Vpgm1 is applied to the selected word line WL127.

[0384] Fig.29(b) indicates the state where the string component SU1 of the array chip 3a is selected. The string component SU1 is not the first string component SU (that is, the string component SU0) of the first array chip 3 corresponding to the selected word line WL127. Therefore, in the write operation of the string component SU1, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, a voltage (Vpgm1+dV6) is applied to the selected word line WL127. The offset voltage dV6 is set based on the result of the write operation of the string component SU0. The same is true for the string components SU2 and SU3.

[0385] Fig.29 (c) indicates the state where the string component SU4 of the array chip 3b is selected. The string component SU4 is not the first string component SU (that is, the string component SU0) corresponding to the selected word line WL127. Therefore, the second programming mode is selected in the write operation of the string component SU4. For example, in the programming operation PG2_1 of the first programming loop, a voltage (Vpgm1+dV6-α) is applied to the selected word line WL127. The offset voltage (dV6-α) is a voltage lower than the offset voltage dV.

[0386] Fig.29 (d) indicates the state in which the string component SU5 of the array chip 3b is selected. As with the string component SU4, in the write operation of the string component SU5, the second programming mode is selected. For example, in the programming operation PG2_1 of the first programming loop, a voltage (Vpgm1+dV7) is applied to the selected word line WL127. The offset voltage dV7 is set based on the result of the write operation of the string component SU4. In addition, the offset voltage dV7 may be the same as or different from the offset voltage dV6. The same is true for the string components SU6 and SU7.

[0387] 3.2 Write Action Process

[0388] Next, refer to Fig.30 , an example of the process of the write action is described. Fig.30 This is a flowchart of the write operation.

[0389] like Fig.30 As shown, the sequencer 53 receives a command set for a write operation from the memory controller 2 ( S1 ).

[0390] The sequencer 53 selects the block BLK, the word line WL, the array chip 3, and the string unit SU based on the memory address ADD (S2).

[0391] The sequencer 53 confirms whether the selected string unit SU is the string unit SU0 ( S31 ). That is, the sequencer 53 confirms whether the selected string unit SU is the first string unit SU of the first array chip 3 corresponding to the selected word line WL.

[0392] When the selected string unit SU is the string unit SU0 ( S31_Yes), the sequencer 53 selects the first program mode ( S4 ) and sets the voltage Vpgm1 as the program voltage Vpgmf in the program operation PG1_1 of the first program loop.

[0393] When the selected string unit SU is not the string unit SU0 (S31_No), the sequencer 53 selects the second programming mode (S32).

[0394] After selecting the second programming mode, the sequencer 53 checks whether the selected array chip 3 is the first array chip 3 (ie, the array chip 3 a ) ( S33 ).

[0395] In the case of the first array chip 3 (S33_Yes), the sequencer 53 sets the voltage (Vpgm1+dV) as the programming voltage Vpgms in the programming operation PG2_1 of the first programming loop (S35). Fig.29 In the example, the voltage is set to (Vpgm1+dV6).

[0396] If it is not the first array chip 3 (S33_No), the sequencer 53 confirms whether the selected string unit SU is the first string unit SU in the array chip 3 (S34). For example, the sequencer 53 confirms whether the selected string unit SU is the string unit SU4.

[0397] In the case of the first string unit SU (S34_Yes), the sequencer 53 sets the voltage (Vpgm1+dV-α) as the programming voltage Vpgms in the programming operation PG2_1 of the first programming loop (S36). Fig.29 In the example of , the voltage is set to (Vpgm1+dV6-α).

[0398] If it is not the first string unit SU (S34_No), the sequencer 53 sets the voltage (Vpgm1+dV') as the programming voltage Vpgms in the programming operation PG2_1 of the first programming loop (S37). Fig.29 In the example, the voltage (Vpgm1+dV7) is set.

[0399] The process after S6 is the same as Fig.17 same.

[0400] 3.3 Effects of this Implementation

[0401] As long as the configuration of this embodiment is adopted, the same effects as those of the first embodiment can be obtained.

[0402] Furthermore, as long as the configuration of this embodiment is adopted, the second programming mode can be selected in the write operation of the first string component SU of the array chip 3 selected after the second one. Moreover, in the array chip 3 after the second one, an offset voltage different from that of the first array chip 3 can be set. For example, the offset voltage (dV-α) of the write operation of the first string component SU of the second array chip 3 can be set lower than the offset voltage dV of the write operation of the first array chip 3. Thus, even when the deviation of the write characteristics of the array chip 3 is relatively large, over-programming can be suppressed. Therefore, the reliability of the semiconductor storage device 1 can be improved.

[0403] Furthermore, by selecting the second programming mode in the write operation of the first string component SU of the array chip 3 selected after the second one, the number of string components SU to which the first programming mode is applied can be suppressed. Therefore, the processing capacity of the write operation can be improved. In other words, the processing capacity of the semiconductor storage device 1 can be improved.

[0404] In addition, this embodiment can be combined with the first modification and the second modification of the first embodiment. In addition, this embodiment can be combined with the second embodiment and the modification of the second embodiment.

[0405] 4. Others

[0406] The semiconductor memory device of the embodiment includes: a first chip (3a) including a first column (MP) having a first memory cell (MC0) and a second column (MP) having a second memory cell (MC0); a second chip (3b) including a third column (MP) having a third memory cell (MC0) and a fourth column (MP) having a fourth memory cell (MC0); and a third chip (4) including a row decoder (20) and a controller (53), wherein the row decoder (20) is connected to a first word line (WL0) connected to each gate of the first to fourth memory cells, and the controller (53) is configured to perform a write operation of repeatedly performing a programming loop including a programming operation and a programming verification operation. In the first programming operation of the write operation of the first memory cell, the row decoder applies a first programming voltage (Vpgm1) to the first word line. In the first programming operation of the write operation of the second memory cell, the row decoder applies a second programming voltage (Vpgm1+dV1) higher than the first programming voltage to the first word line. In the first programming operation of the write operation of the third memory cell, the row decoder applies the third programming voltage (Vpgm1) to the first word line. In the first programming operation of the write operation of the fourth memory cell, the row decoder applies the fourth programming voltage (Vpgm1+dV2) higher than the third programming voltage to the first word line.

[0407] By applying the above-described embodiment, it is possible to provide a semiconductor memory device capable of improving processing performance.

[0408] In addition, the embodiment is not limited to the above-described form, and various changes can be made.

[0409] The term “connected” in the above-described embodiments also includes a state of being indirectly connected with any other object such as a transistor or a resistor interposed therebetween.

[0410] Although some embodiments of the present invention are described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and similarly, they are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor storage device comprising: The first chip includes a first column having a first storage unit and a second column having a second storage unit; a second chip including a third column having a third memory cell and a fourth column having a fourth memory cell; and A third chip includes a row decoder and a controller, wherein the row decoder is connected to the first word line connected to the gates of the first to fourth memory cells, and the controller is configured to perform a write operation of repeatedly performing a programming loop including a programming operation and a programming verification operation; In the first programming operation of the writing operation of the first memory cell, the row decoder applies a first programming voltage to the first word line. In the first programming operation of the writing operation of the second memory cell, the row decoder applies a second programming voltage higher than the first programming voltage to the first word line, In the first programming operation of the writing operation of the third memory cell, the row decoder applies a third programming voltage to the first word line. In the first programming operation of the writing operation of the fourth memory cell, the row decoder applies a fourth programming voltage higher than the third programming voltage to the first word line.

2. The semiconductor memory device according to claim 1, wherein The controller sets the second programming voltage based on a result of the writing operation on the first memory cell, and sets the fourth programming voltage based on a result of the writing operation on the third memory cell.

3. The semiconductor memory device according to claim 1, wherein The first programming voltage is the same as the third programming voltage.

4. The semiconductor memory device according to claim 1, wherein The number of the programming loops in the writing operation of the second memory cell is smaller than the number of the programming loops in the writing operation of the first memory cell.

5. The semiconductor memory device according to claim 1, wherein The first programming voltage increases as the programming loop is repeated.

6. The semiconductor memory device according to claim 1, wherein The third chip further includes a sense amplifier connected to a bit line commonly connected to one end of each of the first to fourth pillars.

7. The semiconductor memory device according to claim 1, wherein The first column further includes a first selection transistor, the first selection transistor is connected in series with the first memory cell, and a gate of the first selection transistor is connected to the row decoder via a first selection gate line. The second column further includes a second selection transistor, the second selection transistor is connected in series with the second memory cell, and a gate of the second selection transistor is connected to the row decoder via a second selection gate line. The third column further includes a third selection transistor, the third selection transistor is connected in series with the third memory cell, and a gate of the third selection transistor is connected to the row decoder via a third selection gate line. The fourth column further includes a fourth selection transistor which is connected in series with the fourth memory cell and has a gate connected to the row decoder via a fourth selection gate line.

8. The semiconductor memory device according to claim 1, wherein The first pillar and the third pillar extend in a first direction respectively, and are arranged side by side along the first direction.

9. The semiconductor memory device according to claim 1, wherein The first column includes a semiconductor layer and a charge storage layer.

10. The semiconductor memory device according to claim 1, wherein The second chip is bonded to the first surface of the first chip, and the third chip is bonded to the second surface of the first chip that is located on the opposite side to the first surface.

11. The semiconductor memory device according to claim 1, wherein The first column further comprises a fifth storage unit connected in series with the first storage unit. The second column further comprises a sixth storage unit connected in series with the second storage unit, The third column further comprises a seventh storage unit connected in series with the third storage unit. The fourth column further comprises an eighth storage unit connected in series with the fourth storage unit, The gates of the fifth to eighth memory cells are connected to the row decoder via the second word line. In the first programming operation of the writing operation of the fifth memory cell, the row decoder applies a fifth programming voltage to the second word line. In the first programming operation of the write operation of the sixth memory cell, the row decoder applies a sixth programming voltage higher than the fifth programming voltage to the second word line, In the first programming operation of the write operation of the seventh memory cell, the row decoder applies the sixth programming voltage to the second word line, In the first programming operation of the writing operation of the eighth memory cell, the row decoder applies the sixth programming voltage to the second word line.

12. The semiconductor memory device according to claim 11, wherein The controller sets the sixth programming voltage based on a result of the writing operation of the fifth memory cell.

13. The semiconductor memory device according to claim 11, wherein The first programming voltage, the third programming voltage, and the fifth programming voltage are the same.

14. The semiconductor memory device according to claim 1, wherein The controller setting the second programming voltage based on the result of the writing operation of the first memory cell, The third programming voltage is set based on the second programming voltage, The fourth programming voltage is set based on a result of the writing operation of the third memory cell.

15. The semiconductor memory device according to claim 1, wherein The third programming voltage is higher than the first programming voltage and lower than the second programming voltage.

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