A method for preparing a dielectric layer based on a volatile sacrificial layer

Abstract

The application discloses a method for preparing a dielectric layer based on a volatile sacrificial layer, and belongs to the technical field of transistor construction processes. The method comprises the following steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; depositing a dielectric layer material on the surface of the volatile sacrificial layer, and then performing post-processing to obtain a van der Waals contact dielectric layer on the surface of the substrate. The method uses a volatile material as a seed layer for the growth of a dielectric layer material and a sacrificial layer for forming a van der Waals gap, avoids damage to a two-dimensional semiconductor material caused by in-situ deposition, and solves the problems of insufficient density of a directly deposited dielectric layer material and uneven film thickness, thereby optimizing the construction process of a transistor device. The method can realize van der Waals contact of an in-situ deposited dielectric layer without transfer, is compatible with a silicon-based transistor construction process, and is expected to be applied to a silicon-based process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of transistor construction process, in particular to a method based on a volatile sacrificial layer assisted dielectric layer preparation. BACKGROUND

[0002] As one of the important parts of transistor construction, dielectric layer plays an irreplaceable role in both silicon-based transistors and two-dimensional transistors with two-dimensional semiconductor materials as the channel. Due to the atomic-level thinness, two-dimensional semiconductor materials have excellent gate control properties, which can effectively avoid the short channel effect. Because of the smooth surface without dangling bonds, the transistor constructed by using extremely thin two-dimensional semiconductor materials can make up for the serious decline of carrier mobility caused by the serious scattering problem of silicon-based transistors after thinning. However, the characteristic of no dangling bonds also leads to the difficulty of directly depositing a gate dielectric layer on the surface of two-dimensional semiconductor materials. Even if atomic layer deposition is used, problems such as uneven deposition and pinholes are inevitable, which seriously limits the application of two-dimensional semiconductor materials.

[0003] The current main solutions involve two directions. One is in-situ pretreatment, including in-situ deposition of a seed layer, a metal seed layer or ozone treatment in the target deposition area of two-dimensional semiconductor materials. This kind of treatment method introduces heterogeneous materials of non-dielectric layer materials on one hand, and the dielectric constant of these heterogeneous materials is usually low, which will lead to the decrease of the overall dielectric constant of the prepared gate dielectric layer structure, the decrease of the gate capacitance and the weakening of the gate control ability. On the other hand, ozone treatment will cause a certain degree of damage to the channel region, resulting in a decrease in electrical performance and being unsuitable for single-layer materials. The other is a non-in-situ transfer process. This method is to transfer the dielectric layer material to the corresponding position of the target substrate through an organic support layer after depositing the dielectric layer material on a non-target substrate, so as to realize the van der Waals contact between the dielectric layer material and the two-dimensional semiconductor material. Although this method can realize a good van der Waals contact interface, it is easy to introduce residual organic matter, which will cause n-type doping to the two-dimensional semiconductor material. At the same time, additional artificial stress is easily introduced in the transfer process, which may cause cracks in the dielectric layer film and affect the intrinsic dielectric properties of the dielectric layer material. Therefore, it is urgent to develop a large-scale dielectric layer film preparation process of a single dielectric layer material with a van der Waals contact interface without damage to the intrinsic properties of the two-dimensional semiconductor channel material and the dielectric layer material. SUMMARY

[0004] The purpose of the present application is to provide a method based on a volatile sacrificial layer assisted dielectric layer material preparation to solve the problems existing in the prior art.

[0005] To achieve the above purpose, the present application provides the following solutions:

[0006] One of the technical solutions of the present application: a method for preparing a dielectric layer based on a volatile sacrificial layer, comprising the following steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; depositing a dielectric layer material on the surface of the volatile sacrificial layer, and then performing post-processing (to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate) to obtain a patterned dielectric layer with van der Waals contact on the surface of the substrate.

[0007] The van der Waals contact specifically refers to that after the volatile sacrificial layer sandwiched between the dielectric layer and the substrate evaporates and disperses, a certain size of van der Waals gap is formed between the in-situ deposited dielectric layer and the substrate (two-dimensional semiconductor material), at this time the dielectric layer material and the substrate material are in van der Waals contact without chemical bond formation, i.e. non-direct contact, thereby avoiding the influence of in-situ deposited dielectric layer on the intrinsic properties of the substrate (two-dimensional semiconductor material).

[0008] The method of the present application utilizes the low-temperature volatile diffusion property of the volatile sacrificial layer, and after the deposition of the dielectric layer material is completed, the volatile sacrificial layer is evaporated and dispersed by post-processing to remove the sacrificial layer, thereby obtaining a good contact interface and realizing the van der Waals contact between the dielectric layer and the substrate (two-dimensional semiconductor material). At the same time, the pre-deposited volatile sacrificial layer during the deposition of the dielectric layer can act as a seed layer for the growth of the dielectric layer, thereby improving the compactness of the dielectric layer material deposited on the surface of the substrate (two-dimensional semiconductor material). In addition, due to the blocking of the sacrificial layer, damage and doping to the channel material during the deposition of the dielectric layer material can be avoided.

[0009] Further, the volatile material includes one or more of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3; the deposition thickness of the volatile material is 1-100 nm, and the surface roughness (Ra) of the volatile sacrificial layer obtained by deposition is ≤3 nm. If the roughness of the sacrificial layer is too large, it will affect the interface state of the dielectric layer material deposited thereon, thereby limiting the gate control performance of the device.

[0010] Further, when the volatile material is multiple of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3, the multiple volatile materials can be combined in any ratio.

[0011] Further, the dielectric layer material includes HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5 and Ba x Sr 1-xone or more of TiO3(0 < x < 1); the deposition thickness of the dielectric layer material is 1-30 nm, and the surface roughness (Ra) of the dielectric layer obtained by deposition is ≤1 nm. The flat dielectric layer surface is conducive to forming a good contact interface with the subsequently deposited gate electrode and obtaining a more uniform gate control effect.

[0012] Further, when the dielectric layer material is HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5, and Ba x Sr 1-x When the dielectric layer material is a plurality of TiO3(0 < x < 1), the plurality of dielectric layer materials can be combined in any ratio.

[0013] Further, the step of patterning processing is included before the deposition of the dielectric layer material on the surface of the volatile sacrificial layer after the deposition of the volatile material on the substrate.

[0014] Alternatively, the step of patterning processing is included before the deposition of the dielectric layer material on the surface of the volatile sacrificial layer after the deposition of the dielectric layer material on the substrate.

[0015] Further, the step of patterning processing includes: first, spin-coating an exposure resist (including an electron beam exposure resist or a photoresist) on the surface of the volatile sacrificial layer, drying at 100-200°C for 1-3 min; then, exposing a pre-designed pattern area by an electron beam, ultraviolet light, or laser; finally, developing the exposed sample in a developing solution and fixing it in a fixing solution, so that the area designed to deposit the dielectric layer is exposed, i.e., the patterning process is completed.

[0016] Alternatively, first, spin-coating an exposure resist (including an electron beam exposure resist or a photoresist) on the surface of the substrate, drying at 100-200°C for 1-3 min; then, exposing a pre-designed pattern area by an electron beam, ultraviolet light, or laser; finally, developing the exposed sample in a developing solution and fixing it in a fixing solution, so that the area designed to deposit the dielectric layer is exposed, i.e., the patterning process is completed.

[0017] Further, the exposure mode in the step of patterning processing includes electron beam exposure, ultraviolet lithography, or laser direct writing.

[0018] Further, when the exposure is performed by an electron beam, the exposure resist corresponding to the spin-coating is an electron beam exposure resist; when the exposure is performed by ultraviolet light or laser, the exposure resist corresponding to the spin-coating is a photoresist.

[0019] Further, the post-treatment further comprises a step of de-gluing treatment; the de-gluing treatment comprises: immersing the sample in hot acetone at 85-150℃ for 15-30min and ultrasonicating for 5-10s, then taking out the sample, washing the residual acetone with isopropyl alcohol and blowing dry with nitrogen.

[0020] The purpose of immersing in hot acetone is to dissolve and remove the exposure glue used in the patterning process, and at the same time, the non-patterning excess dielectric layer or non-patterning excess dielectric layer and excess volatile sacrificial layer covering the surface of the exposure glue are also removed, only leaving the dielectric layer and the volatile sacrificial layer in the patterning area, obtaining a patterned dielectric layer / sacrificial layer structure.

[0021] Further, the post-treatment comprises an annealing treatment. The purpose of the post-treatment is to evaporate and disperse the volatile sacrificial layer covered by the patterned dielectric layer.

[0022] Further, the annealing treatment comprises vacuum annealing treatment, annealing treatment in normal pressure atmosphere, Se vapor atmosphere annealing treatment, Te vapor atmosphere annealing treatment or S vapor atmosphere annealing treatment.

[0023] The conditions of the vacuum annealing treatment comprise: annealing temperature of 80-300℃, annealing vacuum degree of 5x10 -1 ~1x10 -9 mbar, annealing time of 0.5-3h, and annealing atmosphere of Ar, N2, H2, Cl2, SF6, N2O, CO2, O2 or CH 4-y F y (0≤y≤4) and gas flow of 0-100sccm.

[0024] Further, the method of depositing the volatile material comprises one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition.

[0025] Further, the method of depositing the dielectric layer material comprises one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition.

[0026] Further, the substrate comprises a two-dimensional semiconductor material; the two-dimensional semiconductor material comprises but is not limited to: MoS2, WSe2, WS2, MoTe2 or NbSe2.

[0027] Further, the two-dimensional semiconductor material surface is also deposited with metal electrodes (source and drain); the metal electrodes include but are not limited to Au, Ag, Cu, Pt, Cr, Pb, Ni or Al.

[0028] The second technical solution of the present application: the transistor device prepared by the above method based on the volatile sacrificial layer assisted dielectric layer.

[0029] The present application discloses the following technical effects:

[0030] The present application realizes the van der Waals contact between the in-situ grown patterned dielectric layer and the substrate (two-dimensional semiconductor material), optimizes the electrical properties of the transistor device including the on-off ratio, the hysteresis window, the off-state current, etc. The present application obtains a good dielectric layer / two-dimensional semiconductor material contact interface, which is conducive to promoting the development of two-dimensional transistors in the field of electronic devices. Compared with the existing dielectric layer preparation method in the art, the method of the present application has the following advantages:

[0031] (1) Compared with directly depositing a dielectric layer on the surface of a two-dimensional semiconductor material in-situ, the volatile sacrificial layer deposited in advance in the present application can effectively prevent damage and doping of the extremely thin two-dimensional semiconductor material caused by in-situ deposition.

[0032] (2) The volatile sacrificial layer deposited in advance in the present application can serve as a seed layer for the deposition of the dielectric layer material, thereby improving the density of the in-situ deposited dielectric layer.

[0033] (3) The method of the present application can realize the van der Waals contact between the in-situ deposited dielectric layer and the two-dimensional semiconductor material by removing the volatile sacrificial layer through post-processing, thereby optimizing the serious carrier scattering problem caused by poor contact interface.

[0034] (4) Compared with the method of transferring the dielectric layer, the present application does not introduce additional artificial stress, thereby avoiding damage to the dielectric layer during the transfer process.

[0035] (5) The volatile sacrificial layer of the present application is compatible with the patterning process and can meet any pattern design requirements.

[0036] (6) The technical solution of the present application is compatible with the silicon-based process, does not require a complex transfer process, and has the potential to be applied to the construction process of the gate dielectric layer of a silicon-based transistor. At the same time, through continuous optimization of the process parameters of the present application, large-scale preparation at the wafer level can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0038] Figure 1 Process flow diagram of the method for preparing the dielectric layer based on the volatile sacrificial layer in Example 1;

[0039] Figure 2 AFM topography characterization photo of the hafnium oxide dielectric layer with Se as the sacrificial layer deposited in Example 1;

[0040] Figure 3 AFM height characterization data of the hafnium oxide dielectric layer with Se as the sacrificial layer deposited in Example 1 (i.e. total thickness curve of the dielectric layer + sacrificial layer);

[0041] Figure 4 Structure diagram of the top-gate field effect transistor device constructed based on the process of depositing the hafnium oxide dielectric layer with Se as the sacrificial layer in situ in Example 1;

[0042] Figure 5 500 times magnification optical microscope photo of the top-gate field effect transistor device constructed based on the process of depositing the hafnium oxide dielectric layer with Se as the sacrificial layer in situ in Example 1;

[0043] Figure 6 Electrical performance test curve of the top-gate field effect transistor device constructed based on the process of depositing the hafnium oxide dielectric layer with Se as the sacrificial layer in situ in Example 1;

[0044] Figure 7 Electrical performance test curve of the top-gate field effect transistor device constructed based on the process of transferring the hafnium oxide dielectric layer based on the organic support layer in the comparative example. DETAILED DESCRIPTION

[0045] The various exemplary embodiments of the present application will now be described in detail, which should not be considered as limiting the present application, but should be understood as a more detailed description of some aspects, characteristics and embodiments of the present application.

[0046] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Additionally, for a range of values of, an understanding exists that each intervening value, to the upper or lower limit, is also specifically included within the scope of the present application. The upper and lower limits of these intervening values are also contemplated as being encompassed within the scope of the present application. These smaller ranges are not insubstantial as the smaller the range the more precise the scope of a concomitant patentable claim.

[0047] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Although preferred methods and materials are described herein, any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present application. All documents mentioned herein are incorporated by reference to disclose and describe in full the methods and / or materials which are described herein. In case of conflict, the present document will control.

[0048] Various modifications and changes can be made to the specific embodiments of the present application described herein without departing from the scope or spirit of the application. Other embodiments of the application will be apparent to those of ordinary skill in the art from the description and examples presented herein. The description and examples are illustrative of the application and are not intended to limit the scope of the application.

[0049] With respect to the use of "comprising", "including", "containing", "having" and "ensing" and the like, these terms are used in the sense of "open ended" and are intended to mean including but not limited to.

[0050] As a first aspect of the present application, the present application provides a method for fabricating a dielectric layer based on a volatile sacrificial layer, comprising the following steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; depositing a dielectric layer material on the surface of the volatile sacrificial layer, and then performing post-processing (to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate) to obtain a dielectric layer with van der Waals contact on the surface of the substrate.

[0051] The method is characterized in that a volatile material is used as a sacrificial layer and a seed layer for the growth of the dielectric layer. After the completion of the densification deposition of the dielectric layer on the surface of the volatile sacrificial layer, the volatile sacrificial layer is removed by post-processing, so that a van der Waals gap of a certain size is formed between the in-situ deposited dielectric layer and the underlying substrate (two-dimensional semiconductor material), and van der Waals contact is achieved between the in-situ deposited dielectric layer and the substrate (two-dimensional semiconductor material). At the same time, the scale of the preparation can be expanded to wafer level through optimization of the process parameters of the present application.

[0052] As a preferred embodiment of the present application, the volatile material comprises one or more of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3.

[0053] As a preferred embodiment of the present application, when the volatile material is a plurality of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3, the plurality of volatile materials can be combined in any ratio.

[0054] As a preferred embodiment of the present application, the deposition thickness of the volatile sacrificial layer is 1-100 nm, and the surface roughness of the deposited volatile sacrificial layer is ≤3 nm.

[0055] As a preferred embodiment of the present application, the dielectric layer material comprises one or more of HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5and Ba x Sr 1-x TiO3(0

[0056] As a preferred embodiment of the present application, when the dielectric layer material is a plurality of HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5and Ba x Sr 1-x TiO3(0

[0057] As a preferred embodiment of the present application, the deposition thickness of the dielectric layer material is 1-30 nm, and the surface roughness of the deposited dielectric layer is ≤1 nm.

[0058] As a preferred embodiment of the present application, the process further comprises a patterning step before depositing the volatile material on the substrate and before depositing the dielectric layer material on the surface of the volatile sacrificial layer.

[0059] Alternatively, the process further comprises a patterning step before depositing the volatile material on the substrate.

[0060] As a preferred embodiment of the present application, the process further comprises a de-gluing step before the post-processing.

[0061] As a preferred embodiment of the present application, the method for preparing the sacrificial layer assisted dielectric layer further comprises the following steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; performing a patterning process on the surface of the volatile sacrificial layer; depositing a dielectric layer material on the surface of the volatile sacrificial layer after the patterning process, and then sequentially performing a stripping process and a post-treatment process to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate, thereby obtaining a patterned dielectric layer in van der Waals contact with the substrate.

[0062] Alternatively, the substrate is subjected to a patterning process; a volatile material is deposited on the surface of the substrate after the patterning process to obtain a volatile sacrificial layer; a dielectric layer material is deposited on the surface of the volatile sacrificial layer, and then a stripping process and a post-treatment process are sequentially performed to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate, thereby obtaining a patterned dielectric layer in van der Waals contact with the substrate.

[0063] As a preferred embodiment of the present application, the patterning process includes electron beam exposure, ultraviolet lithography or laser direct writing.

[0064] As a preferred embodiment of the present application, the patterning process includes the following steps: first, spin-coating an exposure resist (including an electron beam exposure resist or a photoresist) on the surface of the volatile sacrificial layer, and baking at 100-200°C for 1-3 min; then, exposing a pre-designed pattern area by an electron beam, ultraviolet light or laser; finally, developing the exposed sample in a developing solution and fixing it in a fixing solution, so that the designed area to be deposited with a dielectric layer is exposed, i.e., the patterning process is completed.

[0065] Alternatively, first, spin-coating an exposure resist (including an electron beam exposure resist or a photoresist) on the surface of the substrate, and baking at 100-200°C for 1-3 min; then, exposing a pre-designed pattern area by an electron beam, ultraviolet light or laser; finally, developing the exposed sample in a developing solution and fixing it in a fixing solution, so that the designed area to be deposited with a dielectric layer is exposed, i.e., the patterning process is completed.

[0066] As a preferred embodiment of the present application, when the exposure is performed by an electron beam, the corresponding spin-coated exposure resist is an electron beam exposure resist; when the exposure is performed by ultraviolet light or laser, the corresponding spin-coated exposure resist is a photoresist.

[0067] As a preferred embodiment of the present application, the stripping process includes immersing the sample in hot acetone at 85-150°C for 15-30 min and ultrasonicating for 5-10 s, then taking out the sample, washing the residual acetone with isopropyl alcohol and blowing dry with nitrogen.

[0068] As a preferred embodiment of the present application, the post-treatment process includes an annealing process.

[0069] As a preferred embodiment of the present application, the annealing process comprises vacuum annealing, annealing in normal pressure atmosphere, annealing in Se vapor atmosphere, annealing in Te vapor atmosphere or annealing in S vapor atmosphere.

[0070] The conditions of the vacuum annealing process comprise: an annealing temperature of 80-300℃, an annealing vacuum degree of 5x10 -1 -9 mbar, an annealing time of 0.5-3h, and an annealing atmosphere of Ar, N2, H2, Cl2, SF6, N2O, CO2, O2 or CH 4-y F y (0≤y≤4) with a gas flow of 0-100sccm.

[0071] As a preferred embodiment of the present application, the method of depositing the easily-volatile material comprises one of the following methods: magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma-enhanced chemical vapor deposition and metal organic chemical vapor deposition.

[0072] As a preferred embodiment of the present application, the method of depositing the dielectric layer material comprises one of the following methods: magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma-enhanced chemical vapor deposition and metal organic chemical vapor deposition. The method of deposition in the present application is not limited to the above-mentioned methods, as long as the method can realize the deposition of thin film and ensure the stability of the interface properties of the easily-volatile sacrificial layer during the deposition process, and the evaporation and diffusion of the easily-volatile sacrificial layer do not occur.

[0073] As a preferred embodiment of the present application, the substrate comprises a two-dimensional semiconductor material and a source electrode (S) and a drain electrode (D) deposited in advance on the two-dimensional semiconductor material.

[0074] As a preferred embodiment of the present application, the two-dimensional semiconductor material comprises, but is not limited to, MoS2, WSe2, WS2, MoTe2 or NbSe2.

[0075] As a preferred embodiment of the present application, the source electrode (S) and the drain electrode (D) comprise, but are not limited to, Au, Ag, Cu, Pt, Cr, Pb, Ni or Al.

[0076] As a second aspect of the present application, the present application provides a transistor device prepared according to the above-mentioned method based on the easily-volatile sacrificial layer assisted dielectric layer.

[0077] The technical solutions of the present application will be further described below in combination with specific embodiments. ​

[0078] Normal temperature in the embodiments of the present application refers to 20-30℃.

[0079] Embodiment 1

[0080] A method for preparing a dielectric layer based on a volatile sacrificial layer (schematic diagram of process flow as shown in Figure 1 The steps are as follows:

[0081] (1) A single layer of MoS2 two-dimensional semiconductor material is prepared on the surface of a silicon substrate, and then 30 nm thick Au electrodes (source and drain) are evaporated on the surface of the MoS2 two-dimensional semiconductor material as a substrate. A 6 nm thick Se volatile sacrificial layer film is deposited on the surface of the substrate by thermal evaporation. The specific parameters of thermal evaporation are: power ratio of 10.8%, power change rate of 0.5 u / s, evaporation rate of The vacuum degree of the cavity is 2.1×10 -8 torr, and the rotating motor rate is 10 rpm. The surface roughness Ra of the Se volatile sacrificial layer film after deposition is about 1.2 nm, and the deposition thickness is 6 nm.

[0082] (2) The electron beam exposure glue (polymethyl methacrylate) is spin-coated on the surface of the Se volatile sacrificial layer, and baked at 100℃ for 1 min. Then, the exposure glue is patterned and exposed by electron beam. Finally, the exposed sample is developed in the developing solution, fixed in isopropyl alcohol, and dried with nitrogen, which completes the patterning process on the surface of the Se volatile sacrificial layer film.

[0083] (3) The patterned sample is subjected to deposition of dielectric layer material. Hafnium oxide (HfO2) film is deposited on the surface of the patterned Se volatile sacrificial layer film by atomic layer deposition method for 180 cycles. The deposition procedure of each cycle is as follows: first, the hafnium (Hf) source is injected into the cavity, and then it is swept uniformly. Then, the water source is injected into the chamber, and then it is swept uniformly and reacted. After that, the water source is injected again, and then it is swept uniformly and reacted. The continuous cycle of water source injection and reaction for two times is to make the hafnium source of the previous layer react more completely. The deposition temperature is 90℃, and the low-temperature deposition is to ensure that the volatile Se sacrificial layer film does not change during hafnium oxide deposition, and to maintain a stable interface state. The surface roughness Ra of the hafnium oxide film after deposition is about 0.8 nm (as shown in the AFM topography characterization photo in Figure 2 ), and the deposition thickness is 26 nm (as shown in the AFM height characterization data graph in Figure 3 ).

[0084] (4) The deposited sample was placed in 120°C hot acetone for resist removal, soaked for 30 min, and then sonicated for 10 s. The sample was then removed, and the residual acetone on the sample was cleaned with room temperature isopropanol and dried with nitrogen. The purpose of soaking in hot acetone is to dissolve and remove the exposure adhesive used in the patterning process. When the exposure adhesive is dissolved and removed, the excess non-patterned dielectric layer covering the surface of the exposure adhesive is also removed, leaving only the dielectric layer of the patterned area. In addition, since Se has a low evaporation temperature and weak adhesion to the target substrate during the thermal evaporation process, the Se film directly exposed in acetone will be removed along with the exposure adhesive during the acetone resist removal process. The Se film covered with hafnium oxide is not removed, thus obtaining a patterned hafnium oxide dielectric layer (HfO2 / Se structure) with Se as the sacrificial layer.

[0085] (5) Since the volatile Se sacrificial layer film can evaporate at relatively low temperatures, the sample after resist removal is subjected to vacuum annealing. The purpose is to remove the volatile Se sacrificial layer through annealing, while retaining the hafnium oxide deposited on the Se, so as to achieve van der Waals contact between the hafnium oxide dielectric layer and the two-dimensional semiconductor channel material. The annealing parameters are: vacuum degree 2.1 × 10⁻⁶ -5 The annealing temperature was 150℃, and the annealing time was 2 hours. The volatile Se sacrificial layer film serves two purposes: firstly, it acts as an auxiliary layer for hafnium oxide growth, aiding in the densification of the dielectric layer and preventing damage to the channel material during in-situ hafnium oxide growth; secondly, after hafnium oxide growth, the volatile Se sacrificial layer film can be removed by simple annealing, creating a van der Waals gap (vdW gap) of a certain size between the hafnium oxide and the channel material. This achieves van der Waals stacking of the hafnium oxide dielectric layer and the two-dimensional semiconductor material, optimizing the contact interface and avoiding severe carrier interface scattering. Furthermore, the surface flatness of the hafnium oxide dielectric layer is further optimized through annealing.

[0086] (6) Finally, a 30 nm thick Au electrode is thermally deposited on the annealed hafnium oxide dielectric layer as the gate of the transistor device. A schematic diagram and optical mirror image of the transistor device (top-gate field-effect transistor) constructed in the embodiment are shown below. Figure 4 and Figure 5 As shown.

[0087] The electrical performance of the van der Waals stacked field-effect transistor constructed in this embodiment was tested, and the applied drain bias voltage V was used for the test. ds =1V, source grounded V s =0, substrate grounded, top gate voltage swept from -2V to 2V, test results are shown in [link to test results]. Figure 6 .like Figure 6 I ds -V tgAs shown in the curve, the off-state current of the device is as low as the order of 10fA, the on-off ratio is about 7 orders of magnitude, and the hysteresis window is only about 130mV, which proves that the contact interface between hafnium oxide and the two-dimensional semiconductor material has few defects, and the capture of electrons during the first test curve scanning process is small, so that the required voltage is not much different at the same current during the reverse scanning process. The on-off ratio of 7 orders of magnitude meets the requirements of the International Roadmap for Devices and Systems (IRDS) for transistors, proving that the application of the application to the construction of transistors is feasible.

[0088] Example 2

[0089] A method for preparing a volatile sacrificial layer based on an auxiliary dielectric layer, the steps are as follows:

[0090] (1) A single layer of MoS2 two-dimensional semiconductor material is prepared on the surface of a silicon substrate, and then 25nm thick Au electrodes (source and drain) are evaporated on the surface of the MoS2 two-dimensional semiconductor material as a substrate. The electron beam exposure glue (polymethyl methacrylate) is spin-coated on the surface of the substrate and dried at 150℃ for 2min. Then, the exposure glue is patterned and exposed by an electron beam. Finally, the exposed sample is developed in a developing solution, fixed in isopropyl alcohol, and dried with nitrogen. The target deposition area is exposed by pre-patterning.

[0091] (2) A 10nm thick Te volatile sacrificial layer film is deposited on the surface of the patterned sample by thermal evaporation. The specific parameters of thermal evaporation are as follows: the power ratio of the power source is 13.5%, the power change rate is 0.5u / s, the evaporation rate is The vacuum degree of the cavity is 2.2x10 -8 torr, and the rotation motor rate is 10rpm. The surface roughness Ra of the deposited Se volatile sacrificial layer film is about 1nm, and the deposition thickness is 6nm.

[0092] (3) A hafnium oxide film is deposited on the surface of the deposited Te volatile sacrificial layer film by atomic layer deposition for 180 cycles. The deposition procedure of each cycle is as follows: first, inject hafnium source into the cavity, then blow it evenly, then inject water source into the cavity, blow it evenly and react, then inject water source again, blow it evenly and react. The continuous injection and reaction of water source for two cycles is to make the reaction of the previous layer of hafnium source more complete. The deposition temperature is 90℃, which is a low temperature deposition to ensure that the volatile Te sacrificial layer film does not change during hafnium oxide deposition and maintains a stable interface state. The surface roughness Ra of the deposited hafnium oxide film is about 0.8nm, and the deposition thickness is 26nm.

[0093] (4) After deposition, the sample was put into hot acetone at 120°C for de-gluing, and soaked for 30 min followed by ultrasonic treatment for 10 s. The sample was taken out, washed with room temperature isopropyl alcohol to remove residual acetone, and dried with nitrogen to obtain a patterned hafnium oxide dielectric layer (HfO2 / Te structure) with Te as the sacrificial layer.

[0094] (5) The sample after de-gluing was subjected to vacuum annealing treatment, so as to remove the volatile Te sacrificial layer by annealing and retain the hafnium oxide deposited on the Te, so as to realize van der Waals contact between the hafnium oxide dielectric layer and the two-dimensional semiconductor channel material. The annealing parameters were as follows: vacuum degree 2.1 x 10 -5 mbar, annealing temperature 200°C, and annealing time 2 h. The Te volatile sacrificial layer serves as an auxiliary layer for the growth of hafnium oxide, facilitates the densification growth of the dielectric layer, and avoids damage to the channel material during in-situ growth of hafnium oxide. After the growth of hafnium oxide, the Te volatile sacrificial layer can be removed by simple annealing, so as to generate a vdW gap between the hafnium oxide and the channel material, realize van der Waals stacking of the hafnium oxide dielectric layer and the two-dimensional semiconductor material, and optimize the contact interface between the two to avoid serious carrier interface scattering. In addition, the surface flatness of the hafnium oxide dielectric layer is further optimized under the action of annealing.

[0095] (6) Finally, 25 nm thick Au electrodes were deposited on the annealed hafnium oxide dielectric layer by thermal evaporation as the gate (Gate) of the transistor device.

[0096] The van der Waals stacked field effect transistor constructed in this example was tested for electrical performance. The applied drain bias V ds = 1 V, the source was grounded V s = 0, the substrate was grounded, and the top gate voltage was swept from -2 V to 2 V. The test obtained that the off-state current of the device was as low as the order of 10 fA, the on-off ratio was about 7 orders of magnitude, and the hysteresis window was about 200 mV.

[0097] Comparative Example 1

[0098] The top-gate field effect transistor constructed by the method of organic support layer assisted transfer of hafnium oxide dielectric layer had the following steps:

[0099] (1) After spin-coating 1 layer of PMMA exposure glue on a 300 nm thick silicon oxide and baking for 1 min, electron beam exposure and development were performed to obtain a patterned PMMA glue layer.

[0100] (2) The hafnium oxide dielectric layer material film is deposited on the patterned PMMA adhesive layer by atomic layer deposition method for 180 cycles. The surface roughness Ra of the hafnium oxide film after deposition is about 0.5 nm, and the deposition thickness is 26 nm. Then the deposited sample is placed in 120°C hot acetone for 25 min and ultrasonically treated for 10 s, then removed, washed with room temperature isopropyl alcohol to remove residual acetone, and dried with nitrogen to complete the adhesive removal process, remove the excess hafnium oxide dielectric layer material, and obtain the patterned dielectric layer material.

[0101] (3) Re-spin 2 layers of PMMA on the surface of the sample as a transferred organic support layer, and dry at 90°C on a hot plate for 1 min after each spin.

[0102] (4) Put the sample into deionized water. Since the adhesion of the organic support layer to the patterned dielectric layer material is greater than the adhesion of the hafnium oxide dielectric layer material to the silicon oxide substrate, the hafnium oxide dielectric layer is peeled off together with the organic support layer during the slow peeling process.

[0103] (5) The organic support layer carrying the patterned hafnium oxide dielectric layer material is transferred to the target area of the MoS2 two-dimensional semiconductor material and the source (S) and drain (D) combination structure prepared in advance, then immersed in 85°C hot acetone for adhesive removal, soaked for 30 min and then ultrasonically treated for 10 s, then the sample is taken out, washed with room temperature isopropyl alcohol to remove residual acetone and dried, and the transfer of the hafnium oxide dielectric layer is completed.

[0104] (6) Au electrode is thermally evaporated on the transferred hafnium oxide dielectric layer as a top gate electrode (Gate), and the construction of the field effect transistor is completed.

[0105] In the present comparative example, the preparation process of the hafnium oxide dielectric layer is different from that of Example 1, and the construction process of the other structures of the transistor device is consistent with that of Example 1.

[0106] The transistor constructed by the patterned hafnium oxide dielectric layer transferred by the organic support layer in the present comparative example is tested for electrical performance. The bias voltage V ds = 1 V, V s ground, and the top gate voltage is -3-3 V. The obtained I ds -V tg curve is as follows: Figure 7As shown by the test curve, the hysteresis window of the transistor constructed by the method of transferring the dielectric layer is up to 1.15V, which is much larger than the hysteresis window of the transistor constructed by the process of the application, because a larger artificial stress is introduced in the transfer process, which inevitably causes a certain degree of micro-cracks or hole damage of the hafnium oxide dielectric layer in the transfer process, resulting in an increase in defects of the hafnium oxide dielectric layer after transfer and a decrease in performance. At the same time, the off-state current is in the order of 10pA, which is much larger than the off-state current in the order of 10fA obtained in Example 1 of the application, which will significantly increase the power consumption of the device, which is not in line with the low power consumption requirement of the international device and system roadmap, and the large off-state current also leads to a decrease in the on-off ratio of the transistor constructed by the hafnium oxide transfer process, which is not suitable for subsequent logic cascading.

[0107] The above-described embodiments are only descriptions of the preferred modes of the application and do not limit the scope of the application. Without departing from the design spirit of the application, various modifications and improvements to the technical solutions of the application made by those skilled in the art shall fall within the protection scope determined by the claims of the application.

Claims

1. A method for fabricating a dielectric layer assisted by a volatile sacrificial layer, characterized in that, Includes the following steps: A volatile material is deposited on the substrate to obtain a volatile sacrificial layer; A dielectric layer material is deposited on the surface of the volatile sacrificial layer, followed by post-processing to obtain a van der Waals contact dielectric layer on the substrate surface. The volatile material includes one or more of Te, S, and Se; The post-processing method includes annealing; The annealing treatment includes vacuum annealing, Se vapor atmosphere annealing, Te vapor atmosphere annealing, or S vapor atmosphere annealing. The conditions for the vacuum annealing process include: an annealing temperature of 80~300 ℃ and an annealing vacuum degree of 2.1×10⁻⁶. -5 ~1×10 -9 mbar, annealing time is 0.5~3 h, annealing atmosphere is Ar or N2, gas flow rate is 0~100 sccm.

2. The method for preparing a dielectric layer based on a volatile sacrificial layer as described in claim 1, characterized in that, The deposition thickness of the volatile material is 1~100 nm, and the surface roughness of the volatile sacrificial layer obtained by deposition is ≤3 nm.

3. The method for preparing a dielectric layer based on a volatile sacrificial layer as described in claim 1, characterized in that, The dielectric layer material includes one or more of HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5, and Ba x Sr 1-x TiO3, where 0 < x < 1; the deposition thickness of the dielectric layer material is 1 to 30 nm, and the surface roughness of the deposited dielectric layer ≤ 1 nm.

4. The method for preparing a dielectric layer based on a volatile sacrificial layer as described in claim 1, characterized in that, The process of depositing a volatile material on the substrate and depositing a dielectric layer material on the surface of the volatile sacrificial layer further includes a patterning step. Alternatively, the process may include a patterning step before depositing the volatile material on the substrate.

5. The method for preparing a dielectric layer based on a volatile sacrificial layer as described in claim 4, characterized in that, The patterning process includes electron beam exposure, ultraviolet lithography, or laser direct writing.

6. The method for preparing a dielectric layer based on a volatile sacrificial layer as described in claim 5, characterized in that, The post-processing process includes a degumming step; the degumming step includes: immersing the sample in hot acetone at 85~150 ℃ for 15~30 min and sonicating for 5~10 s, then removing the sample, washing away residual acetone with isopropanol and drying with nitrogen.

7. The method for preparing a dielectric layer based on a volatile sacrificial layer as described in claim 1, characterized in that, The deposition method of volatile materials includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma-enhanced chemical vapor deposition, and metal-organic chemical vapor deposition. And / or, the method of depositing the dielectric layer material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma-enhanced chemical vapor deposition, and metal-organic chemical vapor deposition.

8. A transistor device prepared by the method for preparing a volatile sacrificial layer-assisted dielectric layer according to any one of claims 1 to 7.

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