Transposed hardware acceleration system and method

Abstract

The invention relates to a transpose hardware acceleration system and method. The system comprises a plurality of transposition dimension registers, an acceleration transposition module and a plurality of memories, the acceleration transpose module comprises a plurality of counters in one-to-one correspondence with the plurality of transpose dimension registers and a memory control algorithm logic module; the acceleration transpose module is used for receiving a plurality of transpose dimension registers, an input data initial address, an output data initial address and a transpose enable, triggering a plurality of counters to count, and determining count values corresponding to the current counters; the memory control algorithm logic module is used for reading data according to the current count values of the counters, the determined dimensions of the transpose matrixes and the initial address of the input data, and writing the data according to the current count values of the counters, the determined dimensions of the transpose matrixes and the initial address of the output data; therefore, the accelerated transpose of the lightweight NPU data is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware transposition, and in particular to a transposition hardware acceleration system and method. Background Art

[0002] The embedded neural network processor (NPU, hereinafter referred to as MPU) only supports one input format, but the existing input formats are diverse and there is a problem that the NPU cannot recognize it. Therefore, data transposition is required so that any format can be processed by the NPU; in addition, the operation format between NPU layers may change, so the data also needs to be transposed so that operations can be performed between layers. The general transposition requirement can be implemented through software code. If there is a transposition speed requirement, a hardware accelerator is generally used for acceleration. The software mainly implements the addressing logic algorithm through the software language, and executes it through the CPU after compilation to realize data movement. Hardware accelerators are dedicated circuits, which are generally customized according to requirements to meet the transposition requirements in a specific usage scenario. Hardware accelerators are generally designed from the top-level architecture level of the on-chip network, or a special algorithm is implemented through hardware. The general architecture design includes modules such as buses, storage, control registers or modules, algorithm acceleration, and connections between modules, and the efficiency of data flow is improved through special architecture. The hardware implementation of the algorithm is a single functional module design. The core lies in the hardware customization of the algorithm, which can save the instruction overhead and data flow overhead during pure software execution, increase computing power and save CPU bandwidth. Summary of the invention

[0003] The present invention provides a transposition hardware acceleration system and method for realizing transposition acceleration of data with a small amount of data in the NPU field, that is, transposition acceleration of lightweight data in the NPU.

[0004] One aspect of the present invention provides a transposition hardware acceleration system, characterized in that it includes a plurality of transposition dimension registers, an acceleration transposition module, and a plurality of memories; The accelerated transposition module includes a plurality of counters corresponding to the plurality of transposition dimension registers one by one and a memory control algorithm logic module; The accelerated transposition module is used to receive the plurality of transposition dimension registers, the input data starting address, the output data starting address and the transposition enable, trigger the plurality of counters to count, and determine the count values ​​corresponding to the plurality of counters at present; The memory control algorithm logic module is used to read data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the input data starting address, and to write data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the output data starting address.

[0005] According to an embodiment of the present invention, the number of the transposition dimension registers is the same as the number of the counters.

[0006] According to an embodiment of the present invention, the input data starting address and the output data starting address are corresponding addresses in the plurality of memories respectively.

[0007] Another aspect of the present invention provides a method for implementing a transposition hardware acceleration system using any one of the above-mentioned transposition hardware acceleration systems, comprising the following steps: Pre-configuring a number of transposed dimension registers to determine the dimensions of the corresponding transposed matrices; Transpose enables triggering corresponding counters to count, and determines the count values ​​corresponding to the current counters; Data is read according to the current count values ​​of the counters, the determined dimensions of the transposed matrices and the input data starting address, and data is written according to the current count values ​​of the counters, the determined dimensions of the transposed matrices and the output data starting address.

[0008] According to an embodiment of the present invention, the maximum value of each counter is the same as the upper limit setting value of the range configured by the corresponding transposition dimension register.

[0009] According to an embodiment of the present invention, the transposition enables triggering corresponding counters to perform counting, and determining the current count values ​​corresponding to the counters comprises the following steps: Counting judgment is performed according to the corresponding counters triggered by the transposition enable; Determine whether the several counters have respectively counted to the upper limit setting value of the range configured by the corresponding transposition dimension register; when the judgment result is yes, the transposition is completed, the transposition is ended, and all the counters are cleared; when the judgment result is no, perform a nested loop corresponding to the number of counters.

[0010] According to an embodiment of the present invention, the reading of data according to current count values ​​of a plurality of counters, the dimensions of a plurality of determined transposed matrices and the input data starting address comprises the following steps: Preset the read address algorithm; Before determining whether the counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register each time, the current counting values ​​corresponding to the counters, the dimensions of the determined transposition matrices and the starting address of the input data are substituted into the preset read address algorithm for calculation to obtain the current read address.

[0011] According to an embodiment of the present invention, the step of writing data according to current count values ​​of a plurality of counters, dimensions of a plurality of determined transposed matrices, and output data starting addresses comprises the following steps: Preset write address algorithm; Before determining whether the counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register each time, the current count values ​​corresponding to the counters, the dimensions of the determined transposition matrices and the output data starting address are substituted into the preset write address algorithm for calculation to obtain the current write address.

[0012] According to one embodiment of the present invention, the pre-set write address algorithm includes: read address = read data starting address + (transposed dimension register 4 * transposed dimension register 3 * transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 4 + (transposed dimension register 3 * transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 3 + (transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 2 + (transposed dimension register 1 * transposed dimension register 0) * counter 1 + transposed dimension register 0 * counter 0.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a transposition hardware acceleration system and method, which pre-configures a number of transposition dimension registers to determine the dimensions of the corresponding transposition matrix; transposition enables triggering a number of corresponding counters to count, and determines the count values ​​corresponding to the current number of counters; data is read according to the current count values ​​of the number of counters, the dimensions of the determined number of transposition matrices, and the input data starting address, and data is written according to the current count values ​​of the number of counters, the dimensions of the determined number of transposition matrices, and the output data starting address, so as to realize the accelerated transposition of lightweight NPU data. Due to the use of hardware accelerators, the accelerated transposition speed is faster than that realized by software; and the present application does not need to define a bus or a handshake signal, the transposition step and device are simple, the implementation is simple, and it has its own memory access logic, and does not require an additional memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 According to an embodiment of the present invention, a schematic diagram of the structure of a transposition hardware acceleration system is shown; Figure 2 According to an embodiment of the present invention, a method flow chart of a transposition hardware acceleration method is shown; Figure 3According to an embodiment of the present invention, a flow chart of a method for determining the count values ​​corresponding to the current plurality of counters by triggering a transposition enable to perform counting is shown; Figure 4 According to an embodiment of the present invention, a flow chart of a method for reading data according to current count values ​​of several counters, dimensions of several transposed matrices determined, and a starting address of input data is shown; Figure 5 According to an embodiment of the present invention, a flow chart of a method for writing data according to current count values ​​of several counters, dimensions of several transposed matrices determined, and output data starting addresses is shown; Figure 6 According to an embodiment of the present invention, a method flow chart of a transposed dimension register counting method is shown. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The term "including" and its variations used in this article represent open inclusion, that is, "including but not limited to", and other explicit and implicit definitions may also be included below.

[0016] The existing technology for implementing transposition includes software code implementation and hardware accelerator implementation, but the solution of implementing transposition requirements through software will greatly increase the computing bandwidth of the CPU and be inefficient. If the CPU bandwidth is tight, the transposition function will bring many limitations to the performance of the chip. In addition, software calculations will take up a large amount of instruction storage space. Since the execution of software depends on the CPU, the CPU needs to fetch instructions, decode instructions, execute, access storage and write back instructions to execute instructions. A complete set of calculations requires the participation of a large number of instructions, so it is inefficient and easily occupies a large amount of bus bandwidth, or the calculation will be interrupted by the bus access of other modules in the system. Since the software implementation of the transposition function requires intensive instructions, more storage space must be used to save instructions. However, the hardware accelerator with the transposition function is not very versatile and has a high design complexity. It is generally only used in a specific application scenario. Since the hardware accelerator is a dedicated circuit, it is difficult to meet all application scenarios. Even if the function can meet the requirements, it may not be economical in terms of hardware overhead. For example, in "A High-efficiency Matrix Transposition Cluster and Transposition Method Based on On-Chip Network", it is stipulated that the bus selection is AHB and the CPU selection is ARM, with specific equipment requirements. "Scalable Transform Hardware Architecture with Improved Transposition Buffer" is only applicable to the field of video decoding, and the solution also includes a data buffer, which is relatively complex.

[0017] In the field of NPU, we often encounter the transposition acceleration of small data, such as voice data. If we use software to implement transposition acceleration, it will occupy the CPU and the transposition speed will be slow; if we use the existing single transposition accelerator, it will be difficult to implement because of the large number of devices.

[0018] In response to the above technical problems, the transposition hardware acceleration system and method disclosed in the present invention pre-configures several transposition dimension registers to determine the dimensions of the corresponding transposed matrix; transposition enables triggering the corresponding several counters to count, and determines the count values ​​corresponding to the current several counters; data is read according to the current count values ​​of the several counters, the dimensions of the determined several transposed matrices, and the input data starting address, and data is written according to the current count values ​​of the several counters, the dimensions of the determined several transposed matrices, and the output data starting address, so as to realize the accelerated transposition of lightweight NPU data. Due to the use of hardware accelerators, the accelerated transposition speed is faster than that achieved by software; and the present application does not need to define a bus or a handshake signal, the transposition steps and devices are simple, the implementation is simple, and it has its own memory access logic, and does not require an additional memory controller.

[0019] Embodiment 1 of the present invention provides a specific implementation of a transposition hardware acceleration system, which is applicable to an embedded neural network processor. Figure 1, including several transposition dimension registers, an accelerated transposition module, and several memories; the accelerated transposition module includes several counters corresponding to the several transposition dimension registers and a memory control algorithm logic module; the accelerated transposition module is used to receive several transposition dimension registers, input data starting address, output data starting address and transposition enable, trigger several counters to count, and determine the current count values ​​corresponding to several counters; the memory control algorithm logic module is used to read data according to the current count values ​​of several counters, the dimensions of several determined transposition matrices and the input data starting address, and write data according to the current count values ​​of several counters, the dimensions of several determined transposition matrices and the output data starting address. Among them, the number of transposition dimension registers is the same as the number of counters. Among them, the input data starting address and the output data starting address are the corresponding addresses in several memories respectively.

[0020] Embodiment 2 of the present invention provides a specific implementation method of using the aforementioned transposition hardware acceleration system to implement the transposition hardware acceleration method, see Figure 2-Figure 5 , the transposition hardware acceleration method specifically includes the following steps: S100: pre-configuring a number of transposition dimension registers to determine the dimension of the corresponding transposition matrix; S200: The transposition enable triggers the corresponding counters to count, and determines the count values ​​corresponding to the current counters; wherein the maximum value of each counter is the same as the upper limit setting value of the range configured by the corresponding transposition dimension register.

[0021] S300: reading data according to current count values ​​of several counters, determined dimensions of several transposed matrices and input data starting addresses, and writing data according to current count values ​​of several counters, determined dimensions of several transposed matrices and output data starting addresses.

[0022] Wherein, step S200: the transposition enables triggering the corresponding counters to count, and determining the count values ​​corresponding to the current counters includes the following steps: S210: Triggering a number of corresponding counters to perform counting judgment according to the transposition enable; S220: Determine whether several counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register; when the judgment result is yes, the transposition is completed, the transposition ends, and all counters are cleared; when the judgment result is no, a nested loop corresponding to the number of counters is performed.

[0023] The step S300 of reading data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the input data starting addresses includes the following steps: S311: presetting a read address algorithm; S312: Each time determining whether a plurality of counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register, the current counting values ​​corresponding to the plurality of counters, the dimensions of the plurality of transposition matrices determined, and the starting address of the input data are substituted into a pre-set read address algorithm for calculation to obtain the current read address.

[0024] Wherein, writing data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the output data starting addresses in step S300 includes the following steps: S321: presetting a write address algorithm; S322: Each time it is determined whether several counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register, the current counting values ​​corresponding to several counters, the dimensions of several transposition matrices determined, and the output data starting address are substituted into the pre-set write address algorithm for calculation to obtain the current write address.

[0025] For example, Figure 6As shown, first configure the transposition dimension register to define the dimension of the transposed matrix, and then input a pulse signal through the external transposition enable interface to trigger the transposition function. After the transposition is completed, the hardware will automatically send a pulse signal to the outside through the transposition end interface. The figure below shows the flow chart of the transposition function. The configuration value of the transposition dimension register determines the maximum count value of the corresponding internal counter. The read and write addressing logic of the external memory is determined by the current count value of the internal counter, and the addressing logic algorithm can be combined according to the needs. Exemplarily, the value configured by each transposed dimension register, the current counter value, and the starting address value construct a read address algorithm: read address = read data starting address + (transposed dimension register 4 * transposed dimension register 3 * transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 4 + (transposed dimension register 3 * transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 3 + (transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 2 + (transposed dimension register 1 * transposed dimension register 0) * counter 1 + transposed dimension register 0 * counter 0. The transposed dimension register counting method includes: firstly judging whether counters 0, 1, 2, 3, and 4 have all counted to the set values ​​of the corresponding transposed dimension registers; if so, the transposition ends; if not, counters 0, 1, 2, 3, and 4 are judged respectively. Determine whether counter 0 counts to the set value of transposed dimension register 0. If not, counter 0 accumulates. If so, counter 1 accumulates and counter 0 is cleared. Determine whether counter 1 counts to the set value of transposed dimension register 1. If not, counter 1 accumulates. If so, counter 2 accumulates and counter 1 is cleared. Determine whether counter 2 counts to the set value of transposed dimension register 2. If not, counter 2 accumulates. If so, counter 3 accumulates and counter 2 is cleared. Determine whether counter 3 counts to the set value of transposed dimension register 3. If not, counter 3 accumulates. If so, counter 4 accumulates and counter 3 is cleared. Determine whether counter 4 counts to the set value of transposed dimension register 4. If not, counter 4 accumulates. If so, the transposition ends and counter 4 is cleared.

[0026] This application is a lightweight transposition hardware accelerator that can accelerate the transposition efficiency. The CPU does not need to be involved during operation, which solves the problem of low efficiency of software-implemented transposition functions and releases the CPU bandwidth. This product is not restricted by bus type and has flexible configuration. It is mainly used for data format conversion between NPU multi-layer networks, and supports data transposition and transportation in byte units at the minimum. The design block diagram is shown in the figure below. The top layer of the transposition module has a transposition dimension register 0 / 1 / 2 / 3 / 4 interface, the starting address of the input and output of the transposed data, a memory control interface, a transposition enable and a transposition end signal. The transposition dimension register is connected to the internal counter group, corresponding to counter 0 / 1 / 2 / 3 / 4. The internal memory control algorithm logic module uses the count value of the counter to generate an addressing signal to control the memory connected to the outside. The accessed address can be a different address of a single memory or two different memories. The specific connection form can be determined according to the architecture requirements and the type of memory. For example: a dual-port SRAM can be used, or two single-port SRAMs can be used. The access start and end addresses of the read and write memory can be defined by configuring the external input data start address register and output data start address register.

[0027] In summary, through the technical solution proposed by the present invention, a transposition hardware acceleration system and method are disclosed, by pre-configuring a number of transposition dimension registers to determine the dimension of the corresponding transposed matrix; the transposition enables triggering the corresponding counters to count, and determine the count values ​​corresponding to the current counters; data is read according to the current count values ​​of the counters, the dimensions of the determined transposed matrices, and the input data starting address, and data is written according to the current count values ​​of the counters, the dimensions of the determined transposed matrices, and the output data starting address, so as to realize the accelerated transposition of lightweight NPU data. Due to the use of hardware accelerators, the accelerated transposition speed is faster than that achieved by software; and the present application does not need to define a bus or a handshake signal, the transposition steps and devices are simple, the implementation is simple, and it has its own memory access logic, and does not require an additional memory controller.

[0028] The above description is only a description of the preferred embodiment of the technical solution of the present invention, and is not any limitation on the scope of the technical solution of the present invention. Any changes and modifications made by ordinary technicians in the field of the technical solution of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A transposition hardware acceleration system, characterized in that: It includes a number of transposition dimension registers, an accelerated transposition module, and a number of memories; The accelerated transposition module includes a plurality of counters corresponding to the plurality of transposition dimension registers one by one and a memory control algorithm logic module; The accelerated transposition module is used to receive the plurality of transposition dimension registers, the input data starting address, the output data starting address and the transposition enable, trigger the plurality of counters to count, and determine the count values ​​corresponding to the plurality of counters at present; The memory control algorithm logic module is used to read data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the input data starting address, and to write data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the output data starting address.

2. A transposition hardware acceleration system according to claim 1, characterized in that: The number of the transposition dimension registers is the same as the number of the counters.

3. A transposition hardware acceleration system according to claim 1, characterized in that: The input data starting address and the output data starting address are corresponding addresses in the plurality of memories respectively.

4. A transposition hardware acceleration method is implemented by applying a transposition hardware acceleration system as claimed in any one of claims 1 to 3, characterized in that: The steps include: Pre-configuring a number of transposed dimension registers to determine the dimensions of the corresponding transposed matrices; Transpose enables triggering corresponding counters to count, and determines the count values ​​corresponding to the current counters; Data is read according to the current count values ​​of the counters, the determined dimensions of the transposed matrices and the input data starting address, and data is written according to the current count values ​​of the counters, the determined dimensions of the transposed matrices and the output data starting address.

5. A transposition hardware acceleration method according to claim 4, characterized in that: The maximum value of each counter is the same as the upper limit setting value of the range configured by the corresponding transposition dimension register.

6. A transposition hardware acceleration method according to claim 5, characterized in that: The transposition enables triggering corresponding counters to count, and determining the current count values ​​corresponding to the counters comprises the following steps: Counting judgment is performed according to the corresponding counters triggered by the transposition enable; Determine whether the plurality of counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register; when the determination result is yes, complete the transposition, the transposition ends, and all the counters are cleared; When the judgment result is no, a nested loop corresponding to the number of counters is performed.

7. A transposition hardware acceleration method according to claim 6, characterized in that: The step of reading data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the input data starting addresses comprises the following steps: Preset the read address algorithm; Before determining whether the counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register each time, the current counting values ​​corresponding to the counters, the dimensions of the determined transposition matrices and the starting address of the input data are substituted into the preset read address algorithm for calculation to obtain the current read address.

8. A transposition hardware acceleration method according to claim 4, characterized in that: The step of writing data according to the current count values ​​of the counters, the dimensions of the determined transposed matrices and the output data starting addresses comprises the following steps: Preset write address algorithm; Before determining whether the counters have counted to the upper limit setting value of the range configured by the corresponding transposition dimension register each time, the current count values ​​corresponding to the counters, the dimensions of the determined transposition matrices and the output data starting address are substituted into the preset write address algorithm for calculation to obtain the current write address.

9. A transposition hardware acceleration system according to claim 4, characterized in that: The pre-set write address algorithm includes: read address = read data starting address + (transposed dimension register 4 * transposed dimension register 3 * transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 4 + (transposed dimension register 3 * transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 3 + (transposed dimension register 2 * transposed dimension register 1 * transposed dimension register 0) * counter 2 + (transposed dimension register 1 * transposed dimension register 0) * counter 1 + transposed dimension register 0 * counter 0.

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