Compiled multiport memory

Abstract

The present disclosure relates to a compiled multi-port memory. Certain aspects relate to a multi-port memory cell. The multi-port memory cell may include: an inverter circuit unit; a hold circuit unit having an output coupled to the input of the inverter circuit unit and an input coupled to the output of the inverter circuit unit; and a plurality of unit circuit cells having respective tri-state drivers wherein a first plurality of unit circuit cells of the plurality of unit circuit cells are configured as read circuit cells having inputs coupled to the outputs of the inverter circuit cells, and a second plurality of unit circuit cells of the plurality of unit circuit cells are configured as write circuit cells having an output coupled to the input of the inverter circuit cell.

Description

Technical Field

[0001] The present disclosure relates generally to memory architectures, and more particularly to multi-port memories. Background Art

[0002] Memory plays an important role in electronic devices such as smartphones and computers. In some implementations, a multi-port memory device can be used, which allows more than one access port to the memory cells. For example, a multi-port memory can include multiple read ports and multiple write ports for the memory cells. Different circuits of the system can use the read ports to perform simultaneous read operations from the memory cells. Summary of the invention

[0003] A simplified overview of one or more aspects of the present disclosure is given below in order to provide a basic understanding of such aspects. This overview is not an extensive overview of all expected features of the present disclosure, and is neither intended to identify key or important elements of all aspects of the present disclosure, nor is it intended to define the scope of any or all aspects of the present disclosure. Its sole purpose is to present some concepts of one or more aspects of the present disclosure in a simplified form as a prelude to a more detailed description presented later.

[0004] Certain aspects of the present disclosure relate to a multi-port memory cell. The multi-port memory cell may include: an inverter circuit unit; a holding circuit unit having an output coupled to an input of the inverter circuit unit and an input coupled to the output of the inverter circuit unit; and a plurality of unit circuit units having corresponding tri-state drivers, wherein a first plurality of unit circuit units among the plurality of unit circuit units are configured as a read circuit unit having an input coupled to the output of the inverter circuit unit, and a second plurality of unit circuit units among the plurality of unit circuit units are configured as a write circuit unit having an output coupled to the input of the inverter circuit unit.

[0005] Certain aspects of the present disclosure relate to a method for multi-port memory cell processing. The method generally includes: configuring a first plurality of unit circuit cells among a plurality of unit circuit cells as a read circuit cell by coupling an input of a first plurality of unit circuit cells among a plurality of unit circuit cells to an output of an inverter circuit cell, the plurality of unit circuit cells including corresponding tri-state drivers; and configuring a second plurality of unit circuit cells among a plurality of unit circuit cells as a write cell by coupling an output of a second plurality of unit circuit cells among a plurality of unit circuit cells to an input of an inverter circuit cell, wherein an output of a holding circuit cell is coupled to an input of the inverter circuit cell, and an input of the holding circuit cell is coupled to an output of the inverter circuit cell.

[0006] Certain aspects of the present disclosure relate to an apparatus for multi-port memory cell processing. The apparatus generally includes a memory; and one or more processors coupled to the memory, the one or more processors being configured to: configure a first plurality of unit circuit cells among a plurality of unit circuit cells as a read circuit cell by coupling an input of a first plurality of unit circuit cells among a plurality of unit circuit cells to an output of an inverter circuit cell, the plurality of unit circuit cells having corresponding tri-state drivers; and configure a second plurality of unit circuit cells among a plurality of unit circuit cells as a write cell by coupling an output of a second plurality of unit circuit cells among a plurality of unit circuit cells to an input of an inverter circuit cell, wherein an output of a holding circuit cell is coupled to an input of the inverter circuit cell and an input of the holding circuit cell is coupled to an output of the inverter circuit cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood according to the detailed description given below and the accompanying drawings of the embodiments of the present disclosure. The accompanying drawings are used to provide an understanding and appreciation of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, these drawings are not necessarily drawn to scale.

[0008] Figure 1 illustrates an example memory cell of a static random access memory (SRAM);

[0009] Figure 2A illustrates an example multi-port bit cell including a unit cell according to certain aspects of the present disclosure;

[0010] Figure 2B illustrates an example unit cell according to certain aspects of the present disclosure;

[0011] Figure 3A , Figure 3B , Figure 3C and Figure 3D An example implementation of a tri-state driver is illustrated;

[0012] Figure 4 illustrates a configurable multi-port memory implementation according to certain aspects of the present disclosure;

[0013] Figure 5 illustrates the physical layout of memory cells according to certain aspects of the present disclosure;

[0014] Figure 6 illustrates a physical layout of a memory cell having a mesh of nodes according to certain aspects of the present disclosure;

[0015] Figure 7 illustrates a physical layout with a unit cell implemented as a read unit according to certain aspects of the present disclosure;

[0016] Figure 8 illustrates a physical layout with a unit cell implemented as a write cell according to certain aspects of the present disclosure;

[0017] Fig. 9 and Fig.10 illustrates a wiring plan view of a bit cell according to certain aspects of the present disclosure;

[0018] Fig.11 is a flow chart illustrating example operations of a multi-port memory cell process according to certain aspects of the present disclosure;

[0019] Fig.12 An example set of processes used during the design, verification, and manufacture of an article of manufacture, such as an integrated circuit, to transform and verify design data and instructions representing the integrated circuit is illustrated; and

[0020] Fig.13 An example machine of a computer system is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. DETAILED DESCRIPTION

[0021] Certain aspects of the present disclosure relate to configurable multi-port memory implementations. The memory can be implemented with an inverter circuit unit and a holding circuit unit. The output of the inverter unit can be coupled to the input of the holding unit, and the input of the inverter unit can be coupled to the output of the holding unit. Therefore, the inverter unit and the holding unit form a latch of the memory. The memory can also include a plurality of unit cells that can be configured as a read unit or a write unit. For example, each of the unit cells can include a tri-state driver circuit. In order to configure the unit cell as a read unit, the input of the tri-state driver can be coupled to the output of the inverter unit, and in order to configure the unit cell as a write unit, the output of the tri-state driver can be coupled to the input of the inverter unit. Therefore, a memory compiler can be used to configure any number of unit cells as a read unit or a write unit by adjusting the coupling (e.g., wiring) of the input or output of the unit cell to the inverter unit. Various aspects of the present disclosure provide one or more technical advantages, such as reducing memory footprint. The memory architecture described herein (e.g., using a tri-state driver) reduces the number of lines used to implement a multi-port memory, thereby reducing the size of the memory, as described in more detail herein. In addition, the present disclosure provides a multi-port memory having unit cells that can be efficiently configured as read cells or write cells, thereby improving processing efficiency, design simplicity, and shortening the time to market of the multi-port memory. For example, based on user specifications, a memory compiler can configure a certain number of unit cells as read cells and a certain number of unit cells as write cells by adjusting the wiring of the unit cells as described herein.

[0022] Figure 1An example memory cell 100 of an SRAM is illustrated. As shown, the memory cell 100 may include a cross-coupled inverter pair 124 having an output 114 and an output 116. As shown, the output 114 of the cross-coupled inverter pair is selectively coupled to a bit line (BL) 106 via a pass-gate transistor 102, and the output 116 of the cross-coupled inverter pair is selectively coupled to a complementary bit line (BLB) 120 via a pass-gate transistor 118. BL 106 and BLB 120 are configured to provide complementary digital signals to be written (e.g., stored) in the cross-coupled inverter pair 124. BL and BLB can be used to store bits in the memory cell 100. As shown, the gates of the pass-gate transistors 102, 118 can be coupled to a word line (WL) 104. For example, a digital signal to be written can be provided to the BL (and the complement of the digital signal is provided to the BLB). Then, by providing a logic high signal to WL 104 , the pass-gate transistors 102 , 118 , implemented here as n-type field effect transistors (NFETs), are turned on, thereby storing the digital signal in the cross-coupled inverter pair 124 .

[0023] In some cases, a multi-port SRAM cell can be implemented. For example, the outputs 114, 116 can be selectively coupled to multiple read bit lines and write bit lines to implement multiple read ports and write ports. For example, multiple read operations can be performed simultaneously from the cell. Applications of multi-port memories include microprocessor caches, networking, artificial intelligence (AI) and machine learning, graphics processing, deoxyribonucleic acid (DNA) alignment, and neuromorphic or brain-inspired applications. With the increase in AI activities, high-order multi-port memories are becoming more and more popular.

[0024] Some multi-port cells may have many design issues, and adding ports will make the problems more complicated. Multi-port cells have problems associated with six-transistor (6T) SRAM cells (e.g., cell 100), such as read interference and write failures, which are further complicated by the asynchronous access mode of multiple ports to the same memory cell. For example, two read operations to the same memory cell can occur at the same time or slightly offset in time. The cell may need to respond in a manner covered by specific timing rules. All combinations and arrangements of skewed access must be protected, which makes the design of multi-port memories challenging and leads to a long time to market. In addition, high-order multi-port memories are often limited by lines. That is, the main reason for the large size of multi-port memories is the number of wires that must be wired for all ports of the memory. Therefore, reducing the transistor count may not reduce the cell size, and in fact, may lead to an increase in the cell area because this may lead to an increase in the number of wires that must be wired.

[0025] Certain aspects provide a compiled high-order multi-port (CHOMP) memory that can be implemented with two conductors per port (e.g., one conductor for a select line and one conductor for a data line). The memory architecture described herein provides a robust and disconnected feedback architecture (e.g., where the feedback from a holding unit to an input of an inverter unit is disconnected to facilitate write operations) to allow the memory to be implemented without read and write assist circuitry. In addition, the memory described herein can be implemented without a bit line precharge circuit and associated timing specifications. The memory architecture can operate according to a logic voltage domain (e.g., a power supply voltage for a logic circuit). The memory architecture can operate without dual rails or level converters to make the memory relatively less complex. The memory architecture described herein provides design simplicity, lower memory footprint, and shortened time to market.

[0026] Figure 2A An example multi-port bit cell 200 including a unit cell according to certain aspects of the present disclosure is illustrated. The bit cell 200 may include a memory element formed by a cross-coupled inverter 214 and a tri-state feedback driver 210. The bit cell 200 includes an inverter cell 206 (e.g., including an inverter 214) and a tri-state cell 202 (e.g., including a tri-state driver 210). The output of the tri-state driver 210 may be coupled to the input of the inverter 214, and the output of the inverter 214 may be coupled to the input of the tri-state driver 210 to form a latch.

[0027] The tri-state driver 210 (eg, corresponding to Figure 3A-3D 3 ) can receive a complementary enable signal (e.g., from a write enable WL). The complementary enable signal can also be provided to an inverter 212 (e.g., corresponding to inverter 312 of FIG. 3 ) to generate an enable signal provided to driver 210. Thus, when the complementary enable signal at the write enable WL is logic low, driver 210 can be enabled. Although complementary enable signals are used to enable or disable driver 210 (e.g., enabling driver 210 when the complementary enable signal is logic low), in some implementations, an enable signal can be used (e.g., enabling driver 210 when the enable signal is logic high).

[0028] The unit 200 may include m write units 204, where m is a positive integer indicating a configurable number of write ports. The unit 200 may also include n read units, where n is a positive integer indicating a configurable number of read ports. Each of the write units 204 includes a tri-state driver 220. The write unit 204 is activated by the corresponding m write word lines (WWL) to write data from the write data line (DT<0:m-1>). Each of the write word lines is used to enable the corresponding tri-state driver 220. For example, the write word line signal can be provided to the driver 220 as an enable signal, and can also be provided to the inverter 222 to generate a complementary enable signal for the driver 220. As shown, the output of the write unit 204 (e.g., the output of the driver 220) can be coupled to the input of the inverter unit 206 (e.g., the input of the inverter 214). The output of the inverter unit 206 (e.g., the output of the inverter 214) can be coupled to the input of the read unit 208. The circuitry used to implement each of the read cells 208 may be the same as the circuitry used to implement each of the write cells 204. For example, each of the read cells 208 includes a tri-state driver 216 having an input coupled to the output of the inverter cell 206. The read word line signal may be provided to the driver 216 as an enable signal and may also be provided to the inverter 218 to generate a complementary enable signal for the driver 216.

[0029] In some aspects, when any of the write word lines is activated, the write enable word line that controls the tri-state driver of the holding cell 202 is disabled, thereby interrupting the feedback to the input of the inverter 214 and allowing contention-free writing and avoiding SRAM ratio issues (e.g., issues caused by the strength ratio of the pull-up and pull-down transistors of the SRAM cell). In other words, when enabled, the tri-state driver 210 of the holding cell 202 uses feedback from the output of the inverter 214 to the input of the inverter 214 to maintain the logic value of the memory cell. When a new bit is to be written to the cell, the tri-state driver 210 can be disabled (e.g., via a write enable WL) to allow the bit to be written to the cell 200.

[0030] like Figure 2A As shown, the write WL for the write unit may be coupled to the input of the OR gate 249, wherein the output of the OR gate 249 is used as the write enable WL of the holding unit 202. That is, if any one of the write WL signals transitions to logic high for a write operation, the write enable WL signal may transition to logic high to disable the tri-state driver 210 of the holding unit 202.

[0031] By using the same circuitry for both the read and write cells, the read and write cells can be interchanged, thereby achieving memory configurability. In other words, the same cell can be used as a read cell or a write cell, depending on whether the input of the cell is coupled to the inverter cell 206 or the output of the cell is coupled to the inverter cell 206.

[0032] Figure 2B An example unit cell 265 (e.g., corresponding to write cell 204 or read cell 208) is illustrated in accordance with certain aspects of the present disclosure. Unit cell 265 may include a tri-state driver 272 (e.g., corresponding to driver 220 or 216) and an inverter 270 (e.g., corresponding to inverter 222 or 218). As shown, unit cell 265 may include a gate region 274 (e.g., labeled "T" and corresponding to an input of inverter 272), portions of which are disposed over respective portions of channels 280, 282. As shown, unit cell 265 may include gate regions 276, 286, wherein portions of gate regions 276, 286 are disposed over portions of channels 280, 282, respectively. Gate region 276 may serve as a complementary enable to driver 272 (e.g., in Figure 2B Marked as " W ”), and gate region 286 can be used as an enable for driver 272 (at Figure 2B One end of the channel 280 may be coupled to a voltage rail (e.g., Vdd, Figure 2B ), and one end of the channel 282 may be coupled to electrical ground (e.g., at Figure 2B The other ends of the channels 280 may be coupled together and used as the output of the tri-state driver 272 (e.g., Figure 2B To implement inverter 270, unit cell 265 includes gate region 278 (e.g., coupled to gate region 286 for enable input), portions of which are disposed over respective portions of channels 284, 288. As shown, one end of channel 284 can be coupled to a voltage rail (labeled "V"), and one end of channel 288 can be coupled to electrical ground (labeled "G"). The other ends of channels 284, 288 can be coupled together and to complementary enable inputs of driver 272 (labeled " W ”).

[0033] Figure 3A and Figure 3BAn example implementation of a tri-state driver 300 (e.g., corresponding to tri-state driver 210) is illustrated. The tri-state driver may include an input p-type metal oxide semiconductor (PMOS) transistor 304 and an input n-type metal oxide semiconductor (NMOS) transistor 306. As shown, the gates of transistors 304, 306 may be coupled to an input node of tri-state driver 300, with drains of transistors 304, 306 coupled to an output node of driver 300.

[0034] The driver 300 includes an enabling PMOS transistor 302 having a drain coupled to the source of transistor 304 and a source coupled to a voltage rail Vdd. The driver 300 also includes an enabling NMOS transistor 308 having a drain coupled to the source of transistor 306 and a source coupled to a reference potential node (e.g., electrically grounded). The gates of transistors 302, 308 can be controlled to enable the tri-state driver 300. For example, when the gate of transistor 302 is driven by a logic low signal and the gate of transistor 308 is driven by a logic high signal, the tri-state driver is enabled. When enabled, the output signal of the driver 300 is equal to the inverted signal of the input signal of the driver 300. When the gate of transistor 302 is driven by a logic high signal and the gate of transistor 308 is driven by a logic low signal, the tri-state driver is disabled. When disabled, the output of the driver 300 is in a high impedance state. The gate of transistor 308 may be driven by an enable signal (En), and the gate of transistor 302 may be driven by a complementary enable signal (En). Drive. Figure 3A As shown, the enable signal may be provided to the gate of transistor 308 and the input of inverter 310 (eg, corresponding to inverter 218 or inverter 222) to generate a complementary enable signal at the gate of transistor 302. In some aspects, as shown Figure 3B As shown, the complementary enable signal may be provided to the gate of transistor 302 and the input of inverter 312 (e.g., corresponding to inverter 212) to generate an enable signal at the gate of transistor 308. For example, the complementary enable signal may correspond to a write enable WL signal for enabling or disabling tri-state driver 210.

[0035] Figure 3C and Figure 3DAnother example implementation of a tri-state driver 350 (e.g., corresponding to tri-state driver 210) is illustrated. The tri-state driver may include an input PMOS transistor 354 and an input NMOS transistor 356. As shown, the gates of transistors 354, 356 may be coupled to the input node of tri-state driver 350, with the drains of transistors 354, 355 coupled to the respective sources of enable transistors 352, 358. The sources of transistors 354, 356 are coupled to a voltage rail Vdd and electrical ground, respectively.

[0036] The drains of enable transistors 352, 358 may be coupled to the output node of driver 350. The gates of transistors 352, 358 may be controlled to enable tri-state driver 350. For example, when the gate of transistor 352 is driven by a logic low signal and the gate of transistor 358 is driven by a logic high signal, the tri-state driver is enabled. When enabled, the output signal of driver 350 is equal to the inverted signal of the input signal of driver 350. When the gate of transistor 352 is driven by a logic high signal and the gate of transistor 358 is driven by a logic low signal, the tri-state driver is disabled. When disabled, the output of driver 350 is in a high impedance state. The gate of transistor 358 may be driven by an enable signal (En), and the gate of transistor 352 may be driven by a complementary enable signal (En). Drive. Figure 3C As shown, the enable signal can be provided to the gate of transistor 358 and the input of inverter 310 to generate a complementary enable signal at the gate of transistor 352. Figure 3D As shown, the complementary enable signal may be provided to the gate of transistor 352 and the input of inverter 312 to generate an enable signal at the gate of transistor 358 .

[0037] Figure 4A configurable multi-port memory implementation 400 according to certain aspects of the present disclosure is illustrated. As shown, a multi-port memory of any size can be implemented using a certain number of programmable read cells or write cells, holding cells, and inverter cells. For example, a 23-port memory can be implemented using 5×5 cells, an 18-port memory can be implemented using 4×5 cells, a 14-port memory can be implemented using 4×4 cells, a 10-port memory can be implemented using 3×4 cells, a 7-port memory can be implemented using 3×3 cells, and a 4-port memory can be implemented using 2×3 cells. For example, a 3×4 cell configuration 404 can include a holding cell (marked as "H"), an inverter cell (marked as "I"), 8 read cells (marked as "R"), and 2 write cells (marked as "W") to implement a multi-port memory with 8 read ports and 2 write ports. The holding cell and the inverter cell form a latch of the memory cell. Each read cell or write cell can be programmed (e.g., wired) as a read port or a write port to provide various read / write configurations.

[0038] Figure 5 A physical layout 500 of a 3×3 cell according to certain aspects of the present disclosure is illustrated. As shown, the physical layout 500 includes a holding cell 502 , an inverter cell 518 , and a plurality of read cells or write cells 504 , 506 , 508 , 510 , 512 , 514 , 516 .

[0039] Figure 6 A physical layout 500 with a mesh of nodes according to certain aspects of the present disclosure is illustrated. For example, the layout 500 includes traces 608, 610, 612 for implementing nodes of a memory cell (referred to herein as true nodes), and traces 602, 604, 606 for implementing complementary nodes. Trace 614 is used to couple traces 602, 604, 606 together, and trace 616 is used to couple traces 608, 610, 612 together. As shown, the true node can be coupled to the output of the inverter 214 and the input of the tri-state driver 210, and the complementary node can be coupled to the output of the tri-state driver 210 and the input of the inverter 214 to form a latch of the memory cell.

[0040] Traces 602, 604, 606, 608, 610, 612 may be routed on a metal zero (M0) layer of a multi-layer substrate, and traces 614, 616 may be routed on a metal one (M1) layer of a multi-layer substrate. The node mesh routes true and complementary nodes to each unit cell so that they can be used to program each unit cell as a read port or a write port.

[0041] Figure 7A physical layout 500 is illustrated in accordance with certain aspects of the present disclosure, wherein a cell 504 is implemented as a read cell. As shown, a true node (e.g., trace 612) can be coupled to an input of a tri-state driver 704 (e.g., corresponding to tri-state driver 216). In addition, a trace of a read data line 702 can be coupled to an output of the tri-state driver 704.

[0042] Figure 8 A physical layout 500 is illustrated in accordance with certain aspects of the present disclosure, wherein a cell 504 is implemented as a write cell. As shown, a complementary node (e.g., trace 606) can be coupled to an output of a tri-state driver 804 (e.g., corresponding to tri-state driver 220). In addition, a trace of a write data line 802 can be coupled to an input of the tri-state driver 804. In this manner, each of the cells 504, 506, 508, 510, 512, 514, 516 can be configured as a read cell or a write cell.

[0043] As described herein, each cell may include a local inverter (e.g., inverter 222), with one trace (e.g., wire) for each port. By adding an inverter to each cell, the number of traces (e.g., wires) may be reduced. Without a local inverter within each cell, three wires (instead of two) may be used for each port, one for the write or read data line, one for the enable signal, and one for the complementary enable signal. Figure 2B As shown in the layout in , local inverters (e.g., inverter 270) and tri-state drivers (e.g., tri-state driver 272) employ four polysilicon pitches and share power (e.g., Vdd) and ground to allow each unit cell to be placed anywhere in the arrangement for memory.

[0044] Fig. 9 and Fig.10 A wiring plan view of a 5×5 bit cell 900 in accordance with certain aspects of the present disclosure is illustrated. As shown, six traces 902 (e.g., on the metal two (M2) layer) can be used to support five columns of unit cells. The number of wiring tracks limits the number of unit cells that can be accommodated in the X dimension of the memory cell. The word lines (labeled "WL" for the first row of cells) are wired on the M2 layer and then coupled to each cell using vias. The word lines are pre-connected to each cell and can be used as read word lines or write word lines, which is determined by the unit cell programming, as described herein.

[0045] As shown, a write enable word line can be used to control a hold unit 904 and is activated when any of the write word lines (e.g., m write word lines provided to driver 220) is activated, as described herein. A routing track (e.g., labeled "data line jumper") can be used for each cell to provide a route for the data line (e.g., on the metal three (M3) layer) from the M3 layer down through the M2 layer to the unit cell. Fig.10 As shown, 23 data lines can be used for bit cell 900. As described, the data lines can be routed on the M3 layer. For example, five data lines 1002 can be routed for the five cells of the first column. Each data line can be routed above the corresponding unit cell of the first column and routed down to the unit cell on the M1 layer using a via. Depending on the programming of the unit cell, each data line can be programmed as a read data line or a write data line. The number of unit cells in each column corresponds to the number of write tracks that can be routed for each cell. As shown, for a column including a holding cell 904, a voltage track line 1004 can be routed (e.g., replacing a data line that should be routed for a read cell or a write cell), and for a column including an inverter cell 1008, a ground (GND) track line 1006 can be routed (e.g., replacing a data line that should be routed for a write cell or a read cell).

[0046] Fig.11 1329. is a flow diagram illustrating example operations 1100 for multi-port memory cell processing in accordance with certain aspects of the present disclosure. Operations 1100 may be performed by, for example, a memory compiler (such as memory compiler 1329).

[0047] At 1102, the compiler may generate a plurality of unit circuit cells by converting a first plurality of unit circuit cells (eg, Figure 5 The input of the first subset of unit cells 504, 506, 508, 510, 512, 514, 516 is coupled to the output of the inverter circuit unit (for example, the inverter unit 518), and the first plurality of unit circuit units among the plurality of unit circuit units are configured as read circuit units, and the plurality of unit circuit units include corresponding three-state drivers (for example, the three-state driver 216 or 220 shown in Figure 2).

[0048] At 1104, the compiler may generate a plurality of unit circuit cells (eg, Figure 5The output of the holding circuit unit (e.g., the holding unit 502) is coupled to the input of the inverter circuit unit, and the second plurality of unit circuit units in the plurality of unit circuit units are configured as write circuit units. The output of the holding circuit unit (e.g., the holding unit 502) can be coupled to the input of the inverter circuit unit, and the input of the holding circuit unit can be coupled to the output of the inverter circuit unit. In some aspects, the holding circuit unit may include a tri-state driver (e.g., the tri-state driver 210). The compiler may configure the tri-state driver of the holding circuit unit to be disabled (e.g., via the write enable WL shown in FIG. 2 ) based on one of the write circuit units being enabled.

[0049] In some aspects, the first node may include a first plurality of traces (e.g., traces 608, 610, 612) routed adjacent to the plurality of unit circuit cells. The second node may include a second plurality of traces (e.g., traces 602, 604, 606) routed adjacent to the plurality of unit circuit cells. In some aspects, to configure a first plurality of unit circuit cells in the plurality of unit circuit cells as a read cell, the compiler may couple the first node to a tri-state driver (e.g., Figure 7 To configure a second plurality of unit circuit cells among the plurality of unit circuit cells as a write circuit cell, the compiler may couple the second node to an output of a tri-state driver (e.g., tri-state driver 804) of the second plurality of unit circuit cells among the plurality of unit circuit cells.

[0050] In some aspects, to configure a first plurality of unit circuit cells among the plurality of unit circuit cells as a read circuit cell, the compiler may configure a read data line (eg, Figure 7 In some aspects, the compiler may couple a read data line 702 of the write data line 802 to the output of each of the three-state drivers of the first plurality of unit circuit units in the plurality of unit circuit units. In order to configure the second plurality of unit circuit units in the plurality of unit circuit units as a write circuit unit, the compiler may couple a write data line (e.g., write data line 802) to the input of each of the three-state drivers of the second plurality of unit circuit units in the plurality of unit circuit units. In some aspects, in order to configure the second plurality of unit circuit units in the plurality of unit circuit units as a write circuit unit, the compiler may couple a word line to the corresponding enable input of the three-state driver of the second plurality of unit circuit units in the plurality of unit circuit units. In some aspects, the three-state driver of the holding circuit unit may be configured to be disabled based on a signal at the word line.

[0051] Fig.12An example set of processes 1200 used during the design, verification, and manufacture of an article such as an integrated circuit to transform and verify design data and instructions representing the integrated circuit is illustrated. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA" represents the term "electronic design automation." These processes begin with the creation of a product idea 1210 using information provided by a designer, which is transformed to create an article using a set of EDA processes 1212. When the design is finalized, the design is taped out 1234, which is when the artwork (e.g., geometric pattern) for the integrated circuit is sent to a manufacturing facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die 1236 are manufactured, and packaging and assembly processes 1238 are performed to produce a finished integrated circuit 1240.

[0052] The specification of a circuit or electronic structure can range from a low-level transistor material layout to a high-level description language. The high-level representation can be used to design circuits and systems using a hardware description language ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation as a more detailed description adds more useful detail to the design description, for example, more detail of the modules that comprise the description. The lower-level representation as a more detailed description can be computer-generated, derived from a design library, or created by another design automation process. An example of a lower-level specification language for specifying a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The descriptions at each level of representation can be used by the corresponding tools for that layer (e.g., formal verification tools). The design process can use Fig.12 The sequence shown. The described process is implemented by an EDA product (or tool).

[0053] During system design 1214, the functionality of the integrated circuit to be manufactured is specified. For example, a compiler can be used to generate a design for a memory, as described herein. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. The design can be divided into different types of modules or components at this stage.

[0054] During logic design and functional verification 1216, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, the components of a circuit can be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components called "emulators" or "prototyping systems" are used to speed up functional verification.

[0055] During synthesis and design for testing 1218, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0056] During netlist verification 1220, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 1222, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0057] During layout or physical implementation 1224, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) occur, and selection of cells from the library to enable specific logic functions can be performed. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components, and are enabled as both physical structures and simulations. Parameters (based on "standard cells"), such as size, are specified for the selected cell, and it is made accessible in a database for use by EDA products.

[0058] During analysis and extraction 1226, circuit functionality is verified at the layout level, which allows the layout design to be refined. During physical verification 1228, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 1230, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0059] During tape-out, data is created to be used to produce lithography masks (after applying lithography enhancements where appropriate). During mask data preparation 1232, the "tape-out" data is used to produce lithography masks, which are used to produce finished integrated circuits.

[0060] Computer systems (such as Fig.13 The storage subsystem of the computer system 1300) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and physical and logical design products that use the libraries.

[0061] Fig.13 An example machine of a computer system 1300 is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0062] The machine may be a personal computer (PC), a tablet, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequence, etc.) that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0063] The example computer system 1300 includes a processing device 1302, a main memory 1304 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), a static memory 1306 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage device 13113, which communicate with each other via a bus 1330.

[0064] The processing device 1302 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1302 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 1302 can be configured to execute instructions 1326 for performing the operations and steps described herein.

[0065] The computer system 1300 may also include a network interface device 1308 for communicating over a network 1320. The computer system 1300 may also include a video display unit 1310 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1312 (e.g., a keyboard), a cursor control device 1314 (e.g., a mouse), a graphics processing unit 1322, a signal generating device 1316 (e.g., a speaker), a graphics processing unit 1322, a video processing unit 1328, and an audio processing unit 1332.

[0066] The data storage device 1318 may include a machine-readable storage medium 1324 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 1326 or software embodying any one or more of the methods or functions described herein. During execution of the instructions 1326 by the computer system 1300, the instructions may also reside completely or at least partially within the main memory 1304 and / or within the processing device 1302, the main memory 1304 and the processing device 1302 also constituting machine-readable storage media.

[0067] In some implementations, the instructions 1326 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 1324 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode instruction sets for machine execution and cause the machine and processing device 1302 to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0068] In some aspects of the disclosure, the processing device 1302 may include a memory compiler 1329. According to certain aspects of the disclosure, the memory compiler 1329 may generate a representation of a memory.

[0069] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. Operations are those that require physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0070] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise clearly indicated from this disclosure, it should be understood that throughout the description certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0071] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0072] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program in accordance with the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0073] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, and the instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.

[0074] In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific example implementations thereof. It is clear that various modifications may be made thereto without departing from the broader spirit and scope of implementation of the present disclosure as set forth in the following claims. Where the present disclosure relates to some elements in the singular tense, more than one element may be depicted in the accompanying drawings, and similar elements are marked with similar numbers. Therefore, the present disclosure and the accompanying drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A multi-port memory cell, comprising: Inverter circuit unit; A holding circuit unit having: an output coupled to an input of the inverter circuit unit; and an input coupled to an output of said inverter circuit unit; as well as A plurality of unit circuit units having corresponding three-state drivers, wherein a first plurality of unit circuit units among the plurality of unit circuit units are configured as read circuit units having an input coupled to the output of the inverter circuit unit, and a second plurality of unit circuit units among the plurality of unit circuit units are configured as write circuit units having an output coupled to the input of the inverter circuit unit. 2 . The multi-port memory cell according to claim 1 , wherein the holding circuit unit comprises a tri-state driver. 3 . The multi-port memory cell according to claim 2 , wherein when one of the write circuit units is enabled, the tri-state driver of the holding circuit unit is disabled. 4 . The multi-port memory cell according to claim 2 , wherein the holding circuit unit further comprises an inverter coupled between an enable input and a complementary enable input of the tri-state driver of the holding circuit unit. 5 . The multi-port memory cell of claim 1 , wherein each of the plurality of unit circuit cells comprises an inverter coupled between an enable input and a complementary enable input of a corresponding one of the tri-state drivers.

6. The multi-port memory cell according to claim 1, further comprising: a first node comprising a first plurality of traces routed adjacent to the plurality of unit circuit cells; as well as A second node includes a second plurality of traces routed adjacent to the plurality of unit circuit cells, wherein the second node is configured to route a signal complementary to the signal routed by the first node.

7. The multi-port memory cell of claim 6, wherein the first of the plurality of unit circuit cells is configured as a read unit by coupling the first node to an input of the tri-state driver of the first of the plurality of unit circuit cells.

8. The multi-port memory cell of claim 6, wherein the second plurality of unit circuit cells among the plurality of unit circuit cells are configured as write cells by coupling the second node to outputs of the tri-state drivers of the second plurality of unit circuit cells among the plurality of unit circuit cells.

9. A multi-port memory cell according to claim 1, wherein the first plurality of unit circuit cells among the plurality of unit circuit cells are configured as read cells by coupling a read data line to the output of each of the three-state drivers of the first plurality of unit circuit cells among the plurality of unit circuit cells.

10. A multi-port memory cell according to claim 1, wherein the second plurality of unit circuit cells among the plurality of unit circuit cells are configured as write circuit cells by coupling a write data line to the input of each of the three-state drivers of the second plurality of unit circuit cells among the plurality of unit circuit cells.

11. The multi-port memory cell of claim 1 , wherein the second plurality of unit circuit cells among the plurality of unit circuit cells are configured as write cells by coupling a word line to respective enable inputs of the tri-state drivers of the second plurality of unit circuit cells among the plurality of unit circuit cells.

12. The multi-port memory cell of claim 11, further comprising an OR gate, wherein the word line is further coupled to an input of the OR gate, and wherein an output of the OR gate is coupled to an enable input of the holding circuit unit.

13. A method for multi-port memory cell processing, comprising: configuring a first plurality of unit circuit cells among the plurality of unit circuit cells as a read circuit cell by coupling inputs of the first plurality of unit circuit cells among the plurality of unit circuit cells to outputs of an inverter circuit cell, the plurality of unit circuit cells including corresponding tri-state drivers; as well as The second plurality of unit circuit units among the plurality of unit circuit units are configured as write units by coupling the output of the second plurality of unit circuit units among the plurality of unit circuit units to the input of the inverter circuit unit, wherein the output of the holding circuit unit is coupled to the input of the inverter circuit unit, and the input of the holding circuit unit is coupled to the output of the inverter circuit unit. The method according to claim 13 , wherein the holding circuit unit comprises a tri-state driver. 15 . The method of claim 14 , further comprising configuring the tri-state driver of the holding circuit unit to be disabled based on one of the writing units being enabled.

16. The method of claim 13, wherein: The first node includes a first plurality of traces routed adjacent to the plurality of unit circuit cells; and the second node comprising a second plurality of traces routed adjacent to the plurality of unit circuit cells; Configuring the first of the plurality of unit circuit cells as a read circuit cell includes: coupling the first node to an input of the tri-state driver of the first of the plurality of unit circuit cells; and Configuring the second plurality of unit circuit cells among the plurality of unit circuit cells as write circuit cells includes coupling the second node to outputs of the tri-state drivers of the second plurality of unit circuit cells among the plurality of unit circuit cells.

17. The method according to claim 13, wherein configuring the first of the plurality of unit circuit cells as a read circuit cell comprises: A read data line is coupled to an output of each of the tri-state drivers of the first plurality of unit circuit cells of the plurality of unit circuit cells.

18. The method according to claim 13, wherein configuring the second plurality of unit circuit cells among the plurality of unit circuit cells as write circuit cells comprises: A write data line is coupled to an input of each of the tri-state drivers of the second plurality of unit circuit cells of the plurality of unit circuit cells.

19. The method of claim 13, wherein: Configuring the second plurality of unit circuit cells among the plurality of unit circuit cells as write circuit cells comprises: coupling word lines to respective enable inputs of the tri-state drivers of the second plurality of unit circuit cells among the plurality of unit circuit cells; and The tri-state driver of the retention circuit unit is configured to be disabled based on a signal at the word line.

20. An apparatus for multi-port memory cell processing, comprising: Memory; as well as one or more processors coupled to the memory, the one or more processors configured to: configuring a first plurality of unit circuit cells among the plurality of unit circuit cells as a read circuit cell by coupling inputs of the first plurality of unit circuit cells among the plurality of unit circuit cells to outputs of an inverter circuit cell, the plurality of unit circuit cells including corresponding tri-state drivers; as well as The second plurality of unit circuit units among the plurality of unit circuit units are configured as write units by coupling the output of the second plurality of unit circuit units among the plurality of unit circuit units to the input of the inverter circuit unit, wherein the output of the holding circuit unit is coupled to the input of the inverter circuit unit, and the input of the holding circuit unit is coupled to the output of the inverter circuit unit.

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