Operational amplifier input stage transconductance constant circuit and rail-to-rail input stage system

Abstract

The invention provides an operational amplifier input stage transconductance constant circuit and a rail-to-rail input stage system, and relates to integrated circuit design. The circuit at least comprises a tail current adjusting module, and the tail current adjusting module comprises a plurality of MOS tubes. Wherein the plurality of MOS tubes comprise a target MOS tube, and the other MOS tubes respectively provide different bias voltages for the target MOS tube, so that the target MOS tube generates a preset bias voltage, and further the input stage differential structure, such as a P-type input geminate transistor assembly or an N-type input geminate transistor assembly, generates a corresponding preset tail current, so as to drive the input stage transconductance to keep consistent in each working area. Based on this, the invention can provide a preset bias voltage for the P-type input geminate transistor assembly or the N-type input geminate transistor assembly by setting the structures and / or settings of different MOS transistors under the tail current adjustment module, thereby ensuring that the transconductance of the input stage is kept constant.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an operational amplifier input stage transconductance constant circuit and a rail-to-rail input stage system. Background Art

[0002] As the integration of integrated circuits becomes higher and higher, the operating voltage of the op amp becomes lower and lower, but the threshold voltage of the above op amp does not decrease. At the same time, the common-mode input range of the op amp becomes smaller and smaller, and the rail-to-rail input / output op amp tail current circuit comes into being.

[0003] Typically, the tail current circuit of a rail-to-rail input / output op amp must have a constant gain-bandwidth product over the entire common-mode range. In order to obtain a constant unity gain frequency over the entire common-mode input range, the input stage transconductance must remain constant. In the prior art, the triple current mirror method is often used to keep the transconductance constant, that is, by achieving constant transconductance in the full N-type field effect transistor working area, the full P-type field effect transistor working area, and the midpoint of the switching area.

[0004] However, the triple current mirror method cannot further reduce the variation of transconductance in the entire switching area. When considering chip characteristics, such as PVT characteristics (Process, Voltage, Temperature), that is, the difference in chip performance under different voltage, temperature and process conditions, the variation of transconductance in the entire switching area is even greater, even exceeding 15%.

[0005] Based on this, there is an urgent need for a solution to improve the tail current generation method in the transition region to further reduce the change value of the transconductance and keep the input stage transconductance constant. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide an operational amplifier input stage transconductance constant circuit and a rail-to-rail input stage system, which can provide a preset bias voltage for a P-type input pair tube component or an N-type input pair tube component by setting the structure and / or setting of different MOS tubes under the tail current adjustment module, and improve the transition region tail current generation method according to the square law relationship to ensure that the input stage transconductance remains constant.

[0007] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0008] In a first aspect, the present invention provides an operational amplifier input stage transconductance constant circuit, comprising a P-type input pair tube component, an N-type input pair tube component and a tail current adjustment module; the tail current adjustment module comprises a plurality of MOS tubes; wherein,

[0009] The multiple MOS tubes include a target MOS tube, and the remaining MOS tubes except the target MOS tube respectively provide different bias voltages for the target MOS tube, so that the target MOS tube generates a preset bias voltage;

[0010] A target MOS tube, used for providing a preset bias voltage to the P-type input pair tube component or the N-type input pair tube component;

[0011] A P-type input pair transistor assembly, used to generate a first preset tail current according to a preset bias voltage in a first working region, so that the input operational amplifier transconductance remains consistent in each working region;

[0012] or an N-type input pair tube assembly, used to generate a second preset tail current according to a preset bias voltage in a second working region, so that the input stage transconductance remains consistent in each working region;

[0013] The first working region is used to represent that the P-type input pair tube component works completely; the second working region is used to represent that the N-type input pair tube component works completely.

[0014] Optionally, when the op amp input stage transconductance constant circuit is in the first working region, the remaining MOS transistors respectively provide different bias voltages for the target MOS transistor to generate a first bias voltage and a second bias voltage respectively;

[0015] Among them, the expression of the preset bias voltage satisfies:

[0016] V BS =V gs2 -V gs1 +V TH ;

[0017]

[0018] Among them, V BS is the preset bias voltage; V gs1 is the first bias voltage; V gs2 is the second bias voltage; V TH is the threshold voltage; I p is the tail current corresponding to the P-type input pair tube assembly in the first working area; I0 is the fixed tail current; k n is the first parameter associated with the N-type input pair tube assembly.

[0019] Optionally, the P-type input pair transistor component is further used to generate a second preset tail current according to a preset bias voltage in the first working region based on the square law characteristics of the MOS transistor;

[0020] The calculation formula of the second preset tail current satisfies:

[0021]

[0022] Among them, I n* is the second preset tail current.

[0023] Optionally, all other MOS tubes except the target MOS tube or one of the MOS tubes in the target MOS tube is in a weak inversion region.

[0024] Optionally, the remaining MOS tubes include a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a sixth MOS tube and a seventh MOS tube; the target MOS tube includes a fifth MOS tube;

[0025] The first end of the first MOS tube is connected to the second end of the fifth MOS tube and the second end of the sixth MOS tube; the second end of the first MOS tube is connected to the first end of the second MOS tube; the second end of the second MOS tube is connected to the second end and the control end of the third MOS tube; the control end of the third MOS tube is also connected to the control end of the fourth MOS tube; the second end of the fourth MOS tube is connected to the first end of the fifth MOS tube; the control end of the fifth MOS tube is connected to the control end and the second end of the sixth MOS tube; the second end of the sixth MOS tube is also connected to the second end and the control end of the seventh MOS tube; the first end of the third MOS tube, the first end of the fourth MOS tube, and the first end of the seventh MOS tube are all grounded;

[0026] Among them, the fifth MOS tube is in a weak inversion region.

[0027] Optionally, the tail current adjustment module also includes a first power supply unit, which includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and an eleventh MOS tube; the first end of the eighth MOS tube and the first end of the ninth MOS tube are connected to the power supply; the control end of the eighth MOS tube is respectively connected to the control end of the ninth MOS tube and the second end of the eleventh MOS tube; the second end of the eighth MOS tube is respectively connected to the second end and the control end of the tenth MOS tube; the control end of the tenth MOS tube is also connected to the control end of the eleventh MOS tube; the first end of the eleventh MOS tube is grounded through a first resistor; and the first end of the tenth MOS tube is grounded.

[0028] Optionally, the remaining MOS tubes include an operational amplifier unit and a second power supply unit, the second power supply unit includes multiple different outputs, and under the condition that the operational amplifier unit includes two inputs, each input is respectively connected to one of the outputs of the second power supply unit, wherein each input is respectively connected to a different output, so that the operational amplifier unit generates a preset voltage difference;

[0029] The target MOS tube is also used to generate a preset bias voltage according to a preset voltage difference.

[0030] Optionally, the operational amplifier unit includes an operational amplifier and a resistor module, the resistor module includes a second resistor, a third resistor and a fourth resistor, the remaining MOS tubes include a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube, and the target MOS tube includes an eighteenth MOS tube;

[0031] The first end of the second resistor and the second end of the fourteenth MOS tube are used to receive the first input voltage, and the second end of the second resistor is respectively connected to the first input end of the operational amplifier and the first end of the third resistor; the second input end of the operational amplifier is used to receive the second input voltage, and the second end of the third resistor is connected to the second end of the twelfth MOS tube; the first end of the twelfth MOS tube is connected to the first end of the thirteenth MOS tube and the first end of the fourteenth MOS tube, and the control end of the twelfth MOS tube, the control end of the thirteenth MOS tube and the control end of the fourteenth MOS tube are used to receive the third bias voltage, and the control end of the twelfth MOS tube is also connected to the output end of the operational amplifier, and the second end of the thirteenth MOS tube is respectively connected to the second end and the control end of the fifteenth MOS tube; the second end of the fourteenth MOS tube is respectively connected to the second end of the sixteenth MOS tube, the second end of the seventeenth MOS tube and the control end of the seventeenth MOS tube through the fourth resistor; the control end of the sixteenth MOS tube is connected to the control end and the second end of the fifteenth MOS tube; the first end of the fifteenth MOS tube is respectively connected to the first end of the sixteenth MOS tube, the first end of the seventeenth MOS tube and the first end of the eighteenth MOS tube, and is grounded;

[0032] The resistance values ​​of the second resistor, the third resistor and the fourth resistor are all equal; and the seventeenth MOS transistor is in a weak inversion region.

[0033] Optionally, the remaining MOS tubes also include a nineteenth MOS tube, a twentieth MOS tube and a twenty-first MOS tube, the first end of the twenty-first MOS tube is connected to the first end of the twelfth MOS tube; the control end of the twenty-first MOS tube is used to receive a fourth bias voltage, the second end of the twenty-first MOS tube is connected to the first input end of the operational amplifier, the second end of the twentieth MOS tube and the control end of the twentieth MOS tube; the first end of the nineteenth MOS tube receives a fixed tail current, and the first end of the nineteenth MOS tube is also connected to the second input end of the operational amplifier and the control end of the nineteenth MOS tube; the first end of the twentieth MOS tube and the first end of the nineteenth MOS tube are both grounded.

[0034] In a second aspect, the present invention further provides a rail-to-rail input stage system, comprising the operational amplifier input stage transconductance constant circuit as described in any one of the first aspects above.

[0035] The operational amplifier input stage transconductance constant circuit and rail-to-rail input stage system provided by the embodiments of the present invention have the following beneficial effects:

[0036] The op amp input stage transconductance constant circuit in the present invention includes a P-type input pair tube component, an N-type input pair tube component and a tail current adjustment module. The tail current adjustment module includes a plurality of MOS tubes; wherein, the plurality of MOS tubes include a target MOS tube, and the remaining MOS tubes respectively provide different bias voltages for the target MOS tube, so that the target MOS tube generates a preset bias voltage. The target MOS tube provides a preset bias voltage to the P-type input pair tube component or the N-type input pair tube component; thereby, the P-type input pair tube component generates a first preset tail current according to the preset bias voltage in the first working area or the N-type input pair tube component generates a second preset tail current according to the preset bias voltage in the second working area, so that the input stage transconductance remains consistent in each working area. Based on this, the present invention can provide a preset bias voltage for the P-type input pair tube component or the N-type input pair tube component by setting the structure and / or setting of different MOS tubes under the tail current adjustment module, and improve the transition zone tail current generation method according to the square law relationship to ensure that the input stage transconductance remains constant.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 One of the structural schematic diagrams of the constant transconductance circuit of the operational amplifier input stage in an embodiment of the present invention is shown;

[0040] Figure 2 One of the circuit principle diagrams of the constant transconductance circuit of the operational amplifier input stage in an embodiment of the present invention is shown;

[0041] Figure 3 The second circuit schematic diagram of the constant transconductance circuit of the operational amplifier input stage in the embodiment of the present invention is shown;

[0042] Figure 4 A circuit schematic diagram of a first power supply unit in an embodiment of the present invention is shown;

[0043] Figure 5 The second structural schematic diagram of the constant transconductance circuit of the operational amplifier input stage in the embodiment of the present invention is shown;

[0044] Figure 6The third circuit schematic diagram of the constant transconductance circuit of the operational amplifier input stage in the embodiment of the present invention is shown;

[0045] Figure 7 A simulation schematic diagram of an embodiment of the present invention is shown.

[0046] Icons: 10-op-amp input stage transconductance constant circuit; 101-N-type input pair tube assembly; 102-P-type input pair tube assembly; 103-tail current adjustment module; 201-MOS tube except the target MOS tube; 201-A-target MOS tube; 301-first power supply unit; 303-op-amp unit; 304-second power supply unit; 401-operational amplifier; 402-resistance module; M1-first MOS tube; M2-second MOS tube; M3-third MOS tube; M4-fourth MOS tube; M5-fifth MOS tube; M6-sixth MOS tube; M7-seventh MOS tube; M8-eighth MOS tube; M9-ninth MOS tube; M10-the tenth MOS tube; M11-the eleventh MOS tube; M12-the twelfth MOS tube; M13-the thirteenth MOS tube; M14-the fourteenth MOS tube; M15-the fifteenth MOS tube; M16-the sixteenth MOS tube; M17-the seventeenth MOS tube; M18-the eighteenth MOS tube; M19-the nineteenth MOS tube; M20-the twentieth MOS tube; M21-the twenty-first MOS tube; M22-the twenty-second MOS tube; M23-the twenty-third MOS tube; M24-the twenty-fourth MOS tube; M25-the twenty-fifth MOS tube; R1-the first resistor; R2-the second resistor; R3-the third resistor; R4-the fourth resistor. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0049] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0050] As described in the background technology, the triple current mirror method is a classic circuit for rail-to-rail input op amp tail current switching, including three working areas, for example, a completely P-type MOS tube working area (i.e., completely worked by the P-type input pair tube component), a completely N-type MOS tube working area (i.e., completely worked by the N-type input pair tube component), and an area where the P-type MOS tube and the N-type MOS tube work together (i.e., a switching area). Although the triple current mirror method can reduce the transconductance change in the switching area to 15%, 15% is still a relatively large change value, especially after considering the PVT characteristics, the transconductance change is even greater.

[0051] Based on this, the present invention provides a technical solution for constant transconductance, which can improve the tail current generation method in the transition zone and further reduce the PVT characteristics of the transition zone.

[0052] Please refer to Figure 1 , Figure 1 A schematic structural diagram of an operational amplifier input stage transconductance constant circuit provided in this embodiment is shown, including an N-type input pair transistor assembly 101, a P-type input pair transistor assembly 102 and a tail current adjustment module 103; the tail current adjustment module 103 includes multiple MOS transistors.

[0053] Among them, the multiple MOS tubes include a target MOS tube 201-A, and part or all of the MOS tubes in the remaining MOS tubes 201 except the target MOS tube 201-A respectively provide different bias voltages for the target MOS tube 201-A, so that the target MOS tube 201-A generates a preset bias voltage.

[0054] In this embodiment, the target MOS transistor is used to provide a preset bias voltage to the P-type input pair tube component or the N-type input pair tube component, so that the P-type input pair tube component generates a first preset tail current according to the preset bias voltage in the first working area, so that the input operational amplifier transconductance remains consistent in each working area; or the N-type input pair tube component generates a second preset tail current according to the preset bias voltage in the second working area, so that the input stage transconductance remains consistent in each working area.

[0055] In this embodiment, the first working area is used to represent that the P-type input pair tube assembly works completely; the second working area is used to represent that the N-type input pair tube assembly works completely; and the switching area is used to represent that the P-type input pair tube assembly and the N-type input pair tube assembly work together.

[0056] in, Figure 1 VIP represents the first input voltage; VIN represents the second input voltage; Ib represents a current with a smaller current value; VBS represents a preset bias voltage; I0 is a fixed tail current; Vgs1 is a first bias voltage; and Vgs2 is a second bias voltage.

[0057] Here is a detailed description of how this implementation works:

[0058] Taking the first working area and the switching area as an example, in order to make the input op amp transconductance consistent in each working area, the transconductance corresponding to the first working area and the switching area needs to satisfy the following relationship:

[0059]

[0060] Among them, g m is the input stage transconductance; k n is the first parameter related to the N-type input tube assembly, satisfying: k p is the second parameter related to the P-type input pair assembly, satisfying: μ n is the electron mobility corresponding to the N-type input pair tube component, μ p is the electron mobility corresponding to the P-type input pair tube component, C ox (.) n is the oxide layer capacitance corresponding to the N-type input pair tube assembly; C ox (.) p It is the oxide layer capacitance corresponding to the P-type input pair tube assembly; The ratio between the width and length of the P-type input pair tube assembly; I is the ratio between the width and length of the N-type input pair tube assembly; p is the tail current corresponding to the P-type input pair tube assembly in the first working area; I nis the tail current corresponding to the N-type input pair tube assembly in the second working area; I0 is the fixed tail current.

[0061] Based on the above formula, the following calculation formula can be obtained: It can be seen that the tail current I corresponding to the N-type input pair tube component under the fixed tail current I0 and the second working area can be n After the determination, the tail current value corresponding to the P-type input pair tube assembly in the first working area can be obtained, that is, the first preset tail current.

[0062] Similarly, the tail current I corresponding to the P-type input pair tube assembly under the fixed tail current I0 and the first working area can be p After the determination, the tail current value corresponding to the N-type input pair tube assembly in the second working area can be obtained, that is, the second preset tail current.

[0063] In this embodiment, a preset bias voltage can be provided for the tail current tube under the P-type input pair tube assembly or the N-type input pair tube assembly through the above relationship, thereby improving the scheme for generating the tail current in the transition region, thereby reducing the change value of the transconductance and keeping the input stage transconductance constant.

[0064] It should be noted that the present embodiment does not limit the specific structure of the P-type input pair transistor assembly or the N-type input pair transistor assembly, as long as it can achieve receiving the input stage signal.

[0065] In a possible implementation, taking a P-type input pair tube assembly as an example, the P-type input pair tube assembly in this embodiment generally includes a P-type input pair tube and a correspondingly arranged tail current tube. Please continue to refer to Figure 1 The tail current source tube corresponding to the P-type input pair tube assembly is usually a PMOS tube. Similar to the P-type input pair tube assembly, the N-type input pair tube assembly includes an N-type input pair tube and a correspondingly arranged tail current source tube, such as an NMOS tube.

[0066] It should be noted that, in this embodiment, the bias voltage that meets the requirements can be obtained through the structure and / or setting relationship of the MOS tube under the tail current adjustment module, and then the above-mentioned preset circuit structure can be used to ensure that the input stage transconductance is constant.

[0067] In this embodiment, when the op amp input stage transconductance constant circuit is in the first working region, the remaining MOS transistors respectively provide different bias voltages for the target MOS transistor to generate a first bias voltage and a second bias voltage respectively.

[0068] Among them, the expression of the preset bias voltage satisfies:

[0069] V BS =V gs2 -V gs1 +V TH ;

[0070]

[0071] Among them, V BS is the preset bias voltage; V gs1 is the first bias voltage; V gs2 is the second bias voltage; V TH is the threshold voltage.

[0072] Based on this, under the fixed tail current I0 and the first working area, the tail current I corresponding to the P-type input pair tube assembly p Under the condition that (the first preset tail current) is determined, the N-type input pair transistor component generates a second preset tail current I according to the preset bias voltage in the first working region based on the square law characteristics of the MOS transistor. n* , which can be expressed as:

[0073]

[0074] This embodiment also provides a first preset tail current I p The generating circuit of Figure 1 Based on the reference Figure 2 The generating circuit includes a twenty-second MOS tube M22, a twenty-third MOS tube M23, a twenty-fourth MOS tube M24, and a twenty-fifth MOS tube M25, wherein the twenty-second MOS tube M22 and the twenty-fifth MOS tube M25 are PMOS tubes; the twenty-third MOS tube M23 and the twenty-fourth MOS tube M24 are NMOS tubes.

[0075] The source of the twenty-second MOS tube M22 is connected to the source of the twenty-fifth MOS tube M25, and is connected to the power supply; the drain of the twenty-second MOS tube M22 is respectively connected to the gate of the twenty-second MOS tube M22 and the drain of the twenty-third MOS tube M23; the source of the twenty-third MOS tube M23 is connected to the source of the twenty-fourth MOS tube M24, and is grounded; the drain of the twenty-fourth MOS tube M24 is respectively connected to the drain and the gate of the twenty-fifth MOS tube M25; wherein the gate of the twenty-fourth MOS tube M24 is also used to receive the common mode voltage VCM, and the gate of the twenty-third MOS tube M23 is also used to receive the reference voltage VT of the tail current switching.

[0076] First embodiment

[0077] Under the condition that multiple MOS tubes under the tail current adjustment module only include MOS tubes, please Figure 1 Based on the reference Figure 3 , Figure 3The circuit schematic diagram of a transconductance constant circuit of an operational amplifier input stage provided in this embodiment is shown. Among them, the target MOS transistor 201-A includes a fifth MOS transistor M5; the remaining MOS transistors 201 include a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a sixth MOS transistor M6 and a seventh MOS transistor M7.

[0078] It should be noted that, in the present embodiment, one of the MOS transistors in the target MOS transistor 201 -A is biased into a weak inversion region by a small current Ib.

[0079] The first end of the first MOS tube M1 is connected to the second end of the fifth MOS tube M5 and the second end of the sixth MOS tube M6; the second end of the first MOS tube M1 is connected to the first end of the second MOS tube M2; the second end of the second MOS tube M2 is connected to the second end and the control end of the third MOS tube M3; the control end of the third MOS tube M3 is also connected to the control end of the fourth MOS tube M4; the second end of the fourth MOS tube M4 is connected to the first end of the fifth MOS tube M5; the control end of the fifth MOS tube M5 is connected to the control end and the second end of the sixth MOS tube M6; the second end of the sixth MOS tube M6 is also connected to the second end and the control end of the seventh MOS tube M7; the first end of the third MOS tube M3, the first end of the fourth MOS tube M4, and the first end of the seventh MOS tube M7 are all grounded;

[0080] The fixed tail current I0 supplies power to the sixth MOS tube M6 and the seventh MOS tube M7, and the tail current corresponding to the P-type input pair tube component in the first working region supplies power to the fifth MOS tube M5 to generate a preset bias voltage at the second end of the fifth MOS tube M5. The seventh MOS tube M7 is in a weak inversion region.

[0081] In the above connection relationship, the first end of each MOS tube corresponds to the source of the MOS tube, the second end corresponds to the drain of the MOS tube, and the control end corresponds to the gate of the MOS tube.

[0082] In one possible implementation, please refer to Figure 3 , a bias voltage can be set to generate a small current Ib to bias the seventh MOS tube into a weak inversion region.

[0083] exist Figure 3 On this basis, the working principle of the above circuit schematic diagram will be introduced in detail below.

[0084] In this embodiment, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, and the remaining MOS transistors are NMOS transistors, such as the third MOS transistor M3, the fourth MOS transistor M4, the sixth MOS transistor M6 and the seventh MOS transistor M7. Among them, the first MOS transistor M1 is used to copy the tail current I of the P-type input pair transistor component. pThe fourth MOS tube M4 is used to copy the current of the third MOS tube M3. The fixed tail current I0 generates a second bias voltage V through the sixth MOS tube M6. gs2 At the same time, the fixed tail current I0 is replenished to the source of the sixth MOS tube M6, so that the current of the seventh MOS tube M7 is Ib. At this time, the gate-source voltage of the seventh MOS tube M7 is approximately equal to V TH .

[0085] At the same time, the tail current I of the P-type input pair tube assembly 102 p A first bias voltage V is generated at the fifth MOS tube M5. gs1 Based on this, the voltage at the source of the fifth MOS tube M5 satisfies: V BS =V gS2 -V gS1 +V TH ; V BS The first preset tail current I is biased at the gate of the tail current source tube corresponding to the N-type input pair tube component, thereby generating a first preset tail current I n* , wherein the first preset tail current I n* Satisfy the calculation formula:

[0086] Based on this, the present invention arranges different MOS tubes under the tail current adjustment module into the above structure to ensure that the input stage transconductance remains constant.

[0087] In this embodiment, the tail current adjustment module further includes a first power supply unit to provide a fixed tail current I0 and a small current Ib.

[0088] It should be noted that this embodiment does not limit the structure of the first power supply unit. In a possible implementation, it can be generated by a const_gm structure.

[0089] Please Figure 3 Based on the reference Figure 4 , Figure 4 A circuit diagram of the first power supply unit is shown; wherein the first power supply unit 301 includes an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10 and an eleventh MOS tube M11; the eighth MOS tube M8 and the ninth MOS tube M9 are PMOS tubes; the tenth MOS tube M10 and the eleventh MOS tube M11 are NMOS tubes.

[0090] The first end of the eighth MOS tube M8 and the first end of the ninth MOS tube M9 are connected to the power supply; the control end of the eighth MOS tube M8 is respectively connected to the control end of the ninth MOS tube M9 and the second end of the eleventh MOS tube M11; the second end of the eighth MOS tube M8 is respectively connected to the second end and the control end of the tenth MOS tube M10; the control end of the tenth MOS tube M10 is also connected to the control end of the eleventh MOS tube M11; the first end of the eleventh MOS tube M11 is grounded through the first resistor R1; and the first end of the tenth MOS tube M10 is grounded.

[0091] Based on this, the first power supply unit 301 can generate the above-mentioned fixed tail current I0 and small current Ib respectively through the ninth MOS transistor M9 and the tenth MOS transistor M10.

[0092] Second embodiment

[0093] Under the condition that the tail current adjustment module 103 includes a MOS tube and an operational amplifier device, please Figure 1 Based on the reference Figure 5 , Figure 5 Another structural schematic diagram of an operational amplifier input stage transconductance constant circuit provided by this embodiment is shown.

[0094] In this embodiment, except for the target MOS tube 201-A, the remaining MOS tubes may include an operational amplifier unit 303 and a second power supply unit 304. The second power supply unit 304 includes multiple different outputs. Under the condition that the operational amplifier unit 303 includes two inputs, each input is respectively connected to one of the outputs of the second power supply unit 304, wherein each input is respectively connected to a different output so that the operational amplifier unit 303 generates a preset voltage difference.

[0095] Based on this, the target MOS transistor 201 -A generates a preset bias voltage according to the preset voltage difference.

[0096] It should be noted that, in this embodiment, one of the MOS transistors in the remaining MOS transistors 201 except the target MOS transistor 201 -A is in a weak inversion region.

[0097] Please Figure 5 Based on the reference Figure 6 , Figure 6 The circuit schematic diagram of the operational amplifier unit in this embodiment is shown; the operational amplifier unit 303 includes an operational amplifier 401 and a resistor module 402, the resistor module 402 includes a second resistor R2, a third resistor R3 and a fourth resistor R4, the target MOS tube 201-A includes an eighteenth MOS tube M18, and the remaining MOS tubes also include a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16 and a seventeenth MOS tube M17.

[0098] The first end of the second resistor R2 and the second end of the fourteenth MOS tube M14 are used to receive the first input voltage, and the second end of the second resistor R2 is connected to the first input end of the operational amplifier 401 and the first end of the third resistor R3 respectively; the second input end of the operational amplifier 401 is used to receive the second input voltage, and the second end of the third resistor R3 is connected to the second end of the twelfth MOS tube M12; the first end of the twelfth MOS tube M12 is connected to the first end of the thirteenth MOS tube M13 and the first end of the fourteenth MOS tube M14, the control end of the twelfth MOS tube M12, the control end of the thirteenth MOS tube M13 and the control end of the fourteenth MOS tube M14 are used to receive the third bias voltage, and the twelfth MOS The control end of the transistor M12 is also connected to the output end of the operational amplifier 401; the second end of the thirteenth MOS transistor M13 is respectively connected to the second end and the control end of the fifteenth MOS transistor M15; the second end of the fourteenth MOS transistor M14 is respectively connected to the second end of the sixteenth MOS transistor M16, the second end of the seventeenth MOS transistor M17 and the control end of the seventeenth MOS transistor M17 through the fourth resistor R4; the control end of the sixteenth MOS transistor M16 is connected to the control end and the second end of the fifteenth MOS transistor M15; the first end of the fifteenth MOS transistor M15 is respectively connected to the first end of the sixteenth MOS transistor M16, the first end of the seventeenth MOS transistor M17 and the first end of the eighteenth MOS transistor M18, and is grounded;

[0099] The resistance values ​​of the second resistor R2, the third resistor R3 and the fourth resistor R4 are all equal; and the seventeenth MOS transistor M17 is in a weak inversion region.

[0100] In the above connection relationship, the first end of each MOS tube corresponds to the source of the MOS tube, the second end corresponds to the drain of the MOS tube, and the control end corresponds to the gate of the MOS tube.

[0101] The gate-source voltage of the seventeenth MOS transistor M17 is approximately equal to the corresponding threshold voltage Vgs≈Vth. At this time, the seventeenth switch MOS transistor M17 is in a weak inversion region of the subthreshold region.

[0102] exist Figure 6 On this basis, the working principle of the above circuit schematic diagram will be introduced in detail below.

[0103] In this embodiment, the twelfth MOS tube M12, the thirteenth MOS tube M13 and the fourteenth MOS tube M14 are PMOS tubes, and the remaining MOS tubes are NMOS tubes, namely the fifteenth MOS tube M15, the sixteenth MOS tube M16, the seventeenth MOS tube M17 and the eighteenth MOS tube M18.

[0104] In this embodiment, after obtaining the corresponding input voltage, the first input terminal and the second input terminal of the operational amplifier can use the characteristics of the operational amplifier to generate an output voltage whose value satisfies the difference of the input voltage, and then by setting the resistance module, a certain current value is generated on each MOS tube to reproduce the above voltage value. It should be noted that in this embodiment, the resistance values ​​of the second resistor, the third resistor and the fourth resistor are all equal.

[0105] In this embodiment, the first input voltage and the second input voltage represent the first bias voltage Vgs1 and the second bias voltage Vgs2 respectively; at this time, the current flowing through the twelfth MOS tube M12 satisfies the following numerical value: (Vgs2-Vgs1) / R2; correspondingly, the thirteenth MOS tube M13 and the fourteenth MOS tube M14 both copy the current flowing through the twelfth MOS tube M12, that is, the current flowing through the thirteenth MOS tube M13 and the fourteenth MOS tube M14 both satisfy: (Vgs2-Vgs1) / R2; at the same time, the sixteenth MOS tube M16 copies the current flowing through the fifteenth MOS tube M15; based on this, the voltage corresponding to the fourth resistor R4 satisfies: V R4 =Vgs2-Vgs1; at the same time, since the voltage at the drain end of the sixteenth MOS tube M16 is generated by the seventeenth MOS tube M17, and the gate-source voltage of the seventeenth MOS tube M17 is approximately equal to the threshold voltage, at this time, the first end of the fourth resistor R4, that is, the port connected to the second end of the fourteenth MOS tube M14, corresponds to a preset bias voltage VBS that satisfies: VBS=(Vgs2-Vgs1)+VTH; based on this, a second preset tail current I can be generated on the tail current source tube corresponding to the N-tube input pair tube component. n* , where the second preset tail current I n* Satisfy the formula:

[0106] Please continue to refer to Figure 6 In addition to the target MOS tube 201-A, the remaining MOS tubes include a nineteenth MOS tube M19, a twentieth MOS tube M20 and a twenty-first MOS tube M21, wherein the nineteenth MOS tube M19 and the twentieth MOS tube M20 are NMOS tubes, and the twenty-first MOS tube M21 is a PMOS tube.

[0107] The first end of the twenty-first MOS tube M21 is connected to the first end of the twelfth MOS tube M12; the control end of the twenty-first MOS tube M21 is used to receive the fourth bias voltage, and the second end of the twenty-first MOS tube M21 is connected to the first input end of the operational amplifier 401, the second end of the twentieth MOS tube M20, and the control end of the twentieth MOS tube M20; the first end of the nineteenth MOS tube M19 receives the fixed tail current I0, and the first end of the nineteenth MOS tube M19 is also connected to the second input end of the operational amplifier 401 and the control end of the nineteenth MOS tube M19; the first end of the twentieth MOS tube M20 and the first end of the nineteenth MOS tube M19 are both grounded.

[0108] In this embodiment, the eighteenth MOS tube M18 provides a discharge path for the twelfth MOS tube M12, thereby avoiding interference with the twentieth MOS tube M20 and ensuring the stability of the first bias voltage. The fourth bias voltage may be a voltage generated by the fixed tail current I0 flowing through the twenty-fifth MOS tube M25.

[0109] Based on this, please refer to Figure 7 , Figure 7 The simulation schematic diagram of the above two embodiments is shown. The horizontal axis is the common-mode input voltage corresponding to the constant transconductance circuit 10 of the operational amplifier input stage in the present invention, and the vertical axis is the small signal AC output current (i.e., transconductance). It can be seen that the transconductance is constant with the common-mode input voltage, and the ratio corresponding to the transition zone (switching zone) changes by only 4%. When considering the PVT characteristics, the corresponding change ratio is less than 15%.

[0110] In summary, the present invention can provide a preset bias voltage for a P-type input pair tube component or an N-type input pair tube component by setting the structure and / or setting of different MOS tubes under the tail current adjustment module, and improve the transition zone tail current generation method according to the square law relationship, thereby avoiding a significant increase in the transconductance of the operational amplifier in the transition zone and ensuring that the input stage transconductance remains constant.

[0111] With the same design concept as the previous embodiment, the present invention further provides a rail-to-rail input stage system, including the operational amplifier input stage transconductance constant circuit described in any one of the embodiments.

[0112] In addition, the technical effects of the operational amplifier system in the present invention can refer to the technical effects corresponding to the above-mentioned operational amplifier input stage transconductance constant circuit, which will not be repeated here.

[0113] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0114] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An operational amplifier input stage transconductance constant circuit, characterized in that: It includes a P-type input pair tube component, an N-type input pair tube component and a tail current adjustment module; the tail current adjustment module includes a plurality of MOS tubes; wherein, The plurality of MOS tubes include a target MOS tube, and part or all of the remaining MOS tubes except the target MOS tube respectively provide different bias voltages for the target MOS tube, so that the target MOS tube generates a preset bias voltage; The target MOS tube is used to provide a preset bias voltage to the P-type input pair tube component or the N-type input pair tube component; The P-type input pair transistor assembly is used to generate a first preset tail current according to the preset bias voltage in the first working area, so that the transconductance of the operational amplifier is kept consistent in each working area; or the N-type input pair tube assembly, used to generate a second preset tail current according to the preset bias voltage in the second working region, so that the input stage transconductance remains consistent in each working region; The first working region is used to represent that the P-type input pair tube assembly is fully working; the second working region is used to represent that the N-type input pair tube assembly is fully working.

2. The operational amplifier input stage transconductance constant circuit according to claim 1, characterized in that: When the operational amplifier input stage transconductance constant circuit is in the first working area, part or all of the remaining MOS tubes respectively provide different bias voltages for the target MOS tube to generate a first bias voltage and a second bias voltage respectively; Wherein, the expression of the preset bias voltage satisfies: V BS =V gs2 -V gs1 +V TH ; Among them, V BS is the preset bias voltage; V gs1 is the first bias voltage; V gs2 is the second bias voltage; V TH is the threshold voltage; I p is the tail current corresponding to the P-type input pair tube assembly; I0 is the fixed tail current; k n is the first parameter associated with the N-type input pair tube assembly.

3. The operational amplifier input stage transconductance constant circuit according to claim 2, characterized in that: The P-type input pair transistor component is further used to generate a second preset tail current according to the preset bias voltage in the first working area based on the square law characteristics of the MOS transistor; The calculation formula of the second preset tail current satisfies: Among them, I p is the first preset tail current, I n* is the second preset tail current.

4. The operational amplifier input stage transconductance constant circuit according to claim 1 or 2, characterized in that: At least one of the remaining MOS transistors or the target MOS transistor is in a weak inversion region.

5. The operational amplifier input stage transconductance constant circuit according to claim 4, characterized in that: The remaining MOS tubes include a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a sixth MOS tube and a seventh MOS tube; the target MOS tube includes a fifth MOS tube; The first end of the first MOS tube is connected to the second end of the fifth MOS tube and the second end of the sixth MOS tube; the second end of the first MOS tube is connected to the first end of the second MOS tube; the second end of the second MOS tube is connected to the second end and the control end of the third MOS tube; the control end of the third MOS tube is also connected to the control end of the fourth MOS tube; the second end of the fourth MOS tube is connected to the first end of the fifth MOS tube; the control end of the fifth MOS tube is connected to the control end and the second end of the sixth MOS tube; the second end of the sixth MOS tube is also connected to the second end and the control end of the seventh MOS tube; the first end of the third MOS tube, the first end of the fourth MOS tube, and the first end of the seventh MOS tube are all grounded; Wherein, the seventh MOS transistor is in a weak inversion region.

6. The operational amplifier input stage transconductance constant circuit according to claim 5, characterized in that: The tail current adjustment module also includes a first power supply unit, which includes an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and an eleventh MOS tube; the first end of the eighth MOS tube and the first end of the ninth MOS tube are connected to the power supply; the control end of the eighth MOS tube is respectively connected to the control end of the ninth MOS tube and the second end of the eleventh MOS tube; the second end of the eighth MOS tube is respectively connected to the second end and the control end of the tenth MOS tube; the control end of the tenth MOS tube is also connected to the control end of the eleventh MOS tube; the first end of the eleventh MOS tube is grounded through a first resistor; and the first end of the tenth MOS tube is grounded.

7. The operational amplifier input stage transconductance constant circuit according to claim 4, characterized in that: The remaining MOS tubes include an operational amplifier unit and a second power supply unit, the second power supply unit includes multiple different outputs, and under the condition that the operational amplifier unit includes two inputs, each input is respectively connected to one of the outputs of the second power supply unit, wherein each input is respectively connected to a different output, so that the operational amplifier unit generates a preset voltage difference; The target MOS tube is also used to generate a preset bias voltage according to the preset voltage difference.

8. The operational amplifier input stage transconductance constant circuit according to claim 7, characterized in that: The operational amplifier unit includes an operational amplifier and a resistor module, the resistor module includes a second resistor, a third resistor and a fourth resistor, the remaining MOS tubes include a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube, and the target MOS tube includes an eighteenth MOS tube; The first end of the second resistor and the second end of the fourteenth MOS tube are used to receive a first input voltage, and the second end of the second resistor is respectively connected to the first input end of the operational amplifier and the first end of the third resistor; the second input end of the operational amplifier is used to receive a second input voltage, and the second end of the third resistor is connected to the second end of the twelfth MOS tube; the first end of the twelfth MOS tube is connected to the first end of the thirteenth MOS tube and the first end of the fourteenth MOS tube, and the control end of the twelfth MOS tube, the control end of the thirteenth MOS tube and the control end of the fourteenth MOS tube are used to receive a third bias voltage, and the tenth The control end of the second MOS tube is also connected to the output end of the operational amplifier; the second end of the thirteenth MOS tube is respectively connected to the second end and the control end of the fifteenth MOS tube; the second end of the fourteenth MOS tube is respectively connected to the second end of the sixteenth MOS tube, the second end of the seventeenth MOS tube and the control end of the seventeenth MOS tube through the fourth resistor; the control end of the sixteenth MOS tube is connected to the control end and the second end of the fifteenth MOS tube; the first end of the fifteenth MOS tube is respectively connected to the first end of the sixteenth MOS tube, the first end of the seventeenth MOS tube and the first end of the eighteenth MOS tube, and is grounded; The resistance values ​​of the second resistor, the third resistor and the fourth resistor are all equal; and the seventeenth MOS transistor is in a weak inversion region.

9. The operational amplifier input stage transconductance constant circuit according to claim 8, characterized in that: The remaining MOS tubes also include a nineteenth MOS tube, a twentieth MOS tube and a twenty-first MOS tube, wherein the first end of the twenty-first MOS tube is connected to the first end of the twelfth MOS tube; the control end of the twenty-first MOS tube is used to receive a fourth bias voltage, and the second end of the twenty-first MOS tube is connected to the first input end of the operational amplifier, the second end of the twentieth MOS tube and the control end of the twentieth MOS tube; the first end of the nineteenth MOS tube receives a fixed tail current, and the first end of the nineteenth MOS tube is also connected to the second input end of the operational amplifier and the control end of the nineteenth MOS tube; the first end of the twentieth MOS tube and the first end of the nineteenth MOS tube are both grounded.

10. A rail-to-rail input stage system, characterized in that: The operational amplifier input stage transconductance constant circuit comprises the operational amplifier input stage transconductance constant circuit as described in any one of claims 1 to 9.

Images