High frequency wafers for low jitter applications and methods of making same
By setting the resonance area, electrode, permeability area and coating area of the edge and corner positions on the high-basis frequency quartz chip, the problems of frequency instability and frequency hopping in traditional wafers in low jitter applications are solved, and higher Q value and frequency stability are achieved.
Patent Information
- Application Number
- CN202411742807.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-04-15
AI Technical Summary
Traditional high-basic frequency quartz chips perform poorly in low jitter and low phase noise applications, have unstable frequency and are prone to frequency hopping problems, mainly due to the structural acoustic and vibration coupling of the central resonant region and directive acoustic radiation.
By changing the structure of the high-basis frequency quartz chip, the resonance region is set at the first corner position of the wafer, the electrode is at the unconstrained corner position, the permeability region is at the symmetrical second corner position, and the coating region is outside the boundary of the resonance region, so as to control the acoustic wave direction and reduce the structure's acoustic and oscillation coupling.
The jitter control of high-basis frequency quartz chips is realized, which reduces phase noise, improves Q value and frequency stability, improves vibration sensitivity and adaptability, and meets the application needs of low jitter and low phase noise.
Smart Images
Figure CN119834752A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of quartz devices, and more particularly to a high-frequency chip for low-jitter applications and a manufacturing method thereof. Background Art
[0002] With the advent of the 5G era, especially the rapid development of the communications optoelectronics industry, the market has higher and higher requirements for crystal resonators, requiring resonators to have superior performance such as high fundamental frequency, low jitter, and low power consumption. At the same time, the jitter (phase noise) suppression of the resonator is also particularly important for high fundamental frequency quartz frequency devices. The traditional center concave platform resonance area structure currently used in the industry to prepare high fundamental frequency quartz resonators has large resistance and low Q value, resulting in large phase noise (large jitter), which can easily cause the vibration stability of the resonator to decrease, causing frequency instability and frequency hopping problems, seriously affecting the performance of high-frequency quartz devices. Based on this, a high-frequency chip structure design suitable for low-jitter applications is proposed.
[0003] At present, the conventional solution in the industry is to prepare a highly symmetrical concave platform resonance zone structure in the center of the quartz wafer. Although it can achieve high frequency of the wafer, the high fundamental frequency wafer prepared by this structural solution has unstable frequency and often has frequency hopping problems. The main reason is that the boundary of the resonance zone in the center of the quartz wafer is fully constrained. During the simple harmonic vibration process, the high-frequency sound waves generated in the resonance zone will be refracted and reflected at the boundary of the resonance zone, forming structural acoustic vibration coupling, which seriously affects the simple harmonic vibration of the wafer, reduces the performance indicators of the wafer, and leads to problems such as excessive resistance, low Q value and difficulty in starting. In addition, due to the anisotropy of quartz, its central resonance zone is a non-simple sound source, and the high-frequency sound waves generated are directional (low symmetry), and the structural acoustic vibration coupling generated on the boundaries of the vibration zone in all directions is also different, which also makes it very difficult to reduce the noise of the resonance zone structure. Therefore, traditional high fundamental frequency quartz wafers cannot effectively meet the application requirements of low jitter and low phase noise. Summary of the invention
[0004] In order to solve the above problems, the present invention provides a high-frequency chip for low-jitter applications and a manufacturing method thereof.
[0005] According to one aspect of the present invention, there is provided a high-frequency chip for low-jitter applications, comprising: a resonance zone, arranged at a first corner position of the chip; an electrode, arranged at an unconstrained corner position of the resonance zone; a transparent zone, arranged at a second corner position of the chip symmetrical to the resonance zone; and a coating zone, arranged outside the boundary of the resonance zone; wherein the first corner position and the second corner position are different from each other, constraints exist on two sides of the resonance zone, and no constraints exist on the other two sides.
[0006] Furthermore, the transparent area is a circular through hole or a square transparent area.
[0007] Furthermore, the coating area is a circular coating point or a square coating area.
[0008] Further, the electrode is away from the inner boundary of the resonance region.
[0009] Furthermore, the wafer further comprises an assembly area, and the assembly area is arranged at a far end of the wafer away from the resonance area and the transparent area.
[0010] According to another aspect of the present invention, there is provided a method for preparing a high-frequency chip for low-jitter applications, comprising: setting a resonance zone at a first corner position of the chip; setting an electrode at an unconstrained corner position of the resonance zone; setting a transparent zone at a second corner position of the chip symmetrical to the resonance zone; and setting a coating zone outside the boundary of the resonance zone, wherein the first corner position and the second corner position are different from each other, constraints exist on two sides of the resonance zone, and no constraints exist on the other two sides.
[0011] Furthermore, the transparent area is a circular through hole or a square transparent area.
[0012] Furthermore, the coating area is a circular coating point or a square coating area.
[0013] Further, the electrode is away from the inner boundary of the resonance region.
[0014] Furthermore, the method further includes setting a mounting area at a far end of the wafer away from the resonance area and the through-area.
[0015] The present invention improves the structural acoustic-vibration coupling problem of the central resonance area of the traditional chip by changing the structure of the high fundamental frequency quartz chip, including changing the position of the resonance area, the position of the electrode, and increasing the transparent area and the coating area of the chip, etc., controls the directional acoustic radiation of the chip, improves the Q value of the chip, reduces the resistance, and improves the starting sensitivity. It improves the low jitter and low phase noise performance of the high fundamental frequency quartz crystal oscillator, and improves the adaptability and applicability of the high fundamental frequency quartz crystal oscillator in 5G communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1( a ) to FIG. 1 ( i ) are schematic diagrams showing the composition structure of a high-frequency wafer for low-jitter applications according to an embodiment of the present invention.
[0017] 2( a ) to 2 ( f ) are schematic diagrams showing the assembly structure of a high-frequency wafer for low-jitter applications according to an embodiment of the present invention. DETAILED DESCRIPTION
[0018] Embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0019] The present invention can achieve accurate and reliable chip jitter control, reduce chip phase noise, increase chip Q value, reduce resistance and oscillation difficulty, and improve oscillation sensitivity by changing the structure of the high fundamental frequency quartz chip, including changing the resonance zone position, electrode position, and adding chip through holes and circular coating points.
[0020] The present invention can be applied to all quartz crystal frequency chips with a frequency of 100M (base frequency) to 1.2G (base frequency), and is used to improve the large jitter and high phase noise problems of traditional high base frequency quartz chips. The present invention can improve the starting sensitivity and Q value of the high base frequency chip, and improve the use stability of the high base frequency quartz chip.
[0021] The present invention proposes a chip structure of a low-jitter resonator, which includes a resonance zone located at the corner of the chip, an electrode at the corner, a transparent zone at the corner, and a radiation suppression coating zone. Furthermore, the chip may also include a remote assembly area. The present invention aims to achieve accurate and reliable jitter control of the chip, reduce the phase noise of the chip, improve the Q value of the chip, reduce the resistance and the difficulty of starting, and improve the sensitivity of starting, thereby improving the resonance index of the chip.
[0022] Specifically, the chip design of the present invention includes: a quartz chip, which is used to provide a resonance matrix for electrode attachment and assembly with a base; unconstrained resonance zones on both sides, which are used as the starting center to determine the main vibration frequency of the chip, wherein the resonance zone can be thinned on one side or on both sides; a transparent zone on the chip, which can have different shapes and sizes, for example, it can be a through hole / square transparent zone, which is used to achieve mass balance and suppress the acoustic radiation diffused in the resonance zone; a coating zone, which can have different shapes and sizes, for example, it can be a circular coating point / square coating zone, which is used to suppress the acoustic radiation diffused in the resonance zone; electrodes on the chip surface, which are used for the input and output of alternating current, and the resonance zone is made to resonate by powering on to generate a frequency output, wherein the resonance zone electrodes are located at the corners of the unconstrained sides of the resonance zone.
[0023] The composition structure of a high-frequency chip for low-jitter applications according to an embodiment of the present invention is described below with reference to FIG. 1( a ) to FIG. 1 ( i ).
[0024] FIG1( a ) shows the composition of a quartz wafer, which includes a resonance region, upper and lower electrodes, and a through hole.
[0025] In the present invention, the resonance region on the quartz wafer can be located at a corner of the wafer, and the resonance boundary is constrained on two sides and unconstrained on two sides. The resonance region can be located at any position of the four corners of the rectangular wafer. In Figure 1 (a), the resonance region is located at the upper left corner of the four corners.
[0026] In the present invention, the electrodes (upper electrode and lower electrode) of the resonance region can be located at the unconstrained corners of the resonance region, away from the inner boundary of the resonance region. In FIG1 (a), the electrodes (upper electrode and lower electrode) are located at the unconstrained corners of the resonance region away from the inner boundary of the resonance region.
[0027] In the present invention, the through area can have different shapes and sizes. In FIG1( a ), the through area is a circular through hole.
[0028] In the present invention, the transparent area can be located at a corner of the quartz wafer that is symmetrical to the resonance area.
[0029] FIG. 1( b ) further illustrates the composition of the quartz wafer, which further shows the through-hole 2 .
[0030] In an embodiment, the number of transparent areas may not be limited but may be adjusted as needed.
[0031] For example, in FIG. 1( b ), the quartz wafer may include two through holes, but the present invention is not limited thereto.
[0032] FIG1( c ) further illustrates the composition of the quartz wafer, which further shows the coating spots.
[0033] In the present invention, the coating area can have different shapes and sizes.
[0034] In Figure 1(c), the coating area is a circular coating spot.
[0035] In the present invention, the coating area can be arranged outside the other main side of the resonance area.
[0036] In the present invention, the plated film region may be formed by evaporation.
[0037] FIG1( d ) further illustrates the composition of the quartz wafer, which further shows the square through-area.
[0038] In the present invention, the transparent area can have different shapes and sizes. In FIG1( d ), the transparent area is a square transparent area.
[0039] FIG1( e ) further illustrates the composition of the quartz wafer, which further shows a square through area and a square coating area.
[0040] In the present invention, the through area and the coating area can have different shapes and sizes.
[0041] In FIG1( e ), the transparent area is a square transparent area, and the coating area is a square coating area.
[0042] The composition of the quartz wafer is further illustrated in FIG1(f), which further shows the resonant region electrodes.
[0043] In the present invention, the resonance region electrodes can have different shapes and sizes. In FIG1( f ), the resonance region electrodes are formed by circular and square electrodes connected to each other.
[0044] FIG1( g ) further illustrates the composition of the quartz wafer, which further illustrates the resonant region and the resonant region electrodes.
[0045] In the present invention, the resonance region can have different shapes and sizes. In FIG1( g ), the resonance region is fan-shaped.
[0046] In the present invention, the electrodes (upper electrode and lower electrode) in the resonance region can have different shapes and sizes. In FIG1( g ), the upper electrode in the resonance region is cylindrical and the lower electrode is circular.
[0047] FIG1(h) further illustrates the composition of the quartz wafer, which further illustrates the resonant region and the resonant region electrodes.
[0048] In the present invention, the resonance region can have different shapes and sizes. In FIG1( g ), the resonance region is a rectangle.
[0049] In the present invention, the electrodes (upper electrode and lower electrode) in the resonance region can have different shapes and sizes. In FIG1(h), the upper electrode and the lower electrode in the resonance region are rectangular.
[0050] FIG1(i) further illustrates the composition of the quartz wafer, which further shows the square through-region forming the resonance region.
[0051] In the present invention, the quartz wafer may include a square transparent area so that both sides of the resonance area can achieve an unconstrained state.
[0052] In Figure 1 (i), the through area is a through hole, and the coating area is a square coating area.
[0053] The assembly structure of a high frequency chip for low jitter applications according to an embodiment of the present invention will be described below with reference to FIGS. 2( a ) to 2 ( f ).
[0054] According to the present invention, a mounting region can be provided at a distal end of the wafer away from the resonance region and the through hole.
[0055] The assembly area may be a two-point structure that is symmetrical on both sides (eg, FIG. 2(a), FIG. 2(b)).
[0056] The assembly area can also be a central single-point structure (for example, Figure 2(c), Figure 2(d), Figure 2(e), Figure 2(f)).
[0057] The shape of the mounting area is not particularly limited, and may be circular (eg, FIG. 2( c ), FIG. 2( d )).
[0058] The shape of the assembly area may also be a square (eg, FIG. 2( a ) and FIG. 2( b )).
[0059] The shape of the assembly area may also be a polygon (eg, FIG. 2( e ) and FIG. 2( f )).
[0060] According to the present invention, the resonance region can be formed by an etching process, and the etching process includes dry etching and wet etching.
[0061] According to the present invention, the electrode may be formed by a deposition process, including CVD, PVD, and the like.
[0062] According to the present invention, the through region can be formed by an etching process, and the etching process includes dry etching and wet etching.
[0063] According to the present invention, the coating area can be formed by a deposition process, and the deposition process includes CVD, PVD and the like.
[0064] The present invention can achieve jitter suppression for quartz frequency chips with frequencies of 100M (base frequency) to 1.2G (base frequency), and form resonance zones, corner electrodes, corner transparent zones, radiation suppression coating zones, and remote assembly zones at the corners through processes such as photolithography, corrosion, and evaporation. This structural invention scheme can effectively reduce structural acoustic vibration coupling, control the directivity of sound waves, reduce acoustic self-radiation, effectively improve the Q value and frequency stability of the chip, and achieve low jitter and low phase noise performance of high-frequency quartz crystal oscillators. In addition, it has been verified that the optimized process route designed by the present invention, which combines the multi-corner resonance zones, electrodes, transparent zones, and coating points, can meet the reliability and stability requirements of the chip for long-term use.
[0065] This specification includes many details of specific embodiments, but it should be understood that these details do not limit any inventive concepts or what is claimed in the specification, but rather describe features of some exemplary embodiments.
[0066] Features described in the specification in the context of each exemplary embodiment may be implemented as a combination in one or more single exemplary embodiments. Conversely, various features described in the specification in the context of a single exemplary embodiment may be implemented as multiple exemplary embodiments individually or in appropriate sub-combinations.
[0067] Furthermore, features may be operated in a particular combination and may initially be described as claimed in the combination, but in certain cases one or more features may be excluded from the claimed combination and the claimed combination may be changed into a sub-combination or a modification of the sub-combination.
[0068] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that the operations be performed in a particular order or sequentially to achieve desirable results, nor should it be understood as requiring that all operations be performed.
[0069] While the inventive concept has been described in conjunction with what are presently considered to be practical exemplary embodiments, it should be understood that the inventive concept is not limited to such exemplary embodiments. Rather, the inventive concept is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.
Claims
1. A high frequency chip for low jitter applications, characterized in that: include: A resonance region is arranged at a first corner position of the wafer; Electrodes are arranged at unconstrained corner positions of the resonance region; A transparent area is arranged at a second corner position of the wafer symmetrical to the resonance area; as well as A coating region, arranged outside the boundary of the resonance region; The first corner position and the second corner position are different from each other, and there are constraints on two sides of the resonance region, but no constraints on the other two sides.
2. The high frequency chip for low jitter applications according to claim 1, characterized in that: The transparent area is a circular through hole or a square transparent area.
3. The high frequency chip for low jitter applications according to claim 1, characterized in that: The coating area is a circular coating point or a square coating area.
4. The high frequency chip for low jitter applications according to claim 1, characterized in that: The electrode is away from the inner boundary of the resonance region.
5. The high frequency chip for low jitter applications according to any one of claims 1 to 4, characterized in that: The wafer further includes a mounting area, which is disposed at a distal end of the wafer away from the resonance area and the through-area.
6. A method for preparing a high-frequency chip for low-jitter applications, characterized in that: include: Setting a resonance region at a first corner position of the wafer by an etching process; By means of a deposition process, electrodes are arranged at unconstrained corner positions of the resonance region; By means of an etching process, a transparent area is provided at a second corner position of the wafer which is symmetrical to the resonance area; as well as By means of a deposition process, a coating region is provided outside the boundary of the resonance region; The first corner position and the second corner position are different from each other, and there are constraints on two sides of the resonance region, but no constraints on the other two sides.
7. The method for preparing a high frequency wafer for low jitter applications according to claim 6, characterized in that: The transparent area is a circular through hole or a square transparent area.
8. The method for preparing a high frequency wafer for low jitter applications according to claim 6, characterized in that: The coating area is a circular coating point or a square coating area.
9. The method for preparing a high frequency wafer for low jitter applications according to claim 6, characterized in that: The electrode is away from the inner boundary of the resonance region.
10. The method for preparing a high frequency wafer for low jitter applications according to any one of claims 6 to 9, characterized in that: The method further includes setting a mounting area at a far end of the wafer away from the resonance area and the through area.