Novel pseudo-random sequence injection method for accelerating convergence of bit weight calibration algorithm

Abstract

The invention discloses a novel pseudo-random sequence injection method for accelerating convergence of a bit weight calibration algorithm. The method comprises the following steps: detecting residual voltage generated in a first-stage SAR ADC each time by using a metastable state detector group to obtain a D sequence; each bit in the D sequence corresponds to a bit weight; a PN code is generated according to the D sequence and then injected into a first-stage SAR ADC, so that the first-stage SAR ADC in the SAR ADC circuit uses the PN code to replace output of a comparator in the first-stage SAR ADC to complete quantization operation, a first-stage output code is obtained, and meanwhile residual voltage is generated; the residual amplifier amplifies the residual voltage and then inputs the amplified residual voltage to the rear-end ADC to be quantized into a second-stage output code; calculating a true value of each bit weight in the D sequence according to the second-level output code; and according to the first-level output code, the second-level output code and the true value, digital code synthesis is performed to obtain a complete output code, so that bit weight calibration is realized, and the convergence speed of a calibration algorithm is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm. Background Art

[0002] The pipelined successive approximation analog-to-digital converter (SAR ADC) has become the preferred architecture for high-speed, high-precision system-level applications due to its excellent balance between accuracy, speed, and power consumption. However, the inevitable process deviations in the manufacturing process, such as capacitor mismatch and inter-stage gain error, seriously affect the performance of the ADC (Analog-to-Digital Converter). These non-ideal effects can be suppressed to a certain extent by using a design strategy based on the octagon rule, but they cannot be completely eliminated. With the advancement of integrated circuit manufacturing technology, digital-aided design technology has been widely adopted. Its goal is to utilize the advantages of digital circuits in production process, integration, and power consumption, break through the limitations of traditional analog circuit design by increasing the complexity of digital circuits, and improve the performance of low-precision analog circuits with digital processing technology.

[0003] The Bit Weight correction technology was proposed by Yuan Zhou in 2015. This technology can correct the first-stage gain error and capacitor mismatch in the background at one time, and quickly became one of the popular calibration algorithms. However, the Bit Weight technology based on the traditional pseudo-random sequence injection is calibrated by using a single PN code (Pseudo-Noise Code) controlled by a clock, which has certain limitations. The white noise characteristics of the PN code will be damaged during the calculation process, and additional algorithms need to be introduced, which increases the overhead of the digital circuit and seriously affects the convergence speed of the calibration algorithm. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm, which is applied to a SAR ADC circuit, wherein the SAR ADC circuit includes a first-stage SAR ADC, a residual amplifier, a back-end ADC, and a digital error correction module, and the method includes:

[0007] A PN code injection module is introduced; the PN code injection module includes a metastable detector group, a PN code generator and a PN jitter signal injection module;

[0008] Using the metastable detector group to detect the residual voltage generated each time in the first-stage SAR ADC, to obtain a D sequence; each bit in the D sequence corresponds to a bit weight;

[0009] Inputting the D sequence into the PN code generator to generate a PN code;

[0010] The PN code is injected into the first-stage SAR ADC through the PN jitter signal injection module, so that the SAR ADC circuit works as follows: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, obtain the first-stage output code, and generate a residual voltage at the same time; the residual amplifier amplifies the residual voltage and inputs it to the back-end ADC for quantization into the second-stage output code;

[0011] Calculate the true value of each bit weight in the D sequence according to the second-level output code;

[0012] A complete output code is obtained by performing digital code synthesis according to the first-level output code, the second-level output code and the real value, so as to realize bit weight calibration.

[0013] Optionally, using the metastable detector group to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence includes:

[0014] Using the metastable detector group to identify the metastable state of the residual voltage generated each time in the first-stage SAR ADC;

[0015] The D sequence is generated according to a plurality of metastable state identifiers.

[0016] Optionally, the residual voltage includes:

[0017]

[0018] Wherein, Vin represents the initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the i-th bit; W i Indicates the bit weight of the i-th bit; PN j represents the PN code corresponding to the jth bit; W j represents the bit weight of the j-th bit.

[0019] Optionally, calculating the true value of each bit weight in the D sequence according to the second-stage output code includes:

[0020] According to the second-stage output code, using the white noise characteristic of the PN code, obtaining information including the true value of each bit weight;

[0021] The second-level output codes are grouped by using the D sequence and the information containing the true value of each bit weight, and each group of the second-level output codes is accumulated and averaged to obtain multiple groups of operation results;

[0022] The multiple groups of operation results are added together to obtain the true value of each weight in the D sequence.

[0023] Optionally, according to the second-stage output code, using the white noise characteristic of the PN code, obtaining information including the true value of each bit weight includes:

[0024]

[0025] in, represents information containing the true value of the bit weight of the first j bits; h represents a counter; N represents the total number of counts of the counter; and D2 represents the second-level output code.

[0026] In a second aspect, the present invention provides a novel pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm, which is used to perform bit weight calibration on a SAR ADC circuit, wherein the SAR ADC circuit includes a first-stage SAR ADC, a residual amplifier, a back-end ADC, and a digital error correction module, and the device includes:

[0027] PN code injection module; the PN code injection module includes a metastable detector group, a PN code generator and a PN jitter signal injection module;

[0028] The metastable detector group is used to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight;

[0029] The PN code generator is used to generate a PN code according to the D sequence input to itself;

[0030] The PN jitter signal injection module is used to inject the PN code into the first-stage SAR ADC, so that the SAR ADC circuit works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, obtain the first-stage output code, and generate a residual voltage at the same time; the residual amplifier amplifies the residual voltage and inputs it to the back-end ADC for quantization into the second-stage output code;

[0031] The device also includes:

[0032] A true value calculation module, used for calculating the true value of each weight in the D sequence according to the second-level output code;

[0033] The complete output code generation module is used to perform digital code synthesis according to the first-level output code, the second-level output code and the real value to obtain a complete output code to achieve bit weight calibration.

[0034] Optionally, the metastable detector group is specifically used to detect the residual voltage generated each time in the first-stage SAR ADC to perform a metastable state identification; and generate the D sequence according to multiple metastable state identifications.

[0035] Optionally, the residual voltage includes:

[0036]

[0037] Wherein, Vin represents the initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the i-th bit; W i Indicates the bit weight of the i-th bit; PN j represents the PN code corresponding to the jth bit; W j represents the bit weight of the j-th bit.

[0038] Optionally, the true value calculation module is specifically used to obtain information containing the true value of each bit weight based on the second-level output code by utilizing the white noise characteristics of the PN code; group the second-level output codes using the D sequence and the information containing the true value of each bit weight, and accumulate and average the grouped second-level output codes to obtain multiple groups of calculation results; and add the multiple groups of calculation results to obtain the true value of each bit weight.

[0039] Optionally, the true value calculation module obtains information including the true value of each bit weight according to the second-stage output code by using the white noise characteristic of the PN code, including:

[0040]

[0041] in, represents information containing the true value of the bit weight of the first j bits; h represents a counter; N represents the total number of counts of the counter; and D2 represents the second-level output code.

[0042] In a novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm provided by the present invention, the generation of a PN code no longer depends on a clock, but is controlled by a D sequence generated by a metastable detector group through detecting a residual voltage, and then the PN code is used to replace the output result of the comparator in the first-stage SAR ADC to complete the quantization operation. Since each bit in the D sequence corresponds to a bit weight, it can be ensured that each PN code generated using the D sequence corresponds to a different bit weight, so that the pseudo-random robustness can still be maintained in the subsequent processing process, avoiding the damage to the white noise characteristics of the PN code during the operation process, and there is no need to introduce an additional algorithm, thereby improving the convergence speed of the bit weight calibration algorithm.

[0043] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of the existing pseudo-random sequence injection scenario;

[0045] Figure 2 It is a schematic diagram of the impact of common mode code error on the calibration algorithm;

[0046] Figure 3 It is a flow chart of a novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm provided by an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of the circuit structure of a SAR ADC provided by an embodiment of the present invention;

[0048] Figure 5 It is a schematic diagram of the distribution of positive codes and negative codes generated by the new PN injection within a specific time interval provided by an embodiment of the present invention;

[0049] Figure 6 It is a schematic diagram of bit weight extraction;

[0050] Figure 7 It is a comparison diagram of SFDR convergence curves between the traditional PN injection method and the new pseudo-random sequence injection method;

[0051] Figure 8 It is a structural schematic diagram of a novel pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0053] First, the existing pseudo-random sequence injection methods are introduced, see Figure 1 , Figure 11 is a schematic diagram of a scenario of an existing pseudo-random sequence injection. The circuit diagram of the existing application of pseudo-random sequence injection includes a first-stage DAC (Digital-to-Analog Converter) 1 st DAC, residual amplifier RA, first-stage logic module 1 st SARLogic, backend ADC and digital error correction module. The traditional pseudo-random sequence injection method only uses a single PN code, which is a coding sequence composed of 0 and 1 with autocorrelation properties similar to white noise. The PN generator is controlled by the clock CLK; when the residual voltage V res When it is lower than the metastable state, the PN code replaces the output of the comparator, and finally the white noise characteristic of the PN code is used to extract the bit weight information in the subsequent digital output code, that is, the output code output by the back-end ADC. Figure 1 It can be regarded as an extraction of the PN code. This means that the PN code is divided into discrete window segments representing different bit weights. In other words, for PN codes located in different weight windows, their white noise characteristics may not be effectively maintained. Although its impact can be minimized by using a sufficiently large average number N in the averager, the positive and negative PN code values ​​after extraction are unbalanced, and common mode code (Middle code) errors will be generated in the cumulative averaging process, which seriously affects the convergence speed of the algorithm, see Figure 2 , Figure 2 It is a schematic diagram of the impact of common mode code error on the calibration algorithm, where D CM The digital code representing the common mode voltage, D BE This problem can be solved by using a separation average algorithm in the back end, but the white noise characteristics of the PN code are still damaged, and the separation average algorithm requires additional digital circuit overhead.

[0054] Therefore, the Bit Weight technology based on traditional pseudo-random sequence injection performs calibration by using a single PN code controlled by a clock, which has certain limitations. During the calculation process, the PN code destroys its white noise characteristics because it acts on multiple bit weights at the same time, and additional algorithms need to be introduced, which increases the overhead of the digital circuit and seriously affects the convergence speed of the calibration algorithm.

[0055] In order to solve the above technical problems, the embodiment of the present invention provides a novel pseudo-random sequence injection method for accelerating the convergence of the bit weight calibration algorithm. Figure 3 , Figure 3 : is a flow chart of a novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm provided by an embodiment of the present invention, which specifically includes the following steps:

[0056] Step S301, introducing a PN code injection module; the PN code injection module includes a metastable detector group, a PN code generator and a PN jitter signal injection module.

[0057] In order to facilitate the understanding of the novel pseudo-random sequence injection method provided by the embodiment of the present invention, the following will be described in conjunction with the SAR ADC (Successive Approximation Register Analog-to-Digital Converter) circuit used by the novel pseudo-random sequence injection method provided by the embodiment of the present invention, see Figure 4 , Figure 4 1 is a schematic diagram of the structure of a SAR ADC circuit provided by an embodiment of the present invention.

[0058] The PN code injection module provided by the embodiment of the present invention comprises a metastable detector group, a PN code generator PNGenerator and a PN jitter signal injection module PN Injection.

[0059] In the embodiment of the present invention, the metastable phenomenon of the SAR ADC circuit mainly refers to the metastable state of the comparator in the SAR ADC circuit, which refers to the situation that the comparator cannot generate a correct comparison result for a long time because the difference between the input signals of the two input terminals is too small. The metastable phenomenon has a great impact on the normal operation of the SAR ADC circuit, making it possible that the SAR ADC circuit cannot complete the normal comparison. Therefore, this situation can be detected by a metastable detector group. The two input terminals of the metastable detector group input the first-stage DAC 1st DAC to generate two residual voltages, that is, the same signal as the input terminal of the comparator. By detecting the residual voltage, the metastable detection of the comparator can be realized. Among them, the metastable detector group can include 5 groups of metastable detectors.

[0060] The PN code generator (PN Generator) is connected to the output end of the metastable detector group, and the PN code generator is used for generating a PN code.

[0061] The PN jitter signal injection module PN Injection is used to inject the generated PN code into the 1st DAC.

[0062] Step S302 : using a metastable detector group to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight.

[0063] In the embodiment of the present invention, the first-stage SAR ADC 1 stDAC refers to the first-stage digital-to-analog converter in the first-stage SAR ADC circuit, which is used to convert the input digital signal Vin into an analog signal. res Refers to 1 st The difference between the DAC output and the input signal. When quantizing, the DAC will try to get close to the input signal and convert it into a corresponding voltage, but there will be an error, which is called the residual voltage. The metastable detector can detect the residual voltage to determine whether it has entered a metastable state.

[0064] In the embodiment of the present invention, the residual voltage detected by the metastable detector group, that is, at which comparison the circuit is in a metastable state, can be used to generate a corresponding D sequence by metastable identification. The D sequence can be used to reflect the state or situation of the circuit corresponding to different bits, that is, whether a certain bit is in a metastable state.

[0065] For example, when the metastable detector group detects that the residual voltage at the jth bit falls into the preset metastable window, it is determined that the jth bit D(j) in the D sequence is 1, and the other bits are all 0.

[0066] In the embodiment of the present invention, when the metastable detector group includes 5 groups of metastable detectors, the length of the generated D sequence is 5. Each group of metastable detectors is used to detect one comparison result of the comparator, that is, the comparator can detect five comparison results, and one bit in the D sequence is generated in each comparison.

[0067] In the embodiment of the present invention, the metastable window may be determined by a technician according to the metastable state of components specifically used in the circuit, and is not limited here.

[0068] Step S303: input the D sequence into a PN code generator to generate a PN code.

[0069] In the PN code injection module provided by the embodiment of the present invention, the generation of the PN code no longer depends on the clock, but is obtained based on the D sequence determined by the residual voltage generated each time in the first-stage SAR ADC.

[0070] The metastable detector group detects a residual voltage after the corresponding comparator compares. When the presence of a metastable phenomenon is determined by detecting the residual voltage after a certain comparator comparison, a metastable identification is performed, and finally a D sequence is obtained through multiple detections. Inputting a D sequence including multiple different bit weights into the PN code generator can drive the PN code generator to generate a PN code.

[0071] Step S304, injecting the PN code into the first-stage SAR ADC through the PN jitter signal injection module, so that the SAR ADC circuit works as follows: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, obtain the first-stage output code, and generate a residual voltage at the same time; the residual amplifier amplifies the residual voltage and inputs it to the back-end ADC to quantize it into a second-stage output code.

[0072] In the embodiment of the present invention, the first-stage SAR ADC includes 1 st DAC, comparator and first SAR logic circuit 1 st SAR Logic.

[0073] The PN code is injected into the first-stage SAR ADC through the PN jitter signal injection module. Specifically, the PN code is injected into the 1st DAC through the PN jitter signal injection module, and then the PN code is used to replace the output result of the comparator in the first-stage SAR ADC, and then the input result is input into 1 st In SAR Logic, quantization is completed through quantization operation to output the first-level output code.

[0074] In the embodiment of the present invention, the residual voltage generated by the 1st DAC in the first-stage SAR ADC after PN code injection is amplified by the residual amplifier RA to increase the amplitude of the signal and ensure that the rear-end input signal after subsequent amplification can be effectively transmitted and processed.

[0075] In the embodiment of the present invention, after the back-end input signal is input into the back-end ADC, the back-end ADC may perform a quantization operation thereof, that is, convert the sampled analog signal into a corresponding digital representation to obtain a second-level output code.

[0076] Step S305, calculating the true value of each bit weight in the D sequence according to the second-stage output code.

[0077] Since the input signal at the back end is obtained by amplifying the residual voltage generated by the 1st DAC after PN code injection through the residual amplifier, and the PN code is generated by D sequence control, the second-level output code obtained by quantizing the input signal at the back end contains all the bit weight information. According to the second-level output code, the coefficients of different bit weights are classified by identifying the D sequence, and the low-pass filtering operation of accumulation and averaging is combined with the PN code to calculate the true value of each bit weight in the D sequence.

[0078] Step S306 , performing digital code synthesis according to the first-level output code, the second-level output code and the real value to obtain a complete output code, so as to achieve bit weight calibration.

[0079] In the embodiment of the present invention, the digital code is synthesized by using the first-level output code and the second-level output code and making full use of the real value of each weight in the D sequence, so that the final generated complete output code D out It can more accurately reflect the real characteristics of the collected signal and realize bit weight calibration.

[0080] In the embodiment of the present invention, the generation of the PN code no longer depends on the clock, but is controlled by the metastable detector group through the D sequence generated by detecting the residual voltage, and then the PN code is used to replace the output result of the comparator in the first-stage SAR ADC to complete the quantization operation. Since each bit in the D sequence corresponds to a bit weight, it can be ensured that each PN code generated by using the D sequence corresponds to a different bit weight, so that its pseudo-random robustness can still be maintained in the subsequent processing process, avoiding the damage of the white noise characteristics of the PN code during the operation process, and there is no need to introduce additional algorithms, thereby improving the convergence speed of the bit weight calibration algorithm.

[0081] In one implementation, a metastable detector group is used to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence, including:

[0082] Using a metastable detector group to identify the metastable state of each residual voltage generated in the first-stage SAR ADC;

[0083] A plurality of D sequences corresponding to the bit weights are generated according to the plurality of metastable state identifiers.

[0084] In the embodiment of the present invention, the metastable detector group is used to detect the residual voltage generated each time in the first-stage SAR ADC, so as to identify the metastable state. If a certain time passes through the residual voltage detection circuit, it is identified that the circuit is in a metastable state. On the contrary, if a certain time passes through the residual voltage detection circuit, it is identified that the circuit is in a non-metastable state.

[0085] A D sequence is generated according to a plurality of metastable state identifiers corresponding to a bit weight of each bit in the D sequence.

[0086] In one implementation, assuming that the residual voltage falls into the j-th metastable window in a certain period, when the circuit is in a metastable state, the residual voltage includes:

[0087]

[0088] Wherein, Vin represents the initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the i-th bit; W i Indicates the bit weight of the i-th bit; PN j represents the PN code corresponding to the jth bit; W jrepresents the bit weight of the j-th bit.

[0089] Based on the above residual voltage, the rear-end input signal Vin2 includes:

[0090]

[0091] Where G represents the op amp gain of the residue amplifier.

[0092] In one implementation, calculating the true value of each bit weight in the D sequence according to the second-stage output code includes:

[0093] According to the second-stage output code, the information containing the true value of each bit weight is obtained by utilizing the white noise characteristics of the PN code;

[0094] The second-level output codes are grouped using the D sequence and information containing the true value of each bit weight, and each group of the second-level output codes is accumulated and averaged to obtain multiple groups of operation results;

[0095] Add up multiple groups of operation results to get the true value of each weight in the D sequence.

[0096] The back-end input signal is quantized into the second-level output code D2 by the back-end ADC. In the digital domain, the cross-correlation algorithm is used to calculate the bit weight. Assume that V res When the jth bit falls into the metastable window, D(j) is 1, and the other D bits are all zero, resulting in a D sequence. The D2 corresponding to this D sequence is correlated with the PN code N times, and then the sum is averaged to be:

[0097]

[0098] Where, h represents the counter; N represents the total number of counts of the counter; D2 represents the second-level output code; PN j Indicates the PN code corresponding to the jth bit.

[0099] In one implementation, the information containing the true value of each weight is obtained based on the second-stage output code by using the white noise characteristics of the PN code. According to the white noise characteristics of the PN code, if N is large enough, through low-pass filtering operation, the result of summing and averaging can be approximated as follows:

[0100]

[0101] in, represents the information containing the real value of the bit weight of the first j bits; h represents the counter; N represents the total number of counts of the counter; D2 represents the second-level output code; PN j Indicates the PN code corresponding to the jth bit.

[0102] In the back-end digital processing, the actual value of the bit weight decreases by approximately two times from the most significant bit to the least significant bit. Smaller bit weights require more samples to achieve the same accuracy. For full-swing input, the number of windows per bit weight, and the number of samples captured, doubles from the most significant bit to the least significant bit. See Figure 5 , Figure 5 It is a schematic diagram of the distribution of positive and negative codes generated by the new PN injection in a specific time interval provided by an embodiment of the present invention, wherein the horizontal axis represents the number of windows of bit weight, the left side of the vertical axis represents the number of positive PN codes, and the right side of the vertical axis represents the number of negative PN codes; the new PN injection is the PN code injection method provided by an embodiment of the present invention. Without affecting the calibration speed, setting an exponentially growing averager can improve the robustness and calibration accuracy of the algorithm. The averaging period is an integer multiple of the PN sequence period, which ensures that the number of positive and negative PN codes is equal, thereby preventing interference from common-mode codes and accelerating the convergence speed of the algorithm. See Figure 6 , Figure 6 : This is a schematic diagram of bit weight extraction. The second-level output code D2 is divided into five groups according to the information containing the true value of each bit weight and D(j) with different bit weights, and each group is accumulated and averaged. For example, in the first group, D(1) is point-multiplied with PN1, and the obtained value is accumulated and averaged. Then, the values ​​obtained by performing the same operation on other groups are accumulated, and finally GW5, GW4-GW5, GW3-GW4-GW5, GW2-GW3-GW4-GW5 and GW1-GW2-GW3-GW4-GW5 are obtained respectively. Finally, the true value GW of the bit weight of D(j) is obtained by adding the operation results of each group. j , completing the bit weight calibration.

[0103] See also Figure 7 , Figure 7 The figure is a comparison diagram of the SFDR (Spurious-free Dynamic Range) convergence curves of the traditional PN injection method and the new pseudo-random sequence injection method. In the figure, Multi-PN refers to the new pseudo-random sequence injection method provided in the embodiment of the present invention, Traditional PN refers to the traditional PN injection method, the horizontal axis represents the number of samples, and the vertical axis represents SFDR. After about 600k samples, the calibrated dynamic performance converges stably. The new PN injection retains the white noise characteristics of the PN code, minimizes the impact of the common mode code on the algorithm convergence, and shortens the convergence time to about a quarter of the traditional injection method.

[0104] The present invention optimizes the PN sequence generation logic and proposes a novel pseudo-random sequence injection method to accelerate the convergence of the bit weight calibration algorithm. This method effectively solves the problems of white noise destruction and common mode code interference in traditional bit weight technology. This technology is applicable to all architectures that use bit weight calibration, and achieves a three-fold increase in convergence speed by adding a small amount of overhead.

[0105] Based on the same inventive concept, an embodiment of the present invention further provides a novel pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm, which is used to calibrate a bit weight of a SAR ADC circuit. The SAR ADC circuit includes a first-stage SAR ADC, a residual amplifier, a back-end ADC, and a digital error correction module. Figure 8 , Figure 8 : is a structural schematic diagram of a novel pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm provided by an embodiment of the present invention, the device comprising:

[0106] PN code injection module 801; the PN code injection module includes a metastable detector group, a PN code generator and a PN jitter signal injection module;

[0107] The metastable detector group 802 is used to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight;

[0108] The PN code generator 803 is used to generate a PN code according to the D sequence input to itself;

[0109] The PN jitter signal injection module 804 is used to inject the PN code into the first-stage SAR ADC, so that the SAR ADC works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, obtain the first-stage output code, and generate a residual voltage at the same time; the residual amplifier amplifies the residual voltage and inputs it to the back-end ADC for quantization into the second-stage output code;

[0110] The device also includes:

[0111] A true value calculation module 805, used for calculating the true value of each weight in the D sequence according to the second-level output code;

[0112] The complete output code generation module 806 is used to perform digital code synthesis according to the first-level output code, the second-level output code and the real value to obtain a complete output code to achieve bit weight calibration.

[0113] In the embodiment of the present invention, the generation of the PN code no longer depends on the clock, but is controlled by the metastable detector group through the D sequence generated by detecting the residual voltage, and then the PN code is used to replace the output result of the comparator in the first-stage SAR ADC to complete the quantization operation. Since each bit in the D sequence corresponds to a bit weight, it can be ensured that each PN code generated by using the D sequence corresponds to a different bit weight, so that its pseudo-random robustness can still be maintained in the subsequent processing process, avoiding the damage of the white noise characteristics of the PN code during the operation process, and there is no need to introduce additional algorithms, thereby improving the convergence speed of the bit weight calibration algorithm.

[0114] Optionally, the metastable detector group is specifically used to detect the residual voltage generated each time in the first-stage SAR ADC to perform a metastable state identification; and generate the D sequence according to multiple metastable state identifications.

[0115] Optionally, the residual voltage includes:

[0116]

[0117] Wherein, Vin represents the initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the i-th bit; W i Indicates the bit weight of the i-th bit; PN j represents the PN code corresponding to the jth bit; W j represents the bit weight of the j-th bit.

[0118] Optionally, the true value calculation module is specifically used to obtain information containing the true value of each bit weight based on the second-level output code by utilizing the white noise characteristics of the PN code; group the second-level output codes using the D sequence and the information containing the true value of each bit weight, and obtain multiple groups of calculation results by accumulating and averaging each group of grouped second-level output codes; and add the multiple groups of calculation results to obtain the true value of each bit weight.

[0119] Optionally, the true value calculation module obtains information including the true value of each bit weight according to the second-stage output code by using the white noise characteristic of the PN code, including:

[0120]

[0121] in, represents information containing the true value of the bit weight of the first j bits; h represents a counter; N represents the total number of counts of the counter; and D2 represents the second-level output code.

[0122] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0123] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0124] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0125] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0126] It should be noted that the device of an embodiment of the present invention is a device that applies the above-mentioned new pseudo-random sequence injection method that accelerates the convergence of the bit weight calibration algorithm. All embodiments of the above-mentioned new pseudo-random sequence injection method that accelerates the convergence of the bit weight calibration algorithm are applicable to the device and can achieve the same or similar beneficial effects.

[0127] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A novel pseudo-random sequence injection method for accelerating the convergence of a bit weight calibration algorithm is applied to a SAR ADC circuit, wherein the SAR ADC circuit includes a first-stage SAR ADC, a residual amplifier, a back-end ADC, and a digital error correction module, and is characterized in that: The method comprises: Introducing a PN code injection module; the PN code injection module includes a metastable detector group, a PN code generator and a PN jitter signal injection module; Using the metastable detector group to detect the residual voltage generated each time in the first-stage SAR ADC, to obtain a D sequence; each bit in the D sequence corresponds to a bit weight; Inputting the D sequence into the PN code generator to generate a PN code; The PN code is injected into the first-stage SAR ADC through the PN jitter signal injection module, so that the SAR ADC circuit works as follows: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, obtain the first-stage output code, and generate a residual voltage at the same time; the residual amplifier amplifies the residual voltage and inputs it to the back-end ADC for quantization into a second-stage output code; Calculate the true value of each bit weight in the D sequence according to the second-level output code; A complete output code is obtained by performing digital code synthesis according to the first-level output code, the second-level output code and the real value, so as to realize bit weight calibration.

2. The novel pseudo-random sequence injection method according to claim 1, characterized in that: Detecting the residual voltage generated each time in the first-stage SAR ADC using the metastable detector group to obtain a D sequence includes: Using the metastable detector group to identify the metastable state of the residual voltage generated each time in the first-stage SAR ADC; The D sequence is generated according to a plurality of metastable state identifiers.

3. The novel pseudo-random sequence injection method according to claim 1, characterized in that: The residual voltage includes: Wherein, Vin represents the initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the i-th bit; W i Indicates the bit weight of the i-th bit; PN j represents the PN code corresponding to the jth bit; W j represents the bit weight of the j-th bit.

4. The novel pseudo-random sequence injection method according to claim 3 is characterized in that: Calculating the true value of each bit weight in the D sequence according to the second-stage output code includes: According to the second-stage output code, using the white noise characteristic of the PN code, obtaining information including the true value of each bit weight; The second-level output codes are grouped by using the D sequence and the information containing the true value of each bit weight, and each group of the second-level output codes is accumulated and averaged to obtain multiple groups of operation results; The multiple groups of operation results are added together to obtain the true value of each weight in the D sequence.

5. The novel pseudo-random sequence injection method according to claim 4, characterized in that: According to the second-stage output code, the information including the true value of each bit weight is obtained by utilizing the white noise characteristic of the PN code, including: in, represents information containing the true value of the bit weight of the first j bits; h represents a counter; N represents the total number of counts of the counter; D2 represents the second-level output code.

6. A novel pseudo-random sequence injection device for accelerating the convergence of a bit weight calibration algorithm, used for performing bit weight calibration on a SAR ADC circuit, wherein the SAR ADC circuit comprises a first-stage SAR ADC, a residual amplifier, a back-end ADC and a digital error correction module, characterized in that: The device comprises: PN code injection module; the PN code injection module includes a metastable detector group, a PN code generator and a PN jitter signal injection module; The metastable detector group is used to detect the residual voltage generated each time in the first-stage SAR ADC to obtain a D sequence; each bit in the D sequence corresponds to a bit weight; The PN code generator is used to generate a PN code according to the D sequence input to itself; The PN jitter signal injection module is used to inject the PN code into the first-stage SAR ADC, so that the SAR ADC circuit works in the following manner: the first-stage SAR ADC uses the PN code to replace the output of the comparator in the first-stage SAR ADC to complete the quantization operation, obtain the first-stage output code, and generate a residual voltage at the same time; the residual amplifier amplifies the residual voltage and inputs it to the back-end ADC for quantization into the second-stage output code; The device also includes: A true value calculation module, used for calculating the true value of each weight in the D sequence according to the second-level output code; The complete output code generation module is used to perform digital code synthesis according to the first-level output code, the second-level output code and the real value to obtain a complete output code to achieve bit weight calibration.

7. The novel pseudo-random sequence injection device according to claim 6, characterized in that: The metastable detector group is specifically used to detect the residual voltage generated each time in the first-stage SAR ADC to identify the metastable state; and generate the D sequence according to multiple metastable state identifiers.

8. The novel pseudo-random sequence injection device according to claim 6, characterized in that: The residual voltage includes: Wherein, Vin represents the initial input signal of the first-stage SAR ADC; B(i) represents the output result of the comparator corresponding to the i-th bit; W i Indicates the bit weight of the i-th bit; PN j represents the PN code corresponding to the jth bit; W j represents the bit weight of the j-th bit.

9. The novel pseudo-random sequence injection device according to claim 8, characterized in that: The true value calculation module is specifically used to obtain information containing the true value of each bit weight according to the second-level output code using the white noise characteristics of the PN code; group the second-level output codes using the D sequence and the information containing the true value of each bit weight, and accumulate and average the grouped second-level output codes to obtain multiple groups of operation results; and add the multiple groups of operation results to obtain the true value of each bit weight.

10. The novel pseudo-random sequence injection device according to claim 9, characterized in that: The true value calculation module obtains information including the true value of each bit weight according to the second-stage output code and using the white noise characteristic of the PN code, including: in, represents information containing the true value of the bit weight of the first j bits; h represents a counter; N represents the total number of counts of the counter; D2 represents the second-level output code.

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