Printed circuit board and manufacturing method thereof

Abstract

The present disclosure provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a wiring layer disposed on the insulating layer and including a plurality of metal pads and at least one metal pattern; and a solder resist layer disposed on an upper portion of the insulating layer, covering at least a portion of the wiring layer, and having a plurality of first opening portions exposing at least a portion of each of the plurality of metal pads, and one or more second opening portions exposing at least a portion of the at least one metal pattern, respectively. The second opening portion has, in a plane, at least two recessed portions recessed toward an interior of the second opening portion. The plurality of first opening portions and the one or more second opening portions are provided in a mounting region of a semiconductor chip of the solder resist layer.

Description

[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0189429 filed on December 22, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0135919 filed on October 12, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board and a method for manufacturing the same. Background Art

[0003] When mounting a semiconductor chip on a package substrate, solder balls may be used as bumps. For example, the semiconductor chip and the package substrate may be connected by contacting a connection pad formed on the semiconductor chip with a solder ball formed on the outermost side of the package substrate. On the other hand, in the process of mounting such a semiconductor chip, due to the difference in thermal expansion coefficient between the semiconductor chip and the package substrate, the semiconductor chip and the package substrate may be bent to different degrees during heating. As a result, since stress may be concentrated on the bumps at the edge of the semiconductor chip, cracks may be generated in the bumps. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board and a method of manufacturing the same which can improve adhesion between a semiconductor chip and a package substrate when mounting the semiconductor chip.

[0005] An aspect of the present disclosure is to provide a printed circuit board and a method of manufacturing the same that can prevent cracks from being generated in bumps formed using micro balls or the like at edge portions of semiconductor chips when mounting the semiconductor chips.

[0006] According to one aspect of the present disclosure, in a mounting area of ​​a semiconductor chip formed on an outermost solder resist layer of a board, in addition to a plurality of first openings that respectively expose a plurality of metal pads, one or more second openings are further formed to include second openings in a form that are connected to each other when two holes respectively expose metal patterns, and solder bumps are respectively formed on the plurality of first openings and the second openings for mounting the semiconductor chip.

[0007] According to one aspect of the present disclosure, a printed circuit board includes: an insulating layer; a wiring layer, which is arranged on the insulating layer and includes a plurality of metal pads and at least one metal pattern; and a solder resist layer, which is arranged on the upper part of the insulating layer, covers at least a portion of the wiring layer, and has a plurality of first openings that expose at least a portion of each of the plurality of metal pads and one or more second openings that expose at least a portion of the at least one metal pattern. The second opening has at least two recesses that are recessed toward the inside of the second opening in a plane. The plurality of first openings and the one or more second openings are arranged in the mounting area of ​​the semiconductor chip of the solder resist layer.

[0008] According to one aspect of the present disclosure, a method for manufacturing a printed circuit board includes: forming a wiring layer including a plurality of metal pads and at least one metal pattern on an upper portion of an insulating layer; forming a solder resist layer covering at least a portion of the wiring layer on the upper portion of the insulating layer; and forming a plurality of first openings respectively exposing at least a portion of each of the plurality of metal pads and one or more second openings respectively exposing at least a portion of the at least one metal pattern in the solder resist layer. In the step of forming the plurality of first openings and the one or more second openings: the second opening is formed to have at least two recesses on a plane that are recessed toward the inside of the second opening, and the plurality of first openings and the one or more second openings are formed in a mounting region of a semiconductor chip of the solder resist layer.

[0009] According to one aspect of the present disclosure, a printed circuit board includes: an insulating layer; a wiring layer, which is arranged on the insulating layer and includes a plurality of metal pads and a metal pattern; a solder resist layer, which is arranged on an upper portion of the insulating layer, covers at least a portion of the wiring layer, and has a plurality of first opening portions that respectively expose at least a portion of each of the plurality of metal pads and two openings that respectively expose at least a portion of the metal pattern, wherein the two openings are connected to each other and have at least two recesses that are recessed toward the inside of the two openings in a plane; a plurality of first solder bumps, which are respectively arranged on the plurality of first opening portions and respectively connected to the plurality of metal pads; and a second solder bump, which is arranged on the two openings and connected to the metal pattern.

[0010] According to one aspect of the present disclosure, a printed circuit board includes: an insulating layer; a wiring layer, which is disposed on the insulating layer and includes a plurality of metal pads and a ground pattern; a solder resist layer, which is disposed on an upper portion of the insulating layer, covers at least a portion of the wiring layer, and has a plurality of first openings that expose at least a portion of each of the plurality of metal pads and two openings that expose at least a portion of the ground pattern. The two openings are connected to each other and have at least two recesses that are recessed toward the inside of the two openings in a plane, and the ground pattern is spaced apart from and surrounds at least one of the plurality of metal pads on the plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board; Figure 4 yes Figure 3 A schematic top view of a printed circuit board; Figure 5 yes Figure 3 Another schematic top view of a printed circuit board; Figure 6 yes Figure 3 Another schematic top view of a printed circuit board; Figure 7 yes Figure 3 Another schematic top view of a printed circuit board; Figure 8 is a cross-sectional view schematically showing another example of a printed circuit board; Fig. 9 is a cross-sectional view schematically showing another example of a printed circuit board; Fig.10 is a cross-sectional view schematically showing another example of a printed circuit board; FIG. 11A to FIG. 11G is a process diagram schematically showing an example of manufacturing a printed circuit board; and FIG. 12A to FIG. 12F Another example process for manufacturing a printed circuit board is schematically illustrated. DETAILED DESCRIPTION

[0012] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0013] Electronic Devices Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0014] Reference Figure 1 , a mainboard 1010 may be accommodated in the electronic device 1000. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below via various signal lines 1090.

[0015] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may also be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0016] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE802.16 series, etc.), IEEE802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), etc. +), Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Wireless Local Area Network (Wireless LAN), Bluetooth, Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol and Fifth Generation Mobile Communication Technology (5G) Protocol, and any other wireless standards or protocols and wired standards or protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components that are compatible with various other wireless standards or protocols or wired standards or protocols or communicate according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020.

[0017] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components in the form of chip components for various other purposes, etc. In addition, the other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080, etc., but are not limited thereto. These other electronic components may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, etc., the electronic device 1000 may also include other electronic components for various purposes.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0020] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0021] Referring to the accompanying drawings, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 is housed inside the smart phone 1100, and an electronic component 1120 is physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 are housed in the smart phone 1100. Some of the electronic components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device need not be limited to the smart phone 1100, and may also be other electronic devices as described above.

[0022] Printed Circuit Board Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0023] Figure 4 yes Figure 3 Schematic top view of a printed circuit board.

[0024] Referring to the drawings, a printed circuit board 100A according to an example may include: an insulating layer 111; a wiring layer 121 disposed on an upper portion of the insulating layer 111; and a solder resist layer 151 disposed on an upper portion of the insulating layer 111 and covering at least a portion of the wiring layer 121. The wiring layer 121 may include a plurality of metal pads 121-1 and at least one metal pattern 121-2. The solder resist layer 151 may have a plurality of first openings h1 exposing at least a portion of each of the plurality of metal pads 121-1 and one or more second openings h2 exposing at least a portion of each of the at least one metal pattern 121-2. The plurality of first openings h1 and the one or more second openings h2 may be disposed in a mounting region A of a semiconductor chip.

[0025] Each of the plurality of first openings h1 may have one opening. On the other hand, each of the one or more second openings h2 may have two openings h2-1 and h2-2 connected to each other, and if necessary, each second opening may have more openings. Here, "each of the plurality of first openings has one opening" may also be briefly described as "the first opening has one opening", and "each of the one or more second openings has two openings connected to each other" may also be briefly described as "the second opening has two openings connected to each other". In the cross section, each opening h2-1 and h2-2 may penetrate the solder resist layer 151 in the thickness direction, and each opening h2-1 and h2-2 may have a predetermined shape such as a substantially circular, elliptical, polygonal or star-shaped shape in the plane. Specifically, each of the openings h2-1 and h2-2 may have a substantially circular or elliptical shape in the plane. Therefore, the second opening h2 may have at least two recesses e1 and e2 that are recessed toward the inside of the second opening h2 in the plane.

[0026] Each of the one or more second openings h2 may have a shape in which two openings h2-1 and h2-2 are connected in a plane so that at least a portion of the two openings h2-1 and h2-2 overlap each other. Therefore, each of the one or more second openings h2 has at least two recesses e1 and e2, and the recesses e1 and e2 may have sharp inflection points facing each other. For example, each of the one or more second openings h2 may have a snowman shape in a plane. On the other hand, when the two openings h2-1 and h2-2 overlap each other, based on the remaining non-overlapping shapes of the two openings h2-1 and h2-2, an imaginary shape when they do not overlap in a plane can be derived. Therefore, even if it does not have a complete predetermined shape in a plane due to overlap, etc., it can be defined as an opening used in the present disclosure.

[0027] As described above, in the process of mounting the semiconductor chip on the package substrate, due to the difference in physical properties between the package substrate and the semiconductor chip, such as the difference in bending due to thermal behavior, stress concentration may be generated at the bump located at the lower part of the semiconductor chip. On the other hand, in a printed circuit board 100A according to an example, one or more second openings h2 (each of the second openings h2 may have two openings h2-1 and h2-2 connected to each other) may be provided in the mounting area A of the semiconductor chip, and in this case, when the solder balls are provided in the respective openings h2-1 and h2-2 and then reflowed, for example, a double-ball solder bump may be formed. Therefore, adhesion to the connected semiconductor chip may be enhanced. In addition, the second opening h2 may be provided on the edge side of the mounting area A of the semiconductor chip, and therefore, the solder bump formed in the second opening h2, for example, in the form of a double ball, may be connected to the edge portion of the semiconductor chip. For example, a plurality of first openings h1 may be provided in the central portion of the mounting area A, and one or more second openings h2 may be provided in the peripheral portion surrounding the central portion of the mounting area A. Therefore, cracks can be more effectively prevented from being generated in the solder bumps at the edge portion of the semiconductor chip where stress is concentrated during the installation of the semiconductor chip. In addition, the solder bumps formed in the form of double balls and arranged on the edge side of the mounting area A of the semiconductor chip are sufficiently spaced apart from the signal solder bumps arranged in the central portion of the mounting area A of the semiconductor chip, thereby eliminating potential risks such as short circuits. In addition, some of the solder bumps connected to the edge portion of the semiconductor chip may not be connected to the signal and may be arranged to be grounded, and in this case, these solder bumps may only be responsible for the bonding between the semiconductor chip and the package substrate. Therefore, for example, even if the double-ball solder bump is connected to the connection pad of the semiconductor chip, it can be regarded as a good product. On the other hand, if the size of the second opening h2 is simply made larger than the size of the first opening h1, errors may occur in the solder ball installation process, and in addition, it may be difficult to control the height deviation of the solder bump. Therefore, it is expected that the second opening h2 is formed in the above-mentioned form.

[0028] On the other hand, each of the maximum radii r2-1 and r2-2 on the plane of the two openings h2-1 and h2-2 of each of the one or more second openings h2 may be larger than the maximum radius r1 of each of the plurality of first openings h1 on the plane. In this case, the maximum radius may be the distance from the center (or center point) of the opening to the farthest edge, regardless of the shape of the opening. For example, the area of ​​each of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on the plane may be larger than the area of ​​each of the plurality of first openings h1 on the plane. In this case, for example, the reliability of the double-ball solder bump formed in the one or more second openings h2 may be further improved.

[0029] On the other hand, in at least one of the one or more second openings h2, an imaginary line connecting the center point of each of the two openings h2-1 and h2-2 may be approximately parallel or approximately perpendicular to an imaginary edge of the mounting area A of the semiconductor chip. In addition, in at least another second opening h2 of the one or more second openings h2, a first imaginary line connecting the center point of each of the two openings h2-1 and h2-2 may be approximately parallel or approximately perpendicular to a second imaginary line connecting the center point of the mounting area A of the semiconductor chip and the center point of the at least another second opening h2 (i.e., the midpoint of the first imaginary line). For example, the one or more second openings h2 may be arranged in various shapes to distribute stress. In this case, the center point may be the spatial center of the construction on the plane.

[0030] On the other hand, the solder resist layer 151 may also have a plurality of third openings h3 that expose at least another portion of at least one metal pattern 121-2, respectively. Each of the plurality of third openings h3 may have one opening. For example, the plurality of third openings h3 may be disposed on a ground or power source, and may be disposed in various spaces within the mounting region A of the semiconductor chip. Therefore, the reliability of the connection with the semiconductor chip may be further improved by the solder bumps disposed on the plurality of third openings h3.

[0031] On the other hand, the mounting area A of the semiconductor chip may include a quadrilateral area created by roughly connecting the outer edges of the outermost openings of the openings including a plurality of first openings h1, one or more second openings h2, and a plurality of third openings h3 with straight lines. On the other hand, when delimiting the quadrilateral area, when drawing imaginary lines, some protruding or partially concave portions of the outer edges of the outermost openings on the plane may be excluded. In addition, the angle at which different imaginary straight lines intersect may be roughly a right angle. For example, the quadrilateral area may have a roughly rectangular or roughly square shape in a plane. The mounting area A of the semiconductor chip including the quadrilateral area may be a bump area formed with solder bumps for mounting the semiconductor chip. Therefore, when delimiting the quadrilateral area, a plurality of fourth openings h4 or reference mark M may be excluded. For example, the reference mark M is used to indicate the mounting area of ​​the semiconductor chip with a larger area, and may be specifically formed near at least one of all four corners of the mounting area A (e.g., quadrilateral area) of the semiconductor chip. In addition, the plurality of fourth opening portions h4 are used to mount passive components, and may be formed near the mounting region A (eg, a quadrangular region) of the semiconductor chip.

[0032] On the other hand, at least one of the plurality of metal pads 121-1 may be spaced apart from at least one metal pattern 121-2, and the entire side thereof may be continuously surrounded by at least one metal pattern 121-2. Figure 4 , referring to the accompanying drawings on the right side, in the case where the solder resist layer 151 is omitted from the enlarged view, an annular groove exposing the insulating layer 111 may be formed between each of the at least one metal pad 121-1 and at least one metal pattern 121-2 surrounding the corresponding one metal pad 121-1. For example, each of the plurality of metal pads 121-1 may include a metal pad for a signal, and at least one metal pattern 121-2 may include a metal pattern for grounding. As shown in the accompanying drawings, the grounding metal pattern may be formed to be wider, so that the at least two second openings h2 may respectively expose different portions of the grounding metal pattern.

[0033] On the other hand, the plurality of first openings h1 are of solder mask defined (SMD) type, and may expose a portion of each of the plurality of metal pads 121-1. In addition, the one or more second openings h2 may also be of solder mask defined (SMD) type, and may expose at least a portion of at least one metal pattern 121-2, respectively. In addition, the plurality of third openings h3 are also of solder mask defined (SMD) type, and may expose at least another portion of at least one metal pattern 121-2, respectively. Therefore, the solder bump may be formed more stably. However, the present disclosure is not limited thereto, and a non-solder mask defined (NSMD) type, a combination type of SMD and NSMD, or other modified types may be applied.

[0034] On the other hand, the printed circuit board 100A according to one example may be used as the outermost layer of a multilayer circuit board. The multilayer circuit board may be used as a flip chip board (FCB), a ball grid array (BGA) board, an interposer, a package board, etc. However, the present disclosure is not limited thereto, and various other types of boards may be used.

[0035] Hereinafter, components of a printed circuit board 100A according to an example will be described in more detail with reference to the accompanying drawings.

[0036] The insulating layer 111 may include an inorganic insulating material and / or an organic insulating material. Examples of organic insulating materials may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or resins including inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabrics using glass cloth as an example). For example, the organic insulating material may be a copper clad laminate (CCL), a prepreg (PPG), an Ajinomoto deposited film (ABF), a photoimageable dielectric (PID), etc., but are not limited thereto. The inorganic insulating material may include a glass substrate, a silicon substrate, and / or a ceramic substrate. For example, the glass substrate may include glass, for example, the glass may include pure silicon dioxide (approximately 100% SiO 2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc., but the present disclosure is not limited thereto. For example, as optional glass materials, fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as materials for the glass substrate. In addition, other additives may be further included to form glass with specific physical properties. These additives include at least one of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur and antimony, carbonates and oxides of these elements, for example, calcium carbonate (e.g., lime), but the present disclosure is not limited thereto, and the additives may also include sodium carbonate (e.g., soda). On the other hand, glass may be distinguished from glass fibers contained in organic insulating materials (e.g., glass fabrics such as glass cloth). In addition, the silicon substrate may include silicon (Si), and if necessary, may include an oxide layer formed on the silicon (Si). In addition, the silicon substrate may include a nitride layer formed on the oxide layer. On the other hand, the oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but are not limited thereto. In addition, the ceramic substrate may include a ceramic, and the ceramic may include, for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ) etc., but not limited thereto. The insulating layer 111 may include a plurality of layers as required.

[0037] The wiring layer 121 may include a metal. Examples of the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and specifically, copper (Cu) may be included, but the present disclosure is not limited thereto. The wiring layer 121 may perform various functions according to the design, and, for example, may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may include a line pattern, a pad pattern, a plane pattern, and the like. The wiring layer 121 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, and both may also be included. In addition, a copper foil may also be included. The wiring layer 121 may be arranged to protrude on the upper surface of the insulating layer 111. If necessary, the wiring layer 121 may be embedded in the insulating layer 111, and the upper surface of the wiring layer 121 may be exposed from the upper surface of the insulating layer 111.

[0038] The solder resist layer 151 may include a solder resist. The solder resist may be a photosensitive material or a liquid solder resist. However, the solder resist is not limited thereto, and may be a non-photosensitive material, or may be a film-type solder resist. The solder resist layer 151 may have a plurality of first openings h1, one or more second openings h2, a plurality of third openings h3, and a plurality of fourth openings h4. Each of these openings may be formed as a solder mask defined (SMD) type, but is not limited thereto, and a non-solder mask defined (NSMD) type, or a combination type of SMD and NSMD, or other modified types may be applied. The solder resist layer 151 may have a mounting area A of a semiconductor chip, and may have a reference mark M surrounding the mounting area A of the semiconductor chip.

[0039] Figure 5 yes Figure 3 Another schematic top view of a printed circuit board.

[0040] Referring to the accompanying drawings, each of the one or more second openings h2 may have a shape in which two openings h2-1 and h2-2 are spaced apart from each other and connected by a straight groove g (i.e., a straight-line-shaped groove) on a plane. Therefore, each of the one or more second openings h2 may have at least two recesses e1 and e2, each of which may have two inflection points between a curve and a straight line. For example, each of the one or more second openings h2 may have a dumbbell shape in a plan view. The straight groove g may penetrate the solder resist layer 151 in the thickness direction in a cross section, and may have a predetermined shape, such as a substantially quadrilateral, on a plane. In this case, the above-mentioned technical effects may also be obtained. On the other hand, when the respective openings h2-1 and h2-2 are spaced apart from each other and connected by a straight groove g, based on the remaining shape except for the connecting portion of the respective openings h2-1 and h2-2, an imaginary shape when the openings h2-1 and h2-2 are not connected may be derived. Therefore, even if it does not have a complete predetermined shape on a plane due to the connection by the straight groove g, it may be defined as an opening used in the present disclosure.

[0041] On the other hand, the length d of the straight groove g may be less than each of the maximum radii r2-1 and r2-2 of each opening h2-1 and h2-2. In this case, the length d of the straight groove g may be the spacing distance between each opening h2-1 and h2-2. In addition, as described above, the maximum radius may be the distance from the center point of the opening to the farthest edge, regardless of the shape of the opening. If the length d of the straight groove g is longer than the maximum radius r2-1 of the opening h2-1 and / or the maximum radius r2-2 of the opening h2-2, during the reflow process, it may be difficult to connect the solder balls arranged in each opening h2-1 and h2-2 to each other, and it may be difficult to control the height deviation of the solder bump. Alternatively, the two openings h2-1 and h2-2 may be connected by grooves of other shapes, and the width of the groove may be less than the diameter of each of the two openings h2-1 and h2-2.

[0042] In addition, the other contents are substantially the same as the above contents, so redundant descriptions thereof are omitted. On the other hand, the shapes of one or more second openings h2 can be combined into various shapes, for example, Figure 4 The snowman shape shown in Figure 5 The dumbbell shape shown in .

[0043] Figure 6 yes Figure 3 Another schematic top view of a printed circuit board.

[0044] Referring to the accompanying drawings, one or more second openings h2 may have a shape in which two openings h2-1 and h2-2 are connected to each other in an overlapping manner on a plane. Therefore, each of the one or more second openings h2 has at least two recesses e1 and e2, and the recesses e1 and e2 may have sharp inflection points facing each other. For example, each of the one or more second openings h2 may have a snowman shape on a plane. At this time, each of the maximum radii r2-1 and r2-2 of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane is substantially equal to the maximum radius r1 of each of the multiple first openings h1 on a plane, or may be less than the maximum radius r1 of each of the multiple first openings h1 on a plane. In this case, as described above, the maximum radius may be the distance from the center of the opening to the farthest edge, regardless of the shape of the opening. For example, the area of ​​each of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane may be substantially the same as the area of ​​each of the multiple first openings h1 on a plane, or may be less than the area of ​​each of the multiple first openings h1 on a plane. In this case, when a solder ball is mounted in each of the plurality of first openings h1, the solder ball may also be mounted in one or more second openings h2, respectively, and a reflow process may be performed at the same time. Therefore, the process may be further simplified.

[0045] Apart from this, the other contents are roughly the same as the above contents, so any redundant description related thereto will be omitted.

[0046] Figure 7 yes Figure 3 Another schematic top view of a printed circuit board.

[0047] Referring to the accompanying drawings, each of the one or more second openings h2 may have a shape in which two openings h2-1 and h2-2 are spaced apart from each other and connected by a straight groove g on a plane. Therefore, each of the one or more second openings h2 may have at least two recesses e1 and e2, each of which may have two inflection points between a curve and a straight line. For example, each of the one or more second openings h2 may have a dumbbell shape in a plan view. At this time, each of the maximum radii r2-1 and r2-2 of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane is substantially equal to the maximum radius r1 of each of the plurality of first openings h1 on a plane, or may be less than the maximum radius r1 of each of the plurality of first openings h1 on a plane. In this case, as described above, the maximum radius may be the distance from the center of the opening to the farthest edge, regardless of the shape of the opening. For example, the area of ​​each of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane may be substantially the same as the area of ​​each of the plurality of first openings h1 on a plane, or may be smaller than the area of ​​each of the plurality of first openings h1 on a plane. In this case, when solder balls are mounted in the plurality of first openings h1, solder balls may also be mounted in the one or more second openings h2, and the reflow process may be performed simultaneously. Therefore, the process may be further simplified.

[0048] The other contents are substantially the same as those described above, and thus redundant descriptions thereof are omitted. On the other hand, the shapes of one or more second openings h2 can be combined into various shapes, and for example, can be combined and applied. Figure 6 The snowman shape shown in Figure 7 The dumbbell shape shown in .

[0049] Figure 8 is a cross-sectional view schematically showing another example of a printed circuit board.

[0050] Referring to the accompanying drawings, compared with the printed circuit board 100A according to the above example, a printed circuit board 100B according to another example may further include a surface treatment layer P and a solder layer Q, the surface treatment layer P including a first surface treatment layer P1 arranged in a plurality of first opening portions h1 and covering an exposed surface of each of a plurality of metal pads 121-1 and a second surface treatment layer P2 arranged in one or more second opening portions h2 and covering an exposed surface of at least one metal pattern 121-2, the solder layer Q including a plurality of first solder bumps Q1 respectively arranged on the plurality of first opening portions h1 and respectively connected to the plurality of metal pads 121-1 through the first surface treatment layer P1 and one or more second solder bumps Q2 respectively arranged on the one or more second opening portions h2 and respectively connected to at least one metal pattern 121-2 through the second surface treatment layer P2.

[0051] On the other hand, the surface treatment layer P may further include a third surface treatment layer (not shown) disposed on the surface of the metal pattern 121-2 exposed by the plurality of third openings (not shown). In addition, the solder layer Q may further include a plurality of third solder bumps (not shown) respectively connected to the third surface treatment layer (not shown). In addition, the surface treatment layer P may further include a fourth surface treatment layer P4 disposed on the surface of the metal pattern 121-2 exposed by the plurality of fourth openings h4. In addition, the solder layer Q may further include a plurality of fourth solder bumps Q4 respectively connected to the fourth surface treatment layer P4.

[0052] On the other hand, when mounting the semiconductor chip 10 (see Fig. 9 ), the solder layer Q may have excellent flatness before being formed. For example, among the plurality of first solder bumps Q1, the one or more second solder bumps Q2, the plurality of third solder bumps (not shown), and the plurality of fourth solder bumps Q4, the height difference between the solder bump having the maximum height and the solder bump having the minimum height may be in the range of about 20 μm. In this case, the deviation of the bump height can be reduced by improving the process capability, thereby improving the yield and assembly quality, and the defects caused by the bump height during substrate manufacturing can be eliminated, thereby further improving the yield. In this regard, the shape and size of each opening and each groove of the one or more second openings h2 may be controlled so that the height difference of the solder bumps can be maintained.

[0053] Hereinafter, components of a printed circuit board 100B according to another example will be described in more detail with reference to the accompanying drawings.

[0054] The surface treatment layer P can be formed, for example, by electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP), electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, electroless nickel palladium immersion gold (ENEPIG), direct immersion gold (DIG) plating, hot air solder leveling (HASL), etc., but the present disclosure is not limited thereto. For example, the surface treatment layer P can be formed by one or more of electroless nickel plating, electroless palladium plating, and displacement gold plating. Therefore, each of the first surface treatment layer P1, the second surface treatment layer P2, the third surface treatment layer (not shown), and the fourth surface treatment layer P4 may include one or more of a nickel layer, a palladium layer, and a gold layer, and specifically, each of the first surface treatment layer P1, the second surface treatment layer P2, the third surface treatment layer (not shown), and the fourth surface treatment layer P4 may include all of a nickel layer, a palladium layer, and a gold layer, but the present disclosure is not limited thereto.

[0055] The solder layer Q may be formed using a low melting point metal (e.g., tin (Sn)-aluminum (Al)-copper (Cu) solder, etc.), but this is only an example. The material thereof is not particularly limited. The first solder bump Q1, the third solder bump (not shown), and the fourth solder bump Q4 may each have a microball shape, and each of the second solder bumps Q2 may have a shape in which at least two microballs are connected to each other by reflow (e.g., a double ball shape). The double ball may have a protrusion on each top surface, but is not limited thereto, and may have a single protrusion at the center of the top surface, or its top surface may be flat as a whole.

[0056] Apart from this, the other contents are roughly the same as the above contents, so redundant descriptions related to them are omitted. On the other hand, it goes without saying that Figures 3 to 7 The above-described contents can also be applied to a printed circuit board 100B according to another example.

[0057] Fig. 9 is a cross-sectional view schematically showing another example of a printed circuit board.

[0058] Referring to the drawings, compared with the printed circuit board 100B according to the above-mentioned another example, the printed circuit board 100C according to another example may include a semiconductor chip 10 and a passive component 20 respectively disposed on the solder resist layer 151. The semiconductor chip 10 may be disposed on the mounting area A of the semiconductor chip, and the passive component 20 may be disposed around it. The semiconductor chip 10 may include a plurality of connection pads (not shown) respectively connected to the first solder bump Q1, the second solder bump Q2, and the third solder bump (not shown). The passive component 20 may include a plurality of external electrodes (not marked) respectively connected to the fourth solder bump Q4.

[0059] Hereinafter, components of a printed circuit board 100C according to another example will be described in more detail with reference to the accompanying drawings.

[0060] The semiconductor chip 10 may include an integrated circuit (IC) die in which hundreds to millions or more devices are integrated into a single chip. In this case, the integrated circuit die may be a processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (e.g., AP); the integrated circuit die may be a logic chip, such as a field programmable gate array (FPGA), an analog-to-digital converter, an application specific IC (ASIC), etc., but is not limited thereto, and may also be a memory chip such as a volatile memory (e.g., DRAM, high bandwidth memory (HBM)), a non-volatile memory (e.g., ROM, flash memory), or other types of chips such as a power management IC (PMIC). The number of semiconductor chips 10 may be multiple, in which case semiconductor chips of the same type or different types may be respectively arranged on the mounting area A of the semiconductor chip.

[0061] The semiconductor chip 10 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a substrate constituting each body. Various circuits may be formed in the body. A plurality of connection pads may be formed on each body, and each of the plurality of connection pads may include a conductive material such as aluminum (Al) or copper (Cu). The semiconductor chip 10 may be a bare die, and in this case, each metal bump may be provided on the connection pad as required. The semiconductor chip 10 may be a packaged die, and in this case, an additional redistribution layer is formed on the plurality of connection pads, and a plurality of metal bumps may be provided on the redistribution layer as required.

[0062] The passive component 20 may be a chip component, for example, a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-fired ceramic (LTCC) component, an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), etc., but is not limited thereto. There may be a plurality of passive components 20, and the corresponding passive components 20 may be of the same type or of different types.

[0063] Apart from this, the other contents are roughly the same as the above contents, so redundant descriptions related to them are omitted. On the other hand, it goes without saying that Figures 3 to 8 The above-described contents can also be applied to a printed circuit board 100C according to another example.

[0064] Fig.10 is a cross-sectional view schematically showing another example of a printed circuit board.

[0065] Referring to the drawings, a printed circuit board 100D according to another example may be a multi-layered semiconductor package structure including the above-described printed circuit board 100C according to another example as an outermost configuration. For example, according to another example, a printed circuit board 100D may include: a core-type first substrate portion 141; a coreless second substrate portion 142, which is arranged on the first substrate portion 141; a first solder resist layer 151 and a second solder resist layer 152, which are respectively arranged on the first substrate portion 141 and the second substrate portion 142; a surface treatment layer P, which is respectively arranged in a plurality of openings of the first solder resist layer 151 and respectively connected to at least a portion of the exposed top third stacking wiring layer 121; a solder layer Q, including a plurality of solder bumps respectively arranged on a plurality of openings of the first solder resist layer 151 and respectively connected to the surface treatment layer P; a semiconductor chip 10 and a passive component 20, which are arranged on the first solder resist layer 151 and respectively connected to the top third stacking wiring layer 121 through the solder layer Q; and a plurality of electrical connection metals 160, which are respectively arranged on a plurality of openings of the second solder resist layer 152 and respectively connected to at least a portion of the exposed bottom second stacking wiring layer 186.

[0066] On the other hand, the second substrate portion 142 may have a higher wiring density than the wiring density of the first substrate portion 141. For example, the second substrate portion 142 may include high-density wiring with a relatively fine pitch than the wiring of the first substrate portion 141, and the first substrate portion 141 may include wiring with a relatively low density than the wiring of the second substrate portion 142. For example, compared with the wiring of the first substrate portion 141, the wiring of the second substrate portion 142 may be relatively smaller in thickness, line width / spacing, pitch, etc. In addition, the insulation distance between the wirings disposed on different layers of the second substrate portion 142 may be smaller. For example, the printed circuit board 100D according to another example may include a 2.nD package board.

[0067] Hereinafter, components of a printed circuit board 100D according to another example will be described in more detail with reference to the accompanying drawings.

[0068] The first substrate portion 141 may be a core-type multilayer substrate. For example, the first substrate portion 141 may include: a core insulation layer 171; a first core wiring layer 181 and a second core wiring layer 182, which are respectively arranged on the upper surface and the lower surface of the core insulation layer 171; a core via layer 191, which penetrates the core insulation layer 171 and connects the first core wiring layer 181 and the second core wiring layer 182; a plurality of first stacked insulation layers 172, 173 and 174, which are arranged on the upper surface of the core insulation layer 171; a plurality of first stacked wiring layers 183 and 184, which are respectively arranged on the plurality of first stacked insulation layers 172, 173 and 174 or in the plurality of first stacked insulation layers 172, 173 and 174; a plurality of first stacked via layers 192 and 193 , respectively penetrating at least one of the multiple first stacked insulation layers 172, 173 and 174 and respectively connected to at least one of the multiple first stacked wiring layers 183 and 184; multiple second stacked insulation layers 175 and 176, arranged on the lower surface of the core insulation layer 171; multiple second stacked wiring layers 185 and 186, respectively arranged on the multiple second stacked insulation layers 175 and 176 or in the multiple second stacked insulation layers 175 and 176; and multiple second stacked via layers 194 and 195, respectively penetrating at least one of the multiple second stacked insulation layers 175 and 176 and respectively connected to at least one of the multiple second stacked wiring layers 185 and 186.

[0069] The core insulating layer 171 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated into a core material such as glass fiber (e.g., glass fabric with glass cloth as an example) together with an inorganic filler, for example, an insulating material such as a copper clad laminate (CCL), etc. However, the present disclosure is not limited thereto. The core insulating layer 171 may include an inorganic insulating material. The inorganic insulating material may include a glass substrate, a silicon substrate, and / or a ceramic substrate. For example, the glass substrate may include glass, and the glass may include, for example, pure silica (approximately 100% SiO 2), soda-lime glass, borosilicate glass, aluminosilicate glass, and the like. However, the present disclosure is not limited thereto, and optional glass materials such as fluorine glass, phosphate glass, chalcogenide glass, and the like may also be used as materials for the glass layer. In addition, other additives may be further included to form glass having specific physical properties. These additives include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and at least one of carbonates and oxides of these elements, for example, calcium carbonate (e.g., lime), but the present disclosure is not limited thereto, and the additives may also include sodium carbonate (e.g., soda). On the other hand, the glass may be distinguished from glass fibers included in an organic insulating material (e.g., glass fabric exemplified by glass cloth). In addition, the silicon substrate may include silicon (Si), and if necessary, may include an oxide layer formed on the silicon (Si), and in addition, may include a nitride layer formed on the oxide layer. On the other hand, the oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but are not limited thereto. In addition, the ceramic substrate may include a ceramic, and the ceramic may include, for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), etc., but the present disclosure is not limited thereto. If necessary, the core insulation layer 171 may include a plurality of layers. The core insulation layer 171 may be thicker than each of the first buildup insulation layers 172, 173, and 174 and the second buildup insulation layers 175 and 176, but is not limited thereto.

[0070] Each of the plurality of first stacked insulating layers 172, 173, and 174 and the plurality of second stacked insulating layers 175 and 176 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated with a core material such as glass fiber and an inorganic filler, for example, an insulating material such as Ajinomoto stacked film (ABF), a prepreg, and resin coated copper (RCC), but is not limited thereto. The number of layers of each of the plurality of first stacked insulating layers 172, 173, and 174 and the plurality of second stacked insulating layers 175 and 176 is not particularly limited.

[0071] The first core wiring layer 181 and the second core wiring layer 182 may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and may specifically include copper (Cu). Each of the first core wiring layer 181 and the second core wiring layer 182 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but is not limited thereto. As an electroless plating layer, a sputtering layer may be formed instead of a chemical copper plating layer, or both of them may be used. If necessary, a copper foil may be further included. The first core wiring layer 181 and the second core wiring layer 182 may perform various functions according to the design of each layer, and may include, for example, a grounding pattern, a power pattern, a signal pattern, etc. These patterns may include a line pattern, a plane pattern, and / or a pad pattern, respectively.

[0072] Each of the plurality of first buildup wiring layers 183 and 184 and the plurality of second buildup wiring layers 185 and 186 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and may specifically include copper (Cu). The plurality of first buildup wiring layers 183 and 184 and the plurality of second buildup wiring layers 185 and 186 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), respectively, but are not limited thereto. As the electroless plating layer, a sputtering layer may be formed instead of the chemical copper plating layer, and both may also be used. If necessary, a copper foil may be further included. The plurality of first buildup wiring layers 183 and 184 and the plurality of second buildup wiring layers 185 and 186 may perform various functions according to the design of each layer, and may include, for example, a ground pattern, a power pattern, a signal pattern, etc. These patterns may include a line pattern, a plane pattern, and / or a pad pattern, respectively.

[0073] The core via layer 191 may include a through-hole. The through-hole may include a metal layer formed on the wall of the through-hole and a plug filling the inner space of the metal layer. The metal layer may contain a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and may specifically contain copper (Cu). The plug may contain ink as an insulating material. The metal layer may include, but is not limited to, an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). As an electroless plating layer, a sputtering layer may be formed to replace the chemical copper plating layer, and both may be used as needed. The core via layer 191 may perform various functions according to the design, and for example, may include a ground via, a power via, a signal via, etc. The core via layer 191 may have a generally cylindrical shape, but is not limited thereto, and may have a generally hourglass shape.

[0074] Each of the plurality of first stacked via layers 192 and 193 and the plurality of second stacked via layers 194 and 195 may include a micro via. The micro via may be a filled via that fills the via hole or a conformal via arranged along the wall of the via hole. The micro via may be arranged in a stacked type and / or a staggered type. Each of the plurality of first stacked via layers 192 and 193 and the plurality of second stacked via layers 194 and 195 may include a metal, and the metal may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or an alloy thereof, and may specifically include copper (Cu). Each of the plurality of first stacked via layers 192 and 193 and the plurality of second stacked via layers 194 and 195 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but is not limited thereto. As an electroless plating layer, a sputtering layer may be formed instead of a chemical copper plating layer, and both may also be used. The plurality of first stacked via layers 192 and 193 and the plurality of second stacked via layers 194 and 195 may perform various functions according to the design of the corresponding layers, and, for example, may include ground vias, power vias, signal vias, etc. The vias in the plurality of first stacked via layers 192 and 193 and the vias in the plurality of second stacked via layers 194 and 195 may have shapes that taper in opposite directions.

[0075] The second substrate portion 142 may be a coreless multilayer buildup substrate including a microcircuit. For example, the second substrate portion 142 may include: a plurality of third buildup insulating layers 111, 112, 113, and 114; a plurality of third buildup wiring layers 121, 122, 123, 124, and 125, which are respectively disposed on or within the plurality of third buildup insulating layers 111, 112, 113, and 114; and a plurality of third buildup via layers 131, 132, 133, 134, and 135, which respectively penetrate at least one of the plurality of third buildup insulating layers 111, 112, 113, and 114 and are respectively connected to at least one of the plurality of third buildup wiring layers 121, 122, 123, 124, and 125. Furthermore, in the case where the plurality of first buildup via layers 192 and 193 do not penetrate the first buildup insulating layer 174 , the third buildup via layer 135 may penetrate the first buildup insulating layer 174 to connect the third buildup wiring layer 125 to the first buildup wiring layer 184 .

[0076] Each of the plurality of third buildup insulating layers 111, 112, 113, and 114 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material in which these insulating resins are mixed with an inorganic filler (such as silica), or a resin impregnated into a core material (such as glass fiber) together with an inorganic filler, for example, an insulating material such as Ajinomoto buildup film (ABF), a prepreg, and resin coated copper (RCC), but is not limited thereto. The number of layers of the plurality of third buildup insulating layers 111, 112, 113, and 114 is not particularly limited. On the other hand, the third buildup insulating layer 111 disposed on the outermost layer of the plurality of third buildup insulating layers 111, 112, 113, and 114 may be the insulating layer 111 in the above-mentioned printed circuit boards 100A, 100B, and 100C.

[0077] The plurality of third buildup wiring layers 121, 122, 123, 124, and 125 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and specifically, may include copper (Cu). The plurality of third buildup wiring layers 121, 122, 123, 124, and 125 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but are not limited thereto. As the electroless plating layer, a sputtering layer may be formed instead of the chemical copper plating layer, and both may also be used. If necessary, a copper foil may be further included. The plurality of third buildup wiring layers 121, 122, 123, 124, and 125 may perform various functions according to the design of the corresponding layers, and may include, for example, a ground pattern, a power pattern, a signal pattern, and the like. These patterns may include a line pattern, a plane pattern, and / or a pad pattern, respectively. On the other hand, the third buildup wiring layer 121 provided on the outermost layer among the plurality of third buildup wiring layers 121 , 122 , 123 , 124 , and 125 may be the wiring layer 121 in the above-described printed circuit boards 100A, 100B, and 100C.

[0078] Each of the plurality of third stacked via layers 131, 132, 133, 134, and 135 may include a micro via. The micro via may be a filled via that fills the via hole, or may be a conformal via arranged along the wall of the via hole. The micro via may be arranged in a stacked type and / or a staggered type. The plurality of third stacked via layers 131, 132, 133, 134, and 135 may include a metal, and the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and specifically, may include copper (Cu). The plurality of third stacked via layers 131, 132, 133, 134, and 135 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but is not limited thereto. As an electroless plating layer, a sputtering layer may be formed instead of a chemical copper plating layer, and both may also be used. The plurality of third stacked via layers 131, 132, 133, 134, and 135 may perform various functions according to the design of each layer, and, for example, may include ground vias, power vias, signal vias, etc. The vias in the plurality of third stacked via layers 131, 132, 133, 134, and 135 may have a shape tapered in the same direction. The vias in the plurality of third stacked via layers 131, 132, 133, 134, and 135 may have a shape tapered in the same direction as the vias in the plurality of first stacked via layers 192 and 193, and may have a shape tapered in the opposite direction to the vias in the plurality of second stacked via layers 194 and 195.

[0079] The first solder resist layer 151 and the second solder resist layer 152 may each include a solder resist. The solder resist may be a photosensitive material or a liquid solder resist. For example, the solder resist may be a solder resist of product name AUS703 or SR7300, but is not limited thereto. The first solder resist layer 151 may have a plurality of openings, and each opening may expose at least a portion of the third buildup wiring layer 121 of the uppermost layer. Each opening is a solder mask defined (SMD) type and / or a non-solder mask defined (NSMD) type, and may expose at least a portion of the third buildup wiring layer 121 of the uppermost layer, and specifically, may be an SMD type and expose at least a portion of the third buildup wiring layer 121 of the uppermost layer. The second solder resist layer 152 may also have a plurality of openings, and each opening may expose at least a portion of the second buildup wiring layer 186 of the lowermost layer. Each opening may be of SMD type and / or NSMD type and exposes at least a portion of the lowermost second build-up wiring layer 186, and specifically, may be of SMD type and expose at least a portion of the lowermost second build-up wiring layer 186. On the other hand, the first solder resist layer 151 of the first solder resist layer 151 and the second solder resist layer 152 may be the solder resist layer 151 in the above-mentioned printed circuit boards 100A, 100B, and 100C.

[0080] A plurality of electrical connection metals 160 are configured to connect the printed circuit board 100D to a main board, other boards, etc. of an electronic device. A plurality of electrical connection metals 160 may be connected to at least a portion of the second buildup wiring layer 186 of the lowest layer, respectively. If necessary, a plurality of electrical connection metals 160 may be provided by a plurality of under-bump metals, respectively. A plurality of electrical connection metals 160 may be formed using conductive materials such as solder, etc., but this is only an example, and the material is not particularly limited thereto. A plurality of electrical connection metals 160 may each be a pad, a solder ball, a pin, etc. A plurality of electrical connection metals 160 may each be formed into a multilayer structure or a single-layer structure. When formed into a multilayer structure, a plurality of electrical connection metals 160 may include a copper column and a solder formed on the copper column, and when formed into a single layer, a plurality of electrical connection metals 160 may include a tin-silver solder or copper, but is not limited thereto.

[0081] Apart from this, the other contents are roughly the same as the above contents, so redundant descriptions related to them are omitted. On the other hand, it goes without saying that Figures 3 to 9 The above-described contents can also be applied to a printed circuit board 100D according to another example.

[0082] FIG. 11A to FIG. 11G 1 is a process diagram schematically showing an example of manufacturing a printed circuit board. In each figure, the left figure shows a schematic cross-sectional view of each stage, and the right figure shows a schematic top view of each stage.

[0083] Reference Fig.11A , a wiring layer 121 may be formed on the insulating layer 111. The wiring layer 121 may include a plurality of metal pads 121-1 and at least one metal pattern 121-2. In the drawings, for ease of explanation, only a portion of the wiring layer 121 is shown, but similar to the above structure, the wiring layer 121 may include more diverse patterns. The wiring layer 121 may be formed by a plating process using an additive process (AP), a semi-additive process (SAP), a modified SAP (MSAP), a via sealing (TT) process, or the like.

[0084] Reference Fig. 11B , a solder resist layer 151 may be formed on the insulating layer 111 to cover at least a portion of the wiring layer 121. The solder resist layer 151 may be formed through a coating process or a lamination process according to a material.

[0085] Reference Fig. 11CIn the solder resist layer 151, a plurality of first openings h1 exposing at least a portion of each of the plurality of metal pads 121-1 and one or more second openings h2 exposing at least a portion of at least one metal pattern 121-2 may be formed. In the drawings, for ease of explanation, only the first opening h1 and the second opening h2 are shown, but if necessary, a third opening and a fourth opening (not shown) may also be formed. Depending on the material of the solder resist layer 151, each opening may be formed by a photolithography process or a laser processing process. The second opening h2 may be formed to have two openings h2-1 and h2-2 connected to each other. For example, as shown in FIG. Figure 4 As described in the above, at least a portion of the two openings h2-1 and h2-2 may be formed to overlap and connect with each other on a plane. For example, the two openings h2-1 and h2-2 may be formed to have a snowman shape on a plane. Figure 5 As described above, the two openings h2-1 and h2-2 may be spaced apart from each other on a plane and connected to each other by a straight groove g, and, for example, may be formed to have a dumbbell shape on a plane. A plurality of first openings h1 and one or more second openings h2 may be formed in the mounting area A of the semiconductor chip of the above-mentioned solder resist layer 151. On the other hand, each of the maximum radii r2-1 and r2-2 of the two openings h2-1 and h2-2 on a plane of each of the one or more second openings h2 may be greater than the maximum radius r1 of each of the multiple first openings h1 on a plane. In this case, the maximum radius may be the distance from the center of the opening to the farthest edge, regardless of the shape of the opening. For example, the area of ​​each of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane may be formed to be greater than the area of ​​each of the multiple first openings h1 on a plane.

[0086] Reference Fig.11D , a surface treatment layer P may be formed in the plurality of first openings h1 and the one or more second openings h2. For example, a first surface treatment layer P1 covering the exposed surface of each of the plurality of metal pads 121-1 in the plurality of first openings h1 and a second surface treatment layer P2 covering the exposed surface of at least one metal pattern 121-2 in the one or more second openings h2 may be formed. In the accompanying drawings, for ease of explanation, only the first surface treatment layer P1 and the second surface treatment layer P2 are shown, but if necessary, a third surface treatment layer (not shown) and a fourth surface treatment layer (not shown) may also be formed. The surface treatment layer P may be formed using electroless nickel-palladium immersion gold (ENEPIG), but the present disclosure is not limited thereto. For example, the surface treatment layer P may be formed by one or more of electroless nickel plating, electroless palladium plating, and alternative gold plating, but is not limited thereto.

[0087] Reference Fig.11E, at least one first solder ball q1 connected to the first surface treatment layer P1 may be formed on each of the plurality of first openings h1. Next, each first solder ball q1 may be inspected and repaired. For example, it may be determined whether there is a defect in the first solder ball q1, the first solder ball q1 with the defect may be removed, and the first solder ball q1 may be formed again in the area where the first solder ball q1 is removed. If necessary, a third solder ball (not shown) connected to the third surface treatment layer (not shown) and a fourth solder ball (not shown) connected to the fourth surface treatment layer (not shown) may be formed on the third opening (not shown) and the fourth opening (not shown), respectively, and may also be inspected and repaired separately. The formation of the solder ball may use a solder ball mounting technique. Before mounting the solder ball, flux may be applied as needed.

[0088] Reference Fig.11F , at least two second solder balls q2 connected to the second surface treatment layer P2 may be formed on each of the one or more second openings h2. For example, when the area of ​​each of the openings h2-1 and h2-2 of each of the one or more second openings h2 is larger than the area of ​​each of the multiple first openings h1 on a plane, multiple first solder balls q1 may be first formed on the multiple first openings h1, and after inspecting and repairing the multiple first solder balls q1 formed earlier, at least two second solder balls q2 may be formed on each of the one or more second openings h2. If necessary, then at least two second solder balls q2 may be inspected and repaired. The size of each second solder ball q2 may be larger than the size of each first solder ball q1. The formation of the solder balls may use solder ball mounting technology. Before mounting the solder balls, flux may be applied as needed.

[0089] Reference Fig.11G , each of the first solder balls q1 and each of the second solder balls q2 may be reflowed. As a result, a solder layer Q including a plurality of first solder bumps Q1 and one or more second solder bumps Q2 may be formed. The one or more second solder bumps Q2 may be in a form in which at least two second solder balls q2 are connected to each other. If necessary, each of the third solder ball and the fourth solder ball may be reflowed, and as a result, a plurality of third solder bumps (not shown) and a plurality of fourth solder bumps (not shown) may be formed. After reflowing, flux removal may be performed as needed.

[0090] The printed circuit boards 100A and 100B can be formed by a series of processes, and the printed circuit boards 100C and 100D can be formed by further applying semiconductor chips, passive component mounting processes and / or multi-layer substrate forming processes. Other contents are substantially the same as those described above, and thus redundant descriptions thereof are omitted. On the other hand, it goes without saying that by Figures 3 to 10 The above-described contents can also be applied to the method of manufacturing a printed circuit board according to the example.

[0091] FIG. 12A to FIG. 12F 1 is a process diagram schematically showing another example of manufacturing a printed circuit board. In each figure, the left figure shows a schematic cross-sectional view of each stage, and the right figure shows a schematic top view of each stage.

[0092] Reference Fig. 12A , a wiring layer 121 may be formed on the insulating layer 111. The wiring layer 121 may include a plurality of metal pads 121-1 and at least one metal pattern 121-2. In the drawings, for ease of explanation, only a portion of the wiring layer 121 is shown, but similar to the above structure, the wiring layer 121 may include more diverse patterns. The wiring layer 121 may be formed by a plating process using an additive process (AP), a semi-additive process (SAP), a modified SAP (MSAP), a via sealing (TT) process, or the like.

[0093] Reference Fig. 12B , a solder resist layer 151 may be formed on the insulating layer 111 to cover at least a portion of the wiring layer 121. The solder resist layer 151 may be formed through a coating process or a lamination process according to a material.

[0094] Reference Fig. 12C In the solder resist layer 151, a plurality of first openings h1 exposing at least a portion of each of the plurality of metal pads 121-1 and one or more second openings h2 respectively exposing at least a portion of at least one metal pattern 121-2 may be formed. In the accompanying drawings, for ease of explanation, only the first opening h1 and the second opening h2 are shown, but if necessary, a third opening (not shown) and a fourth opening (not shown) may also be formed. Depending on the material of the solder resist layer 151, each opening may be formed by a photolithography process, a laser processing process, or the like. The one or more second openings h2 may be formed to have two openings h2-1 and h2-2 respectively connected to each other. For example, as shown in FIG. Figure 6 As described in the examples above, at least a portion of the two openings h2-1 and h2-2 may be formed to overlap and connect with each other in a plane, and may be formed to have a snowman shape in a plane, for example. Figure 7As described above, the two openings h2-1 and h2-2 may be spaced apart from each other on a plane and connected by a straight groove g, and, for example, may be formed to have a dumbbell shape on a plane. A plurality of first openings h1 and one or more second openings h2 may be formed in the mounting area A of the semiconductor chip of the solder resist layer 151 described above. On the other hand, each of the maximum radii r2-1 and r2-2 of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane may be greater than the maximum radius r1 of each of the multiple first openings h1 on a plane. In this case, the maximum radius may be the distance from the center of the opening to the farthest edge, regardless of the shape of the opening. For example, the area of ​​each of the two openings h2-1 and h2-2 of each of the one or more second openings h2 on a plane may be formed to be greater than the area of ​​each of the multiple first openings h1 on a plane.

[0095] Reference Fig.12D , a surface treatment layer P may be formed in the plurality of first openings h1 and the one or more second openings h2. For example, a first surface treatment layer P1 covering the exposed surface of each of the plurality of metal pads 121-1 in the plurality of first openings h1 and a second surface treatment layer P2 covering the exposed surface of at least one metal pattern 121-2 in the one or more second openings h2 may be formed. In the accompanying drawings, for ease of explanation, only the first surface treatment layer P1 and the second surface treatment layer P2 are shown, but if necessary, a third surface treatment layer (not shown) and a fourth surface treatment layer (not shown) may also be formed. The surface treatment layer P may be formed using electroless nickel-palladium immersion gold (ENEPIG), but is not limited thereto. For example, the surface treatment layer P may be formed by one or more of electroless nickel plating, electroless palladium plating, and alternative gold plating, but is not limited thereto.

[0096] Reference Fig.12E, a first solder ball q1 connected to the first surface treatment layer P1 may be formed on each of the plurality of first openings h1. In addition, at least two second solder balls q2 connected to the second surface treatment layer P2 may be formed on each of the one or more second openings h2. Next, the first solder ball q1 may be inspected and repaired. If necessary, each second solder ball q2 may also be inspected and repaired. For example, when the area of ​​each of the openings h2-1 and h2-2 of each of the one or more second openings h2 is substantially equal to the area of ​​each of the plurality of first openings h1 or is smaller than the area of ​​each of the plurality of first openings h1 on a plane, the solder ball forming process may be performed simultaneously, and if necessary, the inspection process and the repair process may also be performed simultaneously. If necessary, a third solder ball (not shown) connected to the third surface treatment layer (not shown) and a fourth solder ball (not shown) connected to the fourth surface treatment layer (not shown) may be formed on the third opening (not shown) and the fourth opening (not shown), respectively, and the third solder ball (not shown) and the fourth solder ball (not shown) may also be inspected and repaired separately. The size of each second solder ball q2 may be substantially the same as or slightly smaller than the size of each first solder ball q1. The solder balls may be formed using a solder ball mounting technique. Before mounting the solder balls, flux may be applied as needed.

[0097] Reference Fig.12F , each of the first solder balls q1 and each of the second solder balls q2 may be reflowed. As a result, a solder layer Q including a plurality of first solder bumps Q1 and one or more second solder bumps Q2 may be formed. The one or more second solder bumps Q2 may be in a form in which at least two second solder balls q2 are connected to each other. If necessary, each of the third solder ball and the fourth solder ball may be reflowed, and as a result, a plurality of third solder bumps (not shown) and a plurality of fourth solder bumps (not shown) may also be formed. After reflowing, flux removal may be performed as needed.

[0098] The above-mentioned printed circuit boards 100A and 100B can be formed through a series of processes, and if a semiconductor chip, a passive component mounting process and / or a multilayer board forming process are further applied in this case, the above-mentioned printed circuit boards 100C and 100D can be formed. Except for this, the other contents are substantially the same as the above-mentioned contents, and thus redundant descriptions thereof are omitted. On the other hand, it goes without saying that by Figures 3 to 10 The above-described contents can also be applied to a method of manufacturing a printed circuit board according to another example.

[0099] As described above, according to the embodiment, a printed circuit board and a method of manufacturing the same can be provided which can enhance adhesion between a semiconductor chip and a package substrate when mounting the semiconductor chip.

[0100] A printed circuit board and a method of manufacturing the same can be provided which can prevent cracks from being generated in bumps formed of micro balls or the like at edge portions of semiconductor chips when semiconductor chips are mounted.

[0101] In the present disclosure, the expression "covering" may include a case of covering a part and a case of covering the whole, and may also include a case of direct covering and a case of indirect covering. In addition, the expression "filling" may include not only full filling, but also partial filling, and may also include approximately filling. For example, this may include a case where there are some gaps or holes. In addition, the expression "surrounding" may include not only a case of full surrounding, but also a case of partial surrounding and approximately surrounding. In addition, "exposing" includes not only full exposure, but also partial exposure, and exposing may mean exposing the corresponding component from another component (the corresponding component is embedded in the other component). For example, another structure may be set on the exposed structure, in which case, the meaning of exposure may be the same. In addition, in practice, judgment may include process errors, position deviations, and measurement errors that occur during the manufacturing process. For example, "approximately the same" may include approximately the same situation.

[0102] In the present disclosure, the meaning of "cross section" may refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is observed from a side perspective. In addition, the meaning of "plane" may refer to the shape when an object is cut horizontally, or may refer to the plane shape when the object is observed from a top or bottom perspective.

[0103] In the present disclosure, for the sake of convenience, "lower", "lower part", "lower surface" and the like are used to indicate the downward direction based on the cross section of the drawings, and "upper", "upper part", "upper surface" and the like are used to indicate the opposite direction. However, this is for the convenience of describing the defined direction, and of course, the scope of the claims is not particularly limited by the description of the direction, and the concepts of "upper" and "lower" may be changed at any time.

[0104] In the present disclosure, the meaning of "connection" is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of "electrical connection" is a concept including both physical connection situations and non-physical connection situations. In addition, expressions such as "first", "second", etc. are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the claims.

[0105] In the present disclosure, the meaning of "penetration" may include not only complete penetration between the upper and lower surfaces of an object based on the thickness direction or the stacking direction, but also penetration of a portion of the object from the upper surface or from the lower surface in the form of a blind cavity.

[0106] In the present disclosure, thickness, width, length, depth, line width, spacing, pitch, spacing distance, surface roughness, etc. can be measured based on a cross section obtained by polishing or cutting a printed circuit board using a scanning microscope or an optical microscope. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the desired cut section. For example, the width of the upper end and / or lower end of the via can be measured on a cross section cut along the central axis of the via. In this case, if the value is not constant, the value can be determined as the average of the values ​​measured at five random points.

[0107] The expression "(one) example" used in the present disclosure does not mean the same embodiment, but is provided to emphasize and describe different unique features. However, the examples presented above do not exclude implementation in combination with features of other examples. For example, even if a matter described in a specific example is not described in another example, it can be understood as a description related to another example unless there is a description opposite or contradictory to the matter in another example.

[0108] The terms used in the present disclosure are only for describing examples and are not intended to limit the present disclosure. In this case, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0109] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Insulation layer; a wiring layer disposed on the insulating layer and comprising a plurality of metal pads and at least one metal pattern; as well as a solder resist layer, disposed on an upper portion of the insulating layer, covering at least a portion of the wiring layer, and having a plurality of first openings for respectively exposing at least a portion of each of the plurality of metal pads and one or more second openings for respectively exposing at least a portion of the at least one metal pattern, The second opening has at least two recesses in a plane that are recessed toward the inside of the second opening, and The plurality of first opening portions and the one or more second opening portions are provided in a mounting region of a semiconductor chip of the solder resist layer.

2. The printed circuit board according to claim 1, wherein: The second opening portion has a shape in which at least two openings partially overlap and connect with each other in the plane.

3. The printed circuit board according to claim 2, wherein: The second opening portion has a substantially snowman shape in the plane.

4. The printed circuit board according to claim 1, wherein: The second opening portion has a shape on the plane in which at least two openings are spaced apart from each other and connected by a straight-line groove.

5. The printed circuit board according to claim 4, wherein: The length of the slot is less than the maximum radius of each of the at least two openings.

6. The printed circuit board according to claim 4, wherein: The second opening portion has a substantially dumbbell shape in the plane.

7. The printed circuit board according to claim 1, wherein: Each of the plurality of first opening portions has one opening.

8. The printed circuit board according to claim 1, wherein: The solder resist layer further has a plurality of third openings respectively exposing at least another portion of the at least one metal pattern. Wherein, each of the plurality of third opening portions has one opening.

9. The printed circuit board according to claim 8, wherein: The mounting region of the semiconductor chip includes a quadrilateral region created by substantially connecting outer edges of outermost openings among openings including the plurality of first opening portions, the one or more second opening portions, and the plurality of third opening portions with straight lines.

10. The printed circuit board according to claim 1, wherein The plurality of first openings are provided at a central portion of the mounting region of the semiconductor chip, and The one or more second opening portions are provided in a peripheral portion surrounding the central portion of the mounting region of the semiconductor chip.

11. The printed circuit board according to claim 1, wherein: At least one of the plurality of metal pads is spaced apart from the at least one metal pattern, and an entire side surface of at least one of the plurality of metal pads is continuously surrounded by the at least one metal pattern.

12. The printed circuit board according to claim 1, wherein: The one or more second openings are a plurality of second openings, The at least one metal pattern includes a metal pattern for grounding, and At least two of the plurality of second openings respectively expose different portions of the metal pattern for grounding.

13. The printed circuit board according to claim 1, wherein: The plurality of first openings are of a solder mask definition type and respectively expose a portion of each of the plurality of metal pads, and The one or more second opening portions are of a solder mask definition type and respectively expose at least a portion of the at least one metal pattern.

14. The printed circuit board according to claim 1, further comprising: a first surface treatment layer disposed within the plurality of first openings and covering at least a portion of an exposed surface of each of the plurality of metal pads; as well as A second surface treatment layer is disposed in the one or more second openings and covers at least a portion of an exposed surface of the at least one metal pattern.

15. The printed circuit board according to claim 14, wherein: The wiring layer includes a copper layer, The first surface treatment layer includes at least one of a nickel layer, a palladium layer and a gold layer, and The second surface treatment layer includes at least one of a nickel layer, a palladium layer, and a gold layer.

16. The printed circuit board according to claim 14, further comprising: a plurality of first solder bumps, respectively disposed on the plurality of first openings and respectively connected to the plurality of metal pads through the first surface treatment layer; as well as One or more second solder bumps are respectively disposed on the one or more second openings and are respectively connected to the at least one metal pattern through the second surface finishing layer. 17 . The printed circuit board of claim 16 , further comprising a semiconductor chip disposed on the mounting area of ​​the semiconductor chip and connected to the plurality of first solder bumps and the one or more second solder bumps.

18. The printed circuit board according to claim 1, wherein The printed circuit board includes a plurality of buildup insulating layers, a plurality of buildup wiring layers respectively disposed on or in the plurality of buildup insulating layers, and a plurality of buildup via layers respectively penetrating at least one of the plurality of buildup insulating layers and respectively connected to at least one of the plurality of buildup wiring layers. The insulating layer is an outermost buildup insulating layer among the plurality of buildup insulating layers, and The wiring layer is an outermost buildup wiring layer among the plurality of buildup wiring layers.

19. The printed circuit board according to claim 1, wherein: The second opening portion has a shape on the plane in which a first opening having a first center point and a second opening having a second center point are connected to each other, and In at least one of the one or more second openings, an imaginary line connecting the first center point and the second center point is substantially parallel or substantially perpendicular to an imaginary edge of the mounting region of the semiconductor chip.

20. The printed circuit board according to claim 1, wherein The second opening portion has a shape in a plane in which a first opening having a first center point and a second opening having a second center point are connected to each other, and In at least one of the one or more second openings, a first imaginary line connecting the first center point and the second center point is approximately parallel or approximately perpendicular to a second imaginary line connecting the center point of the mounting area of ​​the semiconductor chip and the midpoint of the first imaginary line.

21. A method for manufacturing a printed circuit board, comprising: forming a wiring layer including a plurality of metal pads and at least one metal pattern on an upper portion of the insulating layer; forming a solder resist layer covering at least a portion of the wiring layer on the upper portion of the insulating layer; as well as forming a plurality of first openings respectively exposing at least a portion of each of the plurality of metal pads, and one or more second openings respectively exposing at least a portion of the at least one metal pattern in the solder resist layer, Wherein, in the step of forming the plurality of first openings and the one or more second openings: The second opening is formed to have at least two recesses on a plane that are recessed toward the inside of the second opening, and The plurality of first opening portions and the one or more second opening portions are formed in a mounting region of the semiconductor chip of the solder resist layer.

22. The method according to claim 21, wherein: In the step of forming the plurality of first openings and the one or more second openings, the second openings are formed to have at least two openings at least partially overlapping and connected to each other on the plane.

23. The method according to claim 21, wherein: In the step of forming the plurality of first opening portions and the one or more second opening portions, the second opening portions are formed such that at least two openings are spaced apart from each other on the plane and are connected by a straight-line-shaped groove.

24. The method according to claim 21, further comprising forming a surface treatment layer in the plurality of first openings and the one or more second openings, in, In the step of forming the surface treatment layer, forming a first surface treatment layer within the plurality of first openings to cover at least a portion of an exposed surface of each of the plurality of metal pads, and A second surface treatment layer is formed in the one or more second openings to cover at least a portion of an exposed surface of the at least one metal pattern.

25. The method according to claim 24, wherein: In the step of forming the surface treatment layer, The first surface treatment layer is formed by one or more of electroless nickel plating, electroless palladium plating and displacement gold plating, and The second surface treatment layer is formed by one or more of electroless nickel plating, electroless palladium plating and displacement gold plating.

26. The method according to claim 24, further comprising forming a solder layer connected to the surface treatment layer on the plurality of first openings and the one or more second openings, in, In the step of forming the solder layer: forming a plurality of first solder bumps on the plurality of first openings, respectively, the plurality of first solder bumps being connected to the plurality of metal pads through the first surface treatment layer, and One or more second solder bumps are respectively formed on the one or more second openings, and the one or more second solder bumps are respectively connected to the at least one metal pattern through the second surface treatment layer.

27. The method according to claim 26, wherein: In the step of forming the solder layer, The plurality of first solder bumps are formed by forming at least one first solder ball on each of the plurality of first openings and then reflowing, and The one or more second solder bumps are formed by forming at least two second solder balls on each of the one or more second opening portions and then reflowing.

28. The method according to claim 27, wherein: Forming the solder layer includes: forming the at least one first solder ball on each of the plurality of first openings, inspecting and repairing the first solder balls, respectively, forming the at least two second solder balls on each of the one or more second openings, and reflowing the first solder balls and the second solder balls, respectively, and In the step of forming the plurality of first openings and the one or more second openings: The second opening portion is formed to have at least two openings connected to each other on the plane, and An area of ​​each of the at least two openings on the plane is larger than an area of ​​each of the plurality of first opening portions on the plane.

29. The method according to claim 27, wherein: Forming the solder layer includes: forming the at least one first solder ball and the at least two second solder balls on each of the plurality of first openings and each of the one or more second openings, respectively, inspecting and repairing the first solder ball and the second solder ball, respectively, and reflowing each of the first solder ball and the second solder ball, and In the step of forming the plurality of first openings and the one or more second openings: The second opening portion is formed to have at least two openings connected to each other on the plane, and Each of the at least two openings is formed on the plane with an area substantially the same as an area of ​​each of the plurality of first opening portions, or is formed on the plane with an area smaller than an area of ​​each of the plurality of first opening portions.

30. A printed circuit board comprising: Insulation layer; a wiring layer disposed on the insulating layer and comprising a plurality of metal pads and a metal pattern; a solder resist layer, disposed on an upper portion of the insulating layer, covering at least a portion of the wiring layer, and having a plurality of first openings respectively exposing at least a portion of each of the plurality of metal pads and two openings respectively exposing at least a portion of the metal pattern, wherein the two openings are connected to each other and have at least two recesses in a plane that are recessed toward the inside of the two openings; a plurality of first solder bumps, respectively disposed on the plurality of first openings and respectively connected to the plurality of metal pads; and A second solder bump is disposed on the two openings and connected to the metal pattern.

31. The printed circuit board according to claim 30, wherein: The two openings partially overlap each other in the plane.

32. The printed circuit board according to claim 31, wherein The two openings have a generally snowman shape in the plane.

33. The printed circuit board according to claim 30, wherein: The two openings are connected by a slot having a width smaller than a diameter of each of the two openings.

34. The printed circuit board according to claim 33, wherein: The two openings have a generally dumbbell shape in the plane.

35. The printed circuit board according to claim 30, wherein: At least one of the plurality of metal pads is spaced apart from the metal pattern and an entire side surface of the at least one of the plurality of metal pads is surrounded by the metal pattern on the plane.

36. The printed circuit board of claim 30, further comprising: a first surface treatment layer disposed within the plurality of first openings and covering at least a portion of an exposed surface of each of the plurality of metal pads; as well as a second surface treatment layer disposed in the two openings and covering at least a portion of the exposed surface of the metal pattern, wherein the plurality of first solder bumps are respectively connected to the plurality of metal pads through the first surface treatment layer, and The second solder bump is connected to the metal pattern through the second surface finish layer.

37. A printed circuit board comprising: Insulation layer; a wiring layer disposed on the insulating layer and including a plurality of metal pads and a ground pattern; a solder resist layer, which is disposed on an upper portion of the insulating layer, covers at least a portion of the wiring layer, and has a plurality of first openings that respectively expose at least a portion of each of the plurality of metal pads and two openings that respectively expose at least a portion of the ground pattern, wherein the two openings are connected to each other and have at least two recesses in a plane that are recessed toward the inside of the two openings, and The ground pattern is spaced apart from and surrounds at least one of the plurality of metal pads on the plane.

38. The printed circuit board according to claim 37, wherein: The two openings partially overlap each other in the plane.

39. The printed circuit board according to claim 38, wherein The two openings have a generally snowman shape in the plane.

40. The printed circuit board according to claim 37, wherein: The two openings are connected by a slot having a width smaller than a diameter of each of the two openings.

41. The printed circuit board according to claim 40, wherein The two openings have a generally dumbbell shape in the plane.

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