Memory structure and forming method thereof

Abstract

The invention discloses a memory structure and a forming method thereof, and the method comprises the steps: a plurality of cushion layer structures and active layers located on the surfaces of the cushion layer structures are formed on a substrate, the cushion layer structures are arranged in an array manner along a second direction and a first direction, and the active layers cover the tops of the cushion layer structures and the side walls of the cushion layer structures along the first direction; the active layer exposes the side wall of the cushion layer structure along the second direction, and the active layer extends along the first direction and is arranged in parallel along the second direction; an isolation structure is formed between the adjacent cushion layer structures in the second direction, a plurality of floating gates are formed on the surface of the active layer on each cushion layer structure, the top surface of the isolation structure is higher than or flush with the bottom surface of the active layer, and the floating gates are located between the adjacent isolation structures in the second direction; a plurality of control gates are formed on the surfaces of the floating gates and the surfaces of the isolation structures, and the control gates stretch across the floating gates in the second direction, extend in the second direction and are arranged in parallel in the first direction. The cushion layer structure increases the channel length of the active layer and improves the short channel effect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller, with higher circuit precision and higher circuit complexity. In the development of integrated circuits, the functional density usually increases while the geometric size decreases, which increases the difficulty and complexity of integrated circuit manufacturing.

[0003] Flash memory has been rapidly promoted as the mainstream storage medium today, and its technology has also been rapidly developed. Flash memory is divided into NOT OR (NOR) type flash memory and NOT AND (NAND) type flash memory. As a type of flash memory, NOR type flash memory has received widespread attention due to its efficient programming speed and erasing ability. At present, NOR type flash memory has been widely used in personal computers, digital equipment, mobile terminals, automotive devices and other products.

[0004] However, the current NOR-type flash memory structure still has many problems. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a forming method thereof, so as to improve the performance of the memory structure.

[0006] In order to solve the above technical problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of mutually discrete pad structures and an active layer located on the surface of the pad structure on the substrate, each of the pad structures being arranged in an array along a second direction and a first direction, the first direction being perpendicular to the second direction, the active layer covering the top of the pad structure and the side wall of the pad structure along the first direction, the active layer exposing the side wall of the pad structure along the second direction, the active layer extending along the first direction and being arranged in parallel along the second direction; forming an isolation structure between adjacent pad structures in the second direction and forming a plurality of mutually discrete floating gates on the surface of the active layer on each pad structure, the top surface of the isolation structure being higher than or flush with the surface of the active layer, and the floating gate being located between adjacent isolation structures in the second direction; forming a plurality of control gates on the surface of the floating gate and the surface of the isolation structure, each of the control gates spanning across a plurality of floating gates along the second direction, and each of the control gates extending along the second direction and being arranged in parallel along the first direction.

[0007] Optionally, the floating gate is formed before forming the isolation structure, and the floating gate, the pad structure and the active layer are formed simultaneously.

[0008] Optionally, the method for forming the pad structure, the active layer and the floating gate includes: forming a pad material layer on the surface of the substrate; forming a first mask layer on the surface of the pad material layer, the first mask layer extending along the second direction and arranged in parallel along the first direction, the first mask layer exposing a portion of the surface of the pad material layer; using the first mask layer as a mask, etching the pad material layer by a first etching process until the substrate surface is exposed, forming an initial pad layer and a plurality of first openings located between adjacent initial pad layers, each of the first openings extending along the second direction and each of the first openings arranged in parallel along the first direction, each of the first openings having a first projection in a direction parallel to the substrate surface; forming an active material layer on the initial pad layer and the substrate surface; forming a second mask layer on the surface of the active material layer, the second mask layer extending along the second direction and arranged in parallel along the first direction, the second mask layer exposing a portion of the surface of the active material layer; using the second mask layer as a mask, etching the pad material layer by a first etching process until the substrate surface is exposed. The active material layer is etched by a second etching process to form an initial active layer and a plurality of second openings located between the initial active layers, each of the second openings extending along a second direction and arranged in parallel along a first direction, each of the second openings having a second projection in a direction parallel to the substrate surface, and the second projection is located within the range of the first projection; an initial floating gate layer is formed on the surface of the initial active layer; a third mask layer is formed on the surface of the initial floating gate layer, the third mask layer extends along the first direction and is arranged in parallel along the second direction, and the third mask layer exposes a portion of the surface of the initial floating gate layer; the initial floating gate layer, the initial active layer, and the initial pad layer are etched by a third etching process using the third mask layer as a mask until the substrate surface is exposed, to form the pad layer structure, the active layer, the floating gate, and the third openings located between the pad layer structure, the active layer, and the floating gate, each of the third openings exposes the substrate surface and each of the third openings extends along the first direction.

[0009] Optionally, a cross-sectional morphology of the cushion structure along the first direction includes a trapezoid.

[0010] Optionally, before forming the initial floating gate layer and after forming the initial active layer, the method further includes: forming a first insulating layer on the surface of the initial active layer; the material of the first insulating layer includes: silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

[0011] Optionally, the method for forming the control gate includes: forming a control gate material layer on the surface of the isolation structure and the surface of the floating gate; forming a fourth mask layer on the surface of the control gate material layer, the fourth mask layer extending along the second direction and arranged in parallel along the first direction, the fourth mask layer exposing a portion of the surface of the control gate material layer; using the fourth mask layer as a mask, etching the control gate material layer and the floating gate using a fourth etching process to form a fourth opening and a fifth opening located in the control gate material layer and the floating gate, each of the fourth openings and each of the fifth openings are located between adjacent pad structures and each of the fourth openings is adjacent to each of the fifth openings along the first direction, each of the fourth openings and each of the fifth openings extends along the second direction, and each of the fourth openings and each of the fifth openings exposes the surface of the first insulating layer.

[0012] Optionally, a size of the fourth opening in the first direction is larger than a size of the fifth opening in the first direction.

[0013] Optionally, the method for forming the isolation structure includes: forming an initial isolation structure filling the third openings in each of the third openings; and etching back the initial isolation structure until the top surface of the initial isolation structure is flush with the bottom surface of the active layer to form the isolation structure.

[0014] Optionally, after forming the control gate, the method further includes: forming a fifth mask layer on the surface of the control gate and in the fifth opening, the fifth mask layer extending along the second direction and arranged in parallel along the first direction, and the fifth mask layer exposing the fourth opening; performing a drain light doping treatment on the surface of the active layer at the bottom of the fourth opening to form a drain light doping region; forming a sixth mask layer on the surface of the control gate and in the fourth opening, the sixth mask layer extending along the second direction and arranged in parallel along the first direction, and the sixth mask layer exposing the fifth opening; using the sixth mask layer as a mask, etching the first dielectric layer at the bottom of the fifth opening and the isolation structure at the bottom of the fifth opening by a fifth etching process; after the fifth etching process, performing a source heavy doping treatment on the surface of the substrate and the surface of the active layer at the bottom of the fifth opening Processing to form a source region, connecting adjacent source regions parallel to the first direction to form a common source line parallel to the second direction, the drain lightly doped region and the common source line are adjacent along the first direction and a pad structure is provided between the adjacent drain lightly doped regions and the common source line; forming a second dielectric layer between adjacent control gates and on the surface of the control gates; forming a plurality of sixth openings in the second dielectric layer, each of the sixth openings exposing the surface of the active layer, each of the sixth openings being located in the drain lightly doped region in the first direction and the sixth openings being located between adjacent pad structures in the first direction; heavily doping the drain on the surface of the active layer at the bottom of each of the sixth openings; forming a conductive plug in each of the sixth openings, the conductive plug being connected to the drain lightly doped region.

[0015] Optionally, the doping method of the drain light doping includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 The doping method of the heavily doped source includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 To 5E15atoms / cm 2 between.

[0016] Optionally, before forming the control gate material layer and after forming the isolation structure, the method further includes: forming a first dielectric layer on the surface of the substrate on the isolation structure.

[0017] Correspondingly, the technical solution of the present invention also provides a memory structure, including: a substrate; a plurality of mutually independent pad structures located on the substrate, each of the pad structures is arranged in an array along a second direction and a first direction, and the first direction is perpendicular to the second direction; an active layer located on the surface of the substrate and the surface of the pad structure, the active layer covers the top of the pad structure and the side wall of the pad structure along the first direction, the active layer exposes the side wall of the pad structure along the second direction, the active layer extends along the first direction and is arranged in parallel along the second direction; an isolation structure, located between adjacent pad structures in the second direction, the top surface of the isolation structure is higher than or flush with the bottom surface of the active layer; a plurality of mutually independent floating gates, each of the floating gates is located on the surface of the active layer on each pad structure, and the floating gates are located between adjacent isolation structures in the second direction; a plurality of control gates located on the surface of the floating gate and the surface of the isolation structure, each of the control gates spans across a plurality of floating gates along the second direction, and each of the control gates extends along the second direction and is arranged in parallel along the first direction.

[0018] Optionally, the material of the substrate includes: silicon, silicon carbide, gallium arsenide and gallium nitride; the material of the pad structure includes: silicon oxide, silicon nitride and silicon oxynitride; the thickness range of the pad structure is: 50nm to 300nm; the angle range formed by the pad structure and the substrate is: 30° to 90°.

[0019] Optionally, a cross-sectional morphology of the cushion structure along the first direction includes a trapezoid.

[0020] Optionally, the method further includes: a first insulating layer located between the active layer and the floating gate; the material of the first insulating layer includes: silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

[0021] Optionally, it also includes: a plurality of fourth openings and a plurality of fifth openings located between adjacent control gates, each of the fourth openings and each of the fifth openings are located between adjacent pad structures and each of the fourth openings and each of the fifth openings are adjacent to each of the fifth openings along a first direction, the fourth openings and the fifth openings expose the surface of the first insulating layer, the size of the fourth opening along a direction parallel to the substrate surface is larger than the size of the fifth opening along a direction parallel to the substrate surface, and each of the fourth openings and each of the fifth openings extend along the second direction.

[0022] Optionally, it also includes: a drain lightly doped region located at the bottom of the fourth opening; a source region located at the bottom of the fifth opening; a common source line connecting adjacent source regions parallel to the first direction; the doping method of the drain lightly doped region includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13atoms / cm 2 to 5E15 atoms / cm2 The doping method of the source region includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 between.

[0023] Optionally, it also includes: a second dielectric layer located on the surface of the fourth opening, the fifth opening and the control gate; a sixth opening located in the second dielectric layer, each of the sixth openings exposing the surface of the active layer, each of the sixth openings being located in the drain lightly doped region in the first direction and the sixth openings being located between adjacent pad structures in the first direction; a drain heavily doped region located at the bottom of each of the sixth openings; and a conductive plug located in each of the sixth openings, the conductive plug being connected to the drain lightly doped region.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] The memory structure of the technical solution of the present invention has a plurality of mutually discrete pad structures located on a substrate, and an active layer located on the substrate and the pad structures. On the one hand, an isolation structure is provided between adjacent pad structures in the second direction, and the pad structure is a three-dimensional structure. Compared with the two-dimensional planar structure, the existence of the pad structure effectively increases the channel length of the active layer and improves the short channel effect. On the other hand, the shape of the pad structure is controllable, and the surface of the active layer has a plurality of floating gates, which can make the floating gate located on the pad structure have sharp corners, thereby improving the erasing efficiency of the floating gate.

[0026] In the method for forming a memory structure of the technical solution of the present invention, a plurality of mutually discrete pad structures and an active layer located on the surface of the pad structure are formed on a substrate. On the one hand, an isolation structure is formed between adjacent pad structures in the second direction. The pad structure is a three-dimensional structure. Compared with the two-dimensional planar structure, the existence of the pad structure effectively increases the channel length of the active layer and improves the short channel effect. On the other hand, the shape of the pad structure is controllable, and a plurality of floating gates are formed on the surface of the active layer, so that the floating gate formed on the pad structure has a sharp corner, thereby improving the erasing efficiency of the floating gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 53 It is a schematic structural diagram of each step of a method for forming a memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, the prior art NOT OR (NOR) type flash memory structure still has many problems.

[0029] In an embodiment of a flash memory, the flash memory requires a smaller process node, but the reduction in the geometric size of the flash memory will lead to a reduction in the channel length, resulting in a short channel effect.

[0030] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure and a method for forming the same, wherein a plurality of mutually discrete pad structures and an active layer located on the surface of the pad structure are formed on a substrate. On the one hand, an isolation structure is formed between adjacent pad structures in the second direction. The pad structure is a three-dimensional structure. Compared with the two-dimensional planar structure, the existence of the pad structure effectively increases the channel length of the active layer and improves the short channel effect. On the other hand, the shape of the pad structure is controllable, and a plurality of floating gates are formed on the surface of the active layer, so that the floating gates formed on the pad structure have sharp corners, thereby improving the erasing efficiency of the floating gates.

[0031] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 53 It is a structural schematic diagram of the formation process of the memory structure of an embodiment of the present invention.

[0033] Please refer to Figure 1 , providing a substrate 100.

[0034] The material of the substrate 100 includes silicon, silicon carbide, gallium nitride and gallium arsenide.

[0035] The substrate 100 provides a structural basis for the subsequent formation of a pad structure 109 .

[0036] A plurality of mutually separate pad structures 109 and an active layer 110 located on the surface of the pad structure 109 are formed on the substrate 100, each of the pad structures 109 is arranged in an array along the second direction and the first direction, the first direction is perpendicular to the second direction, the active layer 110 covers the top of the pad structure 109 and the side wall of the pad structure 109 along the first direction, the active layer 110 exposes the side wall of the pad structure 109 along the second direction, and the active layer 110 extends along the first direction and is arranged in parallel along the second direction. For details, please refer to Figures 2 to 17 .

[0037] Please refer to Figure 2 and Figure 3 , Figure 2 for Figure 3 A top view of Figure 3 yes Figure 2In the cross-sectional view along the AA' direction, a cushion material layer 101 is formed on the surface of the substrate 100; a first mask layer (not shown) is formed on the surface of the cushion material layer 101, and the first mask layer (not shown) extends along the second direction and is arranged parallel to the first direction, and the first mask layer (not shown) exposes a portion of the surface of the cushion material layer 101.

[0038] The cushion material layer 101 provides a structural basis for the subsequent formation of a cushion structure 109 .

[0039] The material of the pad material layer 101 includes silicon oxide, silicon nitride and silicon oxynitride.

[0040] The thickness of the cushion material layer 101 ranges from 50 nm to 300 nm.

[0041] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 A top view of Figure 5 yes Figure 4 In the cross-sectional view along the AA' direction, the first mask layer (not shown) is used as a mask, and the pad material layer 101 (such as Figure 3 The first etching process comprises a first etching method, wherein the first etching process comprises a first etching method, a first etching method, a first etching method, and a first etching method. The first etching process comprises a first etching method, a first etching method, and a first etching method. The first etching process comprises a first etching method, a first etching method, and a first etching method. The first etching process comprises a first etching method, a first etching method, and a first etching method. The first etching process comprises a first etching method, a first etching method, and a first etching method. The first etching process comprises a first etching method, a first etching method, and a first etching method. The first etching process comprises a first etching method, a first etching method, and a first etching method.

[0042] The material of the initial pad layer 102 includes silicon oxide, silicon nitride and silicon oxynitride.

[0043] The thickness of the initial pad layer 102 ranges from 50 nm to 300 nm.

[0044] The cross-sectional morphology of the initial pad layer 102 along the first direction includes: trapezoidal, arc-shaped and square; specifically, in this embodiment, the cross-sectional morphology of the initial pad layer 102 along the first direction is trapezoidal.

[0045] The initial pad layer 102 provides a structural basis for the subsequent formation of the pad structure 109. On the one hand, the subsequently formed pad structure 109 is a three-dimensional structure. Compared with the two-dimensional planar structure, the existence of the pad structure 109 effectively increases the channel length of the subsequently formed active layer 110 and improves the short channel effect. On the other hand, the shape of the subsequently formed pad structure 109 is controllable, so that the floating gate 111 located on the pad structure 109 has a sharp corner, thereby improving the erasing efficiency of the floating gate.

[0046] The depth of the first opening 103 ranges from 50 nm to 300 nm.

[0047] The first opening 103 provides a structural basis for the subsequent formation of the fourth opening 117 and the fifth opening 118 .

[0048] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 A top view of Figure 7 yes Figure 6 In the cross-sectional view along the AA' direction, an active material layer 104 is formed on the surface of the initial pad layer 102 and the substrate 100; a second mask layer (not shown) is formed on the surface of the active material layer 104, and the second mask layer (not shown) extends along the second direction and is arranged parallel to the first direction, and the second mask layer (not shown) exposes a portion of the surface of the active material layer 104.

[0049] The active material layer 104 provides a structural basis for the subsequent formation of the initial active layer 105. The active material layer 104 is formed on the surface of the initial pad layer 102 and the cross-section of the initial pad layer 102 along the first direction is a trapezoid, so that the cross-section of the subsequently formed initial active layer 105 along the first direction has an obtuse angle, so that the subsequently formed floating gate 111 has a sharp angle, thereby improving the erasing efficiency of the floating gate.

[0050] The material of the active material layer 104 includes: single crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide and gallium nitride.

[0051] The thickness of the active material layer 104 is in the range of 100 nm to 500 nm.

[0052] Please refer to Figure 8 and Fig. 9 , Figure 8 for Fig. 9 A top view of Fig. 9 yes Figure 8 In the cross-sectional view along the AA' direction, the second mask layer (not shown) is used as a mask and the active material layer 104 (such as Figure 7 As shown), an initial active layer 105 and a plurality of second openings 106 located between the initial active layer 105 are formed, each of the second openings 106 extends along the second direction and each of the second openings 106 is arranged in parallel along the first direction, each of the second openings 106 has a second projection b in a direction parallel to the surface of the substrate 100, and the second projection b is located within the range of the first projection a.

[0053] The second etching process includes dry etching.

[0054] The material of the initial active layer 105 includes: single crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide and gallium nitride.

[0055] The thickness of the initial active layer 105 is in the range of 100 nm to 500 nm.

[0056] The initial active layer 105 is formed on the surface of the initial pad layer 102 and the cross-section of the initial pad layer 102 along the first direction is trapezoidal, so that the cross-section of the initial active layer 105 along the first direction has an obtuse angle, so that the subsequently formed floating gate 111 has a sharp angle, thereby improving the erasing efficiency of the floating gate.

[0057] The depth of the second opening 106 ranges from 50 nm to 300 nm.

[0058] The second opening 106 provides a structural basis for subsequently forming a fourth opening 117 and a fifth opening 118 .

[0059] Please refer to Fig.10 and Fig.11 , Fig.10 for Fig.11 A top view of Fig.11 yes Fig.10 In the cross-sectional view along the AA′ direction, a first insulating layer 107 is formed on the surface of the initial active layer 105 .

[0060] The material of the first insulating layer 107 includes silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

[0061] The thickness of the first insulating layer 107 is in the range of 2 nm to 15 nm.

[0062] The first insulating layer 107 functions to isolate the initial active layer 105 from an initial floating gate layer 108 formed subsequently.

[0063] Please refer to Fig.12 and Fig.13 , Fig.12 for Fig.13 A top view of Fig.13 yes Fig.12 In the cross-sectional view along the AA' direction, an initial floating gate layer 108 is formed on the surface of the initial active layer 105; a third mask layer (not shown) is formed on the surface of the initial floating gate layer 108, and the third mask layer (not shown) extends along the first direction and is arranged in parallel along the second direction, and the third mask layer (not shown) exposes a portion of the surface of the initial floating gate layer 108.

[0064] The initial floating gate layer 108 provides a structural basis for the subsequent formation of the floating gate 111. Since the cross section of the initial active layer 105 along the first direction has an obtuse angle, the subsequently formed floating gate 111 has a sharp angle, thereby improving the erasing efficiency of the floating gate.

[0065] The material of the initial floating gate layer 108 includes polysilicon.

[0066] The thickness of the initial floating gate layer 108 ranges from 120 nm to 600 nm.

[0067] Please refer to Figures 14 to 17 , Fig.14 for Figures 15 to 17 A top view of Fig.15 yes Fig.14 Cross-sectional view along AA' direction, Fig.16 yes Fig.14 Cross-sectional view along BB' direction, Fig.17 yes Fig.14 In the cross-sectional view along the CC' direction, the initial floating gate layer 108 (eg, Fig.13 As shown), the initial active layer 105 (as shown Fig.13 As shown), and the initial pad 102 (as shown Fig.13 As shown), until the surface of the substrate 100 is exposed, the pad structure 109, the active layer 110, the floating gate 111, and the third openings 112 located between the pad structure 109, the active layer 110, and the floating gate 111 are formed, and each of the third openings 112 exposes the surface of the substrate 100 and extends along the first direction.

[0068] The cross-sectional shape of the cushion structure 109 along the first direction includes: square and trapezoid.

[0069] Specifically, in this embodiment, the cross-sectional morphology of the cushion structure 109 along the first direction includes a trapezoid.

[0070] The thickness of the cushion structure 109 is in the range of 50 nm to 300 nm; the angle formed by the cushion structure 109 and the substrate 100 is in the range of 30° to 90°.

[0071] On the one hand, the pad structure 109 is a three-dimensional structure. Compared with the two-dimensional planar structure, the existence of the pad structure 109 effectively increases the channel length of the active layer 110 and improves the short channel effect. On the other hand, the cross-section of the pad structure 109 along the first direction is trapezoidal, which can make the floating gate 111 formed on the pad structure 109 have sharp corners, thereby improving the erasing efficiency of the floating gate.

[0072] Specifically, in this embodiment, the floating gate 111 is formed before the isolation structure 114 is formed, and the floating gate 111, the pad structure 109 and the active layer 110 are formed simultaneously.

[0073] The third etching process includes dry etching.

[0074] The material of the active layer 110 includes: single crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide and gallium nitride.

[0075] The thickness of the active layer 110 ranges from 100 nm to 500 nm.

[0076] The active layer 110 is formed on the surface of the pad structure 109 and the cross-section of the pad structure 109 along the first direction is trapezoidal, so that the cross-section of the active layer 110 along the first direction has an obtuse angle, and the subsequently formed floating gate 111 has a sharp angle, thereby improving the erasing efficiency of the floating gate.

[0077] The depth of the third opening 112 ranges from 150 nm to 650 nm.

[0078] The third opening 112 provides a structural basis for subsequently forming an isolation structure 114 .

[0079] An isolation structure 114 is formed between adjacent pad structures 109 in the second direction, and a plurality of separate floating gates 111 are formed on the surface of the active layer 110 on each pad structure 109. The top surface of the isolation structure 114 is higher than or flush with the bottom surface of the active layer 110, and the floating gate 111 is located between adjacent isolation structures 114 in the second direction. For details, please refer to Figures 18 to 25 .

[0080] Please refer to Figures 18 to 21 , Fig.18 for Figures 19 to 21 A top view of Fig.19 yes Fig.18 Cross-sectional view along AA' direction, Fig. 20 yes Fig.18 Cross-sectional view along BB' direction, Fig.21 yes Fig.18 In the cross-sectional view along the CC′ direction, an initial isolation structure 113 is formed in each of the third openings 112 to fill the third openings 112 .

[0081] The initial isolation structure 113 provides a structural basis for the subsequent formation of the isolation structure 114 .

[0082] The material of the initial isolation structure 113 includes silicon oxide, aluminum oxide, silicon nitride and silicon oxynitride.

[0083] Please refer to Figure 22 to Figure 25 , Fig. 22 for Figure 23 to Figure 25 A top view of Fig.23 yes Fig. 22 Cross-sectional view along AA' direction, Fig.24 yes Fig. 22 Cross-sectional view along BB' direction, Fig.25 yes Fig. 22 The cross-sectional view along the CC' direction shows the initial isolation structure 113 (eg Fig.21 As shown in the figure, a back etching process is performed until the top surface of the initial isolation structure 113 is flush with the bottom surface of the active layer 110, thereby forming the isolation structure 114.

[0084] The back etching method is dry etching.

[0085] The material of the isolation structure 114 includes silicon oxide, aluminum oxide, silicon nitride and silicon oxynitride.

[0086] Specifically, in this embodiment, the top surface of the isolation structure 114 is higher than or flush with the bottom surface of the active layer 110 .

[0087] Please refer to Figure 26 to Figure 29 , Fig.26 for Figure 27 to Figure 29 A top view of Fig. 27 yes Fig.26 Cross-sectional view along AA' direction, Fig.28 yes Fig.26 Cross-sectional view along BB' direction, Fig.29 yes Fig.26 The cross-sectional view along the CC′ direction shows that after the isolation structure 114 is formed, the method further includes: forming a first dielectric layer 115 on the isolation structure 114 and the surface of the substrate 100 .

[0088] The material of the first dielectric layer 115 includes silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

[0089] The first dielectric layer 115 functions to isolate the floating gate 111 from a control gate material layer 116 formed subsequently.

[0090] A plurality of control gates 119 are formed on the surface of the floating gate 111 and the surface of the isolation structure 114. Each of the control gates 119 crosses a plurality of floating gates 111 along the second direction. Each of the control gates 119 extends along the second direction and is arranged in parallel along the first direction. Figures 30 to 37 .

[0091] Please refer to Figure 30 to Figure 33 , Fig.30 for Figure 31 to Figure 33 A top view of Fig.31 yes Fig.30 Cross-sectional view along AA' direction, Fig.32 yes Fig.30 Cross-sectional view along BB' direction, Fig.33 yes Fig.30 In the cross-sectional view along the CC' direction, a control gate material layer 116 is formed on the surface of the isolation structure 114 and the surface of the floating gate 111; a fourth mask layer (not shown) is formed on the surface of the control gate material layer 116, and the fourth mask layer (not shown) extends along the second direction and is arranged parallel to the first direction, and the fourth mask layer (not shown) exposes a portion of the surface of the control gate material layer 116.

[0092] The control gate material layer 116 is made of polysilicon.

[0093] The control gate material layer 116 provides a structural basis for the subsequent formation of a control gate 119 .

[0094] Please refer to Figure 34 to Figure 37 , Fig.34 for Figure 35 to Figure 37 A top view of Fig.35 yes Fig.34 Cross-sectional view along AA' direction, Fig.36 yes Fig.34 Cross-sectional view along CC' direction, Fig.37 yes Fig.34 In the cross-sectional view along the DD' direction, the control gate material layer 116 (eg, Fig.31 As shown) and floating gate 111 (as Fig.31 As shown), a fourth opening 117 and a fifth opening 118 are formed in the control gate material layer 116 and the floating gate 111, each of the fourth openings 117 and each of the fifth openings 118 are located between adjacent pad structures 109 and each of the fourth openings 117 and each of the fifth openings 118 are adjacent to each other along a first direction, each of the fourth openings 117 and each of the fifth openings 118 extend along a second direction, and each of the fourth openings 117 and each of the fifth openings 118 exposes the surface of the first insulating layer 107.

[0095] Specifically, in this embodiment, the control gate 119 is formed by using the control gate material layer 116 while the fourth opening 117 and the fifth opening 118 are formed.

[0096] The control gate 119 crosses a plurality of floating gates 111 along the second direction, and the control gate 119 , the floating gates 111 , the active layer 110 , and the subsequently formed common source line 121 and the drain lightly doped region 120 together form a wordline.

[0097] The fourth etching process includes dry etching. The fourth etching process stops after etching to the bottom first dielectric layer 115, leaving the isolation structure 114 at the bottom.

[0098] Specifically, in this embodiment, the size of the fourth opening 117 in the first direction is larger than the size of the fifth opening 118 in the first direction.

[0099] The fourth opening 117 provides a structural basis for the subsequent formation of a drain lightly doped region 120 ; the fifth opening 118 provides a structural basis for the subsequent formation of a common source line 121 .

[0100] After forming the control gate 119, a fifth mask layer (not shown) is formed on the surface of the control gate 119 and in the fifth opening 118. The fifth mask layer (not shown) extends along the second direction and is arranged in parallel along the first direction. The fifth mask layer (not shown) exposes the fourth opening 117. The surface of the active layer 110 at the bottom of the fourth opening 117 is lightly doped with a drain electrode to form a lightly doped drain region 120. A sixth mask layer (not shown) is formed on the surface of the control gate 119 and in the fourth opening 117. The sixth mask layer (not shown) extends along the second direction and is arranged in parallel along the first direction. The sixth mask layer (not shown) exposes the fifth opening 118. Using the sixth mask layer as a mask, a fifth etching process is used to etch the first dielectric layer 115 at the bottom of the fifth opening 118 and the isolation structure 114 at the bottom of the fifth opening 118. After the fifth etching process, the surface of the substrate 100 and the surface of the active layer 110 at the bottom of the fifth opening 118 are heavily doped with a source electrode to form a source region, and the source regions adjacent to each other parallel to the first direction are connected together to form a common source line 121 parallel to the second direction. The drain lightly doped region 120 and the common source line 121 are adjacent to each other along the first direction, and a pad layer structure 109 is provided between the adjacent drain lightly doped regions 120 and the common source line 121; a pad layer structure 109 is provided between the adjacent control gates 119 and on the surface of the control gates 119. A second dielectric layer 122; a plurality of sixth openings 123 are formed in the second dielectric layer 122, each of the sixth openings 123 exposes the surface of the active layer 110, each of the sixth openings 123 is located in the drain lightly doped region 120 in the first direction and the sixth openings 123 are located between adjacent pad structures 109 in the first direction; the active layer surface at the bottom of each of the sixth openings is heavily doped with the drain; a conductive plug 124 is formed in each of the sixth openings 123, and the conductive plug 124 is connected to the drain lightly doped region 120. For details, please refer to Figures 38 to 49 .

[0101] Please refer to Figures 38 to 41 , Fig.38 for Figure 39 to Figure 41 A top view of Fig.39 yes Fig.38 Cross-sectional view along AA' direction, Fig.40 yes Fig.38 Cross-sectional view along CC' direction, Fig.41 yes Fig.38 In the cross-sectional view along the DD' direction, a fifth mask layer (not shown) is formed on the surface of the control gate 119 and in the fifth opening 118, the fifth mask layer (not shown) extends along the second direction and is arranged in parallel along the first direction, and the fifth mask layer exposes the fourth opening 117; the surface of the active layer 110 at the bottom of the fourth opening 117 is lightly doped with a drain electrode to form a lightly doped drain region 120; a sixth mask layer (not shown) is formed on the surface of the control gate 119 and in the fourth opening 117, the sixth mask layer (not shown) extends along the second direction and is arranged in parallel along the first direction, and the sixth mask layer exposes the fifth opening 118; The sixth mask layer is a mask, and the fifth etching process is used to etch the first dielectric layer 115 at the bottom of the fifth opening 118 and the isolation structure 114 at the bottom of the fifth opening 118; after the fifth etching process, the surface of the substrate 100 and the surface of the active layer 110 at the bottom of the fifth opening 118 are subjected to source heavy doping treatment to form a source region, and the adjacent source regions parallel to the first direction are connected together to form a common source line 121 parallel to the second direction, and the drain lightly doped region 120 and the common source line 121 are adjacent along the first direction and a pad layer structure 109 is provided between the adjacent drain lightly doped region 120 and the common source line 121.

[0102] The doping method of the drain electrode light doping includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13atoms / cm 2 To 5E15atoms / cm 2 The doping method of the heavily doped source includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 between.

[0103] The drain lightly doped region 120 is connected to a conductive plug 124 formed subsequently.

[0104] Please refer to Figure 42 to Figure 45 , Fig.42 for Figure 43 to Figure 45 A top view of Fig.43 yes Fig.42 Cross-sectional view along AA' direction, Fig.44 yes Fig.42Cross-sectional view along BB' direction, Fig.45 yes Fig.42 In the cross-sectional view along the CC′ direction, a second dielectric layer 122 is formed between adjacent control gates 119 and on the surface of the control gates 119 .

[0105] The material of the second dielectric layer 122 includes silicon oxide.

[0106] The method for forming the second dielectric layer 122 includes: forming an initial second dielectric layer (not shown) between adjacent control gates 119 and on the surface of the control gates 119; and planarizing the initial second dielectric layer (not shown). The thickness of the second dielectric layer 122 after planarization is 100 nm higher than the surface of the control gates 119.

[0107] Please refer to Figure 46 to Figure 49 , Fig.46 for Figure 47 to Figure 49 A top view of Fig.47 yes Fig.46 Cross-sectional view along AA' direction, Fig.48 yes Fig.46 Cross-sectional view along BB' direction, Fig.49 yes Fig.46 In the cross-sectional view along the CC' direction, a plurality of sixth openings 123 are formed in the second dielectric layer 122, each of the sixth openings 123 exposes the surface of the active layer 110, each of the sixth openings 123 is located in the drain lightly doped region 120 in the first direction and the sixth openings 123 are located between adjacent pad structures 109 in the first direction; the surface of the active layer 110 at the bottom of each of the sixth openings 123 is heavily drain doped.

[0108] The method for forming the sixth opening 123 includes: forming a seventh mask layer on the surface of the control gate 119, wherein the seventh mask layer extends along the second direction and is arranged in parallel along the first direction, and the seventh mask layer exposes a portion of the surface of the control gate 119; using the seventh mask layer (not shown) as a mask, etching the second dielectric layer 122 using a sixth etching process to form a plurality of sixth openings 123 located in the second dielectric layer 122.

[0109] The sixth opening 123 provides a structural basis for subsequently forming a conductive plug 124 .

[0110] The projection of the sixth opening 123 in a direction parallel to the surface of the substrate 100 is located at the fourth opening 117 (eg Fig.39 ) is within a projection parallel to the surface direction of the substrate 100.

[0111] The depth of the sixth opening 123 ranges from 200 nm to 700 nm.

[0112] The parameters for heavily doping the drain electrode of the sixth opening include: ion species are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 To 5E15atoms / cm 2 between.

[0113] Please refer to Figure 50 to Figure 53 , Fig.50 for Figure 51 to Figure 53 A top view of Fig.51 yes Fig.50 Cross-sectional view along AA' direction, Fig.52 yes Fig.50 Cross-sectional view along BB' direction, Fig.53 yes Fig.50 In the cross-sectional view along the CC′ direction, a conductive plug 124 is formed in each of the sixth openings 123 , and the conductive plug 124 is connected to the drain lightly doped region 120 .

[0114] The conductive plug 124 is made of materials including tungsten and copper.

[0115] Specifically, in this embodiment, the conductive plug 124 is connected to the drain lightly doped region 120, and is connected to the subsequently formed metal layer through the drain lightly doped region 120, the control gate 119 and the common source line 121, so as to realize the programming, erasing and read-write operations of the memory structure. On the one hand, the pad structure 109 is a three-dimensional structure, which effectively increases the channel length of the active layer 110 and improves the short channel effect compared with the two-dimensional planar structure; on the other hand, the shape of the pad structure 109 is controllable, and a plurality of floating gates 111 are formed on the surface of the active layer 110, so that the floating gates 111 formed on the pad structure 109 have sharp corners, thereby improving the erasing efficiency of the floating gates.

[0116] Accordingly, an embodiment of the present invention further provides a memory structure, please refer to Figure 50 to Figure 53 , Fig.50 for Figure 51 to Figure 53 A top view of Fig.51 yes Fig.50 Cross-sectional view along AA' direction, Fig.52 yes Fig.50 Cross-sectional view along BB' direction, Fig.53 yes Fig.50The cross-sectional view along the CC' direction comprises: a substrate 100; a plurality of mutually separate pad structures 109 located on the substrate 100, each of the pad structures 109 being arranged in an array along a second direction and a first direction, wherein the first direction is perpendicular to the second direction; an active layer 110 located on the surface of the substrate 100 and the surface of the pad structure 109, wherein the active layer 110 covers the top of the pad structure 109 and the side wall of the pad structure 109 along the first direction, the active layer 110 exposes the side wall of the pad structure 109 along the second direction, and the active layer 110 extends along the first direction and is arranged in parallel along the second direction; an isolation junction structure 114, which is located between adjacent cushion structures 109 in the second direction, and the top surface of the isolation structure 114 is higher than or flush with the bottom surface of the active layer 110; a plurality of discrete floating gates 111, each floating gate 111 is respectively located on the surface of the active layer 110 on each cushion structure 109, and the floating gates 111 are located between adjacent isolation structures 114 in the second direction; a plurality of control gates 119 are located on the surfaces of the floating gates 111 and the isolation structure 114, each of the control gates 119 spans across the plurality of floating gates 111 along the second direction, and each of the control gates 119 extends along the second direction and is arranged in parallel along the first direction.

[0117] The memory structure includes a substrate 100 .

[0118] The material of the substrate 100 includes silicon, silicon carbide, gallium nitride and gallium arsenide.

[0119] The memory structure includes: a plurality of mutually independent pad structures 109 located on the substrate 100, each of the pad structures 109 is arranged in an array along a second direction and a first direction, and the first direction is perpendicular to the second direction.

[0120] The material of the pad structure 109 includes silicon oxide, silicon nitride and silicon oxynitride; the thickness of the pad structure 109 ranges from 50 nm to 300 nm; the angle formed by the pad structure 109 and the substrate 100 ranges from 30° to 90°.

[0121] The cross-sectional morphology of the cushion structure 109 along the first direction includes: trapezoid, arc and square; specifically, in this embodiment, the cross-sectional morphology of the cushion structure 109 along the first direction includes trapezoid.

[0122] The memory structure includes: an active layer 110 located on the surface of the substrate 100 and the surface of the pad structure 109, the active layer 110 covers the top of the pad structure 109 and the side wall of the pad structure 109 along the first direction, the active layer 110 exposes the side wall of the pad structure 109 along the second direction, and the active layer 110 extends along the first direction and is arranged in parallel along the second direction.

[0123] The material of the active layer 110 includes: single crystal silicon, silicon carbide, polycrystalline silicon, gallium arsenide and gallium nitride.

[0124] The thickness of the active layer 110 ranges from 100 nm to 500 nm.

[0125] The memory structure includes: a first insulating layer 107 located between the active layer 110 and the floating gate 111 .

[0126] The material of the first insulating layer 107 includes silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

[0127] The thickness of the first insulating layer 107 is in the range of 2 nm to 15 nm.

[0128] The memory structure includes an isolation structure 114 located between adjacent pad structures 109 in the second direction, and a top surface of the isolation structure 114 is higher than or flush with a bottom surface of the active layer 110 .

[0129] The material of the isolation structure 114 includes silicon oxide, aluminum oxide, silicon nitride and silicon oxynitride.

[0130] The memory structure includes: a plurality of separate floating gates 111 , each of which is located on the surface of the active layer 110 on each pad structure 109 , and the floating gates 111 are located between adjacent isolation structures 114 in the second direction.

[0131] The floating gate 111 is made of polysilicon.

[0132] The thickness of the floating gate 111 ranges from 120 nm to 600 nm.

[0133] The memory structure includes: a plurality of control gates 119 located on the surface of the floating gate 111 and the surface of the isolation structure 114, each of the control gates 119 crosses a plurality of floating gates 111 along the second direction, and each of the control gates 119 extends along the second direction and is arranged in parallel along the first direction.

[0134] The material of the control gate 119 includes polysilicon.

[0135] The memory structure includes: a first dielectric layer 115 located between the floating gate 111 and the control gate 119 .

[0136] The material of the first dielectric layer 115 includes silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

[0137] The memory structure includes a plurality of fourth openings 117 (eg, Fig.39 as shown) and a plurality of fifth openings 118 (as shown Fig.39 As shown), each of the fourth openings 117 and each of the fifth openings 118 are located between adjacent pad structures 109 and each of the fourth openings 117 and each of the fifth openings 118 are adjacent to each other along a first direction, the fourth openings 117 and the fifth openings 118 expose the surface of the first insulating layer 107, the size of the fourth opening 117 along a direction parallel to the surface of the substrate 100 is larger than the size of the fifth opening 118 along a direction parallel to the surface of the substrate 100, and each of the fourth openings 117 and each of the fifth openings 118 extend along a second direction.

[0138] The memory structure includes: a drain lightly doped region 120 located at the bottom surface of the fourth opening 117; a source region located at the bottom of the fifth opening 118; a common source line 121 connecting adjacent source regions parallel to the first direction; the doping method of the drain lightly doped region 120 includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 The doping method of the source region includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 To 5E15atoms / cm 2 between.

[0139] The memory structure includes: a second dielectric layer 122 located on the surface of the fourth opening 117, the fifth opening 118 and the control gate 119; a sixth opening 123 located in the second dielectric layer 122, each of the sixth openings 123 exposing the surface of the active layer 110, each of the sixth openings 123 being located in the drain lightly doped region 120 in the first direction and the sixth openings 123 being located between adjacent pad structures 109 in the first direction; a drain heavily doped region located at the bottom of each of the sixth openings 123; and a conductive plug 124 located in each of the sixth openings 123, the conductive plug 124 being connected to the drain lightly doped region 120.

[0140] The material of the second dielectric layer 122 includes silicon oxide.

[0141] The depth of the sixth opening 123 ranges from 200 nm to 700 nm.

[0142] The drain heavy doping parameters of the sixth opening 123 include: ion species are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm2 To 5E15atoms / cm 2 between.

[0143] The conductive plug 124 is made of materials including tungsten and copper.

[0144] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: substrate; A plurality of mutually separate pad layer structures located on the substrate, each of the pad layer structures is arranged in an array along a second direction and a first direction, and the first direction is perpendicular to the second direction; An active layer located on the surface of the substrate and the surface of the pad structure, the active layer covers the top of the pad structure and the sidewall of the pad structure along the first direction, the active layer exposes the sidewall of the pad structure along the second direction, and the active layer extends along the first direction and is arranged in parallel along the second direction; An isolation structure, located between adjacent pad layer structures in the second direction, wherein a top surface of the isolation structure is higher than or flush with a bottom surface of the active layer; A plurality of mutually independent floating gates, each of which is located on the surface of the active layer on each pad structure, and the floating gate is located between adjacent isolation structures in the second direction; A plurality of control gates are located on the surface of the floating gate and the surface of the isolation structure, each of the control gates crosses over a plurality of floating gates along the second direction, and each of the control gates extends along the second direction and is arranged in parallel along the first direction.

2. The memory structure according to claim 1, characterized in that: The materials of the substrate include silicon, silicon carbide, gallium arsenide and gallium nitride; the materials of the pad structure include silicon oxide, silicon nitride and silicon oxynitride; the thickness of the pad structure ranges from 50nm to 300nm; the angle formed by the pad structure and the substrate ranges from 30° to 90°.

3. The memory structure according to claim 1, characterized in that: The cross-sectional morphology of the cushion layer structure along the first direction includes a trapezoid.

4. The memory structure according to claim 1, characterized in that: Also includes: a first insulating layer between the active layer and the floating gate; The material of the first insulating layer includes silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

5. The memory structure according to claim 4, characterized in that: Also includes: A plurality of fourth openings and a plurality of fifth openings are located between adjacent control gates, each of the fourth openings and each of the fifth openings are located between adjacent pad structures and each of the fourth openings and each of the fifth openings are adjacent to each of the fifth openings along a first direction, the fourth openings and the fifth openings expose the surface of the first insulating layer, a dimension of the fourth opening along a direction parallel to the substrate surface is greater than a dimension of the fifth opening along a direction parallel to the substrate surface, and each of the fourth openings and each of the fifth openings extend along a second direction.

6. The memory structure according to claim 5, characterized in that: Also includes: a drain lightly doped region located at the bottom of the fourth opening; a source region located at the bottom of the fifth opening; A common source line connecting adjacent source regions parallel to the first direction; The doping method of the drain lightly doped region includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 The doping method of the source region includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13atoms / cm 2 to 5E15 atoms / cm 2 between.

7. The memory structure according to claim 6, characterized in that: Also includes: A second dielectric layer located at the fourth opening, the fifth opening and the surface of the control gate; A sixth opening located in the second dielectric layer, each of the sixth openings exposing a surface of the active layer, each of the sixth openings being located in the drain lightly doped region in the first direction and between adjacent pad layer structures in the first direction; A heavily doped drain region is located at the bottom of each of the sixth openings; and a conductive plug is located in each of the sixth openings, wherein the conductive plug is connected to the lightly doped drain region.

8. A method for forming a memory structure, characterized in that: include: providing a substrate; A plurality of mutually separate pad structures and an active layer located on the surface of the pad structures are formed on the substrate, wherein the pad structures are arranged in an array along a second direction and a first direction, the first direction is perpendicular to the second direction, the active layer covers the top of the pad structure and the side wall of the pad structure along the first direction, the active layer exposes the side wall of the pad structure along the second direction, and the active layer extends along the first direction and is arranged in parallel along the second direction; An isolation structure is formed between adjacent pad structures in the second direction and a plurality of separate floating gates are formed on the surface of the active layer on each pad structure, wherein the top surface of the isolation structure is higher than or flush with the surface of the active layer, and the floating gates are located between adjacent isolation structures in the second direction; A plurality of control gates are formed on the surface of the floating gate and the surface of the isolation structure. Each of the control gates crosses over a plurality of floating gates along the second direction. Each of the control gates extends along the second direction and is arranged in parallel along the first direction.

9. The method for forming a memory structure according to claim 8, wherein: The floating gate is formed before forming the isolation structure, and the floating gate, the pad layer structure and the active layer are formed simultaneously.

10. The method for forming a memory structure according to claim 8, wherein: The method for forming the pad structure, the active layer and the floating gate comprises: forming a pad material layer on the surface of the substrate; forming a first mask layer on the surface of the pad material layer, the first mask layer extending along the second direction and arranged in parallel along the first direction, the first mask layer exposing a portion of the surface of the pad material layer; using the first mask layer as a mask, etching the pad material layer by a first etching process until the substrate surface is exposed, forming an initial pad layer and a plurality of first openings located between adjacent initial pad layers, each of the first openings extending along the second direction and each of the first openings arranged in parallel along the first direction, each of the first openings having a first projection in a direction parallel to the substrate surface; forming an active material layer on the initial pad layer and the substrate surface; forming a second mask layer on the surface of the active material layer, the second mask layer extending along the second direction and arranged in parallel along the first direction, the second mask layer exposing a portion of the surface of the active material layer; using the second mask layer as a mask, etching the pad material layer by a first etching process until the substrate surface is exposed. The active material layer is etched by a second etching process to form an initial active layer and a plurality of second openings located between the initial active layers, each of the second openings extending along a second direction and arranged in parallel along a first direction, each of the second openings having a second projection in a direction parallel to the substrate surface, and the second projection is located within the range of the first projection; an initial floating gate layer is formed on the surface of the initial active layer; a third mask layer is formed on the surface of the initial floating gate layer, the third mask layer extending along the first direction and arranged in parallel along the second direction, the third mask layer exposing a portion of the surface of the initial floating gate layer; the initial floating gate layer, the initial active layer, and the initial pad layer are etched by a third etching process using the third mask layer as a mask until the substrate surface is exposed, to form the pad layer structure, the active layer, the floating gate, and the third openings located between the pad layer structure, the active layer, and the floating gate, each of the third openings exposing the substrate surface and each of the third openings extending along the first direction.

11. The method for forming a memory structure according to claim 8, wherein: The cross-sectional morphology of the cushion layer structure along the first direction includes a trapezoid.

12. The method for forming a memory structure according to claim 10, wherein: Before forming the initial floating gate layer and after forming the initial active layer, the method further includes: forming a first insulating layer on the surface of the initial active layer; the material of the first insulating layer includes: silicon oxide, silicon nitride, aluminum oxide and silicon oxynitride.

13. The method for forming a memory structure according to claim 10, wherein: The method for forming the control gate includes: forming a control gate material layer on the surface of the isolation structure and the surface of the floating gate; forming a fourth mask layer on the surface of the control gate material layer, the fourth mask layer extending along the second direction and arranged in parallel along the first direction, the fourth mask layer exposing a portion of the surface of the control gate material layer; using the fourth mask layer as a mask, etching the control gate material layer and the floating gate by a fourth etching process to form a fourth opening and a fifth opening located in the control gate material layer and the floating gate, each of the fourth openings and each of the fifth openings are located between adjacent pad structures and each of the fourth openings is adjacent to each of the fifth openings along the first direction, each of the fourth openings and each of the fifth openings extends along the second direction, and each of the fourth openings and each of the fifth openings exposes the surface of the first insulating layer.

14. The method for forming a memory structure according to claim 13, wherein: The size of the fourth opening in the first direction is larger than the size of the fifth opening in the first direction.

15. The method for forming a memory structure according to claim 10, wherein: The method for forming the isolation structure comprises: forming an initial isolation structure filling the third openings in each of the third openings; and etching back the initial isolation structure until the top surface of the initial isolation structure is flush with the bottom surface of the active layer to form the isolation structure.

16. The method for forming a memory structure according to claim 13, wherein: After forming the control gate, the method further includes: forming a fifth mask layer on the surface of the control gate and in the fifth opening, the fifth mask layer extending along the second direction and arranged in parallel along the first direction, and the fifth mask layer exposing the fourth opening; performing a drain light doping treatment on the surface of the active layer at the bottom of the fourth opening to form a drain light doping region; forming a sixth mask layer on the surface of the control gate and in the fourth opening, the sixth mask layer extending along the second direction and arranged in parallel along the first direction, and the sixth mask layer exposing the fifth opening; using the sixth mask layer as a mask, etching the first dielectric layer at the bottom of the fifth opening and the isolation structure at the bottom of the fifth opening by a fifth etching process; after the fifth etching process, performing a source heavy doping treatment on the surface of the substrate and the surface of the active layer at the bottom of the fifth opening. To form a source region, the source regions adjacent to each other parallel to the first direction are connected together to form a common source line parallel to the second direction, the drain lightly doped region and the common source line are adjacent to each other along the first direction and a pad structure is provided between the adjacent drain lightly doped regions and the common source line; a second dielectric layer is formed between adjacent control gates and on the surface of the control gates; a plurality of sixth openings are formed in the second dielectric layer, each of the sixth openings exposes the surface of the active layer, each of the sixth openings is located in the drain lightly doped region in the first direction and the sixth openings are located between adjacent pad structures in the first direction; the surface of the active layer at the bottom of each of the sixth openings is heavily doped with a drain; a conductive plug is formed in each of the sixth openings, and the conductive plug is connected to the drain lightly doped region.

17. The method for forming a memory structure according to claim 16, wherein: The doping method of the drain electrode light doping includes ion implantation; the parameters of the ion implantation include: ion types are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 The doping method of the heavily doped source includes ion implantation; the parameters of the ion implantation include: ion species are arsenic and phosphorus, ion implantation energy is between 10KeV and 50KeV, and ion implantation dose is 5E13 atoms / cm 2 to 5E15 atoms / cm 2 between.

18. The method for forming a memory structure according to claim 12, wherein: Before forming the control gate material layer and after forming the isolation structure, the method further includes: forming a first dielectric layer on the surface of the substrate on the isolation structure.

Images