CMOS device and forming method thereof

Abstract

The invention provides a CMOS device and a forming method thereof, and the forming method of the CMOS device comprises the steps: firstly executing a first etching process, and etching a first anti-reflection coating and a second dielectric layer of a second well region, so as to enable the top surface of the second dielectric layer to be lower than the top surface of a first dielectric layer; a second etching process is executed, the first dielectric layer is etched while germanium-silicon grooves are formed in the first well region on the two sides of the first grid electrode, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer. A second dielectric layer is etched in advance in a first etching process before a first extension region is formed in a second well region to the etched height of a subsequent first dielectric layer when a germanium-silicon groove is formed, and then when the germanium-silicon groove is formed, the etched height of the first dielectric layer is the same as the height of the second dielectric layer. Therefore, the problem of the height difference of the gate structures on the first well region and the second well region is solved, namely, the height difference of the gate structures of the PMOS device and the NMOS device is reduced, no additional process is needed, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a CMOS device and a method for forming the same. Background Art

[0002] In order to improve the carrier mobility of PMOS devices, people use the compressive stress generated by the different lattice constants of Si and Ge to embed in the source and drain regions to improve transistor performance. However, since silicon nitride (SiN) protects the gate of NMOS devices, there will be a height difference between the gate structures of PMOS devices and NMOS devices after the silicon germanium (SiGe) trench etching is completed. Subsequently, it is necessary to control the height of the two gates through processes such as ILD0 (Inter-Layer Dielectric 0, the 0th interlayer dielectric layer) and CMP (Chemical Mechanical Polish). The loop of the ILD0 process includes multiple process steps such as OX dep1 (Oxide deposit1, the first oxide layer deposition process), CMP1 (the first chemical mechanical polishing process), ETCH (etching process), OX dep2 (the second oxide layer deposition process), and CMP2 (the second chemical mechanical polishing process) after thinning SP2 (Spacer2, the second sidewall) to control the gate structure height of PMOS devices and NMOS devices to be consistent. Summary of the invention

[0003] The object of the present invention is to provide a CMOS device and a method for forming the same, so as to solve the problem that multiple process steps are required in the prior art to control the gate height consistency of a PMOS device and an NMOS device.

[0004] In order to solve the above technical problems, the present invention provides a method for forming a CMOS device, comprising:

[0005] A substrate is provided, wherein the substrate comprises a first well region and a second well region, wherein a first gate and a first dielectric layer located on the first gate are formed on the first well region, and a second gate and a second dielectric layer located on the second gate are formed on the second well region;

[0006] forming a first anti-reflection coating, wherein the first anti-reflection coating fills a gap between the first gate and the second gate and covers the first dielectric layer and the second dielectric layer;

[0007] Performing a first etching process to etch the first anti-reflection coating and the second dielectric layer of the second well region, so that a top surface of the second dielectric layer is lower than a top surface of the first dielectric layer and a first opening is formed, wherein the first opening penetrates the first anti-reflection coating and exposes a substrate surface of the second well region;

[0008] A second etching process is performed to form germanium silicon trenches in the first well region on both sides of the first gate, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer.

[0009] Optionally, performing the first etching process includes:

[0010] Performing a first sub-etching process to etch the first anti-reflection coating and the second dielectric layer in the second well region to form a first opening, wherein the first opening extends from a surface of the first anti-reflection coating to within the first anti-reflection coating, the first opening exposes the second dielectric layer, and a top surface of the second dielectric layer is lower than a top surface of the first dielectric layer;

[0011] A second sub-etching process is performed to continue etching the first anti-reflection coating of the second well region to extend the depth of the first opening, the first opening penetrates the first anti-reflection coating and exposes the substrate surface of the second well region, and the second dielectric layer is etched to reach a predetermined height.

[0012] Optionally, the etching gas of the first sub-etching process is a fluorine-containing gas.

[0013] Optionally, the first sub-etching process has the same etching selectivity ratio for the first anti-reflective coating layer and the second dielectric layer.

[0014] Optionally, the etching gas of the second sub-etching process is an oxygen-containing gas.

[0015] Optionally, in the second sub-etching process, an etching selectivity ratio between the first anti-reflective coating layer and the second dielectric layer is greater than 10:1.

[0016] Optionally, before performing the first sub-etching process, the method further includes:

[0017] forming a first photoresist layer, wherein the first photoresist layer covers the first anti-reflective coating layer;

[0018] A first photolithography process is performed to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the first anti-reflective coating layer of the second well region.

[0019] Optionally, after performing the first etching process, an ion implantation process is performed in the substrate of the first opening to form a first extension region in the second well region on both sides of the second gate.

[0020] Optionally, before performing the second etching process, the method includes:

[0021] forming a second extension region, wherein the second extension region is located in the first well region on both sides of the first gate;

[0022] forming a protective layer, wherein the protective layer covers the first dielectric layer, the second dielectric layer, the sidewall of the first gate, the sidewall of the second gate, the substrate of the first well region, and the substrate of the second well region;

[0023] forming a second anti-reflection coating, wherein the second anti-reflection coating covers the protective layer;

[0024] forming a third photoresist layer, wherein the third photoresist layer covers the second anti-reflective coating layer;

[0025] A third photolithography process is performed to form a patterned third photoresist layer, wherein the patterned third photoresist layer exposes the second anti-reflective coating layer of the first well region.

[0026] Based on the same inventive concept, the present invention further provides a CMOS device, which is prepared by using any of the above-mentioned methods for forming a CMOS device.

[0027] In the method for forming a CMOS device provided by the present invention, a first etching process is first performed to etch the first anti-reflection coating and the second dielectric layer of the second well region, so that the top surface of the second dielectric layer is lower than the top surface of the first dielectric layer and a first opening is formed, the first opening penetrates the first anti-reflection coating and exposes the substrate surface of the second well region; then a second etching process is performed to form a germanium silicon trench in the first well region on both sides of the first gate and the first dielectric layer is etched at the same time, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer. In the first etching process before the second well region forms the first extension region, the present invention etches the second dielectric layer in advance to the height of the first dielectric layer after being etched when the germanium silicon trench is formed, and then when the germanium silicon trench is formed, the height of the first dielectric layer after being etched is the same as the height of the second dielectric layer. The first gate structure includes the first gate and the first dielectric layer, and the second gate structure includes the second gate and the second dielectric layer, so the height of the first gate structure and the second gate structure are the same. In this way, the problem of the height difference of the gate structure on the first well region and the second well region is solved, that is, the height difference of the gate structure of the PMOS device and the NMOS device is reduced, and no additional process is required, thereby reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0029] Figure 1 It is a flow chart of a method for forming a CMOS device according to an embodiment of the present invention.

[0030] Figures 2 to 11 It is a schematic diagram of the structure corresponding to the steps of the method for forming a CMOS device according to an embodiment of the present invention.

[0031] In the attached figure:

[0032] 10-substrate; 11-shallow trench isolation structure; 12a-first well region; 12b-second well region; 13-gate dielectric layer; 14-barrier layer; 15a-first gate; 15b-second gate; 16-silicon nitride layer; 17a-first dielectric layer; 17b-second dielectric layer; 18-sidewall; 19-first anti-reflective coating; 19a-first opening; 20-first photoresist layer; 20a-patterned first photoresist layer; 21a-first extension region; 21b-second extension region; 22-protective layer; 23-second anti-reflective coating; 23a-second opening; 24-patterned third photoresist layer; 25-SiGe trench; 25a-SiGe stress layer. DETAILED DESCRIPTION

[0033] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0034] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] Figure 1FIG. 1 is a flow chart of a method for forming a CMOS device according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a CMOS device, including:

[0036] Step S10, providing a substrate, wherein the substrate includes a first well region and a second well region, wherein a first gate and a first dielectric layer located on the first gate are formed on the first well region, and a second gate and a second dielectric layer located on the second gate are formed on the second well region;

[0037] Step S20, forming a first anti-reflection coating, wherein the first anti-reflection coating fills the gap between the first gate and the second gate and covers the first dielectric layer and the second dielectric layer;

[0038] Step S30, performing a first etching process to etch the first anti-reflection coating and the second dielectric layer of the second well region, so that the top surface of the second dielectric layer is lower than the top surface of the first dielectric layer and a first opening is formed, wherein the first opening penetrates the first anti-reflection coating and exposes the substrate surface of the second well region;

[0039] Step S40 , performing a second etching process to form germanium silicon trenches in the first well region on both sides of the first gate, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer.

[0040] Figures 2 to 9 1 is a schematic diagram of the structure corresponding to the steps of the method for forming a CMOS device according to an embodiment of the present invention. Figures 2 to 9 The specific embodiments of the present invention are described in detail.

[0041] like Figure 2As shown, a substrate 10 is provided. The substrate 10 can be made of single crystal silicon or polycrystalline silicon, or semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or a composite structure such as silicon on insulator. Those skilled in the art can select the type of the semiconductor substrate according to the semiconductor device formed on the semiconductor substrate, so the type of the semiconductor substrate should not limit the protection scope of the present invention. The substrate 10 includes a first well region 12a and a second well region 12b. The doping type of the first well region 12a is N-type, that is, N-well, for forming a PMOS device. The doping type of the second well region 12b is P-type, that is, P-well, for forming an NMOS device. The adjacent first well region 12a and the second well region 12b are isolated by a shallow trench isolation structure 11. A first gate 15a and a first dielectric layer 17a located on the first gate 15a are formed on the first well region 12a. A gate dielectric layer 13 and a barrier layer 14 are also formed between the first gate 15a and the first well region 12a. The material of the gate dielectric layer 13 includes one or a combination of an oxide layer and a hafnium oxide layer. The hafnium oxide material can effectively improve the gate leakage current due to its high dielectric constant. The oxide layer can be formed by a thermal oxidation process and the hafnium oxide layer can be formed by an atomic layer deposition process. In order to prevent the metal ions and hafnium ions in the hafnium oxide from entering the first gate 15a, a barrier layer 14 is formed on the gate dielectric layer 13. The material of the barrier layer 14 is, for example, titanium nitride. A silicon nitride layer 16 and a first dielectric layer 17a are also formed on the first gate 15a. The material of the first dielectric layer 17a is silicon oxide. The first gate structure includes a gate dielectric layer 13, a barrier layer 14, a first gate 15a, a silicon nitride layer 16 and a first dielectric layer 17a. A second gate 15b and a second dielectric layer 17b located on the second gate 15b are formed on the second well region 12a. A gate dielectric layer 13 and a barrier layer 14 are also formed between the second gate 15b and the second well region 12a. A silicon nitride layer 16 and a second dielectric layer 17b are also formed on the second gate 15b, and the material of the second dielectric layer 17b is silicon oxide. The second gate structure includes a gate dielectric layer 13, a barrier layer 14, a second gate 15b, a silicon nitride layer 16 and a second dielectric layer 17b. Sidewalls 18 are also formed on the sidewalls of the first gate 15a and the second gate 15b.

[0042] Please continue to refer to Figure 2 , forming a first anti-reflection coating 19, wherein the first anti-reflection coating 19 fills the gap between the first gate 15a and the second gate 15b and covers the first dielectric layer 17a and the second dielectric layer 17b.

[0043] Please continue to refer to Figure 2 , a first photoresist layer 20 is formed, wherein the first photoresist layer 20 covers the first anti-reflective coating layer 19 .

[0044] like Figure 3 As shown, a first photolithography process is performed to form a patterned first photoresist layer 20 a , wherein the patterned first photoresist layer 20 a exposes the first anti-reflective coating layer 19 of the second well region 12 b .

[0045] like Figure 4 and Figure 5 As shown, a first etching process is performed to etch the first anti-reflection coating 19 and the second dielectric layer 17b of the second well region 12b, so that the top surface of the second dielectric layer 17b is lower than the top surface of the first dielectric layer 17a and a first opening 19a is formed, and the first opening 19a penetrates the first anti-reflection coating 19 and exposes the substrate surface of the second well region 12b. The first etching process includes a first sub-etching process and a second sub-etching process.

[0046] like Figure 4 As shown, a first sub-etching process is performed, using the patterned first photoresist layer 20a as a mask, to etch the first anti-reflective coating 19, the second dielectric layer 17b and the sidewall 18 of the second well region 12b to form a first opening 19a, wherein the first opening 19a extends from the surface of the first anti-reflective coating 19 to the inside of the first anti-reflective coating 19, the first opening 19a leaks out of the second dielectric layer 17b and the top surface of the second dielectric layer 17b is lower than the top surface of the first dielectric layer 17a. The first sub-etching process is a low etching selectivity process. The first sub-etching process has the same etching selectivity for the first anti-reflective coating 19, the second dielectric layer 17b and the sidewall 18. The etching gas of the first sub-etching process is a fluorine-containing gas, such as CF4.

[0047] like Figure 5As shown, a second sub-etching process is performed, using the patterned first photoresist layer 20a as a mask, and continuing to etch the first anti-reflective coating 19 of the second well region 12b to extend the depth of the first opening 19a, the first opening 19a penetrates the first anti-reflective coating 19 and exposes the substrate surface of the second well region 12b, and at the same time etches the second dielectric layer 17b to reach a predetermined height. The second sub-etching process is a high etching selectivity process. In the second sub-etching process, the etching selectivity of the first anti-reflective coating and the second dielectric layer is greater than 10:1. The second sub-etching process has the same etching selectivity for the sidewall 18 and the second dielectric layer 17b. The etching gas of the second sub-etching process is an oxygen-containing gas, such as one or more of oxygen and sulfur dioxide. The predetermined height of the second dielectric layer 17b is the height of the first dielectric layer 17a after the germanium silicon groove is formed, that is, in the first etching process, a first sub-etching process with a low etching selectivity is used in advance to etch the second dielectric layer 17b to a height substantially the same as the height of the first dielectric layer 17a after the germanium silicon groove is formed, and in the second sub-etching process with a high etching selectivity, the first anti-reflective coating 19 is mainly etched, and the second dielectric layer 17b is also partially etched. After the second sub-etching process, the second dielectric layer 17b has the same height as the first dielectric layer 17a after the germanium silicon groove is formed.

[0048] like Figure 6 As shown, an ion implantation process is performed to form a first extension region 21a in the second well region 12b on both sides of the second gate 15b. That is, the first extension region 21a is located below the boundary of the second gate 15b and between the source and drain regions formed subsequently. The ion implantation process is, for example, an LDD (Lightly Doped Drain) process, and the first extension region 21a is a low-doped extension region.

[0049] like Figure 7 As shown, after the first extension region 21a is formed in the second well region 12b, the second extension region 21b is also formed in the first well region 12a. The method for forming the second extension region 21b includes: forming a second photoresist layer (not shown in the figure), performing a second photolithography process and a development process to expose the substrate surface of the first well region 12a, and then performing an LDD ion implantation process to form the second extension region 21b in the first well region 12a. Since there is no other etching process in the process of forming the second extension region 21b and the photolithography process does not react to the first dielectric layer 17a, the height of the first dielectric layer 17a is not affected.

[0050] like Figure 8As shown, after forming the first extension region 21a and the second extension region 21b, the second photoresist layer is removed. Then, a protective layer 22 is formed, and the protective layer 22 is used to protect the NMOS device region from being etched. The protective layer 22 covers the first dielectric layer 17a, the second dielectric layer 17b, the sidewall of the first gate structure, the sidewall of the second gate structure, the substrate of the first well region 12a, and the substrate of the second well region 12b. The material of the protective layer 22 is, for example, silicon nitride, and can be formed by a chemical vapor deposition process.

[0051] like Fig. 9 As shown, before performing the second etching process, it includes: forming a second anti-reflection coating 23, wherein the second anti-reflection coating 23 covers the protective layer 22. Then forming a third photoresist layer, wherein the third photoresist layer covers the new second anti-reflection coating 23. Performing a second photolithography process to form a patterned third photoresist layer 24, wherein the patterned third photoresist layer 24 exposes the second anti-reflection coating 23 of the first well region 12a.

[0052] like Fig. 9 and Fig.10 As shown, a second etching process is performed to form a germanium silicon groove 25 in the first well region on both sides of the first gate, and the top surface of the first dielectric layer 17a is flush with the top surface of the second dielectric layer 17b. In order to enhance the stress effect of germanium silicon, the groove is usually sigma-shaped (∑-shaped). The second etching process includes a third sub-etching process, a fourth sub-etching process and a fifth sub-etching process.

[0053] like Fig. 9 As shown, a third sub-etching process is performed, and the patterned third photoresist layer 24 is used as a mask to etch the second anti-reflective coating 23 on the first well region 12a to form a second opening 23a, and the second opening 23a penetrates the second anti-reflective coating 23 on the first well region 12a to expose the protective layer 22. The etching process is a high etching selectivity process, which is used to etch the second anti-reflective coating 23. In the third sub-etching process, the etching selectivity of the second anti-reflective coating 23 and the protective layer 22 is greater than 10:1. The etching gas of the third sub-etching process is an oxygen-containing gas, such as one or more of oxygen and sulfur dioxide. A fourth sub-etching process is performed to etch the protective layer 22 on the top of the first gate structure and the protective layer 22 on the surface of the substrate. The fourth sub-etching process is, for example, dry etching, and the etching gas is, for example, a fluorine-containing gas. After the fourth sub-etching process is performed, the top surface of the first dielectric layer 17a and the surface of the substrate 10 are exposed.

[0054] like Fig.10As shown, the fifth sub-etching process is performed, and the substrate 10 of the first well region 12a is etched with the patterned third photoresist layer 24 as a mask, and a germanium silicon groove 25 is formed in the first well region 12a on both sides of the first gate 15a. The fifth sub-etching process includes a dry etching process and a wet etching process. The dry etching process and the wet etching process for forming the germanium silicon groove 25 are known to those skilled in the art and will not be described here. When the fifth sub-etching process etches the substrate 10, the first dielectric layer 17a is also etched. Therefore, after the germanium silicon groove 25 is formed, the height of the first dielectric layer 17a is also reduced. After the germanium silicon groove 25 is formed, the height of the first dielectric layer 17a is the same as the height of the second dielectric layer 17b. That is, the height of the first gate structure is the same as the height of the second gate structure.

[0055] like Fig.11 As shown, a germanium-silicon stress layer 25a is formed, and the germanium-silicon stress layer 25a is located in the germanium-silicon trench 25. Specifically, germanium-silicon is selectively epitaxially grown in the germanium-silicon trench 25, and a cap layer is formed on the top of the germanium-silicon. The germanium-silicon in the germanium-silicon trench 25 and the cap layer on the top of the germanium-silicon together constitute the germanium-silicon stress layer 25a. The germanium-silicon stress layer 25a can change the key parameters such as the band structure, carrier mobility and light absorption coefficient in the PMOS device by applying compressive stress, thereby improving the performance and stability of the PMOS device.

[0056] like Fig.11As shown, this embodiment also provides a CMOS device, which is prepared by the formation method of the CMOS device described in any of the above items. The CMOS device includes a substrate 10 and a first well region 12a and a second well region 12b located in the substrate 10. The doping type of the first well region 12a is N-type, that is, N-well, for forming a PMOS device. The doping type of the second well region 12b is P-type, that is, P-well, for forming an NMOS device. The adjacent first well region 12a and the second well region 12b are isolated by a shallow trench isolation structure 11. A first gate 15a and a first dielectric layer 17a located on the first gate 15a are formed on the first well region 12a. A gate dielectric layer 13 and a barrier layer 14 are also formed between the first gate 15a and the first well region 12a. The material of the gate dielectric layer 13 includes one or a combination of an oxide layer and a hafnium oxide layer. The hafnium oxide material can effectively improve the gate leakage current due to its high dielectric constant. The oxide layer can be formed by a thermal oxidation process and the hafnium oxide layer can be formed by an atomic layer deposition process. In order to prevent the metal ions hafnium ions in hafnium oxide from entering the first gate 15a, a barrier layer 14 is formed on the gate dielectric layer 13, and the material of the barrier layer 14 is, for example, titanium nitride. A silicon nitride layer 16 and a first dielectric layer 17a are also formed on the first gate 15a, and the material of the first dielectric layer 17a is silicon oxide. A second gate 15b and a second dielectric layer 17b located on the second gate 15b are formed on the second well region 12a. A gate dielectric layer 13 and a barrier layer 14 are also formed between the second gate 15b and the second well region 12a. A silicon nitride layer 16 and a second dielectric layer 17b are also formed on the second gate 15b, and the material of the second dielectric layer 17b is silicon oxide. Sidewalls 18 are also formed on the side walls of the first gate 15a and the second gate 15b. A germanium silicon stress layer 25a is formed in the first well region 12a, and the germanium silicon stress layer 25a is located in the first well region 12a on both sides of the first gate 15a. A first extension region 21a is formed in the second well region 12b, and a second extension region 21b is formed in the first well region 12a. The first dielectric layer 17a on the first gate 15a and the second dielectric layer 17b on the second gate 15b have the same height. In this embodiment, in the first etching process for forming the first opening of the first extension region, a first sub-etching process with a low etching selectivity is used in advance to etch the second dielectric layer 17b to a height substantially the same as the height of the first dielectric layer 17a after the germanium silicon trench is formed. In the second sub-etching process with a high etching selectivity, the first anti-reflective coating 19 is mainly etched, and the second dielectric layer 17b is also partially etched. After the second sub-etching process, the second dielectric layer 17b has the same height as the first dielectric layer 17a after the germanium silicon trench is formed. After forming the germanium silicon stress layer 25a of the first well region 12a, the first dielectric layer 17a has the same height as the second dielectric layer 17b, that is, the gate heights of the PMOS device and the NMOS device are the same.The problem of etching the gate heights of the PMOS device and the NMOS device to be consistent through multiple process steps such as deposition process, chemical mechanical polishing process and etching process after forming the germanium silicon stress layer 25a in the prior art is avoided. Since the first opening is opened in the normal process flow before the first extension region is formed, the height difference of the gate structure of the PMOS device and the NMOS device is reduced in this embodiment without adding additional processes, thereby reducing the production cost.

[0057] In summary, in the method for forming a CMOS device provided by an embodiment of the present invention, a first etching process is first performed to etch the first anti-reflective coating and the second dielectric layer of the second well region, so that the top surface of the second dielectric layer is lower than the top surface of the first dielectric layer and a first opening is formed, the first opening penetrates the first anti-reflective coating and exposes the substrate surface of the second well region; then a second etching process is performed to form a germanium silicon trench in the first well region on both sides of the first gate and the first dielectric layer is etched at the same time, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer. In the first etching process before the second well region forms the first extension region, the present invention etches the second dielectric layer in advance to the height of the first dielectric layer after being etched when the germanium silicon trench is formed, and then when the germanium silicon trench is formed, the height of the first dielectric layer after being etched is the same as the height of the second dielectric layer. The first gate structure includes a first gate and a first dielectric layer, and the second gate structure includes a second gate and a second dielectric layer, so the heights of the first gate structure and the second gate structure are the same. In this way, the problem of the height difference of the gate structures on the first well region and the second well region is solved, that is, the height difference of the gate structures of the PMOS device and the NMOS device is reduced, and no additional process is required, thereby reducing production costs.

[0058] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a CMOS device, characterized in that: include: A substrate is provided, wherein the substrate comprises a first well region and a second well region, wherein a first gate and a first dielectric layer located on the first gate are formed on the first well region, and a second gate and a second dielectric layer located on the second gate are formed on the second well region; forming a first anti-reflection coating, wherein the first anti-reflection coating fills a gap between the first gate and the second gate and covers the first dielectric layer and the second dielectric layer; Performing a first etching process to etch the first anti-reflection coating and the second dielectric layer of the second well region, so that a top surface of the second dielectric layer is lower than a top surface of the first dielectric layer and a first opening is formed, wherein the first opening penetrates the first anti-reflection coating and exposes a substrate surface of the second well region; A second etching process is performed to form germanium silicon trenches in the first well region on both sides of the first gate, and the top surface of the first dielectric layer is flush with the top surface of the second dielectric layer.

2. The method for forming a CMOS device according to claim 1, wherein: Performing the first etching process includes: Performing a first sub-etching process to etch the first anti-reflection coating and the second dielectric layer in the second well region to form a first opening, wherein the first opening extends from a surface of the first anti-reflection coating to within the first anti-reflection coating, the first opening exposes the second dielectric layer, and a top surface of the second dielectric layer is lower than a top surface of the first dielectric layer; A second sub-etching process is performed to continue etching the first anti-reflection coating of the second well region to extend the depth of the first opening, the first opening penetrates the first anti-reflection coating and exposes the substrate surface of the second well region, and the second dielectric layer is etched to reach a predetermined height.

3. The method for forming a CMOS device according to claim 2, wherein: The etching gas of the first sub-etching process is a fluorine-containing gas.

4. The method for forming a CMOS device according to claim 3, wherein: The first sub-etching process has the same etching selectivity ratio for the first anti-reflection coating layer and the second dielectric layer.

5. The method for forming a CMOS device according to claim 2, wherein: The etching gas of the second sub-etching process is an oxygen-containing gas.

6. The method for forming a CMOS device according to claim 5, characterized in that: In the second sub-etching process, an etching selectivity ratio between the first anti-reflective coating layer and the second dielectric layer is greater than 10:

1.

7. The method for forming a CMOS device according to claim 2, wherein: Before performing the first sub-etching process, the method further includes: forming a first photoresist layer, wherein the first photoresist layer covers the first anti-reflective coating layer; A first photolithography process is performed to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the first anti-reflective coating layer of the second well region.

8. The method for forming a CMOS device according to claim 1, wherein: After performing the first etching process, an ion implantation process is performed in the substrate of the first opening to form a first extension region in the second well region on both sides of the second gate.

9. The method for forming a CMOS device according to claim 1, wherein: Before performing the second etching process, the method comprises: forming a second extension region, wherein the second extension region is located in the first well region on both sides of the first gate; forming a protective layer, wherein the protective layer covers the first dielectric layer, the second dielectric layer, the sidewall of the first gate, the sidewall of the second gate, the substrate of the first well region, and the substrate of the second well region; forming a second anti-reflection coating, wherein the second anti-reflection coating covers the protective layer; forming a third photoresist layer, wherein the third photoresist layer covers the second anti-reflective coating layer; A third photolithography process is performed to form a patterned third photoresist layer, wherein the patterned third photoresist layer exposes the second anti-reflective coating layer of the first well region.

10. A CMOS device, characterized in that: The CMOS device is manufactured by the method for forming the CMOS device according to any one of claims 1 to 9.

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