Data reuse cache

Abstract

Data reuse caching techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load storage unit for processing by the execution unit, and is also stored to a data reuse cache communicatively coupled between the load storage unit and the execution unit. Upon receiving a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. patent application serial number 17 / 955,618, filed on September 22, 2022, and entitled “Data Reuse Cache,” the entire disclosure of which is hereby incorporated by reference herein in its entirety. Background Art

[0003] Processor units such as central processing units, parallel processors, graphics processing units, etc. are tasked with processing ever-increasing amounts of data. Access to this data is an important factor in the speed at which the processor unit can process the data. To address this issue, cache systems are employed to speed up this access. However, conventional techniques for implementing cache systems face various challenges, including latency, throughput, trade-offs between size and speed, etc. These challenges hinder the operation of processor units in conventional real-world scenarios, the impact of which is exacerbated by the ever-increasing amounts of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The detailed description is given with reference to the accompanying drawings.

[0005] Figure 1 is a block diagram of a non-limiting exemplary system configured to employ data reuse caching techniques.

[0006] Figure 2 is a block diagram of a non-limiting exemplary system configured to employ data reuse cache technology in a multi-core processor architecture, wherein Figure 1 The level 1 cache is implemented as a split cache.

[0007] Figure 3 is a block diagram of a non-limiting exemplary system configured to employ a data reuse cache technique to populate a data reuse cache using load responses as virtual memory addresses.

[0008] Figure 4 is a block diagram of a non-limiting exemplary system configured to employ filter modules and filters as part of a data reuse cache technique to control access to a data reuse cache.

[0009] Figure 5 is a flow chart depicting a procedure in a non-limiting exemplary implementation of the operation of a data reuse cache. DETAILED DESCRIPTION

[0010] Overview

[0011] The efficiency of data access by a processor unit has a significant impact on the speed and operation of the processor unit as a whole. The efficiencies gained in providing such access capabilities increase the speed of operation of the processor unit, reduce power consumption, conserve bandwidth, and support a variety of other technical advantages in utilizing the processor unit and devices employing the processor unit.

[0012] Thus, data reuse cache techniques, systems, and devices are described that further increase the technical advantages obtained by using caches by a processor unit. In one example, a processor unit is implemented in hardware, for example, as a central processing unit, a graphics processing unit, a parallel processor, etc. The processor unit can be configured to include multiple cores that include cache hierarchies that store data within the cores, cache hierarchies that are shared between cores, and the like.

[0013] For example, a core includes an execution unit, a load-store unit, and one or more cache levels. The execution unit is configured to issue instructions to process data using corresponding operations. The load-store unit is configured to load data to be processed by the execution unit and store the data back to the memory. The cache levels are configured to balance size and speed through successively larger levels to improve data access efficiency. The configuration of the cache levels takes advantage of various locality factors. Spatial locality is used to improve operations in the case of requesting data that is physically stored near data that was the object of a previous request. Temporal locality is used to address situations where data that has already been requested will be requested again.

[0014] In cache operations, a "hit" occurs on a cache level when the desired data that is the subject of a load operation is available via the cache level, while a "miss" occurs when the desired data is not available via the cache level. When multiple cache levels are employed, a request proceeds through successive cache levels until the data is located. However, for this reason, frequent cache misses have the adverse effect of reducing or even eliminating the performance gains supported by the cache level as part of the processor unit.

[0015] To address these issues, a data reuse cache is implemented as part of a processor unit between an execution unit and a load-store unit. For example, the data reuse cache is physically closer to the execution unit than the load-store unit or cache system, for example, with a 1-level cache, a 2-level cache, and the like. In one example, the data reuse cache is implemented separately for data reuse for load responses including data obtained by the load-store unit. In addition, in one example, the data reuse cache is configured to be accessed in parallel with the cache system, such as a 1-level data cache.

[0016] For example, a data reuse cache is loaded based on load responses from a load store unit. In real-world scenarios, data loaded in response to a load instruction is often reused by itself or other instructions in rapid succession before being kept dormant. This brings data closer to the execution units for faster reuse and reduces the computational cost of reloading the data. In practice, the four cycles typically used to access data from a level 1 cache are reduced to two cycles to access data from a data reuse cache, improving processor unit and device operation overall.

[0017] In addition, as described above, cache misses introduce additional latency, resulting in reduced advantages obtained by including a cache. For example, configuring a data reuse cache to a smaller size to increase speed may increase miss rates, thereby posing challenges. To address these issues, filter techniques may be employed (e.g., by an execution unit) to filter instructions based on the likelihood that the instruction will result in a hit or miss in the data reuse cache. In this way, filters are used to filter out load instructions that consistently miss the data reuse cache, so that these load instructions are passed directly to the cache hierarchy through the load storage unit without encountering performance penalties due to the inclusion of a data reuse cache. Various other examples are also contemplated, which are described in the discussion below and shown using corresponding figures.

[0018] In some aspects, the technology described herein relates to a method that includes generating a load instruction at an execution unit in response to a load instruction, loading data from a load response obtained from a load-store unit for processing by the execution unit, and storing the data from the load response in a data reuse cache communicatively coupled between the load-store unit and the execution unit, generating a subsequent load instruction at the execution unit for the data, and loading the data from the data reuse cache in response to the subsequent load instruction for processing by the execution unit.

[0019] In some aspects, techniques described herein relate to a method in which loading data includes loading data from a hierarchy of a cache system by a load store unit.

[0020] In some aspects, techniques described herein relate to a method in which loading data from a load response is performed from a hierarchy of a cache system in four cycles, while loading data from a data reuse cache is performed in two cycles.

[0021] In some aspects, the techniques described herein relate to a method that also includes generating a subsequent load instruction and routing the subsequent load instruction to be serviced by a load-store unit based on detecting that the subsequent load instruction spans more than one cache line of a data reuse cache.

[0022] In some aspects, the techniques described herein relate to a method that also includes generating a subsequent load instruction and triggering a resynchronization operation based on detecting that data that is a subject of the subsequent load instruction is stale.

[0023] In some aspects, the technology described herein relates to a method that also includes self-broadcasting a data reuse cache response including data, the self-broadcasting using a broadcast port of a load store unit.

[0024] In some aspects, the techniques described herein relate to a method that also includes controlling, using a filter, whether to allow or restrict access to a data reuse cache by subsequent load instructions.

[0025] In some aspects, the techniques described herein relate to a method in which a filter indicates the likelihood of a subsequent load instruction hitting or missing a data reuse cache.

[0026] In some aspects, the technology described herein relates to a method, wherein a subsequent load instruction is included in a plurality of load instructions, and a filter maintains a plurality of hit counters for the plurality of load instructions, respectively, and control is based on values ​​of the plurality of hit counters.

[0027] In some aspects, the technology described herein relates to a processor unit comprising: a cache system comprising multiple cache hierarchies; a load-store unit configured to generate load responses from the cache system for processing by an execution unit; a data reuse cache communicatively coupled between the execution unit and the load-store unit, the data reuse cache configured to store data for the load responses; and an execution unit configured to filter load instructions for accessing the data reuse cache based on respective probabilities that the load instructions result in a hit or a miss, respectively, to the data reuse cache.

[0028] In some aspects, the techniques described herein relate to a processor unit in which a data reuse cache is physically closer to execution units on the integrated circuit than a load store unit or cache system.

[0029] In some aspects, the techniques described herein relate to a processor unit in which the corresponding probabilities are based on values ​​of hit counters maintained respectively for load instructions, wherein the values ​​of the hit counters respectively indicate the number of times the load instructions hit from a data reuse cache.

[0030] In some aspects, techniques described herein relate to a processor unit in which values ​​of hit counters respectively indicate a number of times a load instruction from a data reuse cache hits within a window defining a threshold number of hits.

[0031] In some aspects, the techniques described herein relate to a processor unit in which an execution unit is configured to control access by generating a corresponding probability that a corresponding load instruction of a load instruction does not result in a hit, and in response to the generating, restricting access to a data reuse cache and allowing direct access to multiple cache levels.

[0032] In some aspects, the technology described herein relates to a processor unit comprising: a cache system comprising a cache hierarchy; an execution unit configured to access a data reuse cache in parallel with access to the cache hierarchy of the cache system through a load-store unit, the data reuse cache being communicatively coupled between the execution unit and the load-store unit; and a load-store unit configured to: in response to a load instruction received from the execution unit, generate a load response from the cache system, load data from the load response to the execution unit for processing, and store the data from the load response to the data reuse cache.

[0033] In some aspects, the techniques described herein relate to a processor unit in which a load instruction is included as part of a plurality of load instructions, and an execution unit is configured to filter the plurality of load instructions based on respective probabilities of a hit or miss on a data reuse cache to control access to the data reuse cache.

[0034] In some aspects, the techniques described herein relate to a processor unit in which respective probabilities are based on values ​​of hit counters maintained for a plurality of load instructions, respectively.

[0035] In some aspects, the techniques described herein relate to a processor unit in which values ​​of a hit counter respectively indicate a number of times a plurality of load instructions hit from a data reuse cache.

[0036] In some aspects, the techniques described herein relate to a processor unit in which the cache hierarchy is a level 1 data cache.

[0037] In some aspects, the techniques described herein relate to a processor unit in which a load instruction is included as part of a plurality of load instructions, and an execution unit is configured to control access by generating a respective probability that a respective load instruction of the plurality of load instructions does not result in a hit, and in response to the generating, restricting access to a data reuse cache and allowing direct access to a cache hierarchy.

[0038] Figure 11 is a block diagram of a non-limiting exemplary system 100 configured to employ data reuse caching technology. System 100 includes a device 102 having a processor unit 104, a physical volatile memory 106 (e.g., a random access memory) and a permanent storage device 108 (e.g., a hard drive). Device 102 can be configured in a variety of ways. As examples and not limitations, examples include computing devices, servers, mobile devices (e.g., wearable devices, mobile phones, tablet computers, laptops), processors (e.g., graphics processing units, central processing units, and accelerators), digital signal processors, disk array controllers, hard drive host adapters, memory cards, solid-state drives, wireless communication hardware connections, Ethernet hardware connections, switches, bridges, network interface controllers, and other device configurations. It should be understood that in various specific implementations, without departing from the spirit or scope of the described technology, device 102 is configured as any one or more of those devices listed just above and / or various other devices.

[0039] Processor unit 104 includes execution unit 110, load store unit 112, and cache system 114. Execution unit 110 represents the functionality of processor unit 104 implemented in hardware, which performs operations based on instructions received by executing software, for example. Execution unit 110 includes registers 116, which are configured to hold data processed by execution unit 110, for example, for arithmetic and logical operations.

[0040] The load store unit 112 represents the functionality of the processor unit 104 to execute load and store instructions. Load instructions and corresponding operations involve loading data from the cache system 114, the physical volatile memory 106, and / or the permanent storage 108 into the registers 116 of the execution unit 110 for processing. Store instructions and corresponding operations include storing data from the registers 116 (e.g., after being processed by the execution unit 110) back to the cache system 114, the physical volatile memory 106, and / or the permanent storage 108.

[0041] For example, the load store unit 112 is configured to support the use of virtual memory by translating virtual memory addresses used by software into physical memory addresses. Virtual memory is a technique for managing the use of shared physical memory. Virtual memory supports a variety of different functions. Examples of such functions include extending the amount of memory available to applications beyond the amount of memory actually available in physical memory, offloading memory management from applications and the operating system, using various different types of memory without the knowledge of the application, supporting memory optimization, addressing memory fragmentation, etc., as described in reference to Figure 4 Further described.

[0042] Cache system 114 includes a plurality of cache tiers 118, examples of which are shown as 1-tier cache 120(1) through "N"-tier cache 120(N). The configuration of cache tiers 118 is used to take advantage of various locality factors. Spatial locality is used to improve operation in situations where data is requested that is physically stored near data that was the subject of a previous request. Temporal locality is used to address situations where data that has already been requested will be requested again.

[0043] In cache operations, a "hit" occurs to a cache level when the data that is the subject of a load operation is available via the cache level, while a "miss" occurs when the desired data is not available via the cache level. When multiple cache levels are employed, a request proceeds through successive cache levels 118 until the data is located. The cache system 114 may be configured in a variety of ways (e.g., in hardware) to handle a variety of processor unit 104 configurations, such as a central processing unit cache, a graphics processing unit cache, a parallel processor unit cache, a digital signal processor cache, etc.

[0044] The processor unit 104 also includes a data reuse cache 122. The data reuse cache 122 is physically located on the processor unit 104 between the load store unit 112 and the execution unit 110 (e.g., using hardware circuitry on an integrated circuit). The data reuse cache 122 is configured to take advantage of scenarios in which data loaded by a load instruction of the load store unit 112 is accessed again in a sequential manner (e.g., by itself or by other instructions). Keeping this data close to the execution unit 110 for faster reuse reduces the cost incurred by loading data from a cache hierarchy 118, such as level 1 cache 120(1). In one example, the data reuse cache 122 can be accessed in parallel with the cache system 114 (e.g., with level 1 data cache) via the load store unit 112, as described with respect to FIG. Figure 2 Further described.

[0045] The data reuse cache 122 may be configured to be "filled" based on load responses generated by the load-store unit 112. In one example, the data reuse cache 122 is configured solely for data reuse. Any load response from the load-store unit 112 may be used to fill the data reuse cache 122, for example, from the cache hierarchy 118 of the cache system 114, the physical volatile memory 106, the permanent storage device 108, etc. In one specific implementation, complex memory data communications are delegated to the load-store unit 112, thereby improving operational efficiency, as described below with respect to Figure 4As further described, in this manner, the likelihood that data stored in the data reuse cache 122 is relevant to subsequent load instructions is increased, thereby reducing the probability of a cache miss.

[0046] In another example of a technique that may be used to address these issues, the execution unit 110 manages load operations using the filter module 124 and the filter 126. The filter module 124 uses the filter 126 to control access of the load operations to the data reuse cache 122. For example, load operations that have a probability of causing a hit in the data reuse cache 122 that is less than a threshold amount are restricted from accessing the data reuse cache 122. Instead, these load operations are directed directly to the cache hierarchy 118 through the load store unit 112.

[0047] Thus, the performance penalty encountered in cache misses of the data reuse cache 122 is avoided, thereby enabling implementation as a smaller cache with improved access efficiency (i.e., speed). Other examples include the data reuse cache 122 using virtual memory addresses, using self-broadcasts to wake up dependent operations instead of conventional broadcasts, and utilizing logic in the load store unit 112 to verify data correctness, such as ordering violations and data integrity. Further discussion of these and other examples is included in the following discussion and is shown in the corresponding figures.

[0048] Figure 2 is a block diagram of a non-limiting exemplary system 200 configured to employ data reuse cache technology in a multi-core processor architecture, wherein Figure 1 The L1 cache 120(1) is implemented as a split cache. The processor unit 104 is configured as a single integrated circuit having multiple cores, illustrated as a first core 202 through an "N" core 204. The first core 202 is shown in greater detail and includes the execution unit 110 and the load store unit 112 as previously described.

[0049] The cache system 114 is illustrated as having a level 1 cache 120(1) and a level 2 cache 210 included as part of the first core 202. The first core 202 and the "N" core 204 share a level 3 cache 212. Other examples are also contemplated, such as where the first core 202 and the "N" core 204 share a level 2 cache 210, including a level 4 cache, etc.

[0050] The level 1 cache 120(1) is implemented using a split cache architecture that is maintained as two independent level 1 caches, i.e., the level 1 instruction cache 206 and the level 1 data cache 208. This architecture supports a number of technical features, including parallel operation, where data is read from the level 1 data cache 208 in parallel with instructions being loaded from the level 1 instruction cache 206.

[0051] As previously described, the data reuse cache 122 is physically located between the execution unit 110 and the load-store unit 112, and is therefore physically closer to the execution unit 110 than the cache hierarchy of the cache system 114. In this example, the data reuse cache 122 can be accessed in parallel with the level 1 data cache 208 through the load-store unit 112. For example, in response to a "hit" to any cache hierarchy or other memory, the data reuse cache 122 is "filled" with the data transmitted in the load response, as further described with respect to the following discussion and corresponding figures. Various other examples are also contemplated.

[0052] Figure 3 is a block diagram of a non-limiting exemplary system 300 configured to employ a data reuse cache technique to populate a data reuse cache 122 using a load response from a load store unit as a virtual memory address. As shown in this example, a load instruction 302 is received by a load store unit 112 and used to access a cache system 114, such as a level 1 data cache 208. A load response 304 from the load store unit 112 is then returned (e.g., for loading into a register 116 of an execution unit 110), which is also used to populate the data reuse cache 122. In this manner, an existing load response bus from the load store unit 112 can also be used to populate the data reuse cache 122, thereby saving power and not using additional hardware circuitry. In one example, the cache line size is configured to match the width of these load response buses.

[0053] In one implementation, data may be accessed via the data reuse cache 122 in fewer cycles than the number of cycles used to access data via the corresponding cache level 118 of the cache system 114. Loading data from the level 1 data cache 208 to the execution unit 110 in response to the load instruction 302 is typically performed in four cycles. However, loading data from the data reuse cache 122 for processing by the execution unit 110 in response to a subsequent load instruction may be performed in two cycles.

[0054] The data reuse cache 122 is configured to utilize the virtual memory address 306 to locate the corresponding data within the data reuse cache 122. In some cases, the physical memory address of the load instruction is not available until the translation lookaside buffer (TLB) translation is performed by the load store unit 112. Therefore, the virtual memory address 306 is utilized using the corresponding tag 308 and data block 310, thereby improving efficiency.

[0055] In some cases, confusion may be encountered where multiple virtual memory addresses point to the same physical address location. In these cases, a load operation may miss in the data reuse cache 122, but the data is actually available at a different virtual memory address. Instead, these cases are serviced by the load-store unit 112, for example, as a reuse cache miss, and serviced in the level 1 cache 120(1) using physical tags. Additionally, in one embodiment, the data reuse cache 122 supports load operations that are aligned to cache line boundaries. Load operations that span more than one cache line may be treated as misses and instead involve routing to the load-store unit 112 to be serviced by the load-store unit, for example, to access other caches, physical memory, etc.

[0056] Figure 4 1 is a block diagram of a non-limiting exemplary system 400 configured to employ a filter module 124 and a filter 126 as part of a data reuse cache technique to control access to a data reuse cache 122. In this example, the filter module 124 is implemented as part of the execution unit 110, for example, by a scheduling unit. The filter module 124 is configured to remove and restrict (i.e., "filter out") access to the data reuse cache 122 by load instructions 302 based on the likelihood of causing a miss. Thus, the filtered out load instructions 302 bypass access to the filter module 124 and directly access the cache hierarchy 118 without incurring a performance penalty.

[0057] For example, the filter module 124 is configured to check the hit / miss indication of the tag 308 to train the filter 126. The filter 126 can be configured as a set associative structure indexed by a program counter (i.e., an instruction pointer), and a hashed version of the program counter serves as the tag 308. For example, once the first hit to the data reuse cache 122 is detected, an entry is allocated for the corresponding program counter. Each entry in the filter 126 uses a hit counter 402 on the window to track a value (e.g., the number of hits), such as a threshold number of lookups of the program counter. In one example, both counters are right-shifted when saturated.

[0058] The filter module 124 then determines whether to allow access or restrict access based on the filter 126. The filter module 124 allows program counters with a hit rate greater than a threshold amount (e.g., fifty percent) to access the data reuse cache 122. In a real-world scenario, this results in a reduction of misses to the data reuse cache 122 by more than 20 times, thereby allowing the data reuse cache 122 to be used.

[0059] Accesses to the data reuse cache 122 may be treated as fixed-cycle execution unit 110 operations. A selected load operation (e.g., an operation that is executed when an instruction or microinstruction {e.g., UOP} is scheduled in the scheduling unit) that has passed the scheduling time in the data reuse cache 122 causes the address generation unit to "self-broadcast" to wake up the dependent operations instead of waiting for the load store unit 112. To avoid adding an additional broadcast port for each address generation unit (which is an arithmetic logic unit used to calculate the address of a load or store microinstruction), the execution unit 110 opportunistically uses the broadcast port of the load store unit 112 to broadcast the data reuse cache 122 data response. In the event of a conflict between the level 1 cache 120 (1) data response and the data reuse cache 122 data response attempt broadcast in the same cycle, the level 1 cache 120 (1) is given priority and the access attempt to the data reuse cache 122 is discarded and treated as a data reuse cache miss instead.

[0060] When an access attempt to the data reuse cache 122 is restricted (i.e., filtered out), the access attempt (i.e., the corresponding load instruction) becomes eligible for level 1 cache 120(1) access by the load-store unit 112. Because the load-store unit 112 is tasked with waiting until it receives an indication of a hit or miss to the data reuse cache 122, these load operations may incur additional latency. Therefore, in some cases, to save power, the load-store unit 112 is configured not to read the data reuse cache 122 load accesses from the level 1 cache 120(1).

[0061] The load store unit 112 includes a data validation module 404, which represents functionality for managing techniques for facilitating data correctness of load responses. For example, the data validation module 404 is used to validate ordering violations and data integrity of hits from the data reuse cache 122. In addition, the data validation module 404 is configured to trigger a resynchronization operation when authorized, for example, when data in the data reuse cache 122 that is the subject of a load instruction is detected as stale.

[0062] The load store unit 112 may also be configured to perform the following functions to support the data reuse cache 122. To fill the data reuse cache 122, the load store unit 112 sends a load data size and waits for a load response from the level 1 cache 120(1) to the execution unit 110, as described above. In another example, a resynchronization operation is triggered for a store interlocked load operation that also hits the data reuse cache 122. In a further example, when a store operation is committed to the level 1 cache 120(1) (e.g., the level 1 data cache 208), an invalidation probe is sent to the data reuse cache 122, when the level 1 data cache 208 is evicted, an invalidation probe is sent to the data reuse cache 122, and so on.

[0063] In one example as described above, the data reuse cache 122 utilizes virtual memory addresses 306 rather than physical addresses. However, for this reason, L1 cache lines cannot be invalidated from the data reuse cache 122 using their physical addresses. To address this issue, in the first case, physical addresses are saved in the data reuse cache 122 rather than virtual addresses. In the second case, each data reuse cache line in the data reuse cache 122 is tagged with the way of its corresponding L1 line, and an L1 index is also included (e.g., using additional bits) to achieve similar functionality. This is due to the increased data storage device size in this example of the L1 cache compared to the data reuse cache 122, so the data reuse cache index bits are a subset of the L1 cache index bits. Non-overlapping portions of the bits are saved. Invalidation detections from storage operations (when submitted to the L1 cache or from an evicted L1 cache line) include the "L1 way" to correctly perform invalidation operations in the data reuse cache 122. In yet another example, if a load operation that “hit” in the data reuse cache 122 misses in the level 1 cache, or if the “L1 way” information in the data use cache 122 does not match the actual way of the level 1 hit, a resynchronization operation is triggered.

[0064] Forwarding data from in-flight stores to in-flight loads involves complex structural timing and priority encoding. In one implementation, the load-store unit 112 is tasked with handling load operations that may interlock (full or partial address match) old in-flight stores to the load-store unit, rather than adding complexity to the execution units. This can be performed by triggering a resynchronization operation (e.g., full pipeline flush / restore and fetch restart) whenever an interlock of a data reuse cache 122 load operation is detected.

[0065] The performance cost of resynchronization operations is high and can overwhelm device operations if not controlled. To reduce the number of resynchronization operations, processor unit 104 can employ various mitigation solutions. In one example, once a store operation has completed address calculation, the cache line of data reuse cache 122 is invalidated. This causes newer load operations that may be interlocked on stores to miss in data reuse cache 122 and be serviced by load store unit 112 instead.

[0066] In another example, a load operation is disqualified from reading the data reuse cache 122, which is predicted to be forwarded from an in-flight store or predicted to trigger a resynchronization operation. This further reduces the chance of a resynchronization operation. Memory dependency prediction, memory renaming, and resynchronization operation prediction are available at execution time.

[0067] In some cases, a store operation that invalidates a cache line of the data reuse cache 122 using a virtual memory address can leave behind an alias copy and cause a stale copy to persist. To clear the stale copy in the data reuse cache 122, the data reuse cache 122 is probed when the store operation is completed, i.e., when the data is written to the level 1 data cache 208. Various other examples are also contemplated.

[0068] Figure 5 A program 500 in an exemplary implementation depicting the operation of a data reuse cache 122. Data is stored (block 502). For example, data is stored by a load store unit 112 in a level 1 cache 120(1) (e.g., level 1 data cache 208) for processing by an execution unit 110. Other examples include additional levels of cache systems 114, physical volatile memory 106, permanent storage 108, and the like.

[0069] A load instruction is generated by the execution unit (block 504 ). For example, the load instruction 302 is generated and transmitted to the load store unit 112 .

[0070] In response to the load instruction (block 506), data is loaded from the load response obtained from the load store unit for processing by the execution unit (block 508). The data is also stored in a data reuse cache (block 510) that is communicatively coupled between the load store unit and the execution unit. For example, in response to the load instruction, data is loaded from the level 1 cache 120(1) (e.g., the level 1 data cache 208) to the execution unit 110 for processing and stored in the data reuse cache 122.

[0071] Generate a subsequent load instruction (block 512). For example, the subsequent load instruction is generated by the execution unit 110. The filter module uses a filter to control whether to allow or restrict access to the data reuse cache by the subsequent load instruction (block 514). For example, the execution unit 110 includes the filter module 124 and the filter 126. The filter 126 is configured to predict the likelihood that the corresponding load instruction will result in a hit or miss to the data reuse cache 122, for example, using a hit counter and a window about a threshold hit rate.

[0072] In response to the control of the filter module allowing access, a load instruction is executed to the data reuse cache (block 516). For example, the execution unit 110 queries the tag 308 of the data reuse cache 122 to determine whether the data is available via the cache. If so, the data is returned for processing by the execution unit 110, for example, in two execution cycles of the processor unit 104. If not, the query continues through the cache hierarchy 118 of the cache system 114.

[0073] In response to the filter module's control to restrict access, the load instruction is executed directly to the cache hierarchy (block 518). For example, no request is made to the data reuse cache 122. Rather, the load store unit 112 checks the level 1 cache 120(1) (e.g., the level 1 data cache 208) to determine data availability. If the data is available, the data is returned for processing by the execution unit 110. If not, the query continues through the cache hierarchy 118 of the cache system 114 to the physical volatile memory 106, to the permanent storage device 108, and so on.

[0074] It should be understood that many variations are possible based on the disclosure herein. Although the above features and elements are described in particular combinations, each feature or element may be used alone without the other features and elements, or in various combinations with or without the other features or elements.

[0075] The various functional units shown in the figures and / or described herein (including device 102 where appropriate) are implemented in any of a variety of different ways, such as hardware circuits, software or firmware executed on a programmable processor, or any combination of two or more of hardware, software and firmware. The provided methods are implemented in various devices such as any of a general-purpose computer, a processor or a processor core. For example, suitable processors include general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), graphics processing units (GPUs), parallel accelerated processors, multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) circuits, any other type of integrated circuit (IC) and / or state machine.

[0076] In one or more specific implementations, the methods or processes provided herein are implemented in a computer program, software, or firmware incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROM disks), and digital versatile disks (DVDs).

[0077] Although the systems and techniques have been described in language specific to structural features and / or methodological acts, it should be understood that the systems and techniques defined in the appended claims are not necessarily limited to the specific features or acts described. These specific features and acts are disclosed as example forms of implementing the claimed subject matter.

Claims

1. A method, comprising: generating a load instruction at an execution unit; In response to the load instruction: loading data from a load response obtained from a load store unit for processing by the execution unit; as well as storing the data from the load response in a data reuse cache communicatively coupled between the load store unit and the execution unit; generating, at the execution unit, a subsequent load instruction for the data; as well as In response to the subsequent load instruction, the data is loaded from the data reuse cache for processing by the execution unit. 2 . The method of claim 1 , wherein loading the data comprises loading the data from a hierarchy of a cache system by the load store unit.

3. The method of claim 2, wherein loading the data from the load response is performed from the hierarchy of the cache system in four cycles, and loading the data from the data reuse cache is performed in two cycles.

4. The method of claim 1 , further comprising generating a subsequent load instruction and routing the subsequent load instruction to be serviced by the load-store unit based on detecting that the subsequent load instruction spans more than one cache line of the data reuse cache. 5 . The method of claim 1 , further comprising generating a subsequent load instruction, and triggering a resynchronization operation based on detecting that data that is the subject of the subsequent load instruction is stale. 6 . The method of claim 1 , further comprising self-broadcasting a data reuse cache response including the data, the self-broadcasting using a broadcast port of the load store unit. 7 . The method according to claim 1 , further comprising using a filter to control whether to allow or restrict the subsequent load instruction from accessing the data reuse cache.

8. The method of claim 7, wherein the filter indicates a likelihood that the subsequent load instruction will hit or miss a cache reuse on the data. 9 . The method according to claim 7 , wherein the subsequent load instruction is included in a plurality of load instructions, and the filter maintains a plurality of hit counters for the plurality of load instructions, respectively, and the controlling is based on values ​​of the plurality of hit counters.

10. A processor unit, comprising: A cache system, the cache system comprising a plurality of cache levels; a load store unit configured to generate a load response from the cache system for processing by an execution unit; a data reuse cache, the data reuse cache being communicatively coupled between the execution unit and the load-store unit, the data reuse cache being configured to store data of the load response; and The execution unit is configured to filter load instructions for accessing the data reuse cache based on respective probabilities that the load instructions result in a hit or a miss, respectively, on the data reuse cache.

11. The processor unit of claim 10, wherein the data reuse cache is physically closer to the execution unit on an integrated circuit than the load store unit or the cache system.

12. The processor unit according to claim 10, wherein the corresponding likelihood is based on values ​​of hit counters maintained respectively for the load instructions, wherein the values ​​of the hit counters respectively indicate the number of times the load instructions hit from the data reuse cache.

13. The processor unit of claim 12, wherein the values ​​of the hit counters respectively indicate the number of times the load instructions from the data reuse cache hit within a window defining a threshold hit number.

14. The processor unit of claim 10, wherein the execution unit is configured to control access by: generating the corresponding probability that the corresponding load instruction of the load instruction does not result in a hit; and In response to the generating, access to the data reuse cache is restricted and direct access to the plurality of cache levels is allowed.

15. A processor unit, comprising: A cache system, the cache system comprising a cache hierarchy; an execution unit configured to access a data reuse cache in parallel with accessing the cache hierarchy of the cache system via a load store unit; the data reuse cache, the data reuse cache communicatively coupled between the execution unit and the load-store unit; and The load storage unit is configured as follows: generating a load response from the cache system in response to a load instruction received from the execution unit; loading data from the load response into the execution unit for processing; as well as The data from the load response is stored in the data reuse cache.

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