Manufacturing method of wafer transfer structure
By forming a cut-off wafer array structure on the intermediate substrate, the problems of substrate fragility and surface treatment damage in the prior art are solved, and a transfer structure with a stronger and more flexible capacity is achieved, which is suitable for substrate manufacturing of large-diameter III-V-type semiconductor materials.
Patent Information
- Application Number
- CN202380062782.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-09-06
- Filing Date
- 2023-09-05
- Publication Date
- 2025-04-15
AI Technical Summary
In the prior art, the substrate is fragile due to the presence of the wafer array bonding to the substrate, and it can be damaged during surface treatment processes such as chemical mechanical polishing.
By providing an intermediate substrate with a first surface, the wafer is connected to the first surface of the intermediate substrate to form a wafer array, and in the step the protruding wafer ends are removed, the wafers in the peripheral portion are cut off to form a more non-fragile transfer structure.
A more non-brittle transfer structure is realized, suitable for the manufacturing of large diameter substrates, especially for the manufacturing of III-V-type semiconductor materials such as indium phosphide, improving the mechanical strength of the structure and application flexibility.
Smart Images
Figure CN119836675A_ABST
Abstract
Description
Technical Field
[0001] The field of the invention relates generally to methods for transferring material from a donor substrate to an acceptor substrate, and more particularly to methods for transferring a dummy substrate formed from a wafer array to an acceptor substrate.
[0002] The present invention relates to a method for manufacturing a structure capable of transferring a dummy substrate formed by a wafer array to a receptor substrate.
[0003] The invention also relates to a transfer structure of this type.
[0004] The invention also relates to a transfer method using such a structure.
[0005] The invention can be applied in many fields of industry, in particular for manufacturing substrates of materials of interest having only small sizes. The invention is particularly advantageous for manufacturing substrates of semiconductor materials, such as III-V type (indium phosphide (InP) in particular).
[0006] The invention is particularly useful because it enables the manufacture of a transfer structure comprising a dummy substrate formed from an array of wafers which is mechanically stable and less prone to breakage than in the prior art. Background Art
[0007] The semiconductor materials gallium arsenide (GaAs) and InP are promising materials for many applications such as photonics and optoelectronics. However, these materials are extremely fragile, rare and expensive. Therefore, they are usually manufactured in the form of small diameter sheets (typically 100 mm or at most 150 mm in diameter), which limits the scope of their application.
[0008] To overcome this drawback, as described in the article by Ghyselen et al. (Solid State Physics A 2022, 219, 2100543), an InP wafer array forming a pseudo substrate can be produced, a thin layer of which is transferred to a silicon on insulator (SOI) substrate, thereby manufacturing an InPOSi substrate with a diameter of 200 mm. The method comprises the following steps: - bonding the wafers to an intermediate substrate (usually a wafer of semiconductor material, such as silicon), thereby obtaining a transfer structure comprising the intermediate substrate covered by an array of wafers forming a pseudo-donor substrate made of the material of interest (InP), -Execute Smart Cut TM Method, a thin layer of a pseudo-donor substrate is transferred to an acceptor substrate.
[0009] At the end of the process, the dummy donor substrate can be reused to transfer a thin layer of the material of interest to another acceptor substrate.
[0010] Generally, as shown in Figure 1, the shape of the wafer is square and the shape of the substrate is circular. Therefore, no wafer can be bonded to the edge of the substrate (Figure 1). The wafer-free area (called the exclusion zone) has a sawtooth shape. As a result, the substrate can be transported in a standard microelectronic box.
[0011] However, the presence of wafers bonded to the substrate results in substrate fragility that is exacerbated by cracking along the spaces between the wafers (inter-wafer spaces) and can impair many surface treatment processes, such as chemical mechanical polishing (CMP).
[0012] Therefore, there is a need to create transfer structures that are less fragile. Summary of the invention
[0013] An object of the present invention is to overcome the disadvantages of the prior art and to propose a method for producing a structure for transferring a wafer which overcomes the disadvantages of the prior art and which has in particular an improved mechanical strength.
[0014] To this end, the present invention proposes a method for manufacturing a wafer transfer structure, comprising the following steps: (i) providing an intermediate substrate having a first surface, (ii) connecting chips to the first surface of the intermediate substrate, thereby forming a chip array, the chips covering the central area and the peripheral area of the first surface of the intermediate substrate, and the chips covering the peripheral area protruding from the first surface of the intermediate substrate, (iii) The method further comprises a repairing step iii) after step ii), in which the end of the chip protruding from the first surface of the intermediate substrate is removed, thereby cutting off the peripheral portion of the chip and obtaining a chip transfer structure comprising the intermediate substrate covered by a pseudo substrate formed by a chip array.
[0015] The present invention differs fundamentally from the prior art in that the intermediate substrate is covered by an array of wafers both in the central area of the first surface and in the peripheral area of the first surface. Thereby an array of wafers is obtained forming a dummy substrate that can be transferred to an acceptor substrate.
[0016] The wafer pattern (ie, the wafer array) formed by all the wafers is circular, like the first surface of the intermediate substrate. This provides a dummy substrate with a standard microelectronic shape.
[0017] The wafer does not protrude from the intermediate substrate, and the structure is easy to transport, place in conventional boxes, and use in microelectronic devices.
[0018] The circular shape also makes it easier to dry the plate using the Marangoni effect or centrifugation, thus facilitating all wet processing steps with a rotating substrate.
[0019] Furthermore, bonding the wafer to all intermediate substrates and subsequently trimming them maximizes the surface area of the transferred layer and thus increases the efficiency of the process. For example, the CMP step tends to round the edge of the outermost wafer. Here, the rounded edge will be the edge of the truncated wafer. Thus the entire wafer in the center region will be preserved.
[0020] The absence of sawtooth on the wafer array at the edge of the pattern will reduce wear on consumables, especially during the manufacturing process of chemical mechanical polishing (CMP).
[0021] Furthermore, the mechanical strength of the resulting structure is improved compared to substrates from the prior art.
[0022] Advantageously, the trimming step iii) is performed by cutting and / or grinding.
[0023] Advantageously, after step ii), the method comprises a step iv), in which the wafer is thinned. Step iii) is preferably performed after step iv). It can also be performed between step ii) and step iii).
[0024] Advantageously, the wafer is bonded to the intermediate substrate by direct bonding.
[0025] According to a particularly advantageous embodiment, the array of wafers is offset from the crystallographic plane of the substrate. In other words, the dicing line formed by the inter-wafer space is rotated relative to the crystallographic plane of the substrate to which it is bonded, thereby limiting the cleavage and thus the breakage of the structure. The resulting structure is therefore less fragile, which makes it easier to handle and use in automated equipment.
[0026] Misalignment is never a problem for the final application, since when the wafer will be transferred it will be possible to realign the crystal plane of the material of interest on the final substrate.
[0027] For example, the wafer is made of semiconductor materials, especially III-V semiconductor materials, such as indium phosphide.
[0028] Advantageously, the wafer covering the peripheral area is different from the wafer covering the central area, for example having a different quality, a different material and / or a different size.
[0029] The present invention also relates to a wafer transfer structure, which includes an intermediate substrate covered by a pseudo donor substrate formed by a wafer array, the wafers are bonded to the first surface of the intermediate substrate, and the wafers cover the central area and the peripheral area of the first surface of the intermediate substrate. The wafers located on the peripheral part are cut off to avoid protruding from the first surface of the intermediate substrate.
[0030] Advantageously, there may be two populations of wafers: a "center" wafer and an edge wafer. The two populations may have different qualities (eg doping level or crystal defect rate). They may also be of different types to minimize manufacturing costs.
[0031] Advantageously, the array of wafers is offset from the crystallographic plane of the substrate.
[0032] Advantageously, the intermediate substrate is made of silicon and / or the wafer is made of InP.
[0033] The present invention also relates to a method for transferring a wafer, comprising the following steps: a) providing a transfer structure as defined above, comprising an intermediate substrate covered by a dummy donor substrate formed by an array of wafers, the wafers being bonded to a first surface of the intermediate substrate, The chips cover the central area and the peripheral area of the first surface of the intermediate substrate, and the chips located on the peripheral portion are cut off to prevent them from protruding from the first surface of the intermediate substrate. b) For example, using Smart Cut TM The method transfers the layers of the dummy substrate to a receptor substrate.
[0034] Other features and advantages of the present invention will become apparent from the following supplementary description.
[0035] It goes without saying that this supplementary description is given only as an illustration of the purpose of the present invention and should not limit this purpose in any way. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The present invention will be better understood by reading the description of the embodiments of the present invention with reference to the accompanying drawings, which are for illustration only and are by no means limiting. In the accompanying drawings: As described above in the prior art, FIG. 1 schematically shows a top view of an intermediate substrate covered by a wafer to be transferred. Figure 2A and Figure 2B The steps of a method for manufacturing a wafer transfer structure according to a first embodiment of the present invention are schematically shown. The wafer transfer structure comprises an intermediate substrate covered by a wafer to be transferred. The transfer structure is shown in a top view. Figure 3A and Figure 3BThe steps of a method for manufacturing a wafer transfer structure according to a second embodiment of the present invention are schematically shown. The wafer transfer structure comprises an intermediate substrate covered by a wafer to be transferred. The transfer structure is shown in a top view. Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Schematic = shows the steps of a method for manufacturing a wafer transfer structure according to a third embodiment of the present invention, the wafer transfer structure comprising an intermediate substrate covered by a wafer to be transferred, the transfer structure being shown in a top view. Figure 5 Shows Figure 4E Schematic cross-section of the transfer structure shown in . Fig. 6A is a photographic image of a wafer transfer structure according to a specific embodiment of the present invention, wherein the wafer array is aligned relative to the notch, the structure being made of silicon. Figure 6B is a photographic image of a wafer transfer structure according to a specific embodiment of the present invention, wherein the wafer array is misaligned at an angle of 7° relative to the notch, the structure being made of silicon.
[0037] To facilitate reading, the different parts shown in the figures are not necessarily drawn to the same scale.
[0038] The various possibilities (variants and embodiments) are not mutually exclusive and can be combined with one another.
[0039] Furthermore, in the description below, directional terms of structures (such as "top", "bottom", etc.) are used with consideration of the orientation of the structures as shown in the drawings. DETAILED DESCRIPTION
[0040] The method for manufacturing a structure 100 for transferring a dummy substrate formed by an array of wafers 121 , 122 made of the material of interest will now be described in more detail.
[0041] The invention is particularly suitable for manufacturing large diameter substrates (typically 200mm or 300mm in diameter), and is particularly suitable for manufacturing large diameter InPOSi substrates. However, the application is not limited to InP and is applicable to many other materials.
[0042] like FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B or FIG. 4D to FIG. 4E As shown in , the method for manufacturing the transfer structure 100 comprises the following consecutive steps: i) providing an intermediate substrate 110, ii) bonding the chips 121 and 122 to the first surface of the intermediate substrate, wherein the first chip group 121 covers the central area of the first surface of the intermediate substrate 110, and the second chip group 122 covers the peripheral area of the first surface of the intermediate substrate 110 and protrudes from the first surface of the intermediate substrate 110 ( Figure 2A , Figure 3A , Figure 4D ), iii) performing a trimming step to remove the ends of the wafers 122 protruding from the first surface of the intermediate substrate 110, thereby truncating the wafers 122 in the peripheral region, and thereby obtaining a transfer structure 100, which includes an intermediate substrate (110) covered by a pseudo donor substrate formed by an array of wafers (121, 122), the array having the same shape as the intermediate substrate 110 ( Figure 2B , Figure 3B , Figure 4E ).
[0043] The method may further include step iv), in which the wafers 121, 122 are thinned. Step iv) may be performed between step ii) and step iii) or after step iii). Preferably, step iv) is performed after step iii).
[0044] The intermediate substrate 110 provided in step i) is preferably made of a semiconductor material. For example, it is made of silicon. For example, the intermediate substrate 110 made of silicon having a crystal orientation 100 or 111 is selected. The intermediate substrate 110 can also be made of germanium. According to another embodiment, the substrate is made of fused silica (or glass).
[0045] The intermediate substrate 110 is a circular plate or wafer, for example, a plate with a diameter of 200 mm or 300 mm.
[0046] The intermediate substrate 110 includes a first surface (or first main surface) and a second surface (or second main surface), to which the wafers 121 and 122 are to be fixed. The first surface and the second surface are parallel to each other. The first surface and the second surface are separated by a certain thickness (for example, the thickness is between 100 and 2000 μm, in particular between 500 μm and 800 μm).
[0047] The intermediate substrate 110 has a marking notch 130 (also called a marking notch or cutout) on its periphery. The marking notch enables the orientation of the board to be identified during the various steps of the method. The notch 130 is substantially semicircular. For example, the notch may penetrate into the intermediate substrate 110 by a few millimeters (e.g. 1 mm). The size of the notch is defined in the SEMI standard.
[0048] In step ii), the wafers 121 and 122 are fixed to the intermediate substrate 110 ( Figure 2A or Figure 3A ).
[0049] The first chip group 121 is located on the central area of the first surface of the intermediate substrate 110. The chips 121 of the first chip group do not protrude from the first surface of the intermediate substrate 110.
[0050] The second chip group 122 is located on the peripheral area of the first surface of the intermediate substrate 110. The chips 122 of the second chip group protrude from the first surface of the intermediate substrate 110.
[0051] The bonded wafers 121, 122 may be the same or different. They may be made of different materials. For example, the wafer 121 of the central region may be made of a first material, while the wafer 122 of the peripheral region may be made of a second material. In particular, it is advantageous to select inexpensive wafers 122 for the peripheral region, because these wafers 122 will be cut off in step iii).
[0052] One or more of the following materials are selected: InP, AsGa, silicon, germanium, LaNiO3 (LNO), lithium titanate (LTO), SiC, diamond, sapphire, silica and glass.
[0053] The wafers 121 and 122 may have a level of integration, such as epitaxial layers, metal interconnect layers and / or CMOS.
[0054] Chips 121 , 122 made of different materials and having different functions may be integrated on the same intermediate substrate 110 .
[0055] The wafers 121, 122 may have the same or different surfaces and / or the same or different shapes. For example, the surface of the wafer 121 in the central region may be larger than the surface of the wafer 122 in the peripheral region to optimize the surface filling. It may be advantageous to avoid excessive material loss during step iii).
[0056] The wafers 121, 122 can have any shape. For example, they can be square or rectangular. Preferably, they are square. For example, the surface of the wafer is between 0.1 mm*0.1 mm and 20*20 mm, preferably between 1 mm*1 mm and 10*10 mm. Here and below, between X and Y means including the boundary values. The wafers 121, 122 are, for example, 1 cm in surface area. 2 of chip.
[0057] The thickness of the wafers 121 , 122 is preferably several tens to several hundreds of micrometers, for example, between 50 μm and 2000 μm, and more specifically between 350 μm and 775 μm.
[0058] The wafers 121, 122 are preferably evenly spaced apart. Very advantageously, the wafers are positioned so as to form cutting lines. More advantageously, the wafers 121, 122 are arranged to form a cutting grid.
[0059] The space between the wafers 121 , 122 (referred to as an inter-wafer space) is, for example, between 0.01 and 10 mm, more specifically between 0.2 and 1 mm.
[0060] The bonding pattern of the wafers 121, 122 can be aligned with the crystal plane of the intermediate substrate 110 to which they are bonded. Figure 2B , Figure 4E If a line L passing through the notch and through the center of the first circular surface of the substrate is considered, the cutting line is parallel or perpendicular to the line L.
[0061] According to an advantageous variant, the patterns of the wafers 121, 122 are not aligned with the crystallographic plane of the intermediate substrate 110 to which they are bonded ( Figure 3B ). It is therefore not aligned with the notch 130. In other words, the cutting line is neither parallel nor perpendicular to the line L as defined above. This misalignment can limit cracking and reduce the fragility of the final structure. Advantageously, in order to enhance this effect, the crystallographic plane of the wafer is also not aligned with the crystallographic plane of the intermediate substrate.
[0062] The wafers 121 , 122 may be bonded using different bonding techniques (direct bonding, polymer bonding, eutectic bonding, thermocompression bonding, anodic bonding).
[0063] Preferably, the bonding is a direct bonding.
[0064] like Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown in , step ii) may include the following sub-steps: - providing one or more substrates 120 to be cut, the substrates 120 may be of the same material or of different materials and / or the substrates 120 may be of the same size or of different sizes (a single substrate to be cut may be Figure 4A ). - Along the cutting line (such as Figure 4B The substrate 120 is cut as shown by the lines in FIG. - manually or preferably automatically (using a pick-and-place machine) placing the wafers 121, 122 onto the adhesive backing 40 ( Figure 4C )superior, - Bonding the wafers 121 and 122 to the intermediate substrate 110 ( Figure 4D ).
[0065] By way of illustration and not limitation, the substrate to be cut may be a circular InP substrate having a diameter of 50, 75 or 100 mm. For example, for an intermediate substrate 110 of 200 mm or 300 mm, 10 plates having a diameter of 100 mm may be cut.
[0066] After bonding the wafers 121 , 122 , heat treatment may be advantageously performed to increase the adhesion energy between the wafers 121 , 122 and the intermediate substrate 110 .
[0067] In step iii), the intermediate substrate 110 is modified to remove at least the ends of the wafers 122 protruding from the intermediate substrate 110 .
[0068] According to one embodiment, only the protruding portion is removed, thereby forming a truncated wafer 122. The wafers 122 on the periphery of the intermediate substrate 110 thus partially match the shape of the substrate 110. Thus, the wafer array has the same shape and the same surface area as the first surface of the intermediate substrate 110 ( Figure 2B and Figure 3B ).
[0069] According to another embodiment, minimal material may be removed to clear the natural edge (“bevel”) of substrate 110 to facilitate use of the structure in an automated machine configured on the natural edge of substrate 110. Thus, the wafer array has the same shape as the first surface of intermediate substrate 100, but has a smaller surface area ( Figure 4E ).
[0070] Advantageously, at least the entire unbonded area of the wafer is removed. This area can be seen, for example, under an acoustic microscope.
[0071] The finishing step is preferably performed by mechanical means.
[0072] Preferably, this step can be performed by mechanical grinding (also called grinding) and / or cutting. Preferably, the trimming will first be performed by cutting and then by mechanical grinding.
[0073] By using the protruding bonding and the trimming step, it is possible to obtain a transfer structure 100 , such as the intermediate substrate 110 , with a circular periphery (specifically, a circular periphery of the dummy substrate).
[0074] In step iv), the wafers 121, 122 are thinned. The wafers 121, 122 can be thinned by mechanical grinding and / or polished by chemical mechanical polishing (CMP). The CMP step gives the wafers 121, 122 a mirror-polished appearance. After step iv), the wafers 121, 122 have the same thickness. For example, the wafers are thinned to have a thickness of about 550 μm. It is also possible to reduce the thickness to a few micrometers to tens of micrometers.
[0075] Advantageously, the remaining thicknesses are chosen so as to enable continuous layer transfer with a single intermediate plate.
[0076] Advantageously, the wafer is thinned by at least fifteen micrometers.
[0077] Step iv) may include the following sub-steps: - depositing a filling material between the wafers 121, 122 (i.e., in the inter-wafer space), the thickness between the wafers preferably being greater than the final thickness of the wafers after thinning, and the filling material may also partially or completely cover the wafers 121, 122 (i.e., the wafers 121, 122 are encapsulated by the filling material), - thinning the wafers 121, 122, - The resulting mixed surface (wafers 121 , 122 —filling material) is subjected to a leveling step, for example by chemical mechanical polishing, to obtain a flat surface, or a surface slightly recessed (for example by a few nanometers to tens of nanometers) from the filling material.
[0078] After the process of manufacturing the transfer structure 100, a structure 100 is obtained, which comprises an intermediate substrate 110 covered by an array of wafers 121, 122 forming a dummy substrate. There is no exclusion zone or circular limited exclusion zone. The presence of a limited exclusion zone allows the extreme edge ("bevel") of the plate to remain free for the robot to grip the substrate.
[0079] The central area and the peripheral area of the intermediate substrate 110 are both covered by the wafers 121 and 122. The wafer 121 in the central area is complete, while the wafer 122 in the peripheral area is cut off so as not to exceed the surface of the intermediate substrate 110.
[0080] The array of wafers 121, 122 has the same shape as the intermediate substrate 110 ( Figure 2B , Figure 3B , Figure 4E , Figure 5 ).
[0081] Fig. 6A and Figure 6BThe photographic images are respectively of an aligned transfer structure 100 (ie, the wafer array aligned with respect to the notch) and a misaligned transfer structure 100 (ie, the wafer array misaligned with respect to the notch; the angle is 7°).
[0082] Thus, the resulting structure 100 can be used to transfer a pseudo donor substrate to an acceptor substrate. Preferably, the acceptor substrate is a wafer. Preferably, the acceptor substrate is made of a semiconductor material. For example, it can be an oxidized silicon substrate or an SOI substrate, i.e. a substrate comprising a silicon layer on an insulator layer, typically a SiO2 layer. SOI substrates are also typically oxidized and thus have an oxide layer on the surface.
[0083] The pseudo-donor substrate is preferably transferred to the acceptor substrate using the Smart Cut™ method.
[0084] Smart CutTM methods may include: The formation of an embrittled zone in the pseudo-donor substrate by implantation, which defines the thin layer to be transferred to the acceptor substrate, Bonding the transferred structure (i.e., the intermediate substrate and the array of wafers) to a receptor substrate by direct bonding, with the wafers being in contact with the receptor substrate, • Splitting the intermediate structure according to the embrittled zone in order to transfer a thin layer of the pseudo-donor substrate to the acceptor substrate.
[0085] The embrittlement is formed by implanting atomic species such as hydrogen or helium. The implantation conditions (dose, energy) will be determined by one of ordinary skill in the art based on the nature of the substrate and the desired implantation depth.
[0086] The dummy substrate and the receptor substrate may be surface treated before bonding to increase the bonding energy.
[0087] Cleavage can be initiated, for example, by applying mechanical forces to the embrittled zone or by heat treatment (annealing).
[0088] After the layer of interest has been transferred to a receptor substrate, transfer structure 100 may be used again to perform a new transfer of the material of interest. Illustrative and non-limiting examples: Cutting the sheets to form wafers:
[0089] The InP board 120 to be cut is mounted on a first UV release adhesive film stretched over a cutting ring. A diamond saw is used to cut wafers 121, 122 from the board. After cutting, the surface of the wafer is cleaned. In order to reconstruct the surface of a 300 mm board or wafer 110, about ten 100 mm diameter InP boards 120 need to be cut. Place the wafer on the adhesive film:
[0090] The adhesive film is exposed to UV light to make it easier to grip the wafer.
[0091] The wafers 121, 122 are picked up and then placed on the second UV release adhesive film 40 stretched over the cutting ring. This step can be performed automatically with a "pick and place" machine. The purpose is to reconstruct a plate larger than the donor plate (i.e., the intermediate substrate) on the adhesive film 40. The diameter of the reconstructed surface is preferably larger than the diameter of the intermediate substrate 110 that accommodates the wafers 121, 122, so as to maximize the reconstructed surface after trimming the wafers 121, 122. Cleaning and bonding the wafer to the intermediate substrate:
[0092] Once the surface has been reconstructed on the adhesive film 40, the wafers 121, 122 are cleaned together to remove hydrocarbons and particles. As an illustration, an initial UV / ozone cleaning may be performed to remove hydrocarbons. The wafers 121, 122 may then be cleaned with ultra-high frequency sound waves.
[0093] The wafers 121, 122 are placed face down on the intermediate substrate 110. Slight pressure is applied to the back of the adhesive film 40 to promote contact between the wafers 121, 122 and the intermediate substrate 110. Once the wafers 121, 122 have been bonded, the adhesive film 40 is exposed and peeled off. The structure with the "protruding" wafer 122 is preferably subjected to a heat treatment, such as an annealing between 250°C and 400°C to strengthen the bonding interface. Dressing by mechanical grinding:
[0094] The intermediate substrate 110 covered with the wafers 121 , 122 , some of which protrude from the surface of the intermediate substrate, may be trimmed by mechanical grinding.
[0095] For this purpose, the intermediate substrate 110 to which the wafers 121 , 122 are bonded is sucked onto a chuck.
[0096] The whole is transferred under the grinding wheel so that the outer periphery of the teeth is vertically positioned with the desired trimming width. Typically, in order to make the board compatible with other microelectronic equipment, this width is reduced to a width greater than 1.5 mm relative to the edge of the substrate 110. This frees up the natural edge of the board 110 and its notch 130.
[0097] The wheel and / or chuck on which the intermediate substrate 110 is placed is then rotated, and the wheel is lowered in parallel in order to remove the thickness of the wafer bonded to the intermediate substrate 110 .
[0098] The rotation speed (between 100 and 3000 revolutions per minute (rpm)) and the wheel descent speed (between 0.01 and 50 μm / s) are adjusted according to the material and thickness to be removed. Multiple descent speeds can be combined in a step. The rotation speed of the chuck can also be adjusted (speed between 100 and 300 rpm). Trimming by cutting:
[0099] An abrasive circular blade cutting technique may be used to trim the intermediate substrate 110 covered with wafers 121 , 122 , portions of which protrude from the surface of the intermediate substrate.
[0100] To this end, the intermediate substrate 110 to which the wafer is bonded is held on a chuck.
[0101] The cutting blade is circular. It has an abrasive lining around its periphery, the height of which is at least equal to the working depth. This abrasive lining comprises: a binder; abrasive particles, such as diamond or corundum, the size of which is adjusted according to the material to be cut and a controlled porosity.
[0102] The intermediate substrate 110 is centered due to optical alignment modules or mechanical spacers defined on the edges of the intermediate substrate.
[0103] The blade is rotated and lowered to a defined height relative to the chuck and a tangent point to the trim diameter.
[0104] The intermediate substrate 110 performs a complete rotational transfer work, which constitutes a trimming operation.
[0105] Depending on the width of the blade and the width being trimmed, multiple passes may be required to trim the board.
[0106] The blade can also enter the intermediate substrate 110 by the edge of the plate instead of vertically. In this case, the intermediate substrate 110 is first moved in translation until the trimmed tangent point is reached, and then the intermediate substrate is completely rotated.
[0107] Typically, in order to make the substrate compatible with other microelectronic equipment, this width is reduced to at least 1.5 mm, which corresponds to the trim value of the recess 130 . Thinning of the wafer placed on the trimmed intermediate substrate:
[0108] The wafers 121 and 122 may be thinned by grinding. The intermediate substrate 110 is positioned on a chuck (also referred to as a chuck). The surface of the intermediate substrate 110 opposite to the wafers 121 and 122 is in contact with the chuck.
[0109] The whole is placed under a grinding wheel. The wheel is vertical relative to the intermediate substrate 110. The wheel comprises a set of teeth arranged around the periphery of a metal base containing synthetic diamond particles sized according to the material, a resin or other binder and controlled porosity.
[0110] The wheel and / or chuck is then rotated and the wheel is lowered to thin the wafer bonded to the support substrate to the same thickness.
[0111] The rotation speed (between 100 and 3000 rpm) and the lowering speed of the wheel (between 0.01 and 50 μm / s) are adjusted according to the material and thickness to be removed. Several lowering speeds can be combined during this step. The rotation speed of the chuck can be between 100 rpm and 300 rpm. Chemical Mechanical Polishing (CMP) on the Trimmed Intermediate Substrate:
[0112] The intermediate substrate 110 covered by the array of wafers 121 , 122 may be subjected to a chemical mechanical polishing (CMP) step.
[0113] This CMP step is used to compensate for the roughness after polishing.
[0114] The intermediate substrate 110 is then subjected to a polishing step followed by a cleaning step. The surfaces of the wafers 121 , 122 are thus compatible with direct bonding. Transfer the wafer to the acceptor substrate:
[0115] The resulting structure 100 may be used to transfer the wafers 121 , 122 to a receptor substrate or a final substrate.
[0116] The wafers 121 , 122 are transferred to a receptor substrate, for example by performing implantation, bonding and breaking steps.
[0117] Misaligned transfer structures (ie, structures where the array is offset from the crystallographic plane of the intermediate substrate 110) and aligned structures (ie, structures where the array is aligned with the crystallographic plane of the intermediate substrate 110) are fabricated.
Claims
1. A method for manufacturing a wafer transfer structure (100), comprising the following steps: i) providing an intermediate substrate (110) having a first surface, ii) bonding chips (121, 122) to the first surface of the intermediate substrate (110), wherein the chips (121, 122) cover the central area and the peripheral area of the first surface of the intermediate substrate (110), and the chip (122) covering the peripheral area protrudes from the surface of the intermediate substrate (110); The method further comprises a trimming step iii) after step ii), in which the ends of the wafers (122) protruding from the first surface of the intermediate substrate (110) are removed, thereby truncating the wafers (122) in the peripheral region and obtaining a transfer structure (100), the transfer structure comprising the intermediate substrate (110) covered by a dummy donor substrate formed by an array of wafers (121, 122), The array of chips (121, 122) is offset from the crystal plane of the intermediate substrate (110).
2. The method according to claim 1, wherein: The crystallographic planes of the wafers (121, 122) are not aligned with the crystallographic plane of the intermediate substrate (110).
3. The method according to claim 1 or 2, wherein: Step iii) is performed by cutting and / or grinding.
4. A method according to any one of the preceding claims, wherein: After step ii), the method comprises a step iv) in which the wafer (121, 122) is thinned.
5. The method according to claim 4, wherein: Step iii) is performed after step iv).
6. A method according to any one of the preceding claims, wherein: The wafers (121, 122) are bonded to the intermediate substrate (110) by direct bonding.
7. A method according to any one of the preceding claims, wherein: The wafer (122) covering the peripheral area is different from the wafer (121) covering the central area, for example having a different quality, a different material and / or a different size.
8. A wafer transfer structure (100), comprising an intermediate substrate (110), the intermediate substrate (110) being covered by a pseudo donor substrate formed by an array of wafers (121, 122), the wafers (121, 122) being bonded to a first surface of the intermediate substrate (110), in, The chips (121, 122) cover the central area and the peripheral area of the first surface of the intermediate substrate (110), the chip (122) located on the peripheral part is cut off to avoid protruding from the first surface of the intermediate substrate (110), and the array of the chips (121, 122) is offset from the crystal plane of the intermediate substrate (110).
9. The structure according to claim 8, wherein: The crystallographic planes of the wafers (121, 122) are not aligned with the crystallographic plane of the intermediate substrate (110).
10. The structure according to any one of claims 8 or 9, wherein: The intermediate substrate (110) is made of silicon and the wafers (121, 122) are made of InP.
11. A method for transferring a wafer, comprising the steps of: a) providing a transfer structure (100) according to any one of claims 8 to 10, comprising an intermediate substrate (110) covered by a dummy donor substrate formed by an array of wafers (121, 122), the wafers (121, 122) being bonded to a first surface of the intermediate substrate (110), The chips (121, 122) cover the central area and the peripheral area of the first surface of the intermediate substrate (110), the chip (122) located on the peripheral portion is cut off to avoid protruding from the first surface of the intermediate substrate (110), and the array of the chips (121, 122) is offset from the crystal plane of the intermediate substrate (110), b) transferring the layer of the pseudo-donor substrate to an acceptor substrate.
12. The method for transferring a wafer according to claim 11, wherein: The crystallographic planes of the wafers (121, 122) are not aligned with the crystallographic plane of the intermediate substrate (110).