Six-switch two-inductor two-phase buck-boost converter

Abstract

The invention provides a multiphase buck-boost converter (101) comprising a first half-bridge circuit (107), a second half-bridge circuit (115), a third half-bridge circuit (111) and a control circuit (130). The first half-bridge circuit (107) is coupled to a first inductor terminal (123). The second half-bridge circuit (115) is coupled to a second inductor terminal (127). The third half-bridge circuit (111) is coupled to a third inductor terminal (125), a system voltage terminal (104), and a battery pack terminal (106). The control circuit (130) is coupled to the first half-bridge circuit (107), the second half-bridge circuit (115), and the third half-bridge circuit (111). The control circuit (130) is configured to transition the first half-bridge circuit (107), the second half-bridge circuit (115), and the third half-bridge circuit (111) from operating in a buck mode to operating in a buck-boost mode based on an off time of the first half-bridge circuit (107) being less than a particular time.

Description

Background Art

[0001] Rechargeable battery packs, such as lithium-ion battery packs, are widely used to power portable electronic devices. Examples of portable electronic devices using rechargeable battery packs include smartphones, laptops, tablet computers, power tools, and the like. Rechargeable battery packs require some form of battery pack charging system. The battery pack charging system transfers power from a power source, such as an AC wall outlet, to the battery pack. The recharging process includes processing and regulating the voltage and current from the power source so that the voltage and current supplied to the battery pack meet the charging specifications of the specific battery pack. For example, if the voltage or current supplied to the battery pack is too large, the battery pack shell may be damaged or even burst. On the other hand, if the voltage or current supplied to the battery pack is too small, the charging process may take an undesirably long time. The battery pack charging system may include a DC-DC converter to generate a suitable charging voltage. Summary of the invention

[0002] In one example, a multiphase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to a third inductor terminal and a system voltage terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to convert the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in a buck mode to operating in a buck-boost mode based on the disconnection time of the first half-bridge circuit being less than a specific time.

[0003] In another example, a multiphase buck-boost converter includes an input voltage terminal, an output voltage terminal, a first inductor terminal, a second inductor terminal, a third inductor terminal, a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to the input voltage terminal and the first inductor terminal. The second half-bridge circuit is coupled to the input voltage terminal and the second inductor terminal. The third half-bridge circuit is coupled to the output voltage terminal and the third inductor terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to operate the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a buck converter based on the on-time of the first half-bridge circuit being less than a first specific time. The control circuit is also configured to operate the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a buck-boost converter based on the off-time of the first half-bridge being less than a second specific time. The control circuit is further configured to operate the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a boost converter based on an off time of the first half-bridge circuit being less than a third specific time.

[0004] In another example, a computer system includes a processor, a battery pack, and a battery pack charger circuit. The battery pack is coupled to the processor and is configured to power the processor. The battery pack charger circuit is coupled to the battery pack and includes a multi-phase buck-boost converter. The multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to a third inductor terminal, a system voltage terminal, and a battery pack terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to convert the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in a buck mode to operating in a buck-boost mode based on a disconnection time of the first half-bridge circuit being less than a first specific time. The control circuit is also configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the buck-boost mode to operating in the boost mode based on an off time of the first half-bridge circuit being less than a second specific time. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an exemplary multi-phase buck-boost converter for implementation in a battery pack charger circuit.

[0006] Figure 2 For display Figure 1 00140] An exemplary state diagram for transitions between operating modes in a multi-phase buck-boost converter.

[0007] Figure 3 for Figure 1 00146] An exemplary timing diagram of buck mode operation in a multi-phase buck-boost converter of FIG.

[0008] Figure 4 for Figure 1 Graph of an exemplary buck mode switching cycle in a multi-phase buck-boost converter.

[0009] Figure 5 for Figure 1 0014-07 14:57:45 FIG. 1 is an exemplary timing diagram of boost mode operation in a multi-phase buck-boost converter.

[0010] Figure 6 for Figure 1 Graph of an exemplary boost mode switching cycle in a multi-phase buck-boost converter.

[0011] Figure 7 for Figure 1 0014-07 14:11:25 FIG. 10 is an exemplary timing diagram of a buck-boost mode operation in a multi-phase buck-boost converter of FIG.

[0012] Figure 8 for Figure 1 Graph of an exemplary boost mode switching cycle in a multi-phase buck-boost converter.

[0013] Fig. 9 for Figure 1 Example graphs of output voltage and inductor current for a buck-boost converter transitioning from buck mode to buck-boost mode to boost mode.

[0014] Fig.10 To include Figure 1 A block diagram of an exemplary computer system of a battery pack charger circuit. DETAILED DESCRIPTION

[0015] In many battery-powered devices, the voltage received to charge the battery may be higher or lower than the battery voltage. To accommodate this range of charging voltages, the battery charger may include a buck-boost DC-DC converter that steps up or down the charging voltage. To increase power output and reduce circuit size, some battery charger circuits include a multi-phase DC-DC converter (e.g., a two-phase DC-DC converter). A multi-phase DC-DC converter includes multiple inductors, and the current per inductor is reduced relative to a single-phase DC-DC converter. Multi-phase conversion is often applied in buck conversion, where higher power is delivered.

[0016] Some dual-phase buck-boost DC-DC converters use eight transistor switches, which increases circuit area, wiring difficulty and cost. Implementations using six transistor switches do not provide true buck-boost operation and only operate properly when the charging voltage is outside a specified voltage range (blind zone) with respect to the battery pack voltage (a specified amount greater or less than the battery pack voltage). The utility of such implementations is limited. Also, in a six-transistor implementation, when operating in boost mode, the input and output ripple currents may increase due to the reduction in effective inductance caused by the inductors of multiple phases in parallel.

[0017] The battery pack charger circuit described herein includes a multiphase buck-boost DC-DC converter implemented with six transistor switches. The example of the DC-DC converter operates over a wide range of input voltages without dead zones and reduces circuit area and cost relative to an eight-transistor implementation. In buck-boost mode, the switching is sequenced to balance the inductor current between phases. More specifically, when one inductor is de-integrated, the other inductor is also de-integrated before allowing boost integration. The switching duty cycle is skewed when operating in buck-boost mode to ensure a smooth transition from buck mode to buck-boost mode to boost mode (i.e., to prevent unnecessary transitions between modes). Some implementations of the DC-DC converter switch at a higher frequency (e.g., higher than when operating in buck mode) when operating in boost mode to reduce input and output current ripple.

[0018] Figure 11 is a block diagram of an exemplary multi-phase buck-boost converter 101 for use in a battery pack charger circuit 100. The battery pack charger circuit 100 includes a battery pack terminal 106 and a pass transistor 120. The multi-phase buck-boost converter 101 includes an input voltage terminal 102, an output voltage terminal 104, an inductor terminal 123, an inductor terminal 125, an inductor terminal 127, a half-bridge circuit 107, a half-bridge circuit 111, a half-bridge circuit 115, and a controller 122. The controller 122 includes a converter control circuit 130. A switching node 109 of the half-bridge circuit 107 is coupled to the inductor terminal 123 and a first terminal of the inductor 126. A switching node 113 of the half-bridge circuit 111 is coupled to the inductor terminal 125, a second terminal of the inductor 126, and a first terminal of the inductor 128. A switching node 117 of the half-bridge circuit 115 is coupled to an inductor terminal 127 and a second terminal of the inductor 128. The half-bridge circuit 107 includes a high-side transistor 108 and a low-side transistor 110. The half-bridge circuit 111 includes a high-side transistor 112 and a low-side transistor 114. The half-bridge circuit 115 includes a high-side transistor 116 and a low-side transistor 118. The high-side transistor 108, the low-side transistor 110, the high-side transistor 112, the low-side transistor 114, the high-side transistor 116, the low-side transistor 118, and the pass transistor 120 may be N-channel field effect transistors (NFETs). In some examples, the high-side transistor 108, the high-side transistor 112, the high-side transistor 116, and the pass transistor 120 may be p-channel FETs (PFETs).

[0019] A drain of the high-side transistor 108 is coupled to the input voltage terminal 102. A gate of the high-side transistor 108 is coupled to the converter control circuit 130. A source of the high-side transistor 108 is coupled to the switching node 109. A drain of the low-side transistor 110 is coupled to the switching node 109. A gate of the low-side transistor 110 is coupled to the converter control circuit 130. A source of the low-side transistor 110 is coupled to the ground terminal. A drain of the high-side transistor 116 is coupled to the input voltage terminal 102. A gate of the high-side transistor 116 is coupled to the converter control circuit 130. A source of the high-side transistor 116 is coupled to the switching node 117. A drain of the low-side transistor 118 is coupled to the switching node 117. A gate of the low-side transistor 118 is coupled to the converter control circuit 130. A source of the low-side transistor 118 is coupled to the ground terminal. A drain of the high-side transistor 112 is coupled to the output voltage terminal 104. The gate of the high side transistor 112 is coupled to the converter control circuit 130. The source of the high side transistor 112 is coupled to the switching node 113. The drain of the low side transistor 114 is coupled to the switching node 113. The gate of the low side transistor 114 is coupled to the converter control circuit 130. The source of the low side transistor 114 is coupled to the ground terminal.

[0020] The converter control circuit 130 controls switching in the half-bridge circuit 107, the half-bridge circuit 111, and the half-bridge circuit 115 to implement buck mode, buck-boost mode, and boost mode operations. When the voltage at the input voltage terminal 102 is substantially greater than the voltage at the output voltage terminal 104, the converter control circuit 130 alternately switches the half-bridge circuit 107 and the half-bridge circuit 115 180 degrees out of phase to implement buck mode operation. Within the half-bridge circuit, the high-side transistor and the low-side transistor switch reciprocally. The minimum difference between the voltage at the input voltage terminal 102 and the voltage at the output voltage terminal 104 required to enter the buck mode is determined by the maximum duty cycle of the buck converter and the resistive voltage drop of the field effect transistor ("FET") and the inductor (which changes based on the inductor current). An exemplary maximum duty cycle may be about 97%. In buck mode, converter control circuit 130 turns off low-side transistor 114 and turns on high-side transistor 112 to connect inductor 126 and inductor 128 to output voltage terminal 104. In buck mode, converter control circuit 130 switches half-bridge circuit 107 and half-bridge circuit 115 at a frequency (f0) selected to reduce inductor ripple and improve conversion efficiency.

[0021] When the voltage at the input voltage terminal 102 is substantially less than the voltage at the output voltage terminal 104, the converter control circuit 130 switches the half-bridge circuit 111 to implement the boost mode operation. The minimum difference between the voltage at the output voltage terminal 104 and the voltage at the input voltage terminal 102 required to enter the boost mode is determined by the minimum duty cycle of the boost converter. During the boost mode operation, the converter control circuit 130 turns on the high-side transistor 108 and the high-side transistor 116, and disconnects the low-side transistor 110 and the low-side transistor 118. The converter control circuit 130 can switch the half-bridge circuit 111 at a frequency higher than f0 when operating in the boost mode to reduce the inductor current ripple. For example, in some embodiments, the converter control circuit 130 can switch the half-bridge circuit 111 at 2f0. In some instances, the converter control circuit 130 can switch the half-bridge circuit 111 at a lower frequency to improve efficiency.

[0022] When the difference between the voltage at the input voltage terminal 102 and the voltage at the output voltage terminal 104 is less than the minimum voltage required to enter the buck mode and the difference between the voltage at the output voltage terminal 104 and the voltage at the input voltage terminal 102 is less than the minimum voltage required to enter the boost mode, the converter control circuit 130 sequentially switches the half-bridge circuit 107, the half-bridge circuit 111, and the half-bridge circuit 115 to implement the buck-boost mode operation. The converter control circuit 130 alternately switches the half-bridge circuit 107 and the half-bridge circuit 115 to balance the currents in the inductor 126 and the inductor 128.

[0023] A battery pack 124 is coupled to the battery pack terminal 106. A pass transistor 120 controls current flowing to the battery pack 124 for charging, and controls current from the battery pack 124 for powering a load coupled to the output voltage terminal 104. A drain of the pass transistor 120 is coupled to the output voltage terminal 104. A gate of the pass transistor 120 is coupled to the controller 122. A source of the pass transistor 120 is coupled to the battery pack terminal 106. The controller 122 controls the pass transistor 120 to enable charging of the battery pack 124.

[0024] Figure 2 For showing the exemplary state diagram of the transition between the operating modes in the multiphase buck-boost DC-DC converter 101. When operating in buck mode, the converter control circuit 130 monitors the disconnection time (the time when the low-side transistor 110 or the low-side transistor 118 is turned on) of the half-bridge circuit 107 and the half-bridge circuit 115. If the disconnection time of the half-bridge circuit 107 and the half-bridge circuit 115 is less than the predetermined buck-boost transition time, the converter control circuit 130 converts the multiphase buck-boost DC-DC converter 101 from the buck mode to the buck-boost mode. Otherwise, the converter control circuit 130 continues to make the multiphase buck-boost DC-DC converter 101 operate in buck mode. The predetermined buck-boost transition time is set to be greater than the minimum possible pulse of the converter. For the embodiment of the multiphase buck-boost DC-DC converter 101 using silicon FET, this value can be within the range of low tens of nanoseconds, but it may be higher for extremely large power converters, and may be lower for high-frequency highly integrated converters.

[0025] When operating in buck-boost mode, converter control circuit 130 monitors the disconnection time (time when low-side transistor 110 or low-side transistor 118 is turned on) of half-bridge circuit 107 and half-bridge circuit 115. If the disconnection time of half-bridge circuit 107 and half-bridge circuit 115 is less than the predetermined boost transition time, converter control circuit 130 converts multi-phase buck-boost DC-DC converter 101 from buck-boost mode to boost mode. The predetermined boost transition time may be similar to the predetermined buck-boost transition time described above. In buck-boost mode, converter control circuit 130 monitors the turn-on time (time when low-side transistor 114 is turned on) of half-bridge circuit. If the turn-on time of half-bridge circuit 111 is less than the predetermined buck transition time, converter control circuit 130 converts multi-phase buck-boost DC-DC converter 101 from buck-boost mode to buck mode. The predetermined buck transition time may be similar to the predetermined buck-boost transition time described above. When the off time of half-bridge circuit 107 and half-bridge circuit 115 is not less than the predetermined boost transition time, and the on time of half-bridge circuit 111 is not greater than the predetermined buck transition time, converter control circuit 130 continues to operate multi-phase buck-boost DC-DC converter 101 in the buck-boost mode.

[0026] When operating in the boost mode, the converter control circuit 130 also monitors the on-time of the half-bridge circuit 111 (the time when the low-side transistor 114 is turned on). If the on-time of the half-bridge circuit 111 is less than a predetermined time (similar to the predetermined buck-boost transition time described above), the converter control circuit 130 transitions the multi-phase buck-boost DC-DC converter 101 from the boost mode to the buck-boost mode. Otherwise, the converter control circuit 130 continues to operate the multi-phase DC-DC converter 101 in the boost mode.

[0027] Figure 31 is an exemplary timing diagram of buck mode operation in a multi-phase buck-boost DC-DC converter 101. The switching cycles of the half-bridge circuit 107 and the half-bridge circuit 115 are offset by about 180° relative to each other, as shown by the inductor current 146 and the inductor current 148. The converter control circuit 130 generates a complementary high-side drive signal 134 and a low-side drive signal 136 to control the high-side transistor 108 and the low-side transistor 110, respectively. The high-side drive signal 134 turns on the high-side transistor 108, and the low-side drive signal 136 turns off the low-side transistor 110 to charge the inductor 126. The low-side drive signal 136 turns on the low-side transistor 110, and the high-side drive signal 134 turns off the high-side transistor 108 to discharge the inductor 126. The converter control circuit 130 generates a complementary high-side drive signal 144 and a low-side drive signal 142 to control the high-side transistor 116 and the low-side transistor 118, respectively. The high-side drive signal 144 turns on the high-side transistor 116, and the low-side drive signal 142 turns off the low-side transistor 118 to charge the inductor 128. The low-side drive signal 142 turns on the low-side transistor 118, and the high-side drive signal 144 turns off the high-side transistor 116 to discharge the inductor 128. The converter control circuit 130 generates the high-side drive signal 140 and the low-side drive signal 138 to control the high-side transistor 112 and the low-side transistor 114. In the buck mode, the high-side drive signal 140 turns on the high-side transistor 112, and the low-side drive signal 138 turns off the low-side transistor 114.

[0028] Figure 4 is a graph of an exemplary buck mode switching cycle. The duration of the switching cycle is indicated as Ts. Ton represents the time when the high-side transistor 108 is turned on and the low-side transistor 110 is turned off, or the time when the high-side transistor 116 is turned on and the low-side transistor 118 is turned off. Toff represents the time when the low-side transistor 110 is turned on and the high-side transistor 108 is turned off, or the time when the low-side transistor 118 is turned on and the high-side transistor 116 is turned off. In buck mode, the transfer function of the multi-phase buck-boost DC-DC converter 101 can be expressed as:

[0029]

[0030] in:

[0031] V OUT is the voltage at the output voltage terminal 104;

[0032] V IN is the voltage at the input voltage terminal 102; and

[0033] T S and T ON like Figure 4 As described in .

[0034] Figure 5 1 is an exemplary timing diagram of a boost mode operation in a multi-phase buck-boost DC-DC converter 101. In boost mode, a high-side drive signal 134 turns on a high-side transistor 108, a high-side drive signal 144 turns on a high-side transistor 116, a low-side drive signal 136 turns off a low-side transistor 110, and a low-side drive signal 142 turns off a low-side transistor 118. The converter control circuit 130 switches a half-bridge circuit 111 to step up the voltage at the output voltage terminal 104. A low-side drive signal 138 turns on a low-side transistor 114, and a high-side drive signal 140 turns off a high-side transistor 112 to charge an inductor 126 and an inductor 128. A high-side drive signal 140 turns on a high-side transistor 112, and a low-side drive signal 138 turns off a low-side transistor 114 to discharge an inductor 126 and an inductor 128. The switching frequency of the low-side drive signal 138 and the high-side drive signal 140 may be higher (e.g., twice) than the switching frequency of the high-side drive signal 134, the low-side drive signal 136, the low-side drive signal 142, or the high-side drive signal 144 in the buck mode to compensate for the reduction in inductance due to the parallel inductors 126 and 128.

[0035] Figure 6 is a diagram of an exemplary boost mode switching cycle. The duration of the switching cycle is labeled Ts. Ton represents the time when the low-side transistor 114 is turned on and the high-side transistor 112 is turned off. Toff represents the time when the high-side transistor 112 is turned on and the low-side transistor 114 is turned off.

[0036] Figure 71 is an exemplary timing diagram of the buck-boost mode operation in the multi-phase buck-boost DC-DC converter 101. In the buck-boost mode, the converter control circuit 130 switches the half-bridge circuit 107, the half-bridge circuit 115 and the half-bridge circuit 111 in sequence. The buck-boost switching cycle begins with the execution of the boost integration cycle, wherein the low-side drive signal 138 turns on the low-side transistor 114, the high-side drive signal 140 turns off the high-side transistor 112, the high-side drive signal 134 turns on the high-side transistor 108, the low-side drive signal 136 turns off the low-side transistor 110, the high-side drive signal 144 turns on the low-side transistor 116, and the low-side drive signal 142 turns off the low-side transistor 118. The boost integration cycle charges the inductors 126 and 128. In the first time interval after the boost cycle, the first buck de-integration cycle is performed in the half-bridge circuit 107 or the half-bridge circuit 115. For example, in the first buck de-integration cycle, the high-side transistor 108 is disconnected, the low-side transistor 110 is turned on, the high-side transistor 116 is turned on, and the low-side transistor 118 is disconnected. In the second time interval after the first buck de-integration cycle, the second buck de-integration cycle is performed in one of the half-bridge circuit 107 and the half-bridge circuit 115 that do not perform the first de-integration cycle. For example, in the second buck de-integration cycle, the low-side transistor 118 is turned on, the high-side transistor 116 is disconnected, the high-side transistor 108 is turned on, and the low-side transistor 110 is disconnected. Therefore, the inductors 126 and 128 are charged simultaneously in the boost cycle and discharged sequentially in the buck de-integration cycle. In two adjacent buck-boost cycles, the de-integration cycles alternate. In the first buck-boost cycle, before the half-bridge circuit 115 performs the de-integration cycle, the half-bridge circuit 107 performs the buck de-integration cycle. In the second buck-boost cycle (immediately after the first buck-boost cycle), the half-bridge circuit 115 performs a buck de-integration cycle before the half-bridge circuit 107 performs a de-integration cycle. The current between the half-bridge circuit 107 and the half-bridge circuit 115 is alternately averaged. The de-integration timing is set by the modulator of the converter control circuit 130, which adjusts the timing to regulate the output current and voltage. If the current or voltage is too large, the de-integration time is increased. This can be achieved through a pulse width modulator (PWM) ramp, a control signal, and a comparator.

[0037] Figure 8 is a diagram of an exemplary buck-boost mode switching cycle in the multi-phase buck-boost DC-DC converter 101. The first buck-boost switching cycle is labeled Ts_bb_1, and the second (subsequent) buck-boost switching cycle is labeled Ts_bb_2. Ton represents the time when the boost integration cycle is active (the part of the buck-boost mode switching cycle). Toff (Toffa and Toffb) represents the time when the buck de-integration is active.

[0038] The buck-boost transfer function can be expressed as:

[0039]

[0040] At the operating mode transition point, a given control signal produces the same output voltage in buck, boost and buck-boost modes. The converter control circuit 130 achieves this by increasing the slope of the PWM ramp generated in the converter control circuit 130 in buck-boost mode. Increasing the ramp slope increases both the Ton and Toff times in buck-boost mode. The Ton and Toff signals are generated by two ramps combined with a control signal and a comparator. When the ramp is higher than the control signal, the Ton and Toff signals are high. When the slope of the PWM ramp increases, it increases the width of both the Ton and Toff signals. The cycle time in buck-boost mode may be different from the cycle time in buck mode because the buck-boost cycle includes a boost cycle. The ramp slope in buck-boost mode is adjusted to account for this difference.

[0041] exist Figure 8 In the figure, current 802 represents the current flowing in inductor 126 in the sequential buck-boost cycle, and current 804 represents the current flowing in inductor 128 in the sequential buck-boost cycle. In the Ton interval, at the beginning of Ts_bb_1 and Ts_bb_2, a boost integration cycle is performed to charge inductors 126 and 128. In the interval COM1a, high-side transistor 108 is turned on, and low-side transistor 110 is disconnected. Similarly, in the interval COM2a, high-side transistor 116 is turned on, and low-side transistor 118 is disconnected. COM1a and COM2a correspond to buck integration and boost de-integration. In the interval Toffa, high-side transistor 108 is turned on, and low-side transistor 110 is disconnected to perform a buck de-integration cycle for inductor 126. In the interval COM1b, after the buck de-integration cycle, high-side transistor 108 is turned on, and low-side transistor 110 is disconnected. Similarly, in interval Toffb, low-side transistor 118 is turned on and high-side transistor 116 is turned off to perform a buck de-integration cycle for inductor 128. By performing Toff at different times (applying different time offsets relative to each other), converter control circuit 130 maintains a two-phase reduction in ripple current in buck-boost mode. In interval COM2b, after the buck de-integration cycle, high-side transistor 116 is turned on and low-side transistor 118 is turned off. COM1b and COM2b correspond to buck integration and boost de-integration.

[0042] In Ts_bb_1, COM1a is longer than COM2a. In Ts_bb_2, COM 2a is longer than COM1a. For example, in Ts_bb_2, COM1a may be the same length as COM2a in Ts_bb_1, and COM2a may be the same length as COM1a in Ts_bb_1. By alternating the lengths of COM1 and COM2 in consecutive switching cycles, the converter control circuit 130 ensures equal average current in the inductor 126 and the inductor 128. The duty cycle of each phase may be adjusted to compensate for propagation delays or mismatches in inductor parameters and to ensure uniform current.

[0043] Fig. 9 FIG. 1 is an exemplary graph of output voltage and inductor current when the multi-phase buck-boost DC-DC converter 101 transitions from buck mode to buck-boost mode to boost mode. Inductor current 146, inductor current 148, and output voltage 150 are shown in FIG. Fig. 9 middle. Fig. 9 It is shown that the multi-phase buck-boost DC-DC converter 101 provides seamless transitions between buck, buck-boost, and boost modes when the output voltage 150 rises, with no imbalance between the inductor currents 146 and 148 when the current waveform changes.

[0044] Fig.10 1 is a block diagram of an exemplary computer system 1000 including a battery pack charger circuit 100. The computer system 1000 includes a battery pack 124 coupled to the battery pack charger circuit 100 and a processor 1002. The processor 1002 may be a general purpose microprocessor, a graphics processor, or a network processor, or other instruction execution device. Implementations of the computer system 1000 may include a variety of additional components (e.g., memory, timing circuitry, communication circuitry, etc.) coupled to the processor 1002 and the battery pack charger circuit 100. The battery pack charger circuit 100 generates a voltage for charging the battery pack 124 and for powering the processor 1002. The battery pack charger circuit 100 operates with a wide range of input voltages and provides seamless transitions between buck, buck-boost, and boost modes as described herein.

[0045] In this description, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0046] Moreover, in this description, the statement “based on” means “based at least in part on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0047] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0048] As used herein, the terms "terminal", "node", "interconnect", "lead" and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0049] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., by an end user and / or a third party, during or after manufacture.

[0050] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0051] Reference herein to a FET being "on" means that there is a conducting channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" means that there is no conducting channel, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0052] The circuits described herein may be reconfigured to include additional components or different components to provide functionality at least partially similar to functionality available prior to component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0053] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0054] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially" or "substantially" before a parameter means within + / -10% of the parameter.

[0055] Modifications to the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. A multiphase buck-boost converter, comprising: a first half-bridge circuit coupled to the first inductor terminal; a second half-bridge circuit coupled to the second inductor terminal; a third half-bridge circuit coupled to the third inductor terminal and the system voltage terminal; as well as a control circuit coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit, the control circuit being configured to: Based on the off time of the first half-bridge circuit being less than a predefined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are switched from operating in the buck mode to operating in the buck-boost mode.

2. The multiphase buck-boost converter of claim 1 , wherein: The predefined time is a first predefined time; and The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the buck-boost mode to operating in the boost mode based on an off time of the first half-bridge circuit being less than a second predefined time.

3. The multi-phase buck-boost converter of claim 1 , wherein: The predefined time is a first predefined time; and The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the buck-boost mode to operating in the buck mode based on an on-time of the first half-bridge circuit being less than a second predefined time.

4. The multi-phase buck-boost converter of claim 1 , wherein: The predefined time is a first predefined time; and The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the boost mode to operating in the buck-boost mode based on an on-time of the first half-bridge circuit being less than a second predefined time.

5. The multi-phase buck-boost converter of claim 1 , wherein: The first half-bridge circuit comprises a first high-side transistor and a first low-side transistor; The second half-bridge circuit comprises a second high-side transistor and a second low-side transistor; The third half-bridge circuit comprises a third high-side transistor and a third low-side transistor; and The control circuit is configured to, in the buck mode: Turning on the third high-side transistor by a switching cycle; turning off the third low-side transistor by the switching cycle; reciprocally switching the first high-side transistor and the first low-side transistor; reciprocally switching the second high-side transistor and the second low-side transistor; as well as Switching in the second half-bridge circuit is offset by 90 degrees from switching of the first half-bridge circuit.

6. The multiphase buck-boost converter of claim 5 , wherein the control circuit is configured to, in a boost mode: turning on the first high-side transistor and the second high-side transistor through the switching cycle; disconnecting the first low-side transistor and the second low-side transistor by the switching cycle; as well as The third high-side transistor and the third low-side transistor are switched reciprocally.

7. The multiphase buck-boost converter of claim 6, wherein the control circuit is configured to switch the third high-side transistor and the third low-side transistor in the boost mode at a higher frequency than switching the first high-side transistor and the first low-side transistor in the buck mode.

8. The multiphase buck-boost converter of claim 5, wherein the control circuit is configured, in the buck-boost mode: In a first interval of the switching cycle: turning on the first high-side transistor, the second high-side transistor, and the third low-side transistor; and disconnecting the first low-side transistor, the second low-side transistor, and the third high-side transistor; In a second interval of the switching cycle: turning on the first high-side transistor, the second low-side transistor and the third high-side transistor; as well as disconnecting the second high-side transistor, the first low-side transistor, and the third low-side transistor; as well as In a third interval of the switching cycle: turning on the second high-side transistor, the first low-side transistor, and the third high-side transistor; and The first high-side transistor, the second low-side transistor, and the third low-side transistor are turned off.

9. A multiphase buck-boost converter comprising: a first half-bridge circuit coupled between an input voltage terminal and a first inductor terminal; a second half-bridge circuit coupled between the input voltage terminal and a second inductor terminal; a third half-bridge circuit coupled between the output voltage terminal and the third inductor terminal; a control circuit coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit, the control circuit being configured to: Based on the on-time of the first half-bridge circuit being less than a first predefined time, operating the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a buck converter; Based on the off time of the first half-bridge circuit being less than a second predefined time, operating the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a buck-boost converter; as well as Based on the off time of the first half-bridge circuit being less than a third predefined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated as a boost converter.

10. The multi-phase buck-boost converter of claim 9, wherein the control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from a boost mode to a buck-boost mode based on an on-time of the first half-bridge circuit being less than a fourth predefined time.

11. The multi-phase buck-boost converter of claim 9, wherein: The control circuit is configured to: connecting the third inductor terminal to the output voltage terminal via the third half-bridge circuit; and The first half-bridge circuit and the second half-bridge circuit are switched alternately.

12. The multiphase buck-boost converter of claim 11 , wherein the control circuit is configured to, in a boost mode: connecting the input voltage terminal to the first inductor terminal via the first half-bridge circuit; connecting the input voltage terminal to the second inductor terminal via the second half-bridge circuit; and The third half-bridge circuit is switched. 13 . The multi-phase buck-boost converter of claim 12 , wherein a switching frequency of the third half-bridge circuit in the boost mode is greater than a switching frequency of the first half-bridge circuit in the buck mode.

14. The multiphase buck-boost converter of claim 9, wherein the control circuit is configured to, in a buck-boost mode: operating the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit to perform a boost integration cycle in a first portion of a switching cycle; operating the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit to perform a first buck de-integrating cycle in a second portion of the switching cycle; as well as The first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform a second buck de-integrating cycle in a third portion of the switching cycle.

15. The multiphase buck-boost converter of claim 14, wherein: performing the second buck de-integration cycle after the first buck de-integration cycle; and In a first switching cycle, the first buck de-integrating cycle is offset from the second buck de-integrating cycle by a first time; and In a second switching cycle, the first buck de-integration cycle is offset from the second buck de-integration cycle by a second time different from the first time.

16. A computer system comprising: processor; a battery pack coupled to the processor and configured to power the processor; a battery charger circuit coupled to the battery pack and comprising: A multiphase buck-boost converter comprising: a first half-bridge circuit coupled to the first inductor terminal; a second half-bridge circuit coupled to the second inductor terminal; a third half-bridge circuit coupled to the third inductor terminal, the system voltage terminal, and the battery pack terminal; as well as a control circuit coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit, the control circuit being configured to: Based on the off time of the first half-bridge circuit being less than a first predefined time, switching the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in a buck mode to operating in a buck-boost mode; as well as Based on the disconnection time of the first half-bridge circuit being less than a second predefined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are converted from the buck-boost mode to a boost mode.

17. The computer system of claim 16, wherein: The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the buck-boost mode to operating in the buck mode based on an on-time of the first half-bridge circuit being less than a second predefined time.

18. The computer system of claim 16, wherein: The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the boost mode to operating in the buck-boost mode based on an on-time of the first half-bridge circuit being less than a second predefined time.

19. The computer system of claim 16, wherein a switching frequency of the third half-bridge circuit in the boost mode is greater than a switching frequency of the first half-bridge circuit in the buck mode.

20. The computer system of claim 16, wherein the control circuit is configured, in the buck-boost mode: operating the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit to perform a boost integration cycle in a first portion of a switching cycle; and The first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform a buck de-integrating cycle in a second portion of a switching cycle.

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