Solid-state imaging device

Abstract

The present disclosure relates to a solid-state imaging device that can improve pixel characteristics. There is provided a solid-state imaging device including a pixel array portion in which pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, the pixel transistor including a transistor having a structure in which the photoelectric conversion element is electrically connected to the pixel array portion, and the photoelectric conversion element is electrically connected to the pixel transistor. Impurities are implanted into a channel that is non-linear in plan view by using a self-aligned mask corresponding to a gate electrode. This disclosure is applicable to, for example, a CMOS-type solid-state imaging device.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, and more particularly to a solid-state imaging device capable of improving pixel characteristics. Background Art

[0002] In recent years, a back-illuminated solid-state imaging device that emits light from the side of the substrate opposite to the side on which the wiring layer is formed has been proposed (for example, see Patent Document 1). As the miniaturization of pixel structures progresses, some back-illuminated solid-state imaging devices may be equipped with pixel transistors having an L-shaped channel due to layout constraints. Citation list Patent Literature

[0003] Patent Document 1: PCT Patent Publication No. WO2017 / 169754 Summary of the invention Technical issues

[0004] In such a solid-state imaging device as described above, it may be impossible to obtain desired characteristics of pixels due to layout constraints. Therefore, it is proposed to improve pixel characteristics.

[0005] The present disclosure has been made in view of the above-described circumstances, and proposes to improve pixel characteristics. Solutions to technical problems

[0006] According to one aspect of the present disclosure, a solid-state imaging device is provided, which includes a pixel array unit in which a plurality of pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, wherein the pixel transistor includes a transistor having the following structure: in the structure, impurities are injected into a channel that is non-linear in a plan view by using a self-aligned mask corresponding to a gate electrode.

[0007] In a solid-state imaging device according to one aspect of the present disclosure, there is provided a pixel transistor of pixels two-dimensionally arranged in a pixel array section, the pixel transistor having a structure in which impurities are implanted into a non-linear channel in a plan view using a self-aligned mask corresponding to a gate electrode.

[0008] According to another aspect of the present disclosure, a solid-state imaging device is provided, which includes a pixel array portion in which a plurality of pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, wherein the pixel transistor includes a transistor having the following structure: in the structure, the amount of overlap between a first impurity region on a source side and a gate electrode and a side wall is different from the amount of overlap between a second impurity region on a drain side and the gate electrode and the side wall.

[0009] In a solid-state imaging device according to another aspect of the present disclosure, a pixel transistor of pixels arranged two-dimensionally in a pixel array portion is provided, wherein the pixel transistor has a structure in which the amount of overlap between a first impurity region on a source side and a gate electrode and a side wall is different from the amount of overlap between a second impurity region on a drain side and the gate electrode and the side wall.

[0010] Incidentally, the solid-state imaging device according to one aspect of the present disclosure may be an independent device or an internal block constituting a part of a single device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 : is a diagram showing an exemplary configuration of an embodiment of a solid-state imaging device to which the present disclosure is applied. Figure 2 is a plan view showing an exemplary configuration of a pixel. Figure 3 yes Figure 2 A cross-sectional view of a pixel in taken along line AA'. Figure 4 is a timing diagram showing how the pixel transistors are driven. Figure 5 is a diagram showing a manufacturing method including steps for forming the structure of the present disclosure. Figure 6 are other diagrams illustrating manufacturing methods including other steps for forming the structures of the present disclosure. Figure 7 FIG. 1 is a diagram illustrating the effect of implanting impurities into a non-linear channel structure using a self-aligned mask. Figure 8 is another diagram illustrating the effect of implanting impurities into a non-linear channel structure using a self-aligned mask. Fig. 9 is a plan view showing an exemplary configuration of a pixel. Fig.10 yes Fig. 9 A plan view of a pixel in and a cross-sectional view taken along line AA'. Fig.11 yes Fig. 9 A plan view of a pixel in and a cross-sectional view taken along line AA'. Fig.12 is a cross-sectional view showing an exemplary configuration of a pixel. Fig.13 is a cross-sectional view showing another exemplary configuration of a pixel. Fig.14 are a plan view and a cross-sectional view showing an exemplary configuration of a pixel. Fig.15 are a plan view and a cross-sectional view showing another exemplary configuration of a pixel. Fig.16 is a plan view showing an exemplary configuration of a pixel transistor. Fig.17 is a plan view showing another exemplary configuration of a pixel transistor. Fig.18 is a cross-sectional view showing another exemplary configuration of a pixel transistor. Fig.19 is a diagram showing a manufacturing method including steps for forming the structure of the present disclosure. Fig. 20 is a graphical representation illustrating the electric field relaxation effect brought about by the structure of the present disclosure. Fig.21 is a plan view showing an exemplary configuration of a pixel transistor. Fig. 22 is a plan view showing another exemplary configuration of a pixel transistor. Fig.23 is a cross-sectional view showing another exemplary configuration of a pixel transistor. Fig.24 : is a block diagram showing an exemplary configuration of an electronic device equipped with a solid-state imaging device to which the present disclosure is applied. Fig.25 is a block diagram showing a schematic configuration example of a vehicle control system. Fig.26 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0012] <<First Implementation Plan>>

[0013] <Device Structure> Figure 1 : is a diagram showing an exemplary configuration of an embodiment of a solid-state imaging device to which the present disclosure is applied.

[0014] exist Figure 1 In the embodiment, the solid-state imaging device 10 is a CMOS (complementary metal oxide semiconductor) type solid-state imaging device. The solid-state imaging device 10 may also be a back-illuminated solid-state imaging device. The solid-state imaging device 10 includes a pixel array unit 21, a vertical drive unit 22, a column signal processing unit 23, a horizontal drive unit 24, an output unit 25, and a control unit 26.

[0015] The pixel array section 21 has a plurality of pixels 100 arranged two-dimensionally on a semiconductor substrate generally composed of silicon (Si). In the case where the plurality of pixels 100 are arranged in a two-dimensional matrix pattern, the pixel array section 21 has a pixel drive line 41 formed for each row of pixels and connected to the vertical drive section 22. The pixel array section 21 also has a vertical signal line 42 formed for each column of pixels and connected to the column signal processing section 23.

[0016] The vertical drive section 22 generally includes a shift register, an address decoder, etc., and drives the pixels 100 arranged in the pixel array section 21. Signals output from the pixels 100 selectively scanned by the vertical drive section 22 are supplied to the column signal processing section 23 via the vertical signal line 42.

[0017] The column signal processing section 23 performs predetermined signal processing (eg, noise removal, sampling, etc.) on each signal output from the pixels 100 of the selected row via the vertical signal line 42 for each pixel column of the pixel array section 21. The column signal processing section 23 temporarily holds the thus processed signal.

[0018] The horizontal driving section 24 generally includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column signal processing section 23. After the horizontal driving section 24 selectively scans, the signal processed by the column signal processing section 23 is output to the output section 25 via the horizontal signal line 51.

[0019] The output section 25 performs predetermined signal processing on the signals sequentially input from the respective column signal processing sections 23 via the horizontal signal line 51. Then, the output section 25 outputs the obtained signals.

[0020] The control section 26 generally includes a timing generator that generates various timing signals, etc. Based on the various timing signals thus generated by the timing generator, the control section 26 drives and controls the vertical drive section 22, the column signal processing section 23, the horizontal drive section 24, and the like.

[0021] <First Structure> Figure 2 is a plan view showing an exemplary configuration of the pixel 100 . Figure 3 yes Figure 2 A cross-sectional view of a pixel 100 taken along line AA' in FIG. Figure 3 When the stacking direction (depth direction) in which the constituent elements of the pixel are stacked one by one in the cross-sectional structure is regarded as the Z direction in the XYZ axis space, Figure 2 The plan view as viewed on the XY plane is shown. This relationship between the plan view and the cross-sectional view also applies to the other figures discussed below.

[0022] The pixel 100 includes a photodiode and a pixel transistor as a photoelectric conversion element. The pixel 100 is a square unit pixel. The photodiode of the pixel is separated by an element separation unit 131 arranged in a square grid. In addition, the elements in the pixel 100 are separated by an element separation unit 132.

[0023] like Figure 2 As shown, the pixel 100 has a transfer transistor 111, a capacitance switching transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115 as pixel transistors.

[0024] The transfer transistor 111 is sandwiched between the photodiode and the FD 121. In response to a drive signal TGL applied to a gate electrode of the transfer transistor 111, the transfer transistor 111 transfers charges stored in the photodiode to the FD 121. The FD 121 denotes a floating diffusion (FD) that converts charges from the photodiode into a voltage signal.

[0025] The FD 121 is connected to the capacitance switching transistor 112 and the reset transistor 113. In response to the drive signal FDG applied to the gate electrode of the capacitance switching transistor 112, the capacitance switching transistor 112 switches the FD capacitance of the FD 121. The FD 121 includes FD 121-1 and FD 121-2 sandwiching the capacitance switching transistor 112.

[0026] The reset transistor 113 is connected to the amplifier transistor 114. In response to the drive signal RST applied to the gate electrode of the reset transistor 113, the reset transistor 113 resets the input of the gate electrode of the amplifier transistor 114 to a predetermined potential. The gate electrode of the amplifier transistor 114 is connected to the FD 121, and its drain is connected to the power supply voltage (VDD). The amplifier transistor 114 amplifies the charge obtained by the photoelectric conversion of the photodiode.

[0027] The selection transistor 115 is connected between the source of the amplifier transistor 114 and the vertical signal line 42. In response to the drive signal SEL applied to the gate electrode of the selection transistor 115, the selection transistor 115 controls the conduction between the source of the amplifier transistor 114 and the vertical signal line 42. When the source of the amplifier transistor 114 and the vertical signal line 42 become conductive, thereby allowing the pixel 100 to be selected, the signal from the amplifier transistor 114 is read out to the column signal processing section 23 via the vertical signal line 42.

[0028] Here, the capacitance switching transistor 112 has an L-shaped non-linear channel 121. That is, the capacitance switching transistor 112 is shaped in such a way that the channel 121 has a right angle region in a plan view. Figure 3As shown, the region of the channel 121 is formed by implanting n-type impurities (impurity ions) into a silicon substrate 161 having a p-type region. The impurity region 162 is also formed by implanting p-type impurities (impurity ions) into the non-linear channel 121 using a self-aligned mask. The self-aligned mask is formed corresponding to the gate electrode 151 of the capacitance switching transistor 112. A side wall 152 is formed on the side of the gate electrode 151.

[0029] The element separation part 131 has an element separation structure in which a groove penetrates the silicon substrate 161 in the stacking direction (i.e., a through groove). A sidewall film and a filler are buried in the through groove. The element separation part 132 has a digging type element separation structure in which the silicon substrate 161 is dug in the stacking direction and oxide is buried.

[0030] In this way, the pixel 100 has a photodiode and a pixel transistor including a capacitance switching transistor 112, and the capacitance switching transistor 112 has a structure in which impurities are injected into the non-linear channel 121 by using a self-aligned mask. The pixel 100 also has an element separation structure composed of element separation parts 131 and 132. It should be noted that in the case where not only the capacitance switching transistor 112 but also other transistors having a non-linear channel are arranged, the relevant transistors may also have a structure in which impurities are injected into the non-linear channel by using a self-aligned mask. For example, in Figure 2 In the plan view of , the amplifying transistor 114 has a non-linear channel, and the amplifying transistor 114 may have a structure in which impurities are implanted by using a self-aligned mask.

[0031] Figure 4 is a timing diagram showing how the pixel transistors of the pixel 100 are driven. Figure 4 1 shows a conventional readout operation of the pixel 100. The symbols SEL, RST, FDG, and TGL denote the Figure 2 The driving signal of the gate electrode of each transistor in the plan view. Figure 4 As shown, the transistor operates in response to the corresponding drive signal to sequentially provide an LCG (low conversion gain) reset level, an HCG (high conversion gain) reset level, an HCG signal level, and an LCG signal level. These signal levels and reset levels are used to perform sampling processes such as CDS (correlated double sampling). This makes it possible to read out a signal obtained from the charge stored in the photodiode.

[0032] Figure 5 and Figure 6 is shown including a method for forming a structure (ie, Figure 3 A diagram of a manufacturing method of a process of (a cross-sectional structure in). Figure 5 and Figure 6The sub-figures A to F in FIG. 1 are plan views and cross-sectional views corresponding to the processes involved. The cross-sectional views are each taken along the line AA' in the plan view.

[0033] Figure 5 The process in sub-figure A in involves forming a through trench in the silicon substrate 161 and burying a sidewall film, a filler, etc. in the trench to form the element separation portion 131 , and digging a region where an oxide is to be buried to form the element separation portion 132 . Figure 5 The process in sub-figure A in FIG. 1 also involves implanting n-type impurities into the silicon substrate 161 to form a region of the channel 121 . Figure 5 The process in sub-figure B in FIG. 1 involves forming an oxide film 153 on the channel 121, and further forming a gate electrode 151 which is generally made of polycrystalline silicon (poly-Si), metal, etc. on the upper surface of the oxide film 153.

[0034] Figure 5 The process in sub-figure C in FIG. 1 involves forming a resist pattern 211 having a wide opening inside the non-linear channel 121. That is, the resist pattern 211 is formed in such a manner that p-type impurities are implanted inside the L-shaped channel 121. Figure 6 The process in sub-figures D and E in FIG. 1 involves using the resist pattern 211 to obliquely implant p-type impurities into the inner side of the L-shaped non-linear channel 121 at an oblique angle (as indicated by arrow I1 in the figure). The oblique angle is a predetermined angle relative to the normal line of the main surface of the substrate. For example, the oblique angle is the angle between the normal line of the surface of the silicon substrate 161 and the ion beam.

[0035] like Figure 6 As shown in sub-figure E in , when the p-type impurity is injected, the p-type impurity region 162 is formed using a self-aligned mask formed corresponding to the gate electrode 151. In this way, by using the previously formed gate electrode 151 as a self-aligned mask, that is, by treating the gate electrode 151 as a pseudo mask, a portion of the p-type impurity injected at an inclined angle is blocked from entering the silicon substrate 161 (that is, not injected therein). As a result, when the gate electrode 151 varies due to manufacturing process deviations, the gate electrode 151 serves as a basis for adaptively correcting the amount of p-type impurity injection.

[0036] Figure 6 The process in sub-figure F in FIG. 1 involves removing the resist pattern 211 to form a sidewall 152 on the gate electrode 151. The above process forms Figure 3 The cross-sectional structure shown.

[0037] Here, refer to Figure 7 and Figure 8The effect produced by the structure of the present disclosure (i.e., a structure in which p-type impurities are injected into a non-linear channel using a self-aligned mask) is described. When arranging pixel transistors, there are cases where a non-linear channel structure such as an L-shape is adopted due to layout constraints. In the structure of a transistor having a non-linear channel, the offset of the gate electrode position caused by manufacturing process deviations will change the channel length. This will affect electrical characteristics such as threshold voltage. In particular, the offset of the gate electrode position toward the outside or inside of the right-angle channel will affect the channel length in two directions. Therefore, the offset of the gate electrode position leads to the problem of increased individual differences.

[0038] Figure 7 The structure in which the gate electrode position is offset to the outside is shown. Figure 7 In FIG. 1 , the solid line represents the actual position of the gate electrode 151, and the dotted line 151I represents the ideal position of the gate electrode 151. Figure 7 As shown in the plan view of sub-figure A in FIG, if the actual position of the gate electrode 151 is offset from the ideal position to the outside, the channel length is shortened (as shown by arrows "a" in two directions in the figure), which reduces the threshold voltage of the transistor. In the structure of the present disclosure, when the position of the gate electrode 151 is offset to the outside, as shown in FIG. Figure 7 As shown in the cross-sectional view of sub-figure B in FIG. 1 , the implantation amount (dose) of the p-type impurity is increased by a self-aligned mask formed corresponding to the gate electrode 151 offset to the outside. This makes it possible to suppress a decrease in the threshold voltage of the transistor.

[0039] Figure 8 The structure in which the gate electrode position is offset inward is shown. Figure 8 As shown in the plan view of sub-figure A in FIG, when the actual position of the gate electrode 151 is shifted inward relative to the ideal position represented by the dotted line 151I, the channel length is extended (as shown by arrows "b" in both directions in the figure), which increases the threshold voltage of the transistor. In the structure of the present disclosure, when the position of the gate electrode 151 is shifted inward, as shown in FIG. Figure 8 As shown in the cross-sectional view of sub-figure B in FIG. 1 , the implantation amount (dose) of the p-type impurity is reduced by a self-aligned mask formed corresponding to the gate electrode 151 shifted inward. This makes it possible to suppress an increase in the transistor threshold voltage.

[0040] In the structure of the present disclosure described above, the amount of p-type impurities injected is changed by self-alignment, which suppresses individual differences in electrical characteristics due to deviations in the gate electrode manufacturing process. In particular, in the case where the element separation portion 131 is formed with an element separation structure using a through groove, since pixel transistors cannot be arranged on the element separation portion 131, it is easy to produce a transistor structure with a non-linear channel in layout. By adopting the structure of the present disclosure, this problem can be easily handled.

[0041] <Second Structure> Fig. 9 is a plan view showing an exemplary configuration of the pixel 100 .

[0042] and Figure 2 The pixel in the plan view is the same as 100. Fig. 9 The pixel 100 in the plan view of FIG. 1 has a photodiode and a pixel transistor. The pixel transistor includes a transfer transistor 111 , a capacitance switching transistor 112 , a reset transistor 113 , an amplification transistor 114 , and a selection transistor 115 .

[0043] and Figure 2 Compared with 100 pixels in the plan view, Fig. 9 The pixel 100 in the plan view of FIG. 1 has its photodiode separated by injecting impurities 133 into the silicon substrate 161. That is, Fig. 9 The pixel 100 in FIG. 1 has an element isolation structure based on impurity implantation, rather than relying on an element isolation structure having a through trench. Fig. 9 In the embodiment, the capacitance switching transistor 112 has an L-shaped non-linear channel 121 .

[0044] Fig.10 and Fig.11 yes Fig. 9 A cross-sectional view of the pixel 100 taken along line AA' in FIG. Fig.10 As shown, the capacitance switching transistor 112 has a structure in which impurities are implanted into the non-linear channel 121 by using a self-aligned mask. Fig.10 As shown in the plan view of sub-figure A in FIG, a resist pattern 211 having a wide opening is formed inside the L-shaped channel 121, so that p-type impurities are injected into the inside of the L-shaped channel 121 at an inclined angle (as shown by arrow I2 in the figure). Fig.10 As shown in the cross-sectional view of sub-figure B in FIG, the previously formed gate electrode 151 is used as a self-aligned mask to prevent a portion of the p-type impurities from being implanted into the silicon substrate 161. This makes it possible to adaptively correct the implantation amount of the p-type impurities when the gate electrode 151 is positionally shifted due to manufacturing process deviations.

[0045] like Fig.11 As shown, n-type impurities may be implanted into the outside of the non-linear channel 121 instead of implanting p-type impurities into the inside of the non-linear channel 121. Specifically, as Fig.11 As shown in the plan view of sub-figure A in FIG. 1 , a resist pattern 211 having a wide opening is formed outside the L-shaped channel 121, so that n-type impurities are injected into the outside of the L-shaped channel 121 at an inclined angle (as shown by arrow I3 in the figure). At this time, Fig.11As shown in the cross-sectional view of sub-figure B in FIG, the previously formed gate electrode 151 is used as a self-aligned mask to prevent a portion of the n-type impurities from being injected into the silicon substrate 161. Therefore, when the n-type impurities are injected into the outside of the L-shaped channel 121, the deviation of the threshold voltage can be suppressed as in the case where the p-type impurities are injected into the inside of the L-shaped channel 121.

[0046] Fig.10 FIG. 1 shows a structure in which p-type impurities are implanted into the inner side of the L-shaped channel 121. Fig.11 The structure of injecting n-type impurities into the outside of the L-shaped channel 121 is shown. These structures can be used alone or in combination. That is, according to the present disclosure, any one of the following three structures can be used: a structure of injecting p-type impurities into the inside of the non-linear channel 121, a structure of injecting n-type impurities into the outside of the non-linear channel 121, or a structure of injecting p-type impurities into the inside of the non-linear channel 121 and injecting n-type impurities into the outside of the non-linear channel 121.

[0047] Incidentally, also in the second configuration, the capacitance switching transistor 112 is an exemplary pixel transistor to which the structure of the present disclosure is applied. In the case where other transistors having non-linear channels are arranged in the pixel 100, the relevant transistors may also have a structure in which impurities are injected into the non-linear channels by using a self-aligned mask.

[0048] <Third Structure> Fig.12 is a cross-sectional view showing an exemplary configuration of the pixel 100 . Fig.12 The relationship between the photodiode and the pixel transistor in pixel 100 is shown.

[0049] exist Fig.12 In the embodiment, the photodiode 171 formed in the silicon substrate 161 has a buried structure and is located in a region away from the surface (Si interface) of the silicon substrate 161 in the stacking direction. An impurity region 172 injected with p-type impurities is formed between the photodiode 171 and the Si interface for separation between the two. In other words, Fig.12 The pixel 100 in FIG. 1 has a buried photodiode structure in which the photodiode 171 is located away from the Si interface and is separated from the Si interface by the p-type impurity region 172 .

[0050] The transfer transistor 111 transfers the charges stored in the photodiode 171 to the FD 121. The capacitance switching transistor 112 has a structure of the present disclosure, that is, a structure in which impurities are implanted into the non-linear channel 121 using a self-aligned mask (as indicated by arrow I4 in the figure).

[0051] here, Fig.13The structure of a pixel 100 that does not rely on a buried photodiode structure is shown for comparison. Fig.13 In the embodiment, the photodiode 171 formed in the silicon substrate 161 is located near the Si interface. The impurity region 172 is formed on the photodiode 171. In the structure of the present disclosure, when the p-type impurity is injected into the non-linear channel 121 by using a self-aligned mask, the area where the p-type impurity is injected becomes larger. For this reason, Fig.13 In the structure shown, that is, in a structure where the buried photodiode structure is not provided and the impurity region 172 for photodiode isolation is not arranged, the photodiode 171 may be affected by the impurity injection (as shown by the arrow I4 in the figure) performed by using a self-aligned mask into the non-linear channel 121. For example, the impurity injection may change the potential and reduce the size of the photodiode 171.

[0052] In view of the above, as the structure of the photodiode of the pixel 100, Fig.12 The buried photodiode structure shown is provided, and a p-type impurity region 172 is arranged for further photodiode separation. This makes it possible to prevent the photodiode 171 from being affected by the impurity implantation into the non-linear channel 121 by using a self-aligned mask.

[0053] Incidentally, in the third configuration, the capacitance switching transistor 112 is an exemplary pixel transistor to which the structure of the present disclosure is applied. In the case where other transistors having non-linear channels are arranged in the pixel 100, the transistors can also use the structure of the present disclosure. In this case as well, Fig.12 The buried photodiode structure shown is used, and a p-type impurity region 172 is arranged in transistors (other pixel transistors except the capacitance switching transistor 112) to which the structure of the present disclosure is applied for separation.

[0054] <Fourth Structure> Fig.14 and Fig.15 1 is a plan view and a cross-sectional view showing an exemplary configuration of the pixel 100. Here, Fig.14 The structure of vertically implanting impurities (along the stacking direction) into a non-linear channel by using a self-aligned mask is shown. Fig.15 A structure in which impurities are obliquely implanted into a non-linear channel at an oblique angle by using a self-aligned mask is shown.

[0055] Specifically, Fig.14 As shown in the plan view of sub-figure A in FIG. 1 , a resist pattern 211 is formed, and p-type impurities are injected into the inner side of the L-shaped channel 121 (as shown by arrow I5 in the figure). Fig.14As shown in the cross-sectional view of sub-figure B in FIG, when the p-type impurities are vertically injected into the inner side of the L-shaped channel 121 without a tilt angle (as shown by arrow I5 in the figure), the previously formed gate electrode 151 is used as a self-aligned mask.

[0056] In contrast, Fig.15 As shown in the plan view of sub-figure A in FIG. 1 , a resist pattern 211 is formed, and p-type impurities are injected into the inner side of the L-shaped channel 121 (as shown by arrow I6 in the figure). At this time, Fig.15 As shown in the cross-sectional view of sub-figure B in FIG, when the p-type impurity is injected into the inner side of the L-shaped channel 121 at an inclined angle (as shown by arrow I6 in the figure), the previously formed gate electrode 151 is used as a self-aligned mask.

[0057] Here, if Fig.15 As shown, in the case of injecting impurities at an inclined angle, the area of ​​the opening 221B needs to be enlarged in consideration of the shielding of the resist pattern 211. In this case, the p-type impurities injected over a large area may affect the photodiode and other pixel transistors. Fig.14 As shown, in the case of vertically implanting impurities, it is possible to reduce the area of ​​the opening 211A of the resist pattern 211. This makes it possible to suppress the above-mentioned adverse effects.

[0058] Specifically, in Fig.14 The opening 211A in the sub-graph A is Fig.15 In the case of comparing the opening 221B in the sub-figure A in FIG. 1 , the area of ​​the opening 211A is relatively smaller than the area of ​​the opening 221B, so that the injected impurities are less likely to affect the photodiode and other pixel transistors. That is, according to the structure of the present disclosure, it is very effective to inject impurities into the non-linear channel 121 at an inclined angle by using a self-aligned mask. However, considering the above-mentioned influence, it is more preferable to vertically inject impurities.

[0059] <Fifth Structure> Fig.16 and Fig.17 is a plan view showing an exemplary configuration of a pixel transistor. Fig.16 and Fig.17 In the embodiment, the pixel transistor 110 may be a pixel transistor of the pixel 100, including a capacitance switching transistor 112 having a non-linear channel 121, etc. That is, the pixel transistor 110 is a pixel transistor to which the structure of the present disclosure is applied.

[0060] exist Fig.16In the embodiment, the pixel transistor 110 is formed in such a way that the channel 121 has a right angle region (L shape). The impurities are injected into the inner side of the channel 121 (inside the L shape) by using a self-aligned mask (as shown by arrow I7 in the figure). In the case where the channel 121 has a right angle shape, the positional deviation of the gate electrode 151 has the greatest influence on the channel length. For this reason, Fig.16 As shown, in the case where impurities are injected into the channel 121 having a right angle shape by using a self-aligned mask, a more favorable effect is obtained. That is, in particular, in the case of a non-linear channel 121 having a right angle shape (L shape), it is expected to be significantly affected by the manufacturing process deviation of the gate electrode. Nevertheless, in this case, individual differences in electrical characteristics can also be suppressed.

[0061] exist Fig.17 In the embodiment, the pixel transistor 110 is shaped in such a way that the channel 121 has an obtuse area. Impurities are injected into the inner side (inner side of the shape) of the channel 121 by using a self-aligned mask (as shown by the arrow I8 in the figure). In the case where the channel 121 has an obtuse shape, the positional offset of the gate electrode 151 has less influence on the channel length than in the case of a right-angle shape. Nevertheless, a substantially similar effect can still be obtained by injecting impurities using a self-aligned mask. In addition, a pixel transistor 110 to which the structure disclosed in the present invention is applied and which includes a channel 121 having an obtuse shape rather than a right-angle shape can be provided for the pixel 100. This makes it possible to increase the degree of freedom in arranging pixel transistors in the pixel 100.

[0062] As described above, the structure of the present disclosure is a structure in which impurities are injected into a non-linear channel of a given pixel transistor by using a self-aligned mask corresponding to a gate electrode. Even in the case where the gate electrode is positionally offset during impurity injection, the above structure allows the amount of impurity injection to be changed by self-alignment. Therefore, the structure suppresses individual differences in electrical characteristics caused by manufacturing process deviations of the gate electrode, etc. For example, with the development of miniaturization of pixel structures, pixel transistors can be given non-linear channel shapes such as L-shaped due to layout constraints. However, in a transistor structure having a non-linear channel shape, the positional offset of the gate electrode caused by manufacturing process deviations changes the channel length. This in turn affects electrical characteristics such as threshold voltage. In a pixel transistor to which the structure of the present disclosure is applied, even in the case where the gate electrode is positionally offset, the amount of impurity injection can be changed by self-alignment, thereby suppressing individual differences in electrical characteristics. This makes it possible to improve the characteristics of the pixel transistor. As a result, the characteristics of a pixel having such a pixel transistor are improved.

[0063] <<Second Implementation Method>>

[0064] <First Structure> Fig.18 is a cross-sectional view showing an exemplary configuration of a pixel transistor in the pixel 100 . Fig.18 The cross-sectional view shows the stacking direction (depth direction) in which the constituent elements of the pixel 100 are stacked.

[0065] The pixel 100 has a photodiode as a photoelectric conversion element and a pixel transistor 110. The pixel transistor 110 includes a transfer transistor, a capacitance switching transistor, a reset transistor, an amplification transistor, a selection transistor, and the like. Figure 2 etc. have described these transistors in detail, so their description will be omitted here.

[0066] like Fig.18 As shown, in the pixel transistor 110, a sidewall 152 is formed on the side of a gate electrode 151 which is generally made of polysilicon, metal, etc. In addition, in the pixel transistor 110, each of the source region and the drain region is an impurity region in which phosphorus or arsenic is dispersed. For example, the concentration of phosphorus or arsenic is about 1×10 18 / cm 3 Up to 5×10 21 / cm 3 .exist Fig.18 In the embodiment, an impurity region 181 and an impurity region 182 are respectively formed on the source side and the drain side of the silicon substrate 161. The impurity region 181 on the source side and the impurity region 182 on the drain side are each a region with a high n-type impurity concentration.

[0067] In the pixel transistor 110, the overlap amount of the source side impurity region 181 with the gate electrode 151 and the side wall 152 and the overlap amount of the drain side impurity region 182 with the gate electrode 151 and the side wall 152 are compared as follows: In this structure, the overlap amount of the source side impurity region 181 is different from the overlap amount of the drain side impurity region 182. More specifically, in the pixel transistor 110, the overlap amount of the source side impurity region 181 with the gate electrode 151 and the side wall 152 is smaller than the overlap amount of the drain side impurity region 182 with the gate electrode 151 and the side wall 152.

[0068] Here, the miniaturization of the pixel structure requires reducing the size of the sidewalls in the pixel transistor. In addition, with respect to the structure under the layout area constraint caused by miniaturization, in addition to the straight line shape, it is proposed that the channel between the source region and the drain region has a non-linear shape (L shape) in the plan view. However, reducing the size of the sidewalls will bring the impurity regions of the source and drain closer to the gate electrode, thereby generating a strong electric field. The strong electric field will deteriorate the white point characteristics of the pixel (for example, increase the white points in the image). Therefore, with the limitation of the reduction of the sidewalls, there will be a problem of limited effect in improving the layout efficiency.

[0069] exist Fig.18In the embodiment, the pixel transistor 110 is constructed in such a way that the overlap amount on the source side is less than the overlap amount on the drain side. This makes it possible to reduce the electric field on the source side even if the side wall 152 is reduced, thereby improving the white spot characteristics. In addition, reducing the side wall 152 can improve the layout efficiency. Incidentally, in the case where the pixel transistor 110 is a reset transistor or a capacitor switching transistor, for example, because the white spot is caused by the strong electric field generated between the floating diffusion (FD), the white spot is called an FD white spot.

[0070] Fig.19 It is a diagram showing a structure including a structure for forming the present disclosure ( Fig.18 A diagram of a manufacturing method of a process of (a cross-sectional structure in). Fig.19 The process shown is performed after the process of forming the gate electrode 151 and the side wall 152 on the silicon substrate 161 .

[0071] Fig.19 The process shown involves obliquely implanting n-type impurities (impurity ions) into the silicon substrate 161 at an oblique angle on the source side of the gate electrode 151 (as shown by arrow I11). The oblique angle is a predetermined angle relative to the normal to the main surface of the substrate. For example, the oblique angle is the angle between the normal to the surface of the silicon substrate 161 and the ion beam. The impurity implantation utilizes the shielding of the gate electrode 151 and the sidewall 152 to form an impurity region 181 at a position away from the sidewall 152 on the source side. It should be noted that since the injection of n-type impurities on the drain side is not affected by shielding, a structure is created in which the amount of overlap between the source side impurity region 181 and the gate electrode 151 and the sidewall 152 is less than the amount of overlap between the drain side impurity region 182 and the gate electrode 151 and the sidewall 152. This makes it possible to form Fig.18 The cross-sectional structure shown.

[0072] The above-described manufacturing method involving simple implantation of impurities at an oblique angle provides the benefit of reducing the electric field without increasing the number of steps involved. Fig. 20 As shown, when the electric field magnitude at the end of the gate electrode 151 in the pixel transistor 110 is represented on the vertical axis, and the tilt angle when the impurity is injected is represented on the horizontal axis, the relationship between the electric field magnitude and the tilt angle of the impurity injection that generates the electric field is drawn by the curve L1. That is, in the absence of a tilt angle when the impurity is injected, a strong electric field is generated at the end of the gate electrode 151. However, for example, by simply setting a relatively small tilt angle of 10°, 15°, etc., the electric field can be significantly improved. In this way, the larger the tilt angle for injecting impurities is set, the farther the impurity region 181 is formed from the side wall 152 on the source side. As a result, the effect of reducing the electric field is enhanced, thereby improving the electric field.

[0073] <Second Structure> Fig.21is a plan view showing an exemplary configuration of the pixel transistor 110 . Fig.21 The pixel transistor 110 is shown to be configured in such a way that the channel 121 has a straight-line region between the source region and the drain region.

[0074] exist Fig.21 In the case where the channel 121 has a straight line shape, the n-type impurity implantation on the source side and the drain side is performed at an inclined angle relative to the gate electrode 151 and the side wall 152 (as shown by the arrow I12 in the figure). At this time, the shielding of the gate electrode 151 and the side wall 152 reduces the overlap amount of the source side impurity region 181 with the gate electrode 151 and the side wall 152. In contrast, the shielding increases the overlap amount of the drain side impurity region 182 with the gate electrode 151 and the side wall 152.

[0075] exist Fig.21 In FIG. 1 , the distance d1 between the source side impurity region 181 and the gate electrode 151 changes according to the tilt angle when the impurity is injected. That is, by using the gate electrode 151 and the sidewall 152 as a mask on the source side, the impurity is less likely to enter the vicinity of the gate electrode 151. Although the intrusion into the drain side changes according to the tilt angle when the impurity is injected, the white spot characteristic is determined by the electric field on the source side. This means that the white spot characteristic does not deteriorate due to the increase in the overlap amount on the drain side.

[0076] In the case where the channel 121 has the linear shape described above, the impurity implantation on the source side and the drain side is performed at an inclined angle relative to the gate electrode 151 and the side wall 152. This allows the gate electrode 151 and the side wall 152 to act as a pseudo mask when forming the source side impurity region 181. Therefore, in the case where the source side and the drain side are configured to be asymmetrical, the overlap amount on the source side can be made smaller than the overlap amount on the drain side.

[0077] <Third Structure> Fig. 22 is a plan view showing an exemplary configuration of the pixel transistor 110 . Fig. 22 The pixel transistor 110 is shown to be configured in such a way that the channel 121 has a right-angled L-shaped region between the source region and the drain region.

[0078] exist Fig. 22 In the case where the channel 121 has an L shape, the n-type impurity injection on the source side and the drain side is performed at an inclined angle relative to the gate electrode 151 and the side wall 152 (as shown by the arrow I13 in the figure). At this time, the shielding of the gate electrode 151 and the side wall 152 reduces the overlap amount of the source side impurity region 181 with the gate electrode 151 and the side wall 152. In contrast, the overlap amount of the drain side impurity region 182 with the gate electrode 151 and the side wall 152 remains fixed and is determined only by the width of the side wall 152.

[0079] exist Fig. 22 In the embodiment, the distance d2 between the source side impurity region 181 and the gate electrode 151 varies according to the tilt angle when the impurities are injected. That is, by using the gate electrode 151 and the sidewall 152 as a mask on the source side, impurities are less likely to enter the vicinity of the gate electrode 151.

[0080] In the case where the channel 121 has the L-shape described above, the impurity implantation on the source side and the drain side is performed at an inclined angle relative to the gate electrode 151 and the side wall 152. This allows the gate electrode 151 and the side wall 152 to act as a pseudo mask when forming the source side impurity region 181. In addition, on the drain side, regardless of the inclined angle, the impurity is vertically implanted to form the impurity region 182 corresponding to the width of the side wall 152. Therefore, in the case where the source side and the drain side are configured to be asymmetrical, the overlap amount on the source side can be made smaller than the overlap amount on the drain side.

[0081] <Fourth Structure> Fig.23 is a cross-sectional view showing an exemplary configuration of the pixel transistor 110 .

[0082] exist Fig.23 In the cross-sectional view of the pixel transistor 110, Fig.18 Compared to the pixel transistor 110 in the cross-sectional view of , the overlap amount of the source side impurity region with the gate electrode 151 and the side wall 152 is different from the overlap amount of the drain side impurity region with the gate electrode 151 and the side wall 152. More specifically, Fig.23 The pixel transistor 110 in the cross-sectional view of FIG. 1 is structured in such a way that the overlap amount of the drain-side impurity region 182 with the gate electrode 151 and the side wall 152 is smaller than the overlap amount of the source-side impurity region 181 with the gate electrode 151 and the side wall 152 .

[0083] Here, the 1 / f noise is more susceptible to the interface state under the sidewall 152 on the source side than the interface state under the sidewall 152 on the drain side. Since the pixel transistor 110 is configured such that the overlap amount on the drain side is smaller than the overlap amount on the source side, the interface state under the sidewall 152 on the source side is not activated, thereby reducing the 1 / f noise.

[0084] It should be noted that when making Fig.23 When the cross-sectional structure shown in FIG. 1 is used, for example, impurities can be implanted into the silicon substrate 161 at an inclined angle relative to the gate electrode 151 on the drain side. This allows shielding by the gate electrode 151 and the sidewall 152 to form the impurity region 182 at a position away from the sidewall 152 on the drain side. At this time, the impurities are implanted on the source side without being affected by the shielding. This makes it possible to produce a structure in which the amount of overlap on the drain side is smaller than the amount of overlap on the source side (i.e., an asymmetric structure).

[0085] According to the present disclosure, as described above, the pixel transistor is constructed in a manner that the amount of overlap between the source side impurity region and the gate electrode and the side wall is different from the amount of overlap between the drain side impurity region and the gate electrode and the side wall. In particular, the amount of overlap between the source side impurity region and the gate electrode and the side wall can be made smaller than the amount of overlap between the drain side impurity region and the gate electrode and the side wall. This structure makes it possible to reduce the side wall without deteriorating the white point characteristic, thereby improving the layout efficiency. In addition, by setting the inclination angle of the impurity injection during the currently performed process, an asymmetrically constructed source side impurity region and a drain side impurity region can be formed. Therefore, the layout efficiency can be improved and the white point characteristic can be improved without increasing the number of processes. Therefore, the pixel transistor applying the structure of the present disclosure can improve the layout efficiency of the pixel and improve the white point characteristic of the pixel. This in turn can improve the characteristics of the pixel transistor, and as a result, the characteristics of the pixel including the pixel transistor constructed as described above can be improved. It should be noted that although the structure of the present disclosure can be applied to pixel transistors such as reset transistors and capacitor switching transistors in view of improving the white point characteristic (FD white point), the structure of the present disclosure can also be applied to other pixel transistors.

[0086] <<Modifications>>

[0087] <Other Exemplary Configurations> In the above description, it is assumed that the solid-state imaging device 10 is a back-illuminated solid-state imaging device. Alternatively, the solid-state imaging device 10 may be a front-illuminated solid-state imaging device. The back-illuminated solid-state imaging device here is constructed in such a manner that, when viewed from a silicon substrate on which a photodiode as a photoelectric conversion element is provided, light is incident on an upper layer (back side) opposite to a wiring layer side (front side) formed in a lower layer. The front-illuminated solid-state imaging device is constructed so that light is incident on the wiring layer side (front side).

[0088] The solid-state imaging device 10 is an exemplary light detection device to which the present disclosure is applied. That is, the light detection device to which the present disclosure is applied can be used not only as the solid-state imaging device 10 but also as any other light detection device such as a distance measuring sensor using an IR laser. Incidentally, not only a CMOS solid-state imaging device can adopt a structure to which the present disclosure is applied, but other solid-state imaging devices such as a CCD (charge coupled device) solid-state imaging device can also adopt a structure to which the present disclosure is applied.

[0089] In the solid-state imaging device 10, each pixel 100 arranged two-dimensionally in the pixel array unit 21 can be provided with not only one photodiode, but also two or more photodiodes as a photoelectric conversion element. In addition, the pixel transistor provided in the pixel 100 can include not only a transfer transistor, a capacitor switching transistor, a reset transistor, an amplification transistor, and a selection transistor, but also other transistors in addition to these transistors. As another option, it is not necessary to provide a capacitor switching transistor as a pixel transistor. It should be noted that in this specification, p-type and n-type are examples of a first conductivity type and a second conductivity type, respectively. Alternatively, the first conductivity type and the second conductivity type may be n-type and p-type, respectively.

[0090] <Structure of electronic equipment> The solid-state imaging device to which the present disclosure is applied can be mounted on electronic devices such as smartphones, tablet terminals, mobile phones, digital cameras, and digital video cameras. Fig.24 : is a block diagram showing an exemplary configuration of an electronic device equipped with a solid-state imaging device to which the present disclosure is applied.

[0091] exist Fig.24 In the embodiment, the electronic device 1000 has a camera system, which includes an optical system 1011 having a lens group, Figure 1 The electronic device 1000 is configured such that, in addition to the imaging system, a CPU (Central Processing Unit) 1010, a frame memory 1014, a display 1015, an operating system 1016, an auxiliary memory 1017, a communication I / F 1018, and a power supply system 1019 connected to each other via a bus 1020 are added.

[0092] The CPU 1010 controls the operation of the components constituting the electronic device 1000. The optical system 1011 receives incident light (image light) from a subject to form an image on a light detection surface of the solid-state imaging device 1012. The solid-state imaging device 1012 converts the amount of incident light focused on the light detection surface by the optical system 1011 into an electrical signal in units of pixels before outputting the electrical signal. The DSP 1013 performs predetermined signal processing on the signal output from the solid-state imaging device 1012.

[0093] The frame memory 1014 temporarily records the image data of the still or moving image captured by the camera system. The display 1015 is a liquid crystal display or an organic EL display that displays the still or moving image captured by the camera system. The operating system 1016 issues operation commands for various functions of the electronic device 1000 in response to the user's operation.

[0094] The auxiliary memory 1017 is a storage medium including a semiconductor memory such as a flash memory, and records image data of a still or moving image acquired by the camera system. The communication I / F 1018 has a communication module supporting a predetermined communication system. The communication I / F 1018 transmits image data of a still or moving image captured by the camera system to other types of devices.

[0095] The power supply system 1019 supplies various power sources used as operation power sources to the CPU 1010 , the DSP 1013 , the frame memory 1014 , the display 1015 , the operating system 1016 , the auxiliary memory 1017 , and the communication I / F 1018 as necessary.

[0096] <Application examples for mobile objects> The technology disclosed herein (the present technology) can be applied to various products. For example, the technology disclosed herein can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0097] Fig.25 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0098] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.25 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0099] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 is used as a control device for the following devices: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a vehicle braking force, etc.

[0100] The body system control unit 12020 controls the operation of various types of devices provided on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal light, a fog light, etc. In this case, a radio wave transmitted from a mobile device that replaces the key or a signal of various types of switches may be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0101] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform detection processing of objects such as people, vehicles, obstacles, signs, characters on the road surface, etc., or may perform detection processing of the distance to the above-mentioned objects.

[0102] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0103] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that takes a picture of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0104] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information outside or inside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output the control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, speed keeping driving, vehicle collision warning, vehicle lane departure warning, etc.

[0105] In addition, by controlling the driving force generating device, steering mechanism, braking device, etc. based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 is able to perform collaborative control aimed at achieving automatic driving, etc., wherein the automatic driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0106] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam, for example, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0107] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle's passengers or the outside of the vehicle of information. Fig.25 In the example of , as the output device, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0108] Fig.26 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0109] exist Fig.26 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0110] The camera units 12101, 12102, 12103, 12104 and 12105 are arranged, for example, at the front nose, rearview mirror, rear bumper and rear door of the vehicle 12100 and at the upper part of the windshield in the vehicle compartment. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly obtain images on both sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect vehicles in front, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0111] By the way, Fig.26An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from above is obtained.

[0112] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0113] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the camera ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100), thereby extracting the nearest three-dimensional object as the front vehicle, in particular, the three-dimensional object exists on the driving path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be maintained with the front vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control such as automatic driving aimed at making the vehicle travel autonomously without relying on the operation of the driver can be performed.

[0114] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 is difficult to visually identify. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collisions.

[0115] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may identify a pedestrian, for example, by determining whether a pedestrian exists in the camera images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following steps: a step of extracting feature points in the camera images of the camera units 12101 to 12104 as infrared cameras; and a step of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the camera images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0116] The vehicle control system as an example to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the camera unit 12031 in the above-mentioned components. Specifically, for example, Figure 1 The solid-state imaging device 10 in FIG. 1 is used as the imaging section 12031. Applying the technology according to the present disclosure to the imaging section 12031 allows an image to be captured with higher definition. This makes it possible to more accurately recognize objects such as pedestrians, for example.

[0117] The embodiments of the present disclosure are not limited to the above embodiments, and various modifications may be made as long as they are within the scope of the present disclosure. For example, the first and second embodiments may be implemented alone or in combination. The advantageous effects described in this specification are merely examples and do not limit the present disclosure. Other advantageous effects may also be present.

[0118] The present disclosure can adopt the following configurations. (1) A solid-state imaging device, comprising: a pixel array section in which a plurality of pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, The pixel transistor includes a transistor having a structure in which impurities are implanted into a channel having a non-linear shape in a plan view by using a self-aligned mask corresponding to a gate electrode. (2) According to the solid-state imaging device described in (1) above, The pixel has an element separation structure in which a groove penetrates a silicon substrate in which the photoelectric conversion element is formed in a stacking direction in a cross-sectional view. (3) According to the solid-state imaging device described in (1) above, The pixel has an element separation structure in which impurities are implanted into a silicon substrate in which the photoelectric conversion element is formed. (4) According to the solid-state imaging device described in (1) above, The pixel has an element separation structure in which a silicon substrate in which the photoelectric conversion element is formed is dug out along a stacking direction in a cross-sectional view and an oxide film is buried. (5) According to the solid-state imaging device described in (1) above, The pixel has: an element separation structure in which a groove penetrates a silicon substrate in which the photoelectric conversion element is formed in a stacking direction in a cross-sectional view; and an element separation structure in which the silicon substrate is dug in the stacking direction and an oxide film is buried. (6) The solid-state imaging device according to any one of (1) to (5) above, The transistor is shaped in such a manner that the channel has a right-angle region in a plan view. (7) The solid-state imaging device according to any one of (1) to (5) above, The transistor is shaped in such a manner that the channel has an obtuse angle region in a plan view. (8) The solid-state imaging device according to any one of (1) to (5) above, The impurities are implanted obliquely at an oblique angle in the cross-sectional view. (9) The solid-state imaging device according to any one of (1) to (5) above, The impurities are implanted vertically in the cross-sectional view. (10) According to the solid-state imaging device described in (3) above, The transistor has a structure in which p-type impurities are implanted into the inner side of the shape of the channel by using the self-aligned mask. (11) According to the solid-state imaging device described in (3) or (10) above, The transistor has a structure in which n-type impurities are implanted outside the shape of the channel by using the self-aligned mask. (12) According to the solid-state imaging device described in (1) above, wherein the photoelectric conversion element comprises a photodiode, and The pixel has a buried photodiode structure in which the photodiode is buried in a region away from a surface of a silicon substrate in a stacking direction in a cross-sectional view and is separated by an impurity region. (13) A solid-state imaging device, comprising: a pixel array section in which a plurality of pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, The pixel transistor includes a transistor having a structure in which an overlap amount of a first impurity region on a source side with a gate electrode and a side wall is different from an overlap amount of a second impurity region on a drain side with the gate electrode and the side wall. (14) According to the solid-state imaging device described in (13) above, The transistor has a structure in which an overlap amount of the first impurity region with the gate electrode and the side wall is smaller than an overlap amount of the second impurity region with the gate electrode and the side wall. (15) According to the solid-state imaging device described in (13) above, The transistor has a structure in which an overlap amount of the second impurity region with the gate electrode and the side wall is smaller than an overlap amount of the first impurity region with the gate electrode and the side wall. (16) The solid-state imaging device according to any one of (13) to (15) above, The transistor has the following structure: in this structure, after the gate electrode and the side wall are formed, impurities are injected at an inclined angle on the source side or the drain side of the gate electrode, and impurities are injected at a position away from the side wall on the source side or the drain side by using the gate electrode and the side wall to provide shielding, so as to form the first impurity region and the second impurity region. (17) The solid-state imaging device according to any one of (13) to (15) above, The source region and the drain region each include an impurity region in which phosphorus or arsenic is dispersed. (18) According to the solid-state imaging device described in (13) above, The transistor is formed in such a manner that a channel formed between a region of the source and a region of the drain has a right angle region in a plan view. (19) According to the solid-state imaging device described in (18) above, The transistor has a structure in which an overlap amount of the first impurity region with the gate electrode and the side wall is smaller than an overlap amount of the second impurity region with the gate electrode and the side wall. (20) According to the solid-state imaging device described in (18) above, The transistor has a structure in which an overlap amount of the second impurity region with the gate electrode and the side wall is smaller than an overlap amount of the first impurity region with the gate electrode and the side wall. (twenty one) The solid-state imaging device according to any one of (18) to (20) above, The transistor has the following structure: in this structure, after the gate electrode and the side wall are formed, impurities are injected at an inclined angle on the source side or the drain side of the gate electrode, and impurities are injected at a position away from the side wall on the source side or the drain side by using the gate electrode and the side wall to provide shielding, so as to form the first impurity region and the second impurity region. (twenty two) The solid-state imaging device according to any one of (18) to (20) above, The region of the source electrode and the region of the drain electrode are each an impurity region in which phosphorus or arsenic is dispersed. Reference numerals list

[0120] 10: Solid-state imaging device 21: Pixel array section 22: Vertical drive unit 23: Column signal processing unit 24: Horizontal drive unit 25: Output 26: Control Department 42: Vertical signal line 100: Pixels 110: Pixel transistor 111: Pass transistor 112: Capacitor switching transistor 113: Reset transistor 114: Amplifying transistor 115: Select transistor 121, 121-1, 121-2: FD 121: Channel 131: Component separation unit 132: Component separation unit 151: Gate electrode 152: Sidewall 161: Silicon substrate 162: Impurity area 171: Photodiode 172: Impurity region 181: Impurity region 182: Impurity area 1000: Electronic equipment 1012: Solid-state imaging device

Claims

1. A solid-state imaging device, comprising: a pixel array section in which a plurality of pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, The pixel transistor includes a transistor having a structure in which impurities are implanted into a channel having a non-linear shape in a plan view by using a self-aligned mask corresponding to a gate electrode.

2. The solid-state imaging device according to claim 1, The pixel has an element separation structure in which a groove penetrates a silicon substrate in which the photoelectric conversion element is formed in a stacking direction in a cross-sectional view.

3. The solid-state imaging device according to claim 1, The pixel has an element separation structure in which impurities are implanted into a silicon substrate in which the photoelectric conversion element is formed.

4. The solid-state imaging device according to claim 1, The pixel has an element separation structure in which a silicon substrate in which the photoelectric conversion element is formed is dug out along a stacking direction in a cross-sectional view and an oxide film is buried.

5. The solid-state imaging device according to claim 1, The pixel has: an element separation structure in which a groove penetrates a silicon substrate in which the photoelectric conversion element is formed in a stacking direction in a cross-sectional view; and an element separation structure in which the silicon substrate is dug in the stacking direction and an oxide film is buried.

6. The solid-state imaging device according to claim 1, The transistor is shaped in such a manner that the channel has a right-angle region in a plan view.

7. The solid-state imaging device according to claim 1, The transistor is shaped in such a manner that the channel has an obtuse angle region in a plan view.

8. The solid-state imaging device according to claim 1, The impurities are implanted obliquely at an oblique angle in the cross-sectional view.

9. The solid-state imaging device according to claim 1, The impurities are implanted vertically in the cross-sectional view.

10. The solid-state imaging device according to claim 3, The transistor has a structure in which p-type impurities are implanted into the inner side of the shape of the channel by using the self-aligned mask.

11. The solid-state imaging device according to claim 3, The transistor has a structure in which n-type impurities are implanted outside the shape of the channel by using the self-aligned mask.

12. The solid-state imaging device according to claim 1, wherein the photoelectric conversion element comprises a photodiode, and The pixel has a buried photodiode structure in which the photodiode is buried in a region away from a surface of a silicon substrate in a stacking direction in a cross-sectional view and is separated by an impurity region.

13. A solid-state imaging device, comprising: a pixel array section in which a plurality of pixels are two-dimensionally arranged, each of the pixels including a photoelectric conversion element and a pixel transistor, The pixel transistor includes a transistor having a structure in which an overlap amount of a first impurity region on a source side with a gate electrode and a side wall is different from an overlap amount of a second impurity region on a drain side with the gate electrode and the side wall.

14. The solid-state imaging device according to claim 13, The transistor has a structure in which an overlap amount of the first impurity region with the gate electrode and the side wall is smaller than an overlap amount of the second impurity region with the gate electrode and the side wall.

15. The solid-state imaging device according to claim 13, The transistor has a structure in which an overlap amount of the second impurity region with the gate electrode and the side wall is smaller than an overlap amount of the first impurity region with the gate electrode and the side wall.

16. The solid-state imaging device according to claim 13, The transistor has the following structure: in this structure, after the gate electrode and the side wall are formed, impurities are injected at an inclined angle on the source side or the drain side of the gate electrode, and impurities are injected at a position away from the side wall on the source side or the drain side by using the gate electrode and the side wall to provide shielding, so as to form the first impurity region and the second impurity region.

17. The solid-state imaging device according to claim 13, The source region and the drain region each include an impurity region in which phosphorus or arsenic is dispersed.

18. The solid-state imaging device according to claim 13, The transistor is formed in such a manner that a channel formed between a region of the source and a region of the drain has a right angle region in a plan view.

19. The solid-state imaging device according to claim 18, The transistor has a structure in which an overlap amount of the first impurity region with the gate electrode and the side wall is smaller than an overlap amount of the second impurity region with the gate electrode and the side wall.

20. The solid-state imaging device according to claim 18, The transistor has a structure in which an overlap amount of the second impurity region with the gate electrode and the side wall is smaller than an overlap amount of the first impurity region with the gate electrode and the side wall.

21. The solid-state imaging device according to claim 18, The transistor has the following structure: in this structure, after the gate electrode and the side wall are formed, impurities are injected at an inclined angle on the source side or the drain side of the gate electrode, and impurities are injected at a position away from the side wall on the source side or the drain side by using the gate electrode and the side wall to provide shielding, so as to form the first impurity region and the second impurity region.

22. The solid-state imaging device according to claim 18, The region of the source electrode and the region of the drain electrode are each an impurity region in which phosphorus or arsenic is dispersed.

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