Overelectric stress detection circuit, controller, method for detecting overelectric stress, and vehicle

Abstract

The invention discloses a chip over-electric stress detection circuit, a controller, a method for detecting chip over-electric stress and a vehicle, the chip over-electric stress detection circuit comprises a detection circuit module, the detection circuit module comprises a voltage dividing unit and a comparator; wherein the first end of the voltage dividing unit is suitable for being connected with a target port of a chip, and the voltage dividing unit is used for collecting an over-electric stress detection signal of the target port and obtaining a voltage dividing signal of the over-electric stress signal; the first input end of the comparator is connected with the second end of the voltage dividing unit, and the comparator is used for outputting an over-electric stress fault signal when the voltage dividing signal exceeds an over-electric stress detection signal threshold value. By adopting the circuit, whether the chip is impacted by the over-electric stress can be detected, and an over-electric stress fault signal is output when the chip is detected to be impacted by the over-electric stress, so that data support can be provided for determining the reason of the fault of the chip caused by the over-electric stress, and fault analysis and technical improvement on the chip are facilitated.

Description

Technical Field

[0001] The present invention relates to the field of vehicle technology, and in particular to a chip over-electrical stress detection circuit, a controller, a method for detecting chip over-electrical stress, and a vehicle. Background Art

[0002] In the prior art, a transient voltage suppression diode is set at the chip port, and the transient voltage suppression diode can clamp and absorb the over-electrical stress to prevent the chip from over-electrical stress. However, the power of the transient voltage suppression diode to clamp and absorb is limited. Once the over-electrical stress exceeds the power that the transient voltage suppression diode can withstand, the transient voltage suppression diode will be broken down, and the internal circuit of the chip will lose protection and cause failure and damage. When the chip is damaged by over-electrical stress, there is a lack of evidence to prove that the failure of the chip is caused by over-electrical stress, rather than by design or manufacturing errors of the chip, and the root cause of the chip failure cannot be determined. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present invention is to provide a chip over-electric stress detection circuit, which can detect whether the chip is subjected to over-electric stress impact, and output an over-electric stress fault signal when the chip is detected to be subjected to over-electric stress impact, thereby providing data support for determining the cause of chip failure due to over-electric stress, and facilitating chip failure analysis and technical improvement.

[0004] The second objective of the present invention is to provide a controller.

[0005] The third object of the present invention is to provide a method for detecting chip over-electrical stress.

[0006] A fourth object of the present invention is to provide a vehicle.

[0007] In order to solve the above problems, an embodiment of the first aspect of the present invention provides a chip over-electrical stress detection circuit, including: a detection circuit module, the detection circuit module includes a voltage divider unit and a comparator; wherein the first end of the voltage divider unit is suitable for connecting to the target port of the chip to be tested, for collecting the input electrical signal of the chip to be tested from the target port and obtaining the voltage divided signal of the input electrical signal; the first input end of the comparator is connected to the second end of the voltage divider unit, for outputting an over-electrical stress fault signal when the voltage divided signal exceeds the over-electrical stress detection signal threshold.

[0008] According to the over-electrical stress detection circuit of the embodiment of the present invention, by connecting the target port of the chip to be tested with the voltage divider unit, the voltage divider signal of the input electrical signal of the chip to be tested input into the target port can be obtained, and the comparator outputs an over-electrical stress fault signal when the voltage divider signal exceeds the over-electrical stress detection signal threshold, thereby realizing the detectability of the over-electrical stress of the chip to be tested, providing data support for the fault analysis of the chip, providing evidence for determining that the chip fails due to over-electrical stress, avoiding the assumption that the chip has design or manufacturing defects, and being more conducive to fault analysis and technical improvement of the chip.

[0009] In some embodiments, the chip over-electrical stress detection circuit further includes: a signal holding module, wherein the input end of the signal holding module is connected to the first output end of the comparator, and the output end of the signal holding module is connected to the chip for maintaining the over-electrical stress fault signal.

[0010] In some embodiments, the chip over-electrical stress detection circuit also includes: a clearing module, a first end of the clearing module is connected to the signal holding module, and a second end of the clearing module is connected to the chip, for controlling the signal holding module to clear the over-electrical stress fault signal in response to a clearing instruction of the chip.

[0011] In some embodiments, the chip over-electrical stress detection circuit further includes: at least one high-pass filter module, and the first end of the voltage divider unit is connected to the corresponding target port through the at least one high-pass filter module.

[0012] In some embodiments, the voltage divider unit includes: a first resistor, a first end of the first resistor is connected to the target port; a second resistor, a first end of the second resistor is connected to the second end of the first resistor, the second end of the second resistor is grounded, and there is a first node between the first end of the second resistor and the second end of the first resistor, and the first node is connected to the first input terminal of the comparator.

[0013] In some embodiments, the detection circuit module also includes: a first diode and a third resistor, the first node is connected to the first input terminal of the comparator through the first diode and the third resistor, wherein the positive terminal of the first diode is connected to the first node, the negative terminal of the first diode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first input terminal of the comparator.

[0014] In some embodiments, the detection circuit module further includes: a fourth resistor, a first end of the fourth resistor is connected to the first input end of the comparator and the second end of the third resistor, and a second end of the fourth resistor is grounded.

[0015] In some embodiments, the detection circuit module also includes: a threshold providing circuit, a first end of the threshold providing circuit is connected to a first end of a power supply, a second end of the threshold providing circuit is grounded, and a third end of the threshold providing circuit is connected to a second input end of the comparator, for providing the over-electrical stress detection signal threshold.

[0016] In some embodiments, the threshold providing circuit includes: a fifth resistor, a first end of the fifth resistor is connected to the first end of the power supply; a sixth resistor, a first end of the sixth resistor is connected to the second end of the fifth resistor, the second end of the sixth resistor is grounded, and a second node is provided between the first end of the sixth resistor and the second end of the fifth resistor, and the second node is connected to the second input end of the comparator.

[0017] In some embodiments, the comparator further includes a first power supply terminal, a second power supply terminal and a second output terminal, the first power supply terminal is connected to the first terminal of the power supply, the second power supply terminal is grounded, and the second output terminal is connected to the first power supply terminal.

[0018] In some embodiments, the signal holding module includes: a first switch tube, wherein the control end of the first switch tube is connected to the first output end of the comparator, the first end of the first switch tube is connected to the first end of the power supply through a seventh resistor, and the second end of the first switch tube is grounded; a second switch tube, wherein the control end of the second switch tube is connected to the first end of the first switch tube, the first end of the second switch tube is grounded, and the second end of the second switch tube is connected to the first end of the power supply through an eighth resistor; wherein the first switch tube and the second switch tube are turned on in response to the over-current stress fault signal to maintain the output of the over-current stress fault signal.

[0019] In some embodiments, the signal holding module also includes: a ninth resistor, a first end of the ninth resistor is connected to the first output end of the comparator, and a second end of the ninth resistor is connected to the control end of the first switch tube; a tenth resistor, a first end of the tenth resistor is connected to the first end of the second switch tube, the control end of the first switch tube and the second end of the ninth resistor.

[0020] In some embodiments, the signal holding module further includes: a first filter, a first end of the first filter is connected to the first output end of the comparator and the first end of the ninth resistor, and a second end of the first filter is grounded.

[0021] In some embodiments, the signal holding module also includes: a second filter, a first end of the second filter is connected to the control end of the first switch tube, a third node is provided between the first end of the second filter and the control end of the first switch tube to serve as the output end of the signal holding module, and a second end of the second filter is grounded.

[0022] In some embodiments, the signal holding module further includes: a third filter, a first end of the third filter is connected to the control end of the second switch tube, and a second end of the third filter is connected to the control end of the first switch tube.

[0023] In some embodiments, the zeroing module includes: a third switch tube, the control end of the third switch tube is connected to the chip, the first end of the third switch tube is grounded, and the second end of the third switch tube is connected to the second end of the second switch tube, and is used to respond to the zeroing instruction of the chip to issue a zeroing signal to clear the over-voltage stress fault signal.

[0024] A second aspect of the present invention provides a controller, comprising: at least one chip over-electrical stress detection circuit as described in the above embodiments; a main control chip, wherein the main control chip comprises at least one target port, and the at least one target port is connected to the at least one chip over-electrical stress detection circuit.

[0025] The controller according to the embodiment of the present invention is connected to the chip over-electrical stress detection circuit through the target port of the main control chip, so as to detect whether the main control chip is subjected to over-electrical stress shock during operation. When it is detected that the main control chip is subjected to over-electrical stress shock, the chip over-electrical stress detection circuit outputs an over-electrical stress fault signal, thereby realizing the detectability of over-electrical stress of the main control chip, thereby providing data support for determining the cause of failure of the main control chip due to over-electrical stress, and facilitating fault analysis and technical improvement of the main control chip.

[0026] In some embodiments, the controller includes a plurality of the chip over-electrical stress detection circuits; the main control chip includes a plurality of the target ports, and the plurality of the target ports are respectively connected one-to-one with the plurality of the chip over-electrical stress detection circuits.

[0027] In some embodiments, each of the chip over-electrical stress detection circuits is connected to the corresponding chip over-electrical stress detection circuit via a high-pass filtering module.

[0028] In some embodiments, the controller includes one chip over-electrical stress detection circuit; the main control chip includes multiple target ports, and the multiple target ports are respectively connected to the chip over-electrical stress detection circuit through a high-pass filtering module.

[0029] In some embodiments, the plurality of target ports include a power port; one of the chip over-current stress detection circuits is connected to the power port via a high-pass filter unit, and the power supply connected to the power port supplies power to the chip over-current stress detection circuit.

[0030] In some embodiments, the controller further includes: an instant register connected to the main control chip and used to store the current over-voltage stress fault signal.

[0031] In some embodiments, the controller further includes: a history register connected to the main control chip, and used to store a preset number of historical over-electrical stress fault signals and time information of generation of the historical over-electrical stress fault signals.

[0032] In some embodiments, a second diode is located between the target port and the chip over-electrical stress detection circuit, and is used to clamp and absorb the over-electrical stress signal.

[0033] The third aspect of the present invention provides a method for detecting chip over-electrical stress, which is used for the controller described in the above embodiment. The method includes: obtaining register information of the over-electrical stress fault signal; determining that the main control chip has over-electrical stress based on the register information, and issuing a chip over-electrical stress fault alarm.

[0034] According to the method for detecting chip over-electrical stress in an embodiment of the present invention, the chip over-electrical stress detection circuit stores the output over-electrical stress fault signal in a register. The register information can be used to determine whether the main control chip has over-electrical stress, thereby providing data support for determining the cause of the main control chip failure due to over-electrical stress, and facilitating fault analysis and technical improvement of the main control chip.

[0035] In some embodiments, determining that over-electrical stress has occurred on the main control chip based on the register information includes: detecting information stored in the historical register of the controller; determining that the information stored in the historical register includes an over-electrical stress fault signal generated by the current functional self-test of the main control chip, and then determining that over-electrical stress has occurred on the main control chip.

[0036] In some embodiments, in response to the over-stress fault signal of the chip over-stress detection circuit, the immediate register and the historical register of the controller are respectively set to correspond to the over-stress fault occurring in the main control chip, and the historical register is controlled to save the time information corresponding to the occurrence of the over-stress fault.

[0037] In some embodiments, in response to the over-stress fault signal of the chip over-stress detection circuit, the instant register and the historical register of the controller are respectively set to correspond to the over-stress fault of the main control chip, and then a clear instruction is sent to the chip over-stress detection circuit.

[0038] A fourth aspect of the present invention provides a vehicle, comprising the controller described in the above embodiment.

[0039] In a vehicle according to an embodiment of the present invention, a chip over-current stress detection circuit is set in the controller, and the main control chip is connected to the chip over-current stress detection circuit through a target port, so as to detect whether the main control chip is subjected to over-current stress shock during operation. When it is detected that the main control chip is subjected to over-current stress shock, the chip over-current stress detection circuit outputs an over-current stress fault signal, thereby providing data support for determining the cause of the main control chip failure, and facilitating fault analysis and technical improvement of the main control chip.

[0040] In some embodiments, the controller includes a battery management controller.

[0041] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0043] Figure 1 is a schematic diagram of a chip over-electrical stress detection circuit according to an embodiment of the present invention;

[0044] Figure 2 is a structural block diagram of a controller according to an embodiment of the present invention;

[0045] Figure 3 is a flow chart of a method for detecting chip over-electrical stress according to an embodiment of the present invention;

[0046] Figure 4 is a flow chart of chip function detection according to an embodiment of the present invention;

[0047] Figure 5 is a structural block diagram of a vehicle according to an embodiment of the present invention.

[0048] Reference numerals:

[0049] Vehicles 300;

[0050] Controller 200;

[0051] Main control chip 210; instant register 230; history register 240; second diode 250; chip over-electric stress target port 211; chip over-electric stress detection circuit 1000;

[0052] Detection circuit module 1100; signal holding module 1200; clearing module 1300; high-pass filtering module 1400;

[0053] Voltage divider unit 1110; comparator U1; threshold providing circuit 1130; signal holding module input terminal 1230; signal holding module output terminal 1240; first resistor 1111; second resistor 1112; first node 1113; first diode 1101; third resistor 1102; fourth resistor 1103; fifth resistor 1131; sixth resistor 1132; second node 1133; seventh resistor 1201; first switch tube 1210; second switch tube 1220; eighth resistor 1202; ninth resistor 1203; tenth resistor 1204; first filter 1205; second filter 1206; third node 1207; third filter 1208; third switch tube 1310. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0055] The first aspect of the present invention provides a chip over-stress detection circuit. The chip over-stress detection circuit can be used to detect whether the chip has over-stress, realize the detectability of chip over-stress, provide data support for chip fault analysis, provide evidence for determining that the chip fails due to over-stress, and avoid assuming that the chip has design or manufacturing defects.

[0056] like Figure 1 As shown, the chip over-stress detection circuit 1000 of the embodiment of the present invention includes a detection circuit module 1100. The detection circuit module 1100 can be arranged at the port of the chip to be tested, for example, in parallel with the diode originally used for clamping and absorbing the over-stress signal of the chip to be tested, and is located after the diode.

[0057] In an embodiment, the detection circuit module 1100 includes a voltage dividing unit 1110 and a comparator U1 .

[0058] The first end of the voltage divider unit 1110 is suitable for connecting to the target port of the chip under test, and is used to collect the input electrical signal input from the target port to the chip under test and obtain a voltage divider signal of the input electrical signal.

[0059] In some embodiments, the target port of the chip to be tested may be a signal acquisition port, a power port, or other port that may input an instantaneous electromagnetic disturbance signal and cause electrical overstress to the chip. Figure 1 The power port is taken as an example.

[0060] The first input terminal 3 of the comparator is connected to the second terminal of the voltage dividing unit, and is used to output an over-electrical stress fault signal when the voltage dividing signal exceeds the over-electrical stress detection signal threshold.

[0061] Specifically, the detection circuit module 1100 in the chip over-electric stress detection circuit 1000 is connected to the chip to be tested to be tested, and can detect whether the chip to be tested is subjected to over-electric stress during operation and causes chip damage; the first end 1118 of the voltage divider unit in the detection circuit module 1100 is connected to the target port of the chip to be tested, and after the voltage divider unit 1110 collects the input electrical signal of the target port, such as the input voltage signal, the voltage divider unit 1110 divides the voltage so that the voltage is proportionally attenuated to reduce the current input to the comparator U1, prevent the comparator U1 from being damaged, and improve the reliability of the circuit. The comparator U1 will set an over-electric stress detection signal threshold. When the comparator U1 receives the voltage divider signal, the voltage divider signal is compared with the over-electric stress detection signal threshold. If the voltage divider signal received by the comparator U1 exceeds the over-electric stress detection signal threshold, the comparator U1 outputs a high-level signal, i.e., an over-electric stress fault signal, and a fault alarm can be performed.

[0062] According to the chip over-electrical stress detection circuit of the embodiment of the present invention, by connecting the target port of the chip to be tested with the voltage divider unit, the voltage divider signal of the input electrical signal of the chip to be tested input into the target port can be obtained, and the comparator outputs an over-electrical stress fault signal when the voltage divider signal exceeds the over-electrical stress detection signal threshold, thereby realizing the detectability of the over-electrical stress of the chip to be tested, providing data support for the chip fault analysis, providing evidence for determining that the chip fails due to over-electrical stress, avoiding the assumption that the chip has design or manufacturing defects, and being more conducive to chip fault analysis and technical improvement.

[0063] In some embodiments, Figure 1 As shown, the chip over-electrical stress detection circuit 1000 further includes: a signal holding module 1200 .

[0064] The signal holding module input terminal 1230 is connected to the first output terminal 1 of the comparator, and the signal holding module output terminal 1240 is connected to the chip to be tested, so as to maintain the over-electrical stress fault signal.

[0065] Specifically, the signal holding module 1200 is connected to the detection circuit module 1100; after the comparator U1 receives the voltage division signal, the voltage division signal is compared with the over-electrical stress detection signal threshold. If the voltage division signal received by the comparator U1 exceeds the over-electrical stress detection signal threshold, the comparator U1 outputs an over-electrical stress fault signal, and the over-electrical stress fault signal is transmitted to the signal holding module 1200. The signal holding module 1200 will hold the fault signal sent by the comparator U1, and at the same time send the over-electrical stress fault signal to the chip through the signal holding module output terminal 1240 to prevent the over-electrical stress from occurring for too short a time and the chip has no time to record the over-electrical stress state.

[0066] In some embodiments, Figure 1 As shown, the chip over-electrical stress detection circuit 1000 further includes: a clearing module 1300 .

[0067] The first end of the clearing module is connected to the signal holding module 1200 , and the second end of the clearing module is connected to the chip, and is used to control the signal holding module to clear the over-voltage stress fault signal in response to the clearing instruction.

[0068] Specifically, the zeroing module 1300 is connected to the signal holding module 1200, and is used to control the signal holding module 1200 to clear the over-electrical stress fault signal. After the chip is subjected to over-electrical stress, the chip is detected to determine whether the chip can work normally. If the chip can still work normally after being subjected to over-electrical stress, the zeroing module 1300 clears the electrical stress fault signal of the signal holding module 1200, so that the chip over-electrical stress detection circuit 1000 starts working again to detect whether the chip is subjected to over-electrical stress; when it is necessary to clear the signal holding module 1200 in the chip over-electrical stress detection circuit 1000, the chip sends the zeroing instruction to the zeroing module 1300 through the second end of the zeroing module, and the zeroing module 1300 controls the signal holding module 1200 to clear the over-electrical stress fault signal through the first end of the zeroing module.

[0069] In some embodiments, Figure 1 As shown, the chip over-electrical stress detection circuit 1000 further includes: at least one high-pass filtering module 1400 .

[0070] The first end of the voltage dividing unit is connected to the corresponding target port through at least one high-pass filter module 1400 .

[0071] Specifically, the voltage divider unit 1110 is connected to the target port through the high-pass filter module 1400. Because over-electrical stress is generally a high-frequency oscillating voltage, the high-pass filter module 1400 can block the normally operating DC voltage from passing through between the voltage divider unit 1110 and the target port, and will not cause the chip over-electrical stress detection circuit of the embodiment of the present invention to be falsely triggered.

[0072] For example, in the specific implementation process, the high-pass filter module 1400 of the chip over-electrical stress detection circuit can be the capacitor isolation solution proposed in the present invention, or any other high-pass filter circuit, which will not ultimately affect the effect of the present invention.

[0073] In some embodiments, Figure 1 As shown, the voltage dividing unit 1110 includes: a first resistor 1111 and a second resistor 1112 .

[0074] Among them, the first end of the first resistor 1111 is connected to the target port; the first end of the second resistor 1112 is connected to the second end of the first resistor 1111, the second end of the second resistor 1112 is grounded, and there is a first node 1113 between the first end of the second resistor 1112 and the second end of the first resistor 1111, and the first node 1113 is connected to the first input terminal 3 of the comparator.

[0075] Specifically, the first resistor 1111 and the second resistor 1112 in the voltage divider unit 1110 are voltage divider resistors for the overstress voltage, and play a voltage divider role. When the chip generates overstress, the first resistor 1111 and the second resistor 1112 in the voltage divider unit 1110 divide the overstress voltage and the voltage is proportionally attenuated. Moreover, because the first resistor 1111 is connected in series, the current input to the comparator U1 can be reduced. After the voltage divider unit 1110 divides the overstress, the current is input to the first input terminal 3 of the comparator through the first node 1113 for comparison. The ratio of the first resistor 1111 to the second resistor 1112 can be adjusted according to the overstress detection signal threshold set by the chip.

[0076] In some embodiments, Figure 1 As shown, the detection circuit module 1100 further includes: a first diode 1101 and a third resistor 1102 .

[0077] The positive terminal of the first diode 1101 is connected to the first node 1113 , the negative terminal of the first diode 1101 is connected to the first end of the third resistor 1102 , and the second end of the third resistor 1102 is connected to the first input terminal 3 of the comparator.

[0078] Specifically, the first node 1113 is connected to the first input terminal 3 of the comparator through the first diode 1101 and the third resistor 1102. The first diode 1101 can input the positive voltage of the divided over-stress voltage into the comparison circuit, and filter out the negative voltage. For example, the first diode 1101 can be a rectifier diode, and the third resistor 1102 plays a current limiting role to prevent the input current of the comparator U1 from being too large and damaging the comparator U1.

[0079] In some embodiments, Figure 1As shown, the detection circuit module 1100 further includes: a fourth resistor 1103 .

[0080] The first end of the fourth resistor 1103 is connected to the first input terminal 3 of the comparator and the second end of the third resistor 1102 , and the second end of the fourth resistor 1103 is grounded.

[0081] Specifically, the fourth resistor 1103 is a pull-down resistor, which plays the role of pulling down the voltage, providing a floating voltage when the comparator U1 is not working and does not receive the voltage division signal, and pulling down the voltage of the first input terminal 3 of the comparator to avoid misdetection of the comparator U1.

[0082] In some embodiments, Figure 1 As shown, the detection circuit module 1100 further includes: a threshold providing circuit 1130 .

[0083] Among them, the first end of the threshold providing circuit 1130 is connected to the first end of the power supply, the second end of the threshold providing circuit 1130 is grounded, and the third end of the threshold providing circuit 1130 is connected to the second input end 2 of the comparator for providing an over-electrical stress detection signal threshold.

[0084] Specifically, a first end of the threshold providing circuit 1130 is connected to a first end of the power supply. In an embodiment, if the target port to which the chip over-electrical stress detection circuit is connected is the power port of the chip, the power supply may be the power supply connected to the power port of the chip to be tested, or may be an independent power supply. If the target port to which the chip over-electrical stress detection circuit is connected is other ports, the power supply may be an independent power supply, such as a +5V power supply, or may be the power supply connected to the power port of the chip to be tested. The threshold providing circuit 1130 provides an over-electrical stress detection signal threshold for the comparator U1. After the comparator U1 receives the voltage division signal, it compares the voltage division signal with the electrical stress detection signal threshold to determine whether the chip is subjected to an over-electrical stress shock.

[0085] In some embodiments, Figure 1 As shown, the threshold providing circuit 1130 includes: a fifth resistor 1131 and a sixth resistor 1132 .

[0086] Among them, the first end of the fifth resistor 1131 is connected to the first end of the power supply; the first end of the sixth resistor 1132 is connected to the second end of the fifth resistor 1131, the second end of the sixth resistor 1132 is grounded, and there is a second node 1133 between the first end of the sixth resistor 1132 and the second end of the fifth resistor 1131, the second node 1133 is connected to the second input terminal 2 of the comparator, and the ratio of the fifth resistor 1131 and the sixth resistor 1132 can be adjusted according to the over-electrical stress detection signal threshold of the chip.

[0087] In some embodiments, Figure 1 As shown, the comparator U1 further includes: a first power supply terminal 1124 , a second power supply terminal 1125 and a second output terminal 1126 .

[0088] The first power supply terminal 8 of the comparator is connected to the first terminal of the power supply, the second power supply terminal 4 of the comparator is grounded, and the second output terminal 6 of the comparator is connected to the first power supply terminal 8 of the comparator.

[0089] Specifically, the first power supply terminal 8 of the comparator is connected to the first terminal of the power supply, and the second power supply terminal 4 of the comparator is grounded, so that the power supply supplies power to the comparator U1 to ensure the normal operation of the comparator U1. When the voltage at the first input terminal 3 of the comparator is greater than the voltage at the second input terminal 2 of the comparator, the voltage division signal exceeds the over-electrical stress detection signal threshold, and the first output terminal 1 of the comparator outputs an over-electrical stress fault signal.

[0090] In some embodiments, Figure 1 As shown, the signal holding module 1200 includes: a first switch tube 1210 and a second switch tube 1220 .

[0091] Among them, the control end of the first switch tube 1210 is connected to the first output end 1 of the comparator, the first end of the first switch tube 1210 is connected to the first end of the power supply through the seventh resistor 1201, and the second end of the first switch tube 1210 is grounded; the control end of the second switch tube 1220 is connected to the first end of the first switch tube 1210, the first end of the second switch tube 1220 is grounded, and the second end of the second switch tube 1220 is connected to the first end of the power supply through the eighth resistor 1202.

[0092] Specifically, the first switch tube 1210 and the second switch tube 1220 are turned on in response to the over-electrical stress fault signal to maintain the output of the over-electrical stress fault signal; after the comparator U1 outputs the over-electrical stress fault signal and reaches the control end of the first switch tube, the first end of the first switch tube 1210 and the second end of the first switch tube 1210 are turned on, and current flows through the first switch tube 1210. At this time, the voltage of the control end of the second switch tube 1220 is pulled down, and the first end of the second switch tube 1220 and the second end of the second switch tube 1220 are turned on, so that current flows through the second switch tube 1220, causing the voltage of the control end of the first switch tube to be pulled up. Therefore, the signal holding module 1200 holds the fault signal. Because over-electrical stress often occurs very briefly, if there is no signal holding module 1200, the chip may not have time to save the fault caused by over-electrical stress.

[0093] For example, the first switch tube 1210 and the second switch tube 1220 in the signal holding module can be a simple signal holding circuit composed of NPN and PNP transistors, or can be other digital signal holding circuits built by various gate circuits. The specific circuit does not affect the design concept of the present invention.

[0094] In some embodiments, Figure 1 As shown, the signal holding module 1200 further includes: a ninth resistor 1203 and a tenth resistor 1204 .

[0095] Among them, the first end of the ninth resistor 1203 is connected to the first output terminal 1 of the comparator, and the second end of the ninth resistor 1203 is connected to the control end of the first switch tube 1210; the first end of the tenth resistor 1204 is connected to the first end of the second switch tube 1220, the control end of the first switch tube 1210 and the second end of the ninth resistor 1203.

[0096] Specifically, the high effective level output by the first output terminal of the comparator U1 is transmitted to the control terminal of the first switch tube 1210 through the ninth resistor 1203. The ninth resistor 1203 plays a current limiting role to prevent a large current from flowing through the control terminal of the first switch tube 1210 and causing damage to the first switch 1210; the tenth resistor 1204 is a pull-down resistor, which is used to pull down the voltage of the first end of the second switch tube 1220 when the second switch tube 1220 is turned on, so that the second switch tube 1220 can be continuously turned on.

[0097] In some embodiments, Figure 1 As shown, the signal holding module 1200 also includes: a first filter 1205 .

[0098] Specifically, the first end of the first filter 1205 is connected to the first output end of the comparator U1 and the first end of the ninth resistor 1203, and the second end of the first filter 1205 is grounded. The first filter 1205 is used to filter the high level output from the first output end of the comparator U1 to eliminate interference clutter signals.

[0099] In some embodiments, Figure 1 As shown, the signal holding module 1200 also includes: a second filter 1206 .

[0100] Specifically, the first end of the second filter 1206 is connected to the control end of the first switch tube 1210, and there is a third node 1207 between the first end of the second filter 1206 and the control end of the first switch tube 1210 as the output end of the signal holding module, and the second end of the second filter 1206 is grounded; the second filter 1206 filters the signal at the third node 1207 in the signal holding module 1200 to eliminate the interference signal, so that the signal holding module 1200 effectively outputs the over-electrical stress fault signal.

[0101] In some embodiments, Figure 1 As shown, the signal holding module 1200 further includes: a third filter 1208 .

[0102] Specifically, the first end of the third filter 1208 is connected to the control end of the second switch tube 1220, and the second end of the third filter 1208 is connected to the control end of the first switch tube 12120. The signals at the control end of the first switch tube 1210 and the control end of the second switch tube 1220 are filtered to eliminate interference signals.

[0103] In some embodiments, Figure 1 As shown, the clearing module 1300 includes: a third switch tube 1310 .

[0104] Among them, the control end of the third switch tube 1310 is connected to the chip, the first end of the third switch tube 1310 is grounded, and the second end of the third switch tube 1310 is connected to the second end of the second switch tube 1220, which is used to respond to the chip's reset instruction to issue a reset signal to clear the over-voltage stress fault signal.

[0105] Specifically, after the chip is subjected to an over-electrical stress shock, a functional test is performed on the chip. If all functions of the chip are normal, the chip can continue to be used. At this time, the chip sends a reset instruction to clear the over-electrical stress fault signal. When the chip sends a reset signal to the control end of the third switch tube 1310, the third switch tube 1310 is turned on. Since the third switch tube 1310 is turned on, the current flows to the ground end through the third switch tube 1310, and the second end voltage of the second switch tube 1220 is pulled down, and the second switch tube 1220 is disconnected. After the second switch tube 1220 is disconnected, the current cannot flow through the second switch tube 1220 to the control end of the first switch tube 1210. Therefore, the first switch tube 1210 is disconnected, and the reset module 1300 cannot output a fault signal to the chip, and the chip can continue to work normally.

[0106] A second aspect of the present invention provides a controller, such as Figure 2 As shown, the controller 200 includes: at least one chip over-electrical stress detection circuit 1000 and a main control chip 210. That is, the chip over-electrical stress detection circuit 1000 is integrated inside the controller 200 where the main control chip 210 is located.

[0107] The main control chip 210 includes at least one target port 211, and the at least one target port 211 is connected to at least one chip over-electric stress detection circuit 1000. The main control chip 210 may include multiple ports, and the target port may be a signal acquisition port, a power port, or other ports of the main control chip 210 that may input instantaneous magnetic interference signals and cause chip over-electric stress, and may be one or more ports.

[0108] Specifically, the chip over-electrical stress detection circuit 1000 is used to detect whether the main control chip 210 in the controller 200 is subjected to over-electrical stress shock. At least one target port 211 is provided on the main control chip 210. The main control chip 210 is connected to the chip over-electrical stress detection circuit 1000 through the target port 211. The target port 211 is a port where high-frequency signals that cause chip over-electrical stress may exist, for example, it may include a power supply port, an acquisition port, a signal transmission port, etc.

[0109] For example, the target port 211 can be a power port. When the target port 211 is a power port, the power supply of the chip over-current stress detection circuit 1000 can be the power supply connected to the power port; if there are multiple target ports 211, and multiple target ports 211 share the chip over-current stress detection circuit 1000, other target ports 211 can be connected between the high-pass filter module 1400 and the first resistor 1111 through a filter capacitor.

[0110] The controller according to the embodiment of the present invention is connected to the chip over-electrical stress detection circuit through the target port of the main control chip, so as to detect whether the main control chip is subjected to over-electrical stress shock during operation. After detecting that the main control chip is subjected to over-electrical stress shock, the chip over-electrical stress detection circuit outputs an over-electrical stress fault signal, thereby realizing the detectability of over-electrical stress of the main control chip, thereby providing data support for determining the cause of failure of the main control chip due to over-electrical stress, and facilitating fault analysis and technical improvement of the main control chip.

[0111] In some embodiments, the controller 200 includes a plurality of chip over-electrical stress detection circuits 1000 ; the main control chip 210 includes a plurality of target ports 211 , and the plurality of target ports 211 are connected to the plurality of chip over-electrical stress detection circuits 1000 in a one-to-one correspondence.

[0112] Specifically, multiple target ports 211 may share a chip over-electrical stress detection circuit 1000, or a chip over-electrical stress detection circuit 1000 may be placed on each target port 211. The chip over-electrical stress detection circuit 1000 detects whether the connected target port 211 is subjected to over-electrical stress, and determines which specific target port 211 is subjected to over-electrical stress and fails based on the fault signals output by different chip over-electrical stress detection circuits 1000.

[0113] In some embodiments, each target port 211 is connected to a corresponding chip over-electrical stress detection circuit 1000 through a corresponding high-pass filter module.

[0114] Specifically, since over-voltage stress is generally a high-frequency oscillating voltage, each target port 211 is connected to the corresponding chip over-voltage stress detection circuit 1000 through a corresponding high-pass filter module to block the normal working DC voltage from passing through and avoid false triggering of the chip over-voltage stress detection circuit 1000.

[0115] In some embodiments, the controller 200 includes a chip over-electrical stress detection circuit 1000; the main control chip 210 includes a plurality of target ports 211, and the plurality of target ports 211 are respectively connected to the chip over-electrical stress detection circuit 1000 through corresponding high-pass filter modules.

[0116] Specifically, a chip over-electric stress detection circuit is provided in the controller, and the chip over-electric stress detection circuit is provided with a plurality of high-pass filter modules such as Figure 1 The high-pass filter capacitor 1400, that is, multiple other high-pass filter capacitors are connected between the first resistor 1111 and the high-pass filter module 1400, and multiple target ports 211 can be connected to the chip over-electrical stress detection circuit 1000 through the corresponding high-pass filter capacitors, so that electrical stress detection can be performed on multiple target ports 211 through one chip over-electrical stress detection circuit, and the over-electrical stress detection signals of the multiple target ports 211 are electrically transmitted to the same chip over-electrical stress detection circuit 1000, thereby reducing complexity and achieving cost optimization.

[0117] In some embodiments, the plurality of target ports 211 include a power port; a chip over-current stress detection circuit 1000 is connected to the power port via a high-pass filter unit, and the power supply connected to the power port 211 supplies power to the chip over-current stress detection circuit.

[0118] Specifically, multiple target ports 211 are connected to a chip over-current stress detection circuit 1000 through a high-pass filtering unit and a power port, and an independent power supply terminal is required. When the multiple target ports 211 include a power port, the power supply of the chip over-current stress detection circuit 1000 can be the power supply connected to the power port, and the power supply connected to the power port 211 powers the chip over-current stress detection circuit 1000, and there is no need to set an independent power supply terminal for the chip over-current stress detection circuit 1000.

[0119] In some embodiments, Figure 2 As shown, the controller 200 further includes an immediate register 230 .

[0120] The instant register 230 is connected to the main control chip 210 and is used to store the current over-voltage stress fault signal.

[0121] Specifically, when the chip over-electrical stress detection circuit 1000 detects that the main control chip 210 is subjected to an over-electrical stress shock, the signal holding module in the chip over-electrical stress detection circuit 1000 sends an over-electrical stress fault signal to the main control chip 210. The main control chip 210 stores the over-electrical stress fault signal in the instant register 230. Based on the information read from the instant register 230, it can be determined whether the main control chip 210 is subjected to an over-electrical stress shock.

[0122] In some embodiments, Figure 2 As shown, the controller 200 further includes a history register 240 .

[0123] The history register 240 is connected to the main control chip 210 and is used to store a preset number of historical over-electrical stress fault signals and time information of the generation of the historical over-electrical stress fault signals.

[0124] Specifically, when the chip over-electrical stress detection circuit 1000 detects that the main control chip 210 is subjected to over-electrical stress shock, the signal holding module in the chip over-electrical stress detection circuit 1000 sends an over-electrical stress fault signal to the main control chip 210. The main control chip 210 stores the over-electrical stress fault signal in the real-time register 230, and stores the over-electrical stress fault signal and time information in the historical register 240.

[0125] For example, the history register 240 can simultaneously record the time information of the most recent 10 over-electrical stress fault signals and the generation of historical over-electrical stress fault signals. The time of the occurrence of the over-electrical stress fault signal can be obtained from the real-time clock circuit or other means. When the time information records of 10 over-electrical stress fault signals and the generation of historical over-electrical stress fault signals are full, the earliest record is automatically erased, so that the history register 240 can save the time information of the most recent 10 over-electrical stress fault signals and the generation of historical over-electrical stress fault signals. The recorded historical over-electrical stress fault signals can assist in analyzing the cause of the over-electrical stress fault, and the reliability of the product can be improved after the fault is eliminated.

[0126] In the specific implementation process, the chip over-current stress detection circuit can be connected to the power port of the main control chip, or it can be connected to all other ports. Multiple ports can share one chip over-current stress detection circuit, or each port can have a chip over-current stress detection circuit. When multiple ports share one chip over-current stress detection circuit, the over-current stress signal of the port can be transmitted to the same chip over-current stress detection circuit through multiple high-pass filtering units, which can achieve cost optimization. The number of chip over-current stress detection circuits is equal to the number of immediate registers and historical registers. When a chip uses two chip over-current stress detection circuits, the number of immediate registers and historical registers is also 2 respectively.

[0127] In some embodiments, Figure 2 As shown, the controller 200 further includes: a second diode 250 .

[0128] The second diode 250 is located between the target port 211 and the chip over-electrical stress detection circuit 1000 and is used to clamp and absorb the over-electrical stress signal.

[0129] Specifically, the second diode 250 can be a transient voltage suppression diode. When the over-electrical stress applied to the chip is small, the second diode 250 clamps and absorbs the over-electrical stress signal. However, the clamping and absorption power of the second diode 250 is limited. Once the over-electrical stress signal exceeds the power that the second diode 250 can withstand, the second diode 250 will be broken down. After the second diode 250 is broken down, the over-electrical stress detection signal is sent to the chip over-electrical stress detection circuit 1000. The over-electrical stress detection signal threshold needs to be greater than the clamping voltage of the port, so that the chip over-electrical stress detection circuit will not be triggered by mistake.

[0130] For example, Figure 1As shown, because the over-electric stress on the new energy vehicle is generally a high-frequency oscillating voltage, the high-pass filter module 1400 can block the normal working DC voltage from passing through here, and will not cause the electrical stress detection circuit of the present invention to be falsely triggered. The first resistor 1111 and the second resistor 1112 are the voltage-dividing resistors of the voltage-dividing unit. After the over-electric stress voltage is divided, the voltage will decay proportionally, and because the first resistor 1111 is connected in series, the current input to the comparator U1 can be reduced to prevent the comparator U1 from being damaged, thereby improving the reliability of the circuit. The ratio of the first resistor 1111 to the second resistor 1112 can be adjusted according to the threshold value of the over-electric stress detection signal set by the chip. The first diode 1101 can be a rectifier diode, and the positive voltage of the over-electric stress voltage after voltage division can be input into the comparison circuit, and the negative voltage is filtered out. The fifth resistor 1131 and the sixth resistor 1132 are the comparison voltages of the comparison circuit. When the electrical stress voltage after voltage division is greater than the comparison voltage, the comparison circuit will output a high effective level. The ratio of the fifth resistor 1131 to the sixth resistor 1132 can be adjusted according to the threshold value of the over-electric stress detection signal of the chip. In this circuit, when the voltage of the first input terminal 3 of the comparator is greater than the voltage of the second input terminal 2 of the comparator, the first output terminal 1 of the comparator will output a high effective signal with a voltage level of the second output terminal 6 of the comparator. The high effective level output by the comparator U1 will be input to the base of the first switch tube 1210 after passing through the ninth resistor 1203, and the collector and emitter of the first switch tube 1210 will be turned on. At this time, the base level of the second switch tube 1220 will be pulled down by the first switch tube 1210, and the collector and emitter of the second switch tube 1220 will be turned on, which will cause the base level of the first switch tube 1210 to be pulled up. The first switch tube 1210 and the second switch tube 1220 form a signal holding circuit. Because over-electrical stress often occurs very briefly, if there is no signal holding circuit, the chip may not have time to save the fault caused by over-electrical stress. At this time, the chip can detect the level of the 1240 pin at the output end of the signal holding module in the circuit. When the level is high, there is an electrical stress fault. The chip will set the instant register and the history register to 1 at the same time. At the same time, the history register has 10 time recording spaces. The over-electric stress occurrence time of the history register can be obtained from the real-time clock circuit or other means, and recorded in the history register according to the specified format. When the over-electric stress occurs and has been recorded in the instant register and the history register, when the chip self-checks that there is no functional damage, the chip can keep the over-electric stress signal cleared by setting the second end 1330 pin of the clearing module to a high level once, and also clear the instant register, and the chip can continue to work normally.

[0131] Reference below Figure 1 A method for detecting chip over-electrical stress according to an embodiment of the third aspect of the present invention is described as follows: Figure 3As shown, the method at least includes step S1 to step S2.

[0132] Step S1, obtaining register information of an over-electrical stress fault signal.

[0133] Specifically, when the chip over-electrical stress detection circuit detects that the chip is subjected to over-electrical stress shock, the signal holding module in the chip over-electrical stress detection circuit sends an over-electrical stress fault signal to the main control chip, and the chip stores the over-electrical stress fault signal in the immediate register and the historical register. The immediate register and the historical register are set to 1 at the same time, and the register information is obtained. According to the register information, it can be determined whether the chip has been subjected to over-electrical stress shock and has failed.

[0134] Step S2, determining that the main control chip has over-electrical stress according to the register information, and issuing a chip over-electrical stress fault alarm.

[0135] Specifically, after the main control chip is powered on, the main control chip obtains the register information for self-checking. When the main control chip self-checks abnormally, it will first check whether the historical register is 1. When the historical register is 1, the chip will output a fault alarm signal. When the historical register is 0, the main control chip outputs other fault alarm signals. When the main control chip function self-checks normally, the main control chip will clear the over-voltage stress hold signal and set the immediate fault register to 0. When the immediate fault register is set to 0, the detection result of the chip over-voltage stress detection circuit will be judged. If there is no over-voltage stress fault, the judgment will be repeated until the chip over-voltage stress detection circuit detects that there is an over-voltage stress fault. Then the immediate register will be set to 1. When the immediate register is 1, the main control chip will output a fault alarm signal.

[0136] According to the method for detecting chip over-electrical stress in an embodiment of the present invention, the chip over-electrical stress detection circuit stores the output over-electrical stress fault signal in a register, and determines whether the main control chip has over-electrical stress through the register information, thereby providing data support for determining the cause of the main control chip failure due to over-electrical stress, and facilitating fault analysis and technical improvement of the main control chip.

[0137] In some embodiments, the information stored in the history register of the controller is detected; and it is determined that the information stored in the history register includes an over-electrical stress fault signal generated by the current functional self-test of the main control chip, and then it is determined that over-electrical stress occurs in the main control chip.

[0138] Specifically, the main control chip performs a self-test after it is powered on. When the chip self-test is abnormal, the information stored in the history register of the detection controller is used to determine whether over-electrical stress has occurred in the main control chip. The information stored in the history register includes the over-electrical stress fault signal previously detected by the main control chip and the over-electrical stress fault signal generated by this functional self-test. If it is detected that the historical register for this functional self-test is 1, it can be determined that over-electrical stress has occurred in the main control chip during this operation.

[0139] In some embodiments, in response to the over-stress fault signal of the chip over-stress detection circuit, the controller's immediate register and historical register are respectively set to correspond to the over-stress fault of the main control chip, and the historical register is controlled to save the time information of the corresponding over-stress fault.

[0140] Specifically, when the main control chip is working, the over-voltage stress fault signal is detected in real time. If there is no over-voltage stress fault, the judgment is repeated until the chip over-voltage stress detection circuit detects that there is an over-voltage stress fault. The immediate fault register will be set to 1. When the immediate register is set to 1, it will determine whether the historical register is 1. If the historical fault register is not 1, the historical fault register will be set to 1 first. At the same time, the time of the current over-voltage stress fault is obtained according to the real-time clock or other means (such as the vehicle clock, GPS timing, etc.) and written into the historical fault register according to the format. Once the historical register is set to 1, it cannot be erased to prevent the loss of historical E fault records after the chip is powered on again, which is convenient for fault tracking after the chip is damaged by over-voltage stress.

[0141] In some embodiments, in response to the over-stress fault signal of the chip over-stress detection circuit, the controller's immediate register and historical register are respectively set to correspond to the over-stress fault of the main control chip, and then a clear instruction is sent to the chip over-stress detection circuit.

[0142] Specifically, after chip over-electrical stress occurs and has been recorded in the immediate register and the historical register, the chip is self-checked. If the chip self-check shows no functional damage, the controller sends a reset instruction to the chip over-electrical stress detection circuit. The chip can reset the over-electrical stress signal by setting the reset module pin to a high level once, and also reset the immediate register, so that the chip can continue to work normally.

[0143] Reference below Figure 4 The chip function detection step of the embodiment of the present invention is described by way of example, and the specific contents are as follows.

[0144] Step S3, start.

[0145] Step S4, whether the chip function self-check is normal, if yes, go to step S5, otherwise go to step S11.

[0146] Step S5, the immediate register is set to 0.

[0147] Step S6, whether there is an over-stress fault signal, if so, execute step S7, otherwise execute step S6.

[0148] Step S7, the immediate register is set to 1.

[0149] Step S8, whether the history register is 1, if so, execute step S10, otherwise execute step S9.

[0150] Step S9, the history register is set to 1 and the fault time is recorded.

[0151] Step S10: the chip outputs a fault alarm signal.

[0152] Step S11, whether the history register is 1, if so, execute step S10, otherwise execute step S12.

[0153] Step S12, other chip fault alarm.

[0154] Step S13, end.

[0155] A fourth aspect of the present invention provides a vehicle, such as Figure 5 As shown, the vehicle 300 includes: a controller 200 .

[0156] According to the vehicle of the embodiment of the present invention, a chip over-current stress detection circuit is set in the controller, and the main control chip is connected to the chip over-current stress detection circuit through the target port, so as to detect whether the main control chip is subjected to over-current stress shock during operation. After detecting that the main control chip is subjected to over-current stress shock, the chip over-current stress detection circuit outputs an over-current stress fault signal, thereby providing data support for determining the cause of the main control chip failure, and facilitating fault analysis and technical improvement of the main control chip.

[0157] In some embodiments, the controller includes a battery management controller. Of course, the controller may also be other controllers that may cause over-electrical stress.

[0158] Specifically, new energy vehicles use an energy structure mainly composed of high-voltage batteries. New energy vehicles will generate transient electromagnetic interference at the moment of high voltage electricity. These transient electromagnetic interferences will then be coupled through conduction, induction or radiation to the controller of the high-voltage system, such as the battery management system. Therefore, a chip over-current stress detection circuit is set in the battery management controller. The detection circuit is connected to the main control chip and can be used to detect whether the main control chip is subjected to over-current stress shock, providing data support for fault analysis of the battery management controller, and providing evidence for the failure of the controller due to over-current stress, thereby avoiding the assumption that the controller has design or manufacturing defects.

[0159] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0160] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip over-electrical stress detection circuit, characterized in that: include: A detection circuit module, wherein the detection circuit module comprises a voltage dividing unit and a comparator; The first end of the voltage divider unit is suitable for connecting to the target port of the chip to be tested, and is used to collect the input electrical signal of the chip to be tested from the target port and obtain the voltage divider signal of the input electrical signal; The first input terminal of the comparator is connected to the second terminal of the voltage dividing unit, and is used to output an over-electrical stress fault signal when the voltage dividing signal exceeds an over-electrical stress detection signal threshold.

2. The chip over-voltage stress detection circuit according to claim 1, characterized in that: The chip over-electrical stress detection circuit also includes: A signal holding module, wherein the input end of the signal holding module is connected to the first output end of the comparator, and the output end of the signal holding module is connected to the chip to be tested, and is used to maintain the over-electrical stress fault signal.

3. The chip over-electrical stress detection circuit according to claim 2, characterized in that: The chip over-electrical stress detection circuit also includes: A clearing module, wherein a first end of the clearing module is connected to the signal holding module, and a second end of the clearing module is connected to the chip under test, and is used to control the signal holding module to clear the over-electrical stress fault signal in response to a clearing instruction.

4. The chip over-voltage stress detection circuit according to claim 1, characterized in that: The chip over-electrical stress detection circuit further includes: At least one high-pass filter module, the first end of the voltage divider unit is connected to the corresponding target port through the at least one high-pass filter module.

5. The chip over-electrical stress detection circuit according to claim 1, characterized in that: The voltage dividing unit comprises: a first resistor, wherein a first end of the first resistor is connected to the target port; A second resistor, wherein a first end of the second resistor is connected to a second end of the first resistor, the second end of the second resistor is grounded, a first node is provided between the first end of the second resistor and the second end of the first resistor, and the first node is connected to a first input end of the comparator.

6. The chip over-electrical stress detection circuit according to claim 5, characterized in that: The detection circuit module also includes: A first diode and a third resistor, the first node is connected to the first input terminal of the comparator through the first diode and the third resistor, wherein the positive terminal of the first diode is connected to the first node, the negative terminal of the first diode is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first input terminal of the comparator.

7. The chip over-electrical stress detection circuit according to claim 6, characterized in that: The detection circuit module also includes: a fourth resistor, wherein a first end of the fourth resistor is connected to the first input end of the comparator and a second end of the third resistor, and a second end of the fourth resistor is grounded.

8. The chip over-electrical stress detection circuit according to claim 1, characterized in that: The detection circuit module also includes: A threshold providing circuit, wherein a first end of the threshold providing circuit is connected to a first end of a power supply, a second end of the threshold providing circuit is grounded, and a third end of the threshold providing circuit is connected to a second input end of the comparator, for providing the over-electrical stress detection signal threshold.

9. The chip over-electrical stress detection circuit according to claim 8, characterized in that: The threshold providing circuit comprises: a fifth resistor, a first end of the fifth resistor being connected to a first end of the power supply; A sixth resistor, wherein the first end of the sixth resistor is connected to the second end of the fifth resistor, the second end of the sixth resistor is grounded, a second node is provided between the first end of the sixth resistor and the second end of the fifth resistor, and the second node is connected to the second input end of the comparator.

10. The chip over-electrical stress detection circuit according to claim 8, characterized in that: The comparator further includes a first power supply terminal, a second power supply terminal and a second output terminal, the first power supply terminal is connected to the first terminal of the power supply, the second power supply terminal is grounded, and the second output terminal is connected to the first power supply terminal.

11. The chip over-electrical stress detection circuit according to claim 3, characterized in that: The signal holding module comprises: A first switch tube, wherein a control end of the first switch tube is connected to a first output end of the comparator, a first end of the first switch tube is connected to a first end of a power supply through a seventh resistor, and a second end of the first switch tube is grounded; a second switch tube, wherein a control end of the second switch tube is connected to a first end of the first switch tube, a first end of the second switch tube is grounded, and a second end of the second switch tube is connected to a first end of the power supply through an eighth resistor; The first switch tube and the second switch tube are turned on in response to the over-electrical stress fault signal to maintain outputting the over-electrical stress fault signal.

12. The chip over-electrical stress detection circuit according to claim 11, characterized in that: The signal holding module also includes: a ninth resistor, wherein a first end of the ninth resistor is connected to the first output end of the comparator, and a second end of the ninth resistor is connected to the control end of the first switch tube; A tenth resistor, wherein a first end of the tenth resistor is connected to the first end of the second switch tube, the control end of the first switch tube and the second end of the ninth resistor.

13. The chip over-electrical stress detection circuit according to claim 12, characterized in that: The signal holding module also includes: A first filter, wherein a first end of the first filter is connected to the first output end of the comparator and the first end of the ninth resistor, and a second end of the first filter is grounded.

14. The chip over-electrical stress detection circuit according to claim 11, characterized in that: The signal holding module also includes: A second filter, wherein the first end of the second filter is connected to the control end of the first switch tube, a third node is provided between the first end of the second filter and the control end of the first switch tube to serve as the output end of the signal holding module, and the second end of the second filter is grounded.

15. The chip over-electrical stress detection circuit according to claim 11, characterized in that: The signal holding module also includes: A third filter, wherein a first end of the third filter is connected to the control end of the second switch tube, and a second end of the third filter is connected to the control end of the first switch tube.

16. The chip over-electrical stress detection circuit according to claim 11, characterized in that: The clearing module comprises: A third switch tube, wherein the control end of the third switch tube is connected to the chip under test, the first end of the third switch tube is grounded, and the second end of the third switch tube is connected to the second end of the second switch tube, and is used to respond to the reset instruction of the chip under test to issue a reset signal for clearing the over-electrical stress fault signal.

17. A controller, characterized in that: The controller comprises: At least one chip over-stress detection circuit according to any one of claims 1 to 16; A main control chip, wherein the main control chip comprises at least one target port, and the at least one target port is connected to the at least one chip over-electrical stress detection circuit.

18. The controller according to claim 17, characterized in that The controller includes a plurality of chip over-electrical stress detection circuits; The main control chip includes a plurality of the target ports, and the plurality of the target ports are respectively connected to the plurality of the chip over-electrical stress detection circuits in a one-to-one correspondence.

19. The controller according to claim 18, characterized in that Each of the target ports is connected to the corresponding chip over-electrical stress detection circuit via a high-pass filter module.

20. The controller according to claim 17, characterized in that The controller includes a chip over-electrical stress detection circuit; The main control chip includes a plurality of target ports, and the plurality of target ports are respectively connected to the chip over-electrical stress detection circuit through a high-pass filter module.

21. The controller according to claim 20, characterized in that The plurality of said target ports include a power port; One of the chip over-electrical stress detection circuits is connected to the power port via a high-pass filter unit, and the power supply connected to the power port supplies power to the chip over-electrical stress detection circuit.

22. The controller according to any one of claims 17 to 21, characterized in that: The controller further comprises: The instant register is connected to the main control chip and is used to store the current over-voltage stress fault signal.

23. The controller according to claim 22, characterized in that The controller further comprises: The history register is connected to the main control chip and is used to store a preset number of historical over-electrical stress fault signals and time information of the generation of the historical over-electrical stress fault signals.

24. The controller according to claim 17, characterized in that The controller further comprises: A second diode is located between the target port and the chip over-electrical stress detection circuit and is used for clamping and absorbing the over-electrical stress signal.

25. A method for detecting chip over-electrical stress, characterized in that: For use in a controller according to any one of claims 17 to 24, the method comprising: Obtain register information of over-voltage stress fault signal; It is determined according to the register information that over-electrical stress occurs on the main control chip, and an over-electrical stress fault alarm is issued on the chip.

26. The method according to claim 25, characterized in that Determining, according to the register information, that over-electrical stress occurs on the main control chip includes: Detecting information stored in a history register of the controller; If it is determined that the information stored in the history register includes the over-electrical stress fault signal generated by the current functional self-test of the main control chip, it is determined that over-electrical stress occurs in the main control chip.

27. The method according to claim 26, characterized in that The method further comprises: In response to the over-stress fault signal of the chip over-stress detection circuit, the instant register and the history register of the controller are respectively set corresponding to the over-stress fault of the main control chip, and the history register is controlled to save the time information corresponding to the occurrence of the over-stress fault.

28. The method according to claim 25, characterized in that The method further comprises: In response to the over-stress fault signal of the chip over-stress detection circuit, after the instant register and the historical register of the controller are respectively set corresponding to the over-stress fault of the main control chip, a clear instruction is sent to the chip over-stress detection circuit.

29. A vehicle, characterized in that: A controller comprising any one of claims 17-24.

30. The vehicle according to claim 29, characterized in that The controller includes a battery management controller.

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