Chip test circuit, method and system, storage medium and program product

Abstract

The invention provides a chip test circuit, method and system, a storage medium and a program product, and the circuit comprises a multiplexing control circuit which is used for obtaining a first time sequence signal outputted by a test machine; the controller is connected with the output end of the multiplexing control circuit, and is used for outputting a test pre-enable signal according to the first time sequence signal when the multiplexing control circuit is in a non-test mode, or forbidding to output the test pre-enable signal according to the first time sequence signal; and the test enabling detection circuit is connected with the output end of the controller and is used for controlling the chip to enter a test mode according to the test pre-enabling signal or forbidding the chip to enter the test mode according to the test pre-enabling signal. According to the circuit, the safety of the chip is guaranteed, the test coverage rate and the resource utilization rate of the chip are improved, the risk that the chip enters a test mode by mistake is reduced, and the chip and design cost is saved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip testing circuit, method, system, storage medium and program product. Background Art

[0002] Safely entering the chip test mode is extremely important for chip quality assurance and usage assurance. In related technologies, methods for entering the chip test mode include: using JTAG (Joint Test Action Group) or an interface similar to JTAG, using specific chip pins, using specific hardware timing, and determining whether a specific register inside the chip meets a specific value.

[0003] However, using the above method cannot guarantee the security of the chip, the test coverage and resource utilization of the chip are low, the risk of the chip mistakenly entering the test mode is high, and the chip and design costs are high. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, an object of the present invention is to propose a chip test circuit, which ensures the security of the chip, improves the test coverage and resource utilization of the chip, reduces the risk of the chip mistakenly entering the test mode, and saves chip and design costs.

[0006] Therefore, a second object of the present invention is to provide a chip testing method.

[0007] To this end, the third object of the present invention is to provide a testing system.

[0008] To this end, a fourth object of the present invention is to provide a computer-readable storage medium.

[0009] To this end, a fifth object of the present invention is to provide a computer program product.

[0010] In order to achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a test circuit for a chip, and the test circuit of the chip includes: a multiplexing control circuit, which is used to obtain a first timing signal output by a test machine; a controller, which is connected to the output end of the multiplexing control circuit, and is used to output a test pre-enable signal according to the first timing signal when the multiplexing control circuit is in a non-test mode, or to prohibit the output of the test pre-enable signal according to the first timing signal; a test enable detection circuit, which is connected to the output end of the controller, and is used to control the chip to enter the test mode according to the test pre-enable signal, or to prohibit the chip from entering the test mode according to the test pre-enable signal.

[0011] According to the test circuit of the chip of the embodiment of the present invention, the controller is connected to the output end of the multiplexing control circuit, the test enable detection circuit is connected to the output end of the controller, and the first timing signal output by the test machine is obtained through the multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, thereby ensuring the security of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0012] In some embodiments, the multiplexing control circuit includes: a first multiplexing sub-circuit, connected to the output end of the test machine, and used to output the first timing signal in the non-test mode, and the first timing signal includes a burning mode timing and a test mode command timing; a second multiplexing sub-circuit, connected to the output end of the test machine, and used to output a second timing signal in the test mode, and the second timing signal includes a digital logic test timing; a selector, respectively connected to the output end of the first multiplexing sub-circuit and the output end of the second multiplexing sub-circuit, and used to select to output the first timing signal or the second timing signal.

[0013] In some embodiments, the controller includes: a timing detection subcircuit, connected to the output end of the multiplexing control circuit, for receiving the first timing signal, and when it is determined according to the first timing signal that the burning mode timing in the first timing signal is correct, entering the burning mode and outputting the test mode command timing in the first timing signal; a safety detection subcircuit, connected to the output end of the timing detection subcircuit, for outputting the test pre-enable signal according to the test mode command timing, or prohibiting the output of the test pre-enable signal according to the test mode command timing.

[0014] In some embodiments, the safety detection subcircuit includes: a test command detection subcircuit, connected to the output end of the timing detection subcircuit, and used to prohibit outputting a test pre-enable signal when a preset number of the test mode command timings are incorrect, or to output a test enable pre-start signal when a preset number of the test mode command timings are correct; a first test output subcircuit, connected to the output end of the test command detection subcircuit, and used to output the test pre-enable signal according to the test enable pre-start signal, or to prohibit outputting a test pre-enable signal according to the test enable pre-start signal.

[0015] In some embodiments, the first test output subcircuit includes: at least two triggers, connected to the output end of the test command detection subcircuit, used to receive the test enable pre-start signal and output at least two trigger output signals; a first AND gate, connected to the output ends of at least two of the triggers, used to prohibit outputting the test pre-enable signal according to the at least two trigger output signals, or output the test pre-enable signal.

[0016] In some embodiments, the first test output subcircuit is specifically used to: when the output signal of one of the triggers is abnormal, prohibit outputting the test pre-enable signal according to the output signals of the remaining triggers.

[0017] In some embodiments, the test enable detection circuit includes: a timer, connected to the output end of the controller, and used to output a reset signal when the test enable detection circuit does not receive the test pre-enable signal within a preset time; at least two second test output sub-circuits, connected to the output end of the timer, and used to reset the second test output sub-circuit when receiving the reset signal, or, when the test pre-enable signal is received within the preset time, control the chip to enter a test mode.

[0018] In some embodiments, the second test output subcircuit includes: a multi-stage trigger connected to the output end of the timer, used to filter out interference signals in the test pre-enable signal; a second AND gate connected to the output end of the multi-stage trigger, used to receive at least two of the test pre-enable signals; a third AND gate connected to the output ends of at least two of the second test output subcircuits, used to output the test enable signal according to at least two of the test pre-enable signals.

[0019] In some embodiments, the second test output subcircuit further includes: an inverter, one end of the inverter is connected to the other end of the multi-stage trigger, and the other end of the inverter is connected to one end of the multi-stage trigger, for isolating static electricity.

[0020] In some embodiments, the test circuit of the chip further includes: a digital logic circuit connected to the output end of the multiplexing control circuit, configured to receive a second timing signal in a test mode and output a test result.

[0021] In order to achieve the above-mentioned purpose, an embodiment of the second aspect of the present invention proposes a chip testing method, which is used for a chip testing circuit. The chip testing circuit includes a multiplexing control circuit, a controller and a test enable detection circuit. The method includes: obtaining a first timing signal output by a test machine; when determining that the multiplexing control circuit is in a non-test mode, outputting a test pre-enable signal according to the first timing signal, or prohibiting the output of the test pre-enable signal according to the first timing signal; controlling the chip to enter the test mode according to the test pre-enable signal, or prohibiting the chip from entering the test mode according to the test pre-enable signal.

[0022] According to the chip testing method of the embodiment of the present invention, the method is used on the test circuit of the chip, the controller is connected to the output end of the multiplexing control circuit, the test enable detection circuit is connected to the output end of the controller, and the first timing signal output by the test machine is obtained through the multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, thereby ensuring the security of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0023] In order to achieve the above-mentioned object, an embodiment of the third aspect of the present invention provides a test system, comprising: a test machine, which is used to output a timing signal; a test circuit of a chip as required in the above-mentioned embodiment, connected to the test machine through IO (input / output, Input / Output ) port is connected to obtain the timing signal and control the chip test according to the timing signal.

[0024] According to the test system of an embodiment of the present invention, when the test circuit of the chip on the system is tested, the test machine is connected to the test circuit of the chip through the IO port, and the test machine outputs a timing signal, such as a first timing signal. The first timing signal output by the test machine is obtained through a multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, so that the test circuit of the chip controls the chip test according to the timing signal, thereby ensuring the safety of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0025] In order to achieve the above-mentioned objectives, an embodiment of the fourth aspect of the present invention proposes a computer-readable storage medium, on which a test circuit program of a chip is stored. When the test circuit program of the chip is executed by a processor, a device equipped with the test circuit program of the chip implements the test circuit of the chip described in the above-mentioned embodiment.

[0026] In order to achieve the above-mentioned purpose, an embodiment of the fifth aspect of the present invention proposes a computer program product, which includes a computer program, and when the computer program is executed by a processor, the test circuit of the chip described in the above-mentioned embodiment is implemented.

[0027] According to a computer program product of an embodiment of the present invention, the computer program product runs on a test system, connects a controller to an output end of a multiplexing control circuit, connects a test enable detection circuit to an output end of the controller, obtains a first timing signal output by a test machine through the multiplexing control circuit, and when the multiplexing control circuit is in a non-test mode, outputs a test pre-enable signal according to the first timing signal, or prohibits outputting the test pre-enable signal according to the first timing signal, controls the chip to enter a test mode according to the test pre-enable signal, or prohibits the chip from entering a test mode according to the test pre-enable signal, so that the test circuit of the chip controls the chip test according to the timing signal, thereby ensuring the safety of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 is a schematic diagram of the structure of a test circuit according to a specific embodiment of the present invention;

[0031] Figure 2 is a schematic structural diagram of a chip test circuit according to an embodiment of the present invention;

[0032] Figure 3 is a schematic structural diagram of a multiplexing control circuit according to an embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of the structure of a controller according to an embodiment of the present invention;

[0034] Figure 5 is a waveform diagram according to an embodiment of the present invention;

[0035] Figure 6 is a schematic structural diagram of a test enable detection circuit according to an embodiment of the present invention;

[0036] Figure 7 is a flow chart of a chip testing method according to an embodiment of the present invention;

[0037] Figure 8 is a flow chart of a chip testing method according to a specific embodiment of the present invention;

[0038] Fig. 9 is a structural block diagram of a test system according to an embodiment of the present invention.

[0039] Reference numerals:

[0040] A chip test circuit 11;

[0041] Testable area 50;

[0042] Test machine 100; multiplexing control circuit 101; controller 102; digital logic circuit 103; test enable detection circuit 104;

[0043] First multiplexing subcircuit 200; second multiplexing subcircuit 201; selector 202;

[0044] Timing detection subcircuit 300; safety detection subcircuit 301; test command detection subcircuit 302; first test output subcircuit 303; first trigger 304; second trigger 305; third trigger 306; first AND gate 307;

[0045] Timer 400; second test output subcircuit 401; second AND gate 403; third AND gate 404; inverter 405; trigger 406;

[0046] Test system 10. DETAILED DESCRIPTION

[0047] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0048] In the related technologies, facing the current design scale of tens of millions or even hundreds of millions of gate circuits, the DFT (Design for Testabi lity) technology that has been developed can improve test efficiency and reduce test costs. DFT technology refers to considering the test requirements of the chip in the design stage and adding specific design elements to the hardware design, so that when the chip is tested later, it can be detected whether there is a manufacturing fault in the chip in the shortest time and at the lowest cost. Its test mode is mainly used to test whether there are manufacturing problems in the production and manufacturing process of the chip, such as short circuit, open circuit, device damage, etc. Therefore, in this mode, the chip does not have the ability to work normally, so it is necessary to strictly prohibit the chip from mistakenly entering the test mode during normal operation, causing unpredictable errors in the system.

[0049] For example, use JTAG (Joint Test Action Group) or an interface similar to JTAG to enter the chip test mode. However, since JTAG is a standard universal test protocol, using JTAG or an interface similar to JTAG to enter the chip test mode will result in its security not being guaranteed. For example, an attacker may enter the test mode through the interface and read or modify internal data; the chip test coverage is low, for example, the JTAG controller part cannot be tested; the chip resource utilization is low and the chip cost is high. For example, using a JTAG-like protocol will add an additional test interface, which increases the chip area and packaging cost.

[0050] Another example is using a specific chip pin to enter the test mode of the chip. However, the specific chip pin, i.e., the non-multiplexed pin, is a very valuable resource for the chip. Using a specific chip pin to enter the test mode of the chip will result in low resource utilization of the chip, and for this pin, it is necessary to pay great attention to its safety issues, which will lead to high design costs, such as isolation of the test pin, activation of the test pin, power management of the test pin, physical design of the test pin, etc.

[0051] Another example is to use specific hardware timing or determine whether a specific register inside the chip meets a specific value to enter the chip test mode. However, both solutions have the risk of the chip mistakenly entering the test mode during normal operation, and the test cannot cover the modules used by the solution, resulting in low test coverage.

[0052] Therefore, a test circuit of the chip according to an embodiment of the present invention is adopted, a controller is connected to the output end of the multiplexing control circuit, a test enable detection circuit is connected to the output end of the controller, a first timing signal output by the test machine is obtained through the multiplexing control circuit, and when the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, thereby ensuring the security of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0053] Combine the following Figure 1-Figure 6 A test circuit of a chip according to an embodiment of the present invention is described.

[0054] like Figure 1 FIG. 1 is a schematic diagram of a test circuit structure of an embodiment of the present invention. The test machine 100 is used to send a specific timing signal when the chip needs to be tested, so that the chip can correctly enter the test mode from the non-test mode, and the subsequent test data stream of the chip is also generated by the test machine 100 and sent to the chip. The test circuit 11 of the chip includes a multiplexing control circuit 101, a controller 102 and a test enable detection circuit 104.

[0055] like Figure 2 , which is a structural block diagram of a chip test circuit according to an embodiment of the present invention, the chip test circuit 11 of the embodiment of the present invention includes a multiplexing control circuit 101 , a controller 102 and a test enable detection circuit 104 .

[0056] Among them, the multiplexing control circuit 101 is used to obtain the first timing signal output by the test machine; the controller 102 is connected to the output end of the multiplexing control circuit, and is used to output a test pre-enable signal according to the first timing signal when the multiplexing control circuit is in a non-test mode, or to prohibit the output of the test pre-enable signal according to the first timing signal; the test enable detection circuit 103 is connected to the output end of the controller, and is used to control the chip to enter the test mode according to the test pre-enable signal, or to prohibit the chip from entering the test mode according to the test pre-enable signal.

[0057] In an embodiment, Figure 1 As shown, the input end of the multiplexing control circuit 101 is connected to the output end of the test machine 100. When the chip is to be tested, the multiplexing control circuit 101 will receive and output the first timing signal output by the test machine 100. The first timing signal is such as the timing of the test mode command and the burning mode timing, so as to realize the test pre-enable control according to the first timing signal.

[0058] The controller 102 is connected to the output end of the multiplexing control circuit 101. When the multiplexing control circuit 101 is in a non-test mode, the test pre-enable signal is output according to the first timing signal, or the test pre-enable signal is prohibited from being output according to the first timing signal. For example, after receiving the first timing signal, the first timing signal such as the test mode command timing and the burning mode timing, the controller 102 will judge the correctness of the received burning mode timing. If the judgment result is wrong, the burning mode cannot be entered, and the output of the test pre-enable signal is prohibited. If the judgment result is correct, the correctness of the received test mode command timing needs to be judged. For example, if it is judged that as long as there is one command error or sequence error in the 10 received test mode command timings, the output of the test pre-enable signal is prohibited. If the commands and sequences of the 10 received test mode command timings are correct, the test pre-enable signal is output. The controller 102 judges the correctness of the first timing signal to control the output of the test pre-enable signal or prohibit the output, so as to facilitate test enable control and reduce the risk of the chip entering the test mode by mistake.

[0059] The test enable detection circuit 104 is connected to the output end of the controller 102, and controls the chip to enter the test mode according to the test pre-enable signal output by the controller 102, or prohibits the chip from entering the test mode according to the test pre-enable signal. For example, the timing starts from the power-on of the chip. If the test enable detection circuit 104 receives the test pre-enable signal output by the controller 102 within the preset time, the chip is controlled to enter the test mode. If the test enable detection circuit 104 does not receive the test pre-enable signal output by the controller 102 within the preset time, the chip is prohibited from entering the test mode, so as to facilitate test mode control and reduce the risk of the chip mistakenly entering the test mode.

[0060] The test enable detection circuit 104 is an independent circuit module with fewer circuits and a low probability of production failure. It is built into the chip, which can save dedicated pins of the chip, ensure the safety of the chip, and save chip and design costs. In addition to the test enable detection circuit 104, the multiplexing control circuit 101 and the controller 102 can both perform test coverage, thereby improving the test coverage and resource utilization of the chip.

[0061] According to the test circuit of the chip of the embodiment of the present invention, the controller is connected to the output end of the multiplexing control circuit, the test enable detection circuit is connected to the output end of the controller, and the first timing signal output by the test machine is obtained through the multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, thereby ensuring the security of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0062] In some embodiments, Figure 3 FIG. 1 is a schematic diagram of a multiplexing control circuit according to an embodiment of the present invention. Figure 1 and Figure 3 The multiplexing control circuit 101 includes a first multiplexing sub-circuit 200, a second multiplexing sub-circuit 201 and a selector 202. The first multiplexing sub-circuit 200 is connected to the output end of the test machine 100, and is used to output a first timing signal in a non-test mode. The first timing signal includes a burning mode timing and a test mode command timing; the second multiplexing sub-circuit 201 is connected to the output end of the test machine 100, and is used to output a second timing signal in a test mode. The second timing signal includes a digital logic test timing; the selector 202 is respectively connected to the output end of the first multiplexing sub-circuit 200 and the output end of the second multiplexing sub-circuit 201, and is used to select the output of the first timing signal or the second timing signal.

[0063] In an embodiment, in combination Figure 1 and Figure 3 The selector 202 is a device with multiple inputs and one output. It selects an output from the multiple inputs according to an input selection signal. The multiplexing control circuit 101 includes a first multiplexing sub-circuit 200, a second multiplexing sub-circuit 201 and a selector 202. The first multiplexing sub-circuit 200 is connected to the output end of the test machine 100, and the second multiplexing sub-circuit 201 is connected to the output end of the test machine 100. The selector 202 is respectively connected to the output end of the first multiplexing sub-circuit 200 and the output end of the second multiplexing sub-circuit 201.

[0064] In non-test mode, the test machine 100 sends the burning mode timing and test mode command timing sent through the input and output pins as the first timing signal to the first multiplexing sub-circuit 200. In test mode, the test machine 100 sends the digital logic test timing sent through the input and output pins as the second timing signal to the second multiplexing sub-circuit 201. The first multiplexing sub-circuit 200 and the second multiplexing sub-circuit 201 send the received timing to the selector 202 respectively. After receiving the corresponding timing signal, the selector 202 selects to output the first timing signal or the second timing signal. The chip is in non-test mode. , the selector 202 switches the signal output to the first multiplexing sub-circuit 200 to use the multiplexing function normally. When the chip is in the test mode, the selector 202 switches the output signal to the second multiplexing sub-circuit 201, wherein the normal multiplexing function of the first multiplexing sub-circuit 200 is a testable logic, and the test multiplexing function of the second multiplexing sub-circuit 201 and the selector 202 are untestable logic, thereby improving the test coverage and resource utilization of the chip, and the selector 202 selects to output the first timing signal or the second timing signal to control the corresponding signal output of the test mode or the non-test mode, which provides a basis for preventing the chip from entering the test mode by mistake.

[0065] In some embodiments, Figure 4 FIG. 1 is a schematic diagram of the structure of a controller according to an embodiment of the present invention. Figure 1 The controller 102 includes a timing detection subcircuit 300 and a safety detection subcircuit 301. The timing detection subcircuit 300 is connected to the output end of the multiplexing control circuit 101, and is used to receive the first timing signal. When it is determined according to the first timing signal that the burning mode timing in the first timing signal is correct, the burning mode is entered and the test mode command timing in the first timing signal is output; the safety detection subcircuit 301 is connected to the output end of the timing detection subcircuit 300, and is used to output a test pre-enable signal according to the test mode command timing, or prohibit the output of the test pre-enable signal according to the test mode command timing.

[0066] In an embodiment, in combination Figure 1 and Figure 4 The controller 102 includes a timing detection subcircuit 300 and a safety detection subcircuit 301 . The timing detection subcircuit 300 is connected to the output end of the multiplexing control circuit 101 , and the safety detection subcircuit 301 is connected to the output end of the timing detection subcircuit 300 .

[0067] The timing detection subcircuit 300 receives the first timing signal, and when it is determined according to the first timing signal that the burning mode timing in the first timing signal is correct, enters the burning mode and outputs the test mode command timing in the first timing signal. For example, after receiving the correct burning mode timing, the timing detection subcircuit 300 can turn on the clock and reset of the safety detection subcircuit 301 area, enter the burning mode, and output the test mode command timing in the first timing signal. After the timing detection subcircuit 300 receives the wrong burning mode timing, the safety detection subcircuit 301 area will be in a reset state, unable to enter the burning mode, and unable to output the test mode command timing in the first timing signal, thereby avoiding entering the test mode and reducing the risk of mistakenly entering the test mode due to abnormal timing; the safety detection subcircuit 301 outputs a test pre-enable signal according to the test mode command timing, or prohibits the output of the test pre-enable signal according to the test mode command timing, so that the controller can implement test pre-enable control.

[0068] In some embodiments, Figure 4 As shown, the safety detection subcircuit 301 includes a test command detection subcircuit 302 and a first test output subcircuit 303. The test command detection subcircuit 302 is connected to the output end of the timing detection subcircuit, and is used to prohibit the output of the test pre-enable signal when a preset number of test mode command timings are incorrect, or to output the test enable pre-start signal when a preset number of test mode command timings are correct; the first test output subcircuit 303 is connected to the output end of the test command detection subcircuit 302, and is used to output the test pre-enable signal according to the test enable pre-start signal, or to prohibit the output of the test pre-enable signal according to the test enable pre-start signal.

[0069] In an embodiment, Figure 4 As shown, the safety detection subcircuit 301 includes a test command detection subcircuit 302 and a first test output subcircuit 303 . The test command detection subcircuit 302 is connected to the output end of the timing detection subcircuit 300 , and the first test output subcircuit 303 is connected to the output end of the test command detection subcircuit 302 .

[0070] The test command detection subcircuit 302 is used to prohibit the output of the test pre-enable signal when the timing of a preset number of test mode commands is wrong, or to output the test enable pre-start signal when the timing of a preset number of test mode commands is correct. For example, assuming that the preset number is 10, after receiving the test mode command timing in the first timing signal output by the timing detection subcircuit 300, the test command detection subcircuit 302 will detect the correctness of the 10 test mode command timings. If there is one error or the sequence is wrong in the 10 test mode command timings, the output of the test pre-enable signal is prohibited, and the chip cannot enter the test mode. If the values ​​and sequences of the 10 test mode command timings are correct, the test enable pre-start signal is output, which reduces the risk of mistakenly entering the test mode due to abnormal timing and lays the foundation for the subsequent output of the test pre-enable signal; the first test output subcircuit 303 outputs the test pre-enable signal according to the test enable pre-start signal, or prohibits the output of the test pre-enable signal according to the test enable pre-start signal, so that the controller can realize test pre-enable control.

[0071] In some embodiments, Figure 4 As shown, the first test output subcircuit 303 includes at least two triggers and a first AND gate 307. The at least two triggers are connected to the output end of the test command detection subcircuit 302, and are used to receive a test enable pre-start signal and output at least two trigger output signals; the first AND gate 307 is connected to the output end of the at least two triggers, and is used to prohibit the output of the test pre-enable signal according to the at least two trigger output signals, or output the test pre-enable signal.

[0072] In an embodiment, Figure 4 As shown, the first test output subcircuit 303 includes at least two triggers and a first AND gate 307, wherein the triggers, such as the first trigger 304, the second trigger 305 and the third trigger 306, at least two triggers are connected to the output ends of the test command detection subcircuit 302, and the first AND gate 307 is connected to the output ends of the at least two triggers.

[0073] At least two triggers receive a test enable pre-start signal and output at least two trigger output signals. For example, if the trigger works normally and no abnormal flip occurs, the output trigger output signal is a test enable pre-start signal. If an abnormal flip occurs, the output trigger output signal is a test pre-enable signal that prohibits output. At least two triggers receive a test pre-enable signal that prohibits output. If the trigger works normally and no abnormal flip occurs, the output trigger output signal is a test pre-enable signal that prohibits output. If an abnormal flip occurs, the output trigger output signal is a test enable pre-start signal. The first AND gate 307 performs a logical AND operation based on at least two trigger output signals and outputs a test pre-enable signal that prohibits output, or outputs a test pre-enable signal. The test pre-enable signal mode is determined by performing a logical AND operation of multiple triggers and the first AND gate, thereby reducing the risk of the chip mistakenly entering the test mode due to a harsh external working environment, such as abnormal flipping of the trigger caused by an electromagnetic pulse or the impact of cosmic rays, thereby reducing the probability of the chip mistakenly entering the test mode.

[0074] In some embodiments, the first test output subcircuit is specifically configured to prohibit outputting a test pre-enable signal according to output signals of other triggers when an output signal of one of the triggers is abnormal.

[0075] In an embodiment, the output signal of one of the triggers is abnormal, for example, Figure 5 In the first test output subcircuit abnormal waveform on the left side of the waveform, the input signal is the output test pre-enable signal, and the first trigger 304, the second trigger 305 and the third trigger 306 receive the output test pre-enable signal, and the corresponding waveforms are respectively Figure 5 The first trigger, the second trigger and the third trigger in the embodiment, wherein the waveform of the first trigger 304 is an abnormal waveform, when one and / or two of the three triggers generate an abnormal flip due to an external environment such as an electromagnetic pulse or cosmic rays and generate an abnormal waveform, for example, the first trigger 304 generates an abnormal flip and the output signal is abnormal, the received output test pre-enable signal is changed to an output test enable pre-start signal and outputted, the waveforms of the first trigger 304, the second trigger 305 and the third trigger 306 are logically ANDed by the first AND gate 307 and the output result is the output test pre-enable signal, which is the correct output result; only when the first trigger 304, the second trigger 305 and the third trigger 306 are abnormally flipped, that is, the output test pre-enable signal received by all triggers is changed to an output test enable pre-start signal and outputted, the output result of the three triggers through the first AND gate 307 is the output test pre-enable signal, which is an incorrect output result. Assuming that a single trigger is used, in Figure 5In the abnormal waveform of a single trigger, the input signal is a signal for disabling the output test pre-enablement. When the trigger abnormally flips over to an output test enable pre-start signal, the output result of the logic AND of the trigger through the first AND gate 307 is the output test pre-enablement signal, which is an erroneous output result. The chip will mistakenly enter the test mode, reducing the risk of the chip mistakenly entering the test mode due to a harsh external working environment, such as an abnormal flip of the trigger caused by an electromagnetic pulse or the impact of cosmic rays, thereby reducing the probability of the chip mistakenly entering the test mode.

[0076] In some embodiments, Figure 6 , which is a schematic diagram of the structure of a test enable detection circuit according to an embodiment of the invention. The test enable detection circuit includes a timer 400 and at least two second test output subcircuits 401. The timer 400 is connected to the output end of the controller 102, and is used to output a reset signal when the test enable detection circuit does not receive a test pre-enable signal within a preset time; at least two second test output subcircuits 401 are connected to the output end of the timer, and are used to reset the second test output subcircuits 401 when receiving a reset signal, or, when a test pre-enable signal is received within a preset time, the control chip enters a test mode.

[0077] In an embodiment, Figure 6 As shown, the test enable detection circuit 104 includes a timer 400 and at least two second test output sub-circuits 401, the timer 400 is connected to the output end of the controller 102, and the at least two second test output sub-circuits 401 are connected to the output end of the timer 400, wherein the logics of the two second test output sub-circuits 401 are exactly the same, and during layout and routing, they are placed in two completely different areas in the chip to physically isolate them to reduce the impact of cosmic rays.

[0078] The timer 400 starts timing from the time the chip is powered on, and receives a test pre-enable signal output by the controller 102 within a preset time. When the test enable detection circuit does not receive the correct test pre-enable signal output by the controller 102 within the preset time, it outputs a reset signal and sends it to at least two second test output sub-circuits 401. When the at least two second test output sub-circuits 401 receive the reset signal, the second test output sub-circuits are reset, thereby preventing the chip from entering the test mode. Alternatively, when the correct test pre-enable signal output by the controller 102 is received within the preset time, the chip is controlled to enter the test mode. The chip is controlled to enter the test mode by the timer and at least two second test output sub-circuits, thereby reducing the risk of mistakenly entering the test mode due to abnormal timing, thereby reducing the risk of the chip mistakenly entering the test mode.

[0079] In some embodiments, Figure 6As shown, the second test output subcircuit includes a multi-stage trigger, a second AND gate 403 and a third AND gate 404. The multi-stage trigger is connected to the output end of the timer to filter out interference signals in the test pre-enable signal; the second AND gate is connected to the output end of the multi-stage trigger to receive at least two test pre-enable signals; the third AND gate is connected to the output ends of at least two second test output subcircuits to output a test enable signal based on at least two test pre-enable signals.

[0080] In an embodiment, Figure 6 As shown, the second test output subcircuit 401 includes a multi-stage trigger, a second AND gate 403 and a third AND gate 404, wherein the multi-stage trigger refers to a plurality of triggers 406 cascaded, the multi-stage trigger is connected to the output end of the timer 400, the second AND gate 403 is connected to the output end of the multi-stage trigger, and the third AND gate 404 is connected to the output ends of at least two second test output subcircuits 401.

[0081] The multi-stage trigger can filter out interference signals in the test pre-enable signal. The second AND gate 403 receives at least two test pre-enable signals, and the third AND gate 404 outputs a test enable signal according to the at least two test pre-enable signals. For example, the input of the timer is a test pre-enable signal for disabling output. When one of the two second test output sub-circuits 401 has problems due to production, packaging, testing, external environment and other factors, the test pre-enable signal for disabling output received by one of the circuits is changed into an output test pre-enable signal and output after the test output sub-circuit, and the test pre-enable signal for disabling output received by the other circuit is not changed and output after the test output sub-circuit. Since the result of whether to enter the test mode is obtained by the output results of the two test output sub-circuits through the logic AND of the third AND gate 404, it is still a test enable signal for disabling output after the logic AND, thereby reducing the risk of entering the erroneous test mode due to combinational logic glitches, thereby reducing the risk of the chip entering the test mode by mistake.

[0082] In some embodiments, the second test output subcircuit further includes an inverter, one end of the inverter is connected to the other end of the multi-stage trigger, and the other end of the inverter is connected to one end of the multi-stage trigger for isolating static electricity.

[0083] In an embodiment, Figure 6 As shown, the second test output subcircuit 401 also includes an inverter 405, one end of the inverter 405 is connected to the other end of the multi-stage trigger, the multi-stage trigger refers to a cascade of multiple triggers 406, the other end of the inverter is connected to one end of the multi-stage trigger, and a structure of a multi-stage trigger plus an inverter is used, and then the output signal result is combined through the second AND gate 403 logic AND, which reduces the risk of the chip mistakenly entering the test mode, and the inverter can reduce the damage to the chip caused by static electricity.

[0084] In some embodiments, the test circuit of the chip further includes a digital logic circuit connected to the output end of the multiplexing control circuit, and configured to receive the second timing signal in the test mode and output the test result.

[0085] In an embodiment, Figure 1 As shown, the test circuit of the chip also includes a digital logic circuit 103 connected to the output end of the multiplexing control circuit 101. The digital logic circuit 103 does not have normal functions in the test mode. When designing the hardware circuit, it is necessary to group the triggers and combinational logics and string them into a logic chain on the basis of completing the original functional design, so that the digital logic circuit 103 can receive a second timing signal in the test mode, such as a digital logic test timing, and output the test result to the multiplexing control circuit 101. The multiplexing control circuit 101 outputs the test result outside the chip to verify the correctness of the digital logic circuit 103. The design of the logic circuit 103 is relatively independent, so the test coverage of this part can reach a very high level.

[0086] The following is a flow chart of a chip testing method according to an embodiment of the second aspect of the present invention.

[0087] like Figure 7 FIG. 1 is a flow chart of a chip testing method according to an embodiment of the present invention. The chip testing method according to an embodiment of the present invention at least includes steps S1 to S3.

[0088] Step S1, obtaining a first timing signal output by a test machine;

[0089] In an embodiment, Figure 1 As shown, the input end of the multiplexing control circuit 101 is connected to the output end of the test machine 100. When the chip is to be tested, the multiplexing control circuit 101 will receive and output the first timing signal output by the test machine 100. The first timing signal is such as the test mode command timing and the burning mode timing, so as to realize the test pre-enable control according to the first timing signal.

[0090] Step S2, when the multiplexing control circuit is in a non-test mode, outputting a test pre-enable signal according to the first timing signal, or prohibiting outputting the test pre-enable signal according to the first timing signal.

[0091] In an embodiment, Figure 1As shown, the controller 102 is connected to the output end of the multiplexing control circuit 101. When the multiplexing control circuit 101 is in the non-test mode, the test pre-enable signal is output according to the first timing signal, or the test pre-enable signal is prohibited from being output according to the first timing signal. For example, after receiving the first timing signal, the first timing signal such as the test mode command timing and the burning mode timing, the controller 102 will judge the correctness of the received burning mode timing. If the judgment result is wrong, the burning mode cannot be entered, and the output of the test pre-enable signal is prohibited. If the judgment result is correct, the correctness of the received test mode command timing needs to be judged. For example, if it is judged that as long as there is one command or sequence error in the 10 received test mode command timings, the output of the test pre-enable signal is prohibited. If the commands and sequences of the 10 received test mode command timings are correct, the test pre-enable signal is output. The controller 102 judges the correctness of the first timing signal to control the output of the test pre-enable signal or prohibit the output, so as to facilitate test enable control and reduce the risk of the chip entering the test mode by mistake.

[0092] Step S3, controlling the chip to enter the test mode according to the test pre-enable signal, or prohibiting the chip from entering the test mode according to the test pre-enable signal.

[0093] In an embodiment, Figure 1 As shown, the test enable detection circuit 104 is connected to the output end of the controller 102, and controls the chip to enter the test mode according to the test pre-enable signal output by the controller 102, or prohibits the chip from entering the test mode according to the test pre-enable signal. For example, the timing starts from the power-on of the chip. If the test enable detection circuit 104 receives the test pre-enable signal output by the controller 102 within the preset time, the chip is controlled to enter the test mode. If the test enable detection circuit 104 does not receive the test pre-enable signal output by the controller 102 within the preset time, the chip is prohibited from entering the test mode, so as to facilitate test mode control and reduce the risk of the chip mistakenly entering the test mode.

[0094] The test enable detection circuit 104 is an independent circuit module with fewer circuits and a low probability of production failure. It is built into the chip, which can save dedicated pins of the chip, ensure the safety of the chip, and save chip and design costs. In addition to the test enable detection circuit 104, the multiplexing control circuit 101 and the controller 102 can both perform test coverage, thereby improving the test coverage and resource utilization of the chip.

[0095] According to the chip testing method of the embodiment of the present invention, the method is used on the test circuit of the chip, the controller is connected to the output end of the multiplexing control circuit, the test enable detection circuit is connected to the output end of the controller, and the first timing signal output by the test machine is obtained through the multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, thereby ensuring the security of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0096] Reference below Figure 8 The chip testing method according to the embodiment of the present invention is described in detail.

[0097] like Figure 8 , which is a flow chart of a chip testing method according to an embodiment of the present invention. The chip testing method according to the embodiment of the present invention at least includes steps S10 to S25.

[0098] Step S10, obtaining a timing signal output by a test machine.

[0099] Step S11, determine whether the multiplexing circuit is in a non-test mode. If yes, execute step S12; otherwise, execute step S13.

[0100] Step S13: the second multiplexing sub-circuit outputs a second timing signal, including a digital logic test timing.

[0101] Step S14: the selector outputs a second timing signal.

[0102] Step S15, testing the chip and outputting the test results.

[0103] Step S12: the first multiplexing sub-circuit outputs a first timing signal, including a programming mode timing and a test mode command timing.

[0104] Step S16: the selector outputs a first timing signal.

[0105] In step S17, the controller determines whether the timing of the programming mode and the preset number of test mode commands is correct. If so, step S18 is executed; otherwise, step S19 is executed.

[0106] Step S18, outputting a test enable pre-start signal.

[0107] Step S19, prohibiting the output of the test pre-enable signal.

[0108] Step S20, the controller determines whether the test enable pre-start signal is correct. If so, step S21 is executed; otherwise, step S22 is executed.

[0109] Step S21, testing the pre-enable signal.

[0110] Step S22, prohibiting the output of the test pre-enable signal.

[0111] Step S23, the test enable detection circuit determines whether a correct test pre-enable signal is received within a preset time. If yes, execute step S24; otherwise, execute step S25.

[0112] Step S24, controlling the chip to enter a test mode.

[0113] Step S25, prohibiting the chip from entering the test mode.

[0114] According to the chip testing method of the embodiment of the present invention, the controller is connected to the output end of the multiplexing control circuit, the test enable detection circuit is connected to the output end of the controller, and the first timing signal output by the test machine is obtained through the multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, so that the chip test circuit controls the chip test according to the timing signal, thereby ensuring the safety of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0115] Reference below Fig. 9 A test system according to an embodiment of the present invention is described.

[0116] like Fig. 9 , which is a structural block diagram of a test system according to an embodiment of the present invention. The test system according to the embodiment of the present invention includes a test machine 100 and a chip test circuit 11.

[0117] The test machine 100 is connected to the chip test circuit 11 through an IO port for outputting timing signals, such as a first timing signal and a second timing signal, so that the chip test circuit 11 controls the chip test according to the timing signals.

[0118] According to the test system of an embodiment of the present invention, when the test circuit of the chip on the system is tested, the test machine 100 is connected to the test circuit 11 of the chip through the IO port, and the test machine outputs a timing signal, such as a first timing signal. The first timing signal output by the test machine is obtained through the multiplexing control circuit. When the multiplexing control circuit is in a non-test mode, a test pre-enable signal is output according to the first timing signal, or the output of the test pre-enable signal is prohibited according to the first timing signal, and the chip is controlled to enter the test mode according to the test pre-enable signal, or the chip is prohibited from entering the test mode according to the test pre-enable signal, so that the test circuit of the chip controls the chip test according to the timing signal, thereby ensuring the safety of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0119] The following describes a computer-readable storage medium according to an embodiment of the present invention.

[0120] The computer-readable storage medium of an embodiment of the present invention stores a chip test circuit program on the computer-readable storage medium. When the chip test circuit program is executed by a processor, a device installed with the chip test circuit program implements the chip test circuit of the above embodiment.

[0121] The following describes a computer program product according to an embodiment of the present invention.

[0122] The computer program product of the embodiment of the present invention includes a computer program, and when the computer program is executed by a processor, the test circuit of the chip of the above embodiment is implemented.

[0123] According to a computer program product of an embodiment of the present invention, the computer program product runs on a test system, connects a controller to an output end of a multiplexing control circuit, connects a test enable detection circuit to an output end of the controller, obtains a first timing signal output by a test machine through the multiplexing control circuit, and when the multiplexing control circuit is in a non-test mode, outputs a test pre-enable signal according to the first timing signal, or prohibits outputting the test pre-enable signal according to the first timing signal, controls the chip to enter a test mode according to the test pre-enable signal, or prohibits the chip from entering a test mode according to the test pre-enable signal, so that the test circuit of the chip controls the chip test according to the timing signal, thereby ensuring the safety of the chip, improving the test coverage and resource utilization of the chip, reducing the risk of the chip mistakenly entering the test mode, and saving chip and design costs.

[0124] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0125] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip test circuit, characterized in that: include: A multiplexing control circuit, used for acquiring a first timing signal output by a test machine; a controller connected to the output end of the multiplexing control circuit, and configured to output a test pre-enable signal according to the first timing signal when the multiplexing control circuit is in a non-test mode, or to prohibit outputting the test pre-enable signal according to the first timing signal; A test enable detection circuit is connected to the output end of the controller and is used to control the chip to enter the test mode according to the test pre-enable signal, or to prohibit the chip from entering the test mode according to the test pre-enable signal.

2. The chip test circuit according to claim 1, characterized in that: The multiplexing control circuit comprises: A first multiplexing sub-circuit is connected to the output terminal of the test machine, and is used to output the first timing signal in the non-test mode, wherein the first timing signal includes a burning mode timing and a test mode command timing; A second multiplexing sub-circuit is connected to the output terminal of the test machine and is used to output a second timing signal in a test mode, wherein the second timing signal includes a digital logic test timing; The selector is connected to the output end of the first multiplexing sub-circuit and the output end of the second multiplexing sub-circuit respectively, and is used for selecting to output the first timing signal or the second timing signal.

3. The chip test circuit according to claim 1, characterized in that: The controller comprises: a timing detection subcircuit connected to the output end of the multiplexing control circuit, and configured to receive the first timing signal, and when it is determined according to the first timing signal that the programming mode timing in the first timing signal is correct, enter the programming mode, and output the test mode command timing in the first timing signal; The safety detection subcircuit is connected to the output end of the timing detection subcircuit, and is used to output the test pre-enable signal according to the test mode command timing, or to prohibit the output of the test pre-enable signal according to the test mode command timing.

4. The chip test circuit according to claim 3, characterized in that: The safety detection subcircuit comprises: A test command detection subcircuit connected to the output end of the timing detection subcircuit, used to prohibit outputting a test pre-enable signal when a preset number of the test mode command timings are wrong, or to output a test enable pre-start signal when a preset number of the test mode command timings are correct; The first test output subcircuit is connected to the output end of the test command detection subcircuit, and is used to output the test pre-enable signal according to the test enable pre-start signal, or prohibit outputting the test pre-enable signal according to the test enable pre-start signal.

5. The chip test circuit according to claim 4, characterized in that: The first test output subcircuit comprises: At least two triggers, connected to the output end of the test command detection subcircuit, for receiving the test enable pre-start signal and outputting at least two trigger output signals; The first AND gate is connected to the output ends of at least two of the triggers, and is used to prohibit outputting the test pre-enable signal or output the test pre-enable signal according to the at least two trigger output signals.

6. The chip test circuit according to claim 4, characterized in that: The first test output subcircuit is specifically used for: When the output signal of one of the triggers is abnormal, the output of the test pre-enable signal is prohibited according to the output signals of the remaining triggers.

7. The chip test circuit according to claim 1, characterized in that: The test enable detection circuit comprises: A timer connected to the output end of the controller, and configured to output a reset signal when the test enable detection circuit does not receive the test pre-enable signal within a preset time; At least two second test output sub-circuits are connected to the output end of the timer, and are used to reset the second test output sub-circuit when receiving the reset signal, or control the chip to enter the test mode when receiving the test pre-enable signal within the preset time.

8. The chip test circuit according to claim 7, characterized in that: The second test output subcircuit comprises: A multi-stage trigger, connected to the output end of the timer, for filtering out interference signals in the test pre-enable signal; A second AND gate, connected to the output end of the multi-stage trigger, for receiving at least two of the test pre-enable signals; A third AND gate is connected to the output terminals of at least two of the second test output sub-circuits, and is used for outputting the test enable signal according to at least two of the test pre-enable signals.

9. The chip test circuit according to claim 8, characterized in that: The second test output subcircuit further includes: An inverter, one end of which is connected to the other end of the multi-stage trigger, and the other end of which is connected to one end of the multi-stage trigger, is used to isolate static electricity.

10. The chip test circuit according to claim 1, characterized in that: The test circuit of the chip also includes: The digital logic circuit is connected to the output end of the multiplexing control circuit and is used to receive the second timing signal in the test mode and output the test result.

11. A chip testing method, characterized in that: A test circuit for a chip, the test circuit of the chip comprising a multiplexing control circuit, a controller and a test enable detection circuit, the method comprising: Acquire a first timing signal output by the test machine; When determining that the multiplexing control circuit is in a non-test mode, outputting a test pre-enable signal according to the first timing signal, or prohibiting outputting the test pre-enable signal according to the first timing signal; The chip is controlled to enter a test mode according to the test pre-enable signal, or the chip is prohibited from entering a test mode according to the test pre-enable signal.

12. A testing system, characterized in that: include: A test machine, used to output timing signals; The chip test circuit according to any one of claims 1 to 10 is connected to the test machine through an IO port, and is used to obtain the timing signal and control the chip test according to the timing signal.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a chip test circuit program, and when the chip test circuit program is executed by a processor, a device installed with the chip test circuit program implements the chip test circuit as described in any one of claims 1-10.

14. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the test circuit of the chip according to any one of claims 1 to 10 is implemented.

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