Redundant backup control circuit based on double DSP and FPGA architecture

Abstract

The invention belongs to the technical field of aviation electrical, and particularly relates to a redundant backup control circuit based on a double-DSP and FPGA architecture. Each set of acquisition module is connected with a set of DSP system, and the two sets of DSP systems are connected with a set of FPGA system; when the two sets of DSP systems are hot backups for each other, the two sets of acquisition modules are used for acquiring external input quantities and respectively inputting the external input quantities into the two corresponding sets of DSP systems; the DSP system is used for calculating an external input quantity, outputting a control quantity and transmitting the control quantity to the FPGA system; the FPGA system carries out decision and outputs the control quantity to the outside; and when the two DSP systems are cold backups for each other, one DSP system operates, and the other DSP system is dormant, so that hot and cold backups are realized according to requirements.

Description

Technical Field

[0001] The present application belongs to the field of aviation electrical technology, and in particular, relates to a redundant backup control circuit based on a dual DSP and FPGA architecture. Background Art

[0002] With the development of modern science and technology and the improvement of automation technology, the complexity of various engineering systems has greatly increased, and higher requirements have been put forward for system reliability and safety. In order to improve system reliability, one solution is to adopt error avoidance design, that is, to reduce the probability of system failure by selecting components with good quality and high reliability. However, in engineering practice, this solution will undoubtedly increase hardware costs. Another solution is to adopt redundant backup technology, that is, when individual modules of the system fail, the system automatically detects and handles the fault to ensure the normal operation of the system. Considering the actual engineering, redundant backup technology can still meet the requirements of high reliability of the system as a whole while appropriately relaxing the reliability requirements of some components.

[0003] The backup system is divided into two states: cold backup and hot backup. A cold backup system means that when the system is working normally, the backup module will not be powered on and will not perform corresponding operations. Only when the main system module fails will the system start the backup module. Although cold backup can save resources and reduce power consumption, it will increase the time delay when the main system module and the faulty backup module are switched to a certain extent, so it often cannot meet the requirements of systems with high timeliness. A hot backup system means that the backup module and the system equipment work at the same time. Once the main system module fails, the hot backup module quickly takes over its work to ensure the normal operation of the system.

[0004] At present, most of the generator controllers or power control boxes used in the onboard power supply system are digital controllers based on DSP and CPLD or DSP and FPGA architecture, in which DSP is the main control chip and CPLD / FPGA is the auxiliary control chip (the main function is to assist DSP to realize product functions), and the entire control circuit has no redundant design. Since the generator controller or power control box is in an environment with strong vibration, strong electromagnetic interference, strong corrosion, and large temperature shock on the aircraft, the electronic components used in the generator controller or power control box are often ceramic packages. After analyzing the statistical results of the failures of the generator controller or power control box that have been installed and used for many years, it is found that most of the failures of the generator controller or power control box on the aircraft occur in the control circuit, which is mainly manifested as DSP software failure, CPLD / FPGA software failure, electronic component pin desoldering or breakage, and abnormal operation of electronic components under high and low temperature. Therefore, the use of a control circuit with no redundant design often causes the aircraft to interrupt the mission and return early due to abnormal power failure of the generator controller or power control box in the air, causing strong dissatisfaction among users. Summary of the invention

[0005] In order to solve the above problems, the present application provides a redundant backup control circuit based on dual DSP and FPGA architecture, including two sets of acquisition modules, two sets of DSP systems, and one set of FPGA system;

[0006] Each set of the acquisition modules is connected to a DSP system respectively, and both sets of DSP systems are connected to a set of FPGA system;

[0007] When two DSP systems serve as hot backup for each other:

[0008] The two sets of acquisition modules are used to acquire external input quantities and input the external input quantities into the corresponding two sets of DSP systems respectively;

[0009] The DSP system is used to calculate the external input quantity and output the control quantity, and transmit the control quantity to the FPGA system;

[0010] The FPGA system is used to judge the two control quantities and output the control quantity output by one of the DSP systems to the outside;

[0011] When two DSP systems serve as cold backup for each other:

[0012] One set of the acquisition modules is used to acquire external input quantities and input the external input quantities into the corresponding DSP system. The DSP system calculates the external input quantities and outputs the control quantities. The DSP system calculates the external input quantities and generates output control quantities, and transmits the output control quantities to the FPGA. Finally, the FPGA outputs the output control quantities. Another set of the acquisition modules and the corresponding DSP system are in a dormant state.

[0013] When the running DSP system fails, the FPGA system recognizes that the running DSP system is abnormal, and the FPGA system will wake up the other sleeping DSP system through the DSP GPIO pin. During the switching process between the two DSP systems, the FPGA will control the control amount output to the outside.

[0014] Preferably, the FPGA system arbitrates the control quantity output by the two DSP systems based on the external input clocks of the two DSP systems, the DSP chip "heartbeat", the task status signal output by the DSP software, and the power supply conditions of the two DSP systems.

[0015] Preferably, each set of acquisition modules includes: a discrete quantity input level conversion module and an analog quantity acquisition module; the two sets of acquisition modules are identical;

[0016] The FPGA system includes: an FPGA chip, an FPGA power module connected to the FPGA chip, an FPGA clock module, a communication level conversion module, and a control quantity level conversion module;

[0017] Each DSP system includes: DSP chip, DSP storage module connected to DSP chip, DSP clock module, DSP power module and RS422 communication module;

[0018] Among them, the CPIO pin of the DSP chip is connected to the FPGA chip for waking up the system; the DSP chip and the FPGA chip communicate through the bus; the FPGA chip is connected to the DSP storage module and the RS422 communication module through the FPGA signal harness.

[0019] Preferably, the bus signals between the DSP chip and the FPGA chip are EMIF bus and SPI bus, which reserve an interface for data interaction between the DSP and the FPGA.

[0020] Preferably, the GPIO pins between the DSP chip and the FPGA chip can be configured by the DSP as NMI interrupt function pins, external shieldable function pins, and DSP sleep state wake-up function pins.

[0021] Preferably, the AD conversion result finally output by the analog quantity acquisition module is sent to the FPGA chip, and the FPGA chip can perform digital processing on the collected analog quantity.

[0022] Preferably, the power supply for the two DSP systems includes a new 5V power supply generated by processing two 5V power supplies through a 5V power supply module; the 5V power supply module includes a voting module, a capacitor module DC / DC module and a capacitor module connected in series, and the voting module is connected to the two 5V power supplies.

[0023] Preferably, when the two DSP systems are in hot backup mode, the two DSP chips will use the on-chip A / D conversion module to collect the power supply of the two DSP chips, and then transmit the collected results to the FPGA chip and record them in the storage modules of the two DSP systems.

[0024] The advantages of this application include: it can realize both hot backup operation of the dual DSP system and cold backup operation of the dual DSP system. On the basis of the traditional DSP and CPLD / FPGA architecture, a set of DSP system circuits is added to realize the redundant backup control circuit design of the dual DSP system, which improves the reliability of the product, reduces the probability of power outage accidents in the air, and improves the completion rate of the aircraft's mission. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1It is the principle block diagram of the redundant backup control circuit of dual DSP and FPGA architecture

[0026] Figure 2 This is the circuit diagram of the 5V power module. DETAILED DESCRIPTION

[0027] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present application will be further described in detail in detail and in detail in conjunction with the accompanying drawings. It can be understood that the specific embodiments described here are only partial embodiments of the present application, which are only used to explain the present application, not to limit the present application. It should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments in the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.

[0028] In addition, it should be noted that, unless otherwise clearly specified and limited, the words "installed", "connected", "connected" and similar terms used in the description of this application should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or the internal connection of two components. Technical personnel in the field can understand their specific meanings in this application according to the specific circumstances.

[0029] like Figure 1 As shown, the present application provides a redundant backup control circuit based on dual DSP and FPGA architecture, including two sets of acquisition modules, two sets of DSP systems, and one set of FPGA system;

[0030] Each set of the acquisition modules is connected to a DSP system respectively, and both sets of DSP systems are connected to a set of FPGA system;

[0031] When two DSP systems serve as hot backup for each other:

[0032] The two sets of acquisition modules are used to acquire external input quantities and input the external input quantities into the corresponding two sets of DSP systems respectively;

[0033] The DSP system is used to calculate the external input quantity and output the control quantity, and transmit the control quantity to the FPGA system;

[0034] The FPGA system is used to judge the two control quantities and output the control quantity output by one of the DSP systems to the outside;

[0035] When two DSP systems serve as cold backup for each other:

[0036] One set of the acquisition modules is used to acquire external input quantities and input the external input quantities into the corresponding DSP system. The DSP system calculates the external input quantities and outputs the control quantities. The DSP system calculates the external input quantities and generates output control quantities, and transmits the output control quantities to the FPGA. Finally, the FPGA outputs the output control quantities. Another set of the acquisition modules and the corresponding DSP system are in a dormant state.

[0037] When the running DSP system fails, the FPGA system recognizes that the running DSP system is abnormal, and the FPGA system will wake up the other sleeping DSP system through the DSP GPIO pin. During the switching process between the two DSP systems, the FPGA will control the control amount output to the outside.

[0038] Preferably, the FPGA system arbitrates the control quantity output by the two DSP systems based on the external input clocks of the two DSP systems, the DSP chip "heartbeat", the task status signal output by the DSP software, and the power supply conditions of the two DSP systems.

[0039] Preferably, each set of acquisition modules includes: a discrete quantity input level conversion module and an analog quantity acquisition module; the two sets of acquisition modules are identical;

[0040] The FPGA system includes: an FPGA chip, an FPGA power module connected to the FPGA chip, an FPGA clock module, a communication level conversion module, and a control quantity level conversion module;

[0041] Each DSP system includes: DSP chip, DSP storage module connected to DSP chip, DSP clock module, DSP power module and RS422 communication module;

[0042] Among them, the CPIO pin of the DSP chip is connected to the FPGA chip for waking up the system; the DSP chip and the FPGA chip communicate through the bus; the FPGA chip is connected to the DSP storage module and the RS422 communication module through the FPGA signal harness.

[0043] according to Figure 1 When designing a circuit based on the principle block diagram shown, the circuit can be flexibly adjusted according to the design requirements. The adjustments can be made as follows:

[0044] 1) The bus signals between DSP and FPGA are EMIF bus and SPI bus, which reserve sufficient interfaces for data interaction between DSP and FPGA;

[0045] 2) The GPIO pins between DSP and FPGA can be configured by DSP as NMI interrupt function pins, external shieldable function pins, and DSP sleep state wake-up function pins;

[0046] 3) According to the design requirements, the AD conversion result finally output by the analog quantity acquisition module can be sent to the FPGA, and the FPGA can perform digital processing on the collected analog quantity, such as digital filtering, effective value calculation, peak value calculation, etc.;

[0047] 4) FPGA has abundant IO pins. If there are many external discrete quantity signals and the DSP GPIO pin resources are insufficient, the external discrete quantity signals can be connected to the FPGA pins.

[0048] 5) When the control board is powered on, it should be ensured that the DSP chip is always in reset state during the FPGA BOOT process. After the FPGA code is loaded, the FPGA releases two DSP chip reset signals at the same time to meet the DSP chip power-on requirements and ensure that the two sets of DSP software run at the same time.

[0049] 6) To improve system stability, if two 5V power supplies are input externally, press Figure 1 As shown, two DSP systems are powered separately, and two 5V power supplies are processed by a 5V power module to generate a new 5V power supply to ensure the stability of the power supply of the FPGA system and the circuit that outputs the control quantity. In addition, the entire control circuit can be powered by the newly generated 5V power module, but this method must consider the power supply problem, and it is necessary to use multiple 5V to 5V DC / DC power supply chips. The power supply strategy can be selected according to the actual situation (such as board area). Figure 2 Shown is the circuit diagram of a 5V power module.

[0050] exist Figure 2 In the circuit principle block diagram shown, the following issues need to be noted:

[0051] 1) The diodes in the voting module should be selected as low as possible with low voltage drop and large conduction current;

[0052] 2) Capacitor module 1 and capacitor module 2 can stabilize the voltage during the switching process of the two external 5V power supplies, thereby preventing the control circuit from working unstably due to the switching process of the two external 5V power supplies;

[0053] 3) Considering external factors such as the voltage drop in the voting module and the time required to switch between the two 5V power supplies, in order to maintain the stability of the system power supply, the DC / DC module should choose a power chip with an input voltage lower limit of about 4V or even lower and an output of 5V to ensure that the 5V voltage output by the DC / DC module is stable during the external power switching process.

[0054] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A redundant backup control circuit based on dual DSP and FPGA architecture, characterized in that: Includes two acquisition modules, two DSP systems, and one FPGA system; Each set of the acquisition modules is connected to a DSP system respectively, and both sets of DSP systems are connected to a set of FPGA system; When two DSP systems serve as hot backup for each other: The two sets of acquisition modules are used to acquire external input quantities and input the external input quantities into the corresponding two sets of DSP systems respectively; The DSP system is used to calculate the external input quantity and output the control quantity, and transmit the control quantity to the FPGA system; The FPGA system is used to judge the two control quantities and output the control quantity output by one of the DSP systems to the outside; When two DSP systems serve as cold backup for each other: One set of the acquisition modules is used to acquire external input quantities and input the external input quantities into the corresponding DSP system. The DSP system generates output control quantities after calculating the external input quantities and transmits the output control quantities to the FPGA system. Finally, the FPGA system outputs the output control quantities. Another set of the acquisition modules and their corresponding DSP systems are in a dormant state. When the running DSP system fails, the FPGA system recognizes that the running DSP system is abnormal, and the FPGA system will wake up the other sleeping DSP system through the DSP GPIO pin. During the switching process between the two DSP systems, the FPGA will control the control amount output to the outside.

2. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 1, characterized in that: The FPGA system arbitrates the control quantity output by the two DSP systems based on the external input clocks of the two DSP systems, the "heartbeat" of the DSP chip, the task status signal output by the DSP software, and the power supply conditions of the two DSP systems.

3. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 1, characterized in that: Each set of acquisition modules includes: discrete quantity input level conversion module and analog quantity acquisition module; the two sets of acquisition modules are the same; The FPGA system includes: an FPGA chip, an FPGA power module connected to the FPGA chip, an FPGA clock module, a communication level conversion module, and a control quantity level conversion module; Each DSP system includes: DSP chip, DSP storage module connected to DSP chip, DSP clock module, DSP power module and RS422 communication module; Among them, the CPIO pin of the DSP chip is connected to the FPGA chip for waking up the system; the DSP chip and the FPGA chip communicate through the bus; the FPGA chip is connected to the DSP storage module and the RS422 communication module through the FPGA signal harness.

4. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 3, characterized in that: The bus signals between the DSP chip and the FPGA chip are the EMIF bus and the SPI bus, which reserve an interface for data interaction between the DSP and the FPGA.

5. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 3, characterized in that: The GPIO pins between the DSP chip and the FPGA chip can be configured by the DSP as NMI interrupt function pins, external maskable function pins, and DSP sleep state wake-up function pins.

6. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 3, characterized in that: The AD conversion result finally output by the analog quantity acquisition module is sent to the FPGA chip, and the FPGA chip can digitize the collected analog quantity.

7. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 3, characterized in that: The power supply for the two DSP systems includes a new 5V power supply generated by processing two 5V power supplies through a 5V power supply module; the 5V power supply module includes a voting module, a capacitor module DC / DC module and a capacitor module connected in series, and the voting module is connected to the two 5V power supplies.

8. The redundant backup control circuit based on dual DSP and FPGA architecture as claimed in claim 7, characterized in that: When the two DSP systems serve as hot backup for each other: the two DSP chips will use the on-chip A / D conversion module to collect the power supply of the two DSP chips, and then transmit the collected results to the FPGA chip and record them in the corresponding storage module of the DSP system.

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