Bias voltage generation circuit and method

Abstract

The invention provides a bias voltage generation circuit and method.The bias voltage generation circuit comprises a current mirror circuit, an operational amplifier circuit, a temperature coefficient trimming circuit and a reference voltage trimming circuit, and zero-temperature-coefficient current and positive-temperature-coefficient current are input to the temperature coefficient trimming circuit through the current mirror circuit; the temperature coefficient trimming circuit generates a first voltage according to the generated resistance value and the two currents, and the reference trimming circuit generates a second voltage according to the generated currents and a preset resistance value, so that the operational amplifier circuit can generate a bias voltage with a temperature coefficient according to the two voltages. And the temperature coefficient trimming circuit and the reference voltage trimming circuit can adjust the output voltage according to the trimming control instruction, so that the operational amplifier circuit generates the bias voltage of which the temperature coefficient can be trimmed to meet the requirements of different module circuits on the bias voltage.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a bias voltage generating circuit and method. Background Art

[0002] In analog circuit design, temperature has a great impact on the performance of semiconductor materials. This is because most process parameters will change with temperature, which may cause the key parameters of the circuit to fail to meet the design requirements. Take the initial control voltage of the phase-locked loop as an example. The phase-locked loop is used to lock the frequency and phase of the input signal to the reference signal. The initial control voltage of the phase-locked loop is used to set the output frequency of the phase-locked loop. If the temperature change causes the initial control voltage of the phase-locked loop to change, the output frequency of the phase-locked loop may also change, which may cause the system performance to deteriorate.

[0003] Therefore, it is necessary to design a bias voltage circuit that can generate a temperature coefficient and can be adjusted so that the generated bias voltage meets the temperature coefficient requirements of the subsequent module circuit. Summary of the invention

[0004] The main purpose of the present application is to provide a bias voltage generation circuit and method, which can at least solve the problem in the related art that the temperature-sensitive bias voltage cannot well meet the temperature coefficient requirements of the module circuit for the voltage.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a bias voltage generating circuit, comprising: a current mirror circuit, an operational amplifier circuit, a temperature coefficient trimming circuit and a reference voltage trimming circuit, wherein the current mirror circuit is electrically connected to the first input terminal of the operational amplifier circuit, the temperature coefficient trimming circuit is electrically connected to the first input terminal and the output terminal of the operational amplifier circuit respectively, and the reference voltage trimming circuit is electrically connected to the second input terminal of the operational amplifier circuit; the current mirror circuit is configured to: generate a preset first current and a second current and mirror them to the temperature coefficient trimming circuit; wherein the first current is a current with a positive temperature coefficient, and the second current is a current with a zero temperature coefficient; the temperature coefficient trimming circuit is configured to: generate a first resistance value according to a first trimming control instruction, and generate a first voltage according to the first resistance value, the first current and the second current; the reference voltage trimming circuit is configured to: generate a third current according to a second trimming control instruction, and generate a second voltage according to the third current and a preset second resistance value; the operational amplifier circuit is configured to: generate a bias voltage according to the first voltage and the second voltage; wherein the bias voltage is used as a control voltage of a subsequent circuit.

[0006] The second aspect of the present application provides a bias voltage generating method, which is applied to the bias voltage generating circuit as described in the first aspect of the present application, and the bias voltage generating method includes: a current mirror circuit generates a preset first current and a second current and mirrors them to a temperature coefficient adjustment circuit; wherein the first current is a current with a positive temperature coefficient, and the second current is a current with a zero temperature coefficient; the temperature coefficient adjustment circuit generates a first resistance value according to a first adjustment control instruction, and generates a first voltage according to the first resistance value, the first current and the second current; the reference voltage adjustment circuit generates a third current according to a second adjustment control instruction, and generates a second voltage according to the third current and a preset second resistance value; the operational amplifier circuit generates a bias voltage according to the first voltage and the second voltage; wherein the bias voltage is used as a control voltage of a subsequent circuit.

[0007] From the above description, it can be seen that the present application inputs a current with a zero temperature coefficient and a current with a positive temperature coefficient to the temperature coefficient adjustment circuit through a current mirror circuit. The temperature coefficient adjustment circuit generates a first voltage according to the generated resistance value and the two currents. The reference adjustment circuit generates a second voltage according to the generated current and the preset resistance value. Thus, the operational amplifier circuit can generate a bias voltage with a temperature coefficient according to the two voltages. Both the temperature coefficient adjustment circuit and the reference voltage adjustment voltage can adjust the output voltage according to the adjustment control instruction, thereby enabling the operational amplifier circuit to generate a bias voltage with an adjustable temperature coefficient, thereby effectively meeting the bias voltage requirements of different module circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 is a structural schematic diagram of a first bias voltage generating circuit according to an embodiment of the present application; Figure 2 is a structural schematic diagram of a second bias voltage generating circuit according to an embodiment of the present application; Figure 3 is a circuit schematic diagram of a current mirror unit according to an embodiment of the present application; Figure 4 is a circuit schematic diagram of a temperature coefficient trimming circuit according to an embodiment of the present application; Figure 5 is a circuit schematic diagram of a reference voltage trimming circuit according to an embodiment of the present application; Figure 6 is a circuit schematic diagram of a bias voltage generating circuit according to an embodiment of the present application; Figure 7 is a circuit schematic diagram of another bias voltage generating circuit according to an embodiment of the present application; Figure 8 It is a basic flow chart of a bias voltage generating method according to an embodiment of the present application. DETAILED DESCRIPTION

[0010] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0011] In the related art, since there is a problem that the temperature-sensitive bias voltage cannot well meet the temperature coefficient requirements of the module circuit for the voltage, for this reason, an embodiment of the present application provides a bias voltage generating circuit.

[0012] like Figure 1 The figure is a schematic diagram of the structure of the first bias voltage generating circuit provided in an embodiment of the present application. The bias voltage generating circuit includes: a current mirror circuit 100, an operational amplifier circuit 200, a temperature coefficient adjustment circuit 300 and a reference voltage adjustment circuit 400. The current mirror circuit 100 is electrically connected to the first input terminal of the operational amplifier circuit 200, the temperature coefficient adjustment circuit 300 is electrically connected to the first input terminal and the output terminal of the operational amplifier circuit 200 respectively, and the reference voltage adjustment circuit 400 is electrically connected to the second input terminal of the operational amplifier circuit 200.

[0013] Among them, the current mirror circuit 100 is configured to: generate a preset first current and a second current and mirror them to the temperature coefficient adjustment circuit 300; wherein, the first current is a current with a positive temperature coefficient, and the second current is a current with a zero temperature coefficient; the temperature coefficient adjustment circuit 300 is configured to: generate a first resistance value according to a first adjustment control instruction, and generate a first voltage according to the first resistance value, the first current and the second current; the reference voltage adjustment circuit 400 is configured to: generate a third current according to a second adjustment control instruction, and generate a second voltage according to the third current and the preset second resistance value; the operational amplifier circuit 200 is configured to: generate a bias voltage according to the first voltage and the second voltage; wherein, the bias voltage is used as the control voltage of the subsequent circuit.

[0014] Specifically, this embodiment inputs a current with a zero temperature coefficient and a current with a positive temperature coefficient to the temperature coefficient adjustment circuit 300 through the current mirror circuit 100. The temperature coefficient adjustment circuit 300 generates a first voltage according to the generated resistance value and the two currents. The reference adjustment circuit generates a second voltage according to the generated current and the preset resistance value. Thus, the operational amplifier circuit 200 can generate a bias voltage with a temperature coefficient according to the two voltages. The temperature coefficient adjustment circuit 300 can adjust the resistance value according to the adjustment control instruction to adjust the output voltage. The reference voltage adjustment voltage can adjust the current value according to the adjustment control instruction to adjust the output voltage. Thus, the operational amplifier circuit 200 generates a bias voltage with an adjustable temperature coefficient, which effectively meets the bias voltage requirements of different module circuits.

[0015] like Figure 2 FIG. 1 is a schematic diagram of the structure of the second bias voltage generating circuit provided in this embodiment, see Figure 2 The current mirror circuit 100 includes a first current mirror unit 110 and a second current mirror unit 120. The first current mirror unit 110 and the second current mirror unit 120 are both electrically connected to the first input terminal of the operational amplifier circuit 200. The second current mirror unit 120 is also electrically connected to the reference voltage trimming circuit 400.

[0016] Wherein, the first current mirror unit 110 is configured to: amplify the input fourth current to the first current and mirror it to the temperature coefficient adjustment circuit 300; wherein, the fourth current is a current with a positive temperature coefficient; the second current mirror unit 120 is configured to: amplify the input fifth current to the second current and mirror it to the temperature coefficient adjustment circuit 300, and mirror the fifth current to the reference voltage adjustment circuit 400; wherein, the fifth current is a current with a zero temperature coefficient.

[0017] Specifically, in the present embodiment, the current mirror circuit 100 includes two current mirror units, the first current mirror unit 110 is used to mirror the current with a positive temperature coefficient to the first input terminal of the operational amplifier circuit 200 and the temperature coefficient adjustment circuit 300, and the second current mirror unit 120 is used to mirror the current with a zero temperature coefficient to the first input terminal of the operational amplifier circuit 200 and the temperature coefficient adjustment circuit 300. The first current mirror unit 110 is used to amplify the input fourth current I1 with a positive temperature coefficient into a first current of M*I1, and transmit the current of M*I1 to the first input terminal of the operational amplifier circuit 200 and the temperature coefficient adjustment circuit 300, and the second current mirror unit 120 is used to amplify the input fifth current I0 with a zero temperature coefficient into a second current of N*I0, and transmit the current of N*I0 to the first input terminal of the operational amplifier circuit 200 and the temperature coefficient adjustment circuit 300.

[0018] Furthermore, the first current mirror unit 110 and the second current mirror unit 120 each include a first current mirror branch 111, a second current mirror branch 112, a third current mirror branch 113 and a fourth current mirror branch 114; the first current mirror branch 111 is configured to: when receiving the fourth current, generate a bias voltage to be transmitted to the operational amplifier circuit 200; the second current mirror branch 112, the third current mirror branch 113, and the fourth current mirror branch 114 are each configured to: mirror the fourth current and generate a corresponding bias voltage to be transmitted to the operational amplifier circuit 200.

[0019] Furthermore, if Figure 3 FIG. 1 is a circuit diagram of a current mirror unit provided in this embodiment, see Figure 3 The first current mirror branch 111 includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4 and a fifth MOS tube M5; the source of the first MOS tube M1 is electrically connected to the current source, the gate of the first MOS tube M1 is electrically connected to the gate of the second MOS tube M2 and is used to be electrically connected to an external control unit, the drain of the first MOS tube M1 is electrically connected to the drains of the second MOS tube M2 and the fourth MOS tube M4, the gates of the third MOS tube M3 and the fifth MOS tube M5, the second current mirror branch 112, the third current mirror branch 113, and the operational amplifier circuit 200, the drain of the third MOS tube M3 is electrically connected to the power supply, the source of the third MOS tube M3 is electrically connected to the gate of the fourth MOS tube M4, the second current mirror branch 112, the third current mirror branch 113, and the fourth current mirror branch 114, the source of the fourth MOS tube M4 is electrically connected to the drain of the fifth MOS tube M5, and the sources of the second MOS tube M2 and the fifth MOS tube M5 are grounded.

[0020] The second current mirror branch 112 includes a sixth MOS tube M10, a seventh MOS tube M11, an eighth MOS tube M15 and a first MOS tube unit of a diode connection structure; the source of the sixth MOS tube M10 is electrically connected to the drain of the seventh MOS tube M11, the drain of the sixth MOS tube M10 is electrically connected to the first end of the first MOS tube unit, the gate of the sixth MOS tube M10 is electrically connected to the first current mirror branch 111, the third current mirror branch 113, and the fourth current mirror branch 114, respectively, the gate of the seventh MOS tube M11 is electrically connected to the first current mirror branch 111, the third current mirror branch 113, and the fourth current mirror branch 114, respectively, The mirror branch 111 and the third current mirror branch 113 are electrically connected, the source of the seventh MOS tube M11 is grounded, the second end of the first MOS tube unit is electrically connected to the power supply, the third end of the first MOS tube unit is electrically connected to the third current mirror branch 113, the fourth current mirror branch 114, and the operational amplifier circuit 200, respectively, the fourth end of the first MOS tube unit is electrically connected to the source of the eighth MOS tube M15 and the third current mirror branch 113, respectively, the gate of the eighth MOS tube M15 is electrically connected to the third current mirror branch 113, and the drain of the eighth MOS tube M15 is grounded.

[0021] The third current mirror branch 113 includes a ninth MOS tube M16, a tenth MOS tube M17, an eleventh MOS tube M14, a twelfth MOS tube M12 and a thirteenth MOS tube M13; the gate of the ninth MOS tube M16 is electrically connected to the first current mirror branch 111, the second current mirror branch 112 and the fourth current mirror branch 114 respectively, the source of the ninth MOS tube M16 is electrically connected to the drain of the tenth MOS tube M17, the drain of the ninth MOS tube M16 is electrically connected to the drain of the eleventh MOS tube M14, the gate of the twelfth MOS tube M12, the fourth current mirror branch 114 and the operational amplifier circuit 200 respectively, and the gate of the tenth MOS tube M17 is electrically connected to the drain of the eleventh MOS tube M14, the gate of the twelfth MOS tube M12, the fourth current mirror branch 114 and the operational amplifier circuit 200 respectively. The gate of the OS transistor M17 is electrically connected to the second current mirror branch 112 and the first current mirror branch 111 respectively, the source of the tenth MOS transistor M17 is grounded, the gate of the eleventh MOS transistor M14 is electrically connected to the second current mirror branch 112, the source of the eleventh MOS transistor M14 is electrically connected to the drain of the thirteenth MOS transistor M13, the source of the twelfth MOS transistor M12 is electrically connected to the power supply, the drain of the twelfth MOS transistor M12 is electrically connected to the source of the thirteenth MOS transistor M13, and the gate of the thirteenth MOS transistor M13 is electrically connected to the first current mirror branch 111, the second current mirror branch 112, and the fourth current mirror branch 114 respectively.

[0022] The fourth current mirror branch 114 includes a fourteenth MOS tube M18, a fifteenth MOS tube M19, and a second MOS tube unit of a diode connection structure; the source of the fourteenth MOS tube M18 is electrically connected to the power supply, the gate of the fourteenth MOS tube M18 is electrically connected to the third current mirror branch 113, the drain of the fourteenth MOS tube M18 is electrically connected to the source of the fifteenth MOS tube M19, the gate of the fifteenth MOS tube M19 is electrically connected to the third current mirror branch 113 and the second current mirror branch 112, the drain of the fifteenth MOS tube M19 is electrically connected to the first end of the second MOS tube unit, the second end of the second MOS tube unit is electrically connected to the first current mirror branch 111, the second current mirror branch 112, the third current mirror branch 113, and the operational amplifier circuit 200, and the third end of the second MOS tube unit is grounded.

[0023] Specifically, in the present embodiment, the current mirror circuit 100 is further used to generate a bias voltage and transmit it to the operational amplifier circuit 200. Taking the first current mirror unit 110 as an example, the first current mirror unit 110 includes four current mirror branches, each of which generates a bias voltage. After the control unit inputs an enable control signal, the first current mirror branch 111 generates a bias voltage Vbn2 after the current I1 with a positive temperature coefficient flows into the first current mirror branch 111 of the low-voltage common-source common-gate structure. The current I1 is mirrored to the second current mirror branch 112, and a bias voltage Vbp1 is generated through the first MOS tube M1 unit (i.e., MOS tubes M6 to M9) of the diode connection structure. The current I1 is mirrored to the third current mirror branch 113, so that the third current mirror branch 113 generates a bias voltage Vbp2. The current I1 is mirrored to the fourth current mirror branch 114, and a bias voltage Vbn1 is generated through the second MOS tube M2 unit (i.e., MOS tubes M20 to M23) of the diode connection structure.

[0024] Further, see Figure 3 The first current mirror unit 110 further includes a fifth current mirror branch 115, which includes a sixteenth MOS tube M24, a seventeenth MOS tube M25 and an eighteenth MOS tube M26; the source of the sixteenth MOS tube M24 is electrically connected to the power supply, the gate of the sixteenth MOS tube M24 is electrically connected to the third current mirror branch 113 and the fourth current mirror branch 114 respectively, the drain of the sixteenth MOS tube M24 is electrically connected to the source of the seventeenth MOS tube M25, the gate of the seventeenth MOS tube M25 is electrically connected to the second current mirror branch 112, the third current mirror branch 113 and the fourth current mirror branch 114 respectively, the drain of the seventeenth MOS tube M25 is electrically connected to the operational amplifier circuit 200 and the drain of the eighteenth MOS tube M26 respectively, and the gate and source of the eighteenth MOS tube M26 are both grounded; the fifth current mirror branch 115 is configured to: amplify the fourth current to the first current and mirror it to the temperature coefficient trimming circuit 300.

[0025] Specifically, in this embodiment, the first current mirror unit 110 further includes a fifth current mirror branch 115, which is used to amplify the current I1 with a positive temperature coefficient to M*I1 and transmit it to the first input terminal VFB of the operational amplifier circuit 200 and the temperature coefficient adjustment circuit 300.

[0026] like Figure 4 FIG. 1 is a circuit diagram of a temperature coefficient adjustment circuit provided in this embodiment. Figure 4 The temperature coefficient adjustment circuit 300 includes a plurality of input voltage adjustment units connected in series, the input voltage adjustment unit includes a transmission gate and a first resistor connected in parallel, the first input voltage adjustment unit is electrically connected to the first input terminal of the operational amplifier circuit 200, and the last input voltage adjustment unit is electrically connected to the output terminal of the operational amplifier circuit 200; the temperature coefficient adjustment circuit 300 is specifically configured as follows: according to the first adjustment control instruction, the corresponding transmission gate is selected to enter the cut-off state, a first resistance value is generated, and a first voltage is generated according to the difference between the first current and the second current and the first resistance value.

[0027] Specifically, in this embodiment, the temperature coefficient trimming circuit 300 includes a plurality of input voltage trimming units, each of which has the same structure, and the plurality of input voltage trimming units are connected in series in sequence. Figure 4 The temperature coefficient adjustment circuit 300 includes 6 input voltage adjustment units as an example, each input voltage adjustment unit includes a transmission gate and a resistor, wherein the transmission gate is composed of a pair of MOS switches. The relationship between the resistance values ​​of each input voltage adjustment unit is RT6=2RT5=4RT4=8RT3=16RT2=32RT1, RT1=R0. The resistance of each input voltage adjustment unit is controlled by independent transmission gates. Among them, the transmission gate can select the corresponding transmission gate to enter the on or off state according to the adjustment control instruction to select the corresponding resistor to be connected or not connected to the circuit, thereby changing the total resistance value. In addition, the input of the temperature coefficient adjustment circuit 300 is the current M*I1 with a positive temperature coefficient and the current N*I0 with a zero temperature coefficient. The current M*I1-N*I0 with a negative temperature coefficient is subtracted, and then the on and off of the MOS switch of the input voltage adjustment unit is controlled according to the adjustment control instruction, thereby realizing compensation for the temperature coefficient of the output voltage VOUT.

[0028] like Figure 5 FIG. 1 is a circuit diagram of a reference voltage adjustment circuit provided in this embodiment. Figure 5The reference voltage trimming circuit 400 includes a second resistor and a plurality of reference voltage trimming units connected in parallel. The reference voltage trimming unit includes a switch tube and a sixth current mirror branch. The current mirror branch is electrically connected to the switch tube, the second resistor, the current mirror circuit 100, and the second input terminal of the operational amplifier circuit 200 respectively. The switch tube is configured to enter a conducting state or a cutting-off state according to a second trimming control instruction. When the switch tube is in a conducting state, the corresponding reference voltage trimming unit enters a working state. The sixth current mirror branch is configured to amplify the current transmitted by the current mirror circuit 100 and transmit the amplified current to the second resistor when in a working state.

[0029] For further information, see Figure 5 The sixth current mirror branch includes a nineteenth MOS tube and a twentieth MOS tube, the source of the nineteenth MOS tube is electrically connected to the switch tube, the drain of the nineteenth MOS tube is electrically connected to the source of the twentieth MOS tube, the drain of the twentieth MOS tube is electrically connected to the second resistor, and the gates of the nineteenth MOS tube and the twentieth MOS tube are both electrically connected to the current mirror circuit 100; wherein the current mirror circuit 100 is used to mirror the current with a zero temperature coefficient to the sixth current mirror branch, and provide a bias voltage for the nineteenth MOS tube and the twentieth MOS tube.

[0030] Specifically, in this embodiment, the reference voltage trimming circuit 400 includes a plurality of reference voltage trimming units, each of which has the same structure, and the plurality of reference voltage trimming units are connected in parallel. Figure 5 For example, the temperature coefficient adjustment circuit 300 includes 6 reference voltage adjustment units, each of which includes a MOS tube, such as a PMOS, and a current mirror branch. The current mirror branches of each reference voltage adjustment unit circuit are controlled by independent PMOS switches. The bias voltage of each group of current mirror branches is provided by the current mirror circuit 100. By controlling the on and off of the PMOS switch of each reference voltage adjustment unit according to the adjustment control instruction, the current flowing into the resistor R1 is changed, and then the output voltage VREF is adjusted.

[0031] Further, Figure 6 Taking the circuit schematic diagram of the bias voltage generating circuit shown in FIG. 1 as an example, the entire working process of the bias voltage generating circuit in this embodiment is described. The principle of temperature compensation in this embodiment is to subtract the positive temperature coefficient current IPTAT current I1 from the zero temperature coefficient ICTAT current I0, and then multiply the difference by the resistance value to generate a temperature-related voltage, and superimpose it on VREF to obtain a voltage VOUT with a temperature coefficient. The calculation formula of the output voltage VOUT is as follows:

[0032]

[0033]

[0034]

[0035]

[0036] Among them, M and N can be And the size of I1 and I0 is calculated, X and Y are the values ​​of reference voltage adjustment and input voltage adjustment respectively, that is, the first resistance value generated by the temperature coefficient adjustment circuit is YR0, and the first voltage generated by the temperature coefficient adjustment circuit is , the third current generated by the reference voltage trimming circuit is XI0. Therefore, the output expression of VOUT consists of two parts. The first part is composed of the zero temperature coefficient ICTAT current I0 and its related coefficients Multiplying by , the second voltage V with zero temperature coefficient is obtained REF By adjusting The size of the output voltage is adjusted to adjust the reference voltage of the output voltage; the second part is composed of the positive temperature coefficient IPTAT current I1 and its related coefficients Multiplying by, the first voltage with a negative temperature coefficient is obtained By adjusting The size of the output voltage is adjusted to adjust the temperature coefficient of the output voltage. The first part is a voltage with a zero temperature coefficient, and the second part is a voltage with a negative temperature coefficient. The two are superimposed to obtain an output voltage with a negative temperature coefficient.

[0037] Furthermore, if Figure 7 FIG. 1 is a circuit schematic diagram of a bias voltage generating circuit provided by this embodiment, wherein the current mirror unit is a second current mirror unit. Figure 7In the circuit shown, after the current I0 with zero temperature coefficient is enabled, it flows to the current mirror branch 121 of the low-voltage common source and common gate structure to generate a bias voltage Vbn2, the current I0 with zero temperature coefficient is mirrored to the current mirror branch 122, and the bias voltage Vbp1 is generated through the MOS tube unit of the diode connection structure, the current I0 is mirrored to the current mirror branch 123 to generate a bias voltage Vbp2, the current I0 is mirrored to the current mirror branch 124, and the bias voltage Vbn1 is generated through the MOS tube unit of the diode connection structure. The bias voltages Vbn1, Vbn2, Vbp1 and Vbp2 provide bias voltages for the folded common source and common gate amplifier. And the current I0 with zero temperature coefficient is mirrored to the 202 branch, that is, the input terminal VFB of the operational amplifier, through the current mirror unit, to obtain the current N*I0 with zero temperature coefficient. The current N*I0 is superimposed with the current M*I1 with positive temperature coefficient mirrored by I1 to obtain the current M*I1-N*I0 with negative temperature coefficient, which flows into the temperature coefficient adjustment circuit. At the same time, the current I0 with zero temperature coefficient is mirrored to the reference voltage adjustment circuit through the current mirror unit, and the current X*I0 with zero temperature coefficient is obtained through adjustment. The current X*I0 flows through the resistor R1 to obtain the reference voltage VREF of the operational amplifier. Among them, the main function of the operational amplifier circuit is to clamp the voltage at the input end so that VREF=VFB.

[0038] Therefore, the bias voltage generating circuit provided in the embodiment of the present application inputs a current with a zero temperature coefficient and a current with a positive temperature coefficient to the temperature coefficient adjustment circuit through a current mirror circuit. The temperature coefficient adjustment circuit generates a first voltage according to the generated resistance value and the two currents. The reference adjustment circuit generates a second voltage according to the generated current and the preset resistance value. Thus, the operational amplifier circuit can generate a bias voltage with a temperature coefficient according to the two voltages. Both the temperature coefficient adjustment circuit and the reference voltage adjustment voltage can adjust the output voltage according to the adjustment control instruction, thereby enabling the operational amplifier circuit to generate a bias voltage with an adjustable temperature coefficient, thereby effectively meeting the bias voltage requirements of different module circuits.

[0039] The embodiment of the present application also provides a bias voltage generation method, which is applied to the above-mentioned bias voltage generation circuit, such as Figure 8 FIG. 1 is a basic flow chart of a bias voltage generating method provided by this embodiment, and the bias voltage generating method includes: Step 801, a current mirror circuit generates a preset first current and a second current and mirrors them to a temperature coefficient adjustment circuit; Step 802: The temperature coefficient trimming circuit generates a first resistance value according to a first trimming control instruction, and generates a first voltage according to the first resistance value, a first current, and a second current; Step 803: the reference voltage trimming circuit generates a third current according to the second trimming control instruction, and generates a second voltage according to the third current and a preset second resistance value; Step 804: The operational amplifier circuit generates a bias voltage according to the first voltage and the second voltage.

[0040] Specifically, in the present embodiment, a second current with a zero temperature coefficient and a first current with a positive temperature coefficient are input to a temperature coefficient adjustment circuit through a current mirror circuit. The temperature coefficient adjustment circuit generates a first voltage according to a generated resistance value and a difference between the two currents. The reference adjustment circuit generates a second voltage according to the generated current and a preset resistance value. Thus, the operational amplifier circuit can generate a bias voltage with a temperature coefficient according to the two voltages. Both the temperature coefficient adjustment circuit and the reference voltage adjustment voltage can adjust the output voltage according to an adjustment control instruction. Thus, the operational amplifier circuit generates a bias voltage with an adjustable temperature coefficient, thereby effectively meeting the bias voltage requirements of different module circuits.

[0041] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0042] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0043] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A bias voltage generating circuit, characterized in that: include: A current mirror circuit, an operational amplifier circuit, a temperature coefficient adjustment circuit and a reference voltage adjustment circuit, wherein the current mirror circuit is electrically connected to a first input terminal of the operational amplifier circuit, the temperature coefficient adjustment circuit is electrically connected to a first input terminal and an output terminal of the operational amplifier circuit respectively, and the reference voltage adjustment circuit is electrically connected to a second input terminal of the operational amplifier circuit; The current mirror circuit is configured to: generate a preset first current and a second current and mirror them to the temperature coefficient adjustment circuit; wherein the first current is a current with a positive temperature coefficient, and the second current is a current with a zero temperature coefficient; The temperature coefficient trimming circuit is configured to: generate a first resistance value according to a first trimming control instruction, and generate a first voltage according to the first resistance value, the first current and the second current; The reference voltage trimming circuit is configured to: generate a third current according to a second trimming control instruction, and generate a second voltage according to the third current and a preset second resistance value; The operational amplifier circuit is configured to generate a bias voltage according to the first voltage and the second voltage; wherein the bias voltage is used as a control voltage of a subsequent circuit.

2. The bias voltage generating circuit according to claim 1, wherein: The current mirror circuit comprises a first current mirror unit and a second current mirror unit, the first current mirror unit and the second current mirror unit are both electrically connected to the first input terminal of the operational amplifier circuit, and the second current mirror unit is also electrically connected to the reference voltage trimming circuit; The first current mirror unit is configured to: amplify the input fourth current to the first current and mirror it to the temperature coefficient trimming circuit; wherein the fourth current is a current with a positive temperature coefficient; The second current mirror unit is configured to: amplify the input fifth current to the second current and mirror it to the temperature coefficient adjustment circuit, and mirror the fifth current to the reference voltage adjustment circuit; wherein the fifth current is a current with a zero temperature coefficient.

3. The bias voltage generating circuit according to claim 2, wherein: The first current mirror unit and the second current mirror unit each include a first current mirror branch, a second current mirror branch, a third current mirror branch and a fourth current mirror branch; The first current mirror branch is configured to: when receiving the fourth current, generate a bias voltage and transmit it to the operational amplifier circuit; The second current mirror branch, the third current mirror branch, and the fourth current mirror branch are all configured to: mirror the fourth current and generate a corresponding bias voltage to be transmitted to the operational amplifier circuit.

4. The bias voltage generating circuit according to claim 3, characterized in that: The first current mirror branch includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; The source of the first MOS tube is electrically connected to the current source, the gate of the first MOS tube is electrically connected to the gate of the second MOS tube and is used to be electrically connected to an external control unit, the drain of the first MOS tube is electrically connected to the drains of the second MOS tube and the fourth MOS tube, the gates of the third MOS tube and the fifth MOS tube, the second current mirror branch, the third current mirror branch, and the operational amplifier circuit respectively, the drain of the third MOS tube is electrically connected to the power supply, the source of the third MOS tube is electrically connected to the gate of the fourth MOS tube, the second current mirror branch, the third current mirror branch, and the fourth current mirror branch respectively, the source of the fourth MOS tube is electrically connected to the drain of the fifth MOS tube, and the sources of the second MOS tube and the fifth MOS tube are grounded.

5. The bias voltage generating circuit according to claim 3, characterized in that: The second current mirror branch includes a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first MOS tube unit of a diode connection structure; The source of the sixth MOS tube is electrically connected to the drain of the seventh MOS tube, the drain of the sixth MOS tube is electrically connected to the first end of the first MOS tube unit, the gate of the sixth MOS tube is electrically connected to the first current mirror branch, the third current mirror branch, and the fourth current mirror branch respectively, the gate of the seventh MOS tube is electrically connected to the first current mirror branch and the third current mirror branch respectively, the source of the seventh MOS tube is grounded, the second end of the first MOS tube unit is electrically connected to the power supply, the third end of the first MOS tube unit is electrically connected to the third current mirror branch, the fourth current mirror branch, and the operational amplifier circuit respectively, the fourth end of the first MOS tube unit is electrically connected to the source of the eighth MOS tube and the third current mirror branch respectively, the gate of the eighth MOS tube is electrically connected to the third current mirror branch, and the drain of the eighth MOS tube is grounded.

6. The bias voltage generating circuit according to claim 3, wherein: The third current mirror branch includes a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube and a thirteenth MOS tube; The gate of the ninth MOS tube is electrically connected to the first current mirror branch, the second current mirror branch, and the fourth current mirror branch, respectively; the source of the ninth MOS tube is electrically connected to the drain of the tenth MOS tube; the drain of the ninth MOS tube is electrically connected to the drain of the eleventh MOS tube, the gate of the twelfth MOS tube, the fourth current mirror branch, and the operational amplifier circuit, respectively; the gate of the tenth MOS tube is electrically connected to the second current mirror branch and the first current mirror branch, respectively; the source of the tenth MOS tube is grounded; the gate of the eleventh MOS tube is electrically connected to the second current mirror branch; the source of the eleventh MOS tube is electrically connected to the drain of the thirteenth MOS tube; the source of the twelfth MOS tube is electrically connected to the power supply; the drain of the twelfth MOS tube is electrically connected to the source of the thirteenth MOS tube; the gate of the thirteenth MOS tube is electrically connected to the first current mirror branch, the second current mirror branch, and the fourth current mirror branch, respectively.

7. The bias voltage generating circuit according to claim 3, characterized in that: The fourth current mirror branch includes a fourteenth MOS tube, a fifteenth MOS tube, and a second MOS tube unit of a diode connection structure; The source of the fourteenth MOS tube is electrically connected to the power supply, the gate of the fourteenth MOS tube is electrically connected to the third current mirror branch respectively, the drain of the fourteenth MOS tube is electrically connected to the source of the fifteenth MOS tube, the gate of the fifteenth MOS tube is electrically connected to the third current mirror branch and the second current mirror branch respectively, the drain of the fifteenth MOS tube is electrically connected to the first end of the second MOS tube unit, the second end of the second MOS tube unit is electrically connected to the first current mirror branch, the second current mirror branch, the third current mirror branch, and the operational amplifier circuit, and the third end of the second MOS tube unit is grounded.

8. The bias voltage generating circuit according to claim 3, characterized in that: The first current mirror unit further includes a fifth current mirror branch, and the fifth current mirror branch includes a sixteenth MOS tube, a seventeenth MOS tube and an eighteenth MOS tube; The source of the sixteenth MOS tube is electrically connected to the power supply, the gate of the sixteenth MOS tube is electrically connected to the third current mirror branch and the fourth current mirror branch respectively, the drain of the sixteenth MOS tube is electrically connected to the source of the seventeenth MOS tube, the gate of the seventeenth MOS tube is electrically connected to the second current mirror branch, the third current mirror branch and the fourth current mirror branch respectively, the drain of the seventeenth MOS tube is electrically connected to the operational amplifier circuit and the drain of the eighteenth MOS tube respectively, and the gate and source of the eighteenth MOS tube are both grounded; The fifth current mirror branch is configured to amplify the fourth current to the first current and mirror the amplified current to the temperature coefficient trimming circuit.

9. The bias voltage generating circuit according to claim 1, wherein: The temperature coefficient trimming circuit comprises a plurality of input voltage trimming units connected in series, wherein the input voltage trimming units comprise a transmission gate and a first resistor connected in parallel, wherein the first input voltage trimming unit is electrically connected to the first input terminal of the operational amplifier circuit, and the last input voltage trimming unit is electrically connected to the output terminal of the operational amplifier circuit; The temperature coefficient trimming circuit is specifically configured to: select the corresponding transmission gate to enter the cut-off state according to the first trimming control instruction, generate a first resistance value, and generate a first voltage according to the difference between the first current and the second current and the first resistance value.

10. The bias voltage generating circuit according to claim 1, wherein: The reference voltage trimming circuit includes a second resistor and a plurality of reference voltage trimming units connected in parallel, wherein the reference voltage trimming unit includes a switch tube and a sixth current mirror branch, wherein the current mirror branch is electrically connected to the switch tube, the second resistor, the current mirror circuit, and the second input end of the operational amplifier circuit respectively; The switch tube is configured to: enter a conducting state or a cutting-off state according to the second trimming control instruction; wherein, when the switch tube is in the conducting state, the corresponding reference voltage trimming unit enters a working state; The sixth current mirror branch is configured to: when in working state, amplify the current transmitted by the current mirror circuit, and transmit the amplified current to the second resistor.

11. The bias voltage generating circuit according to claim 10, characterized in that: The sixth current mirror branch includes a nineteenth MOS tube and a twentieth MOS tube, the source of the nineteenth MOS tube is electrically connected to the switch tube, the drain of the nineteenth MOS tube is electrically connected to the source of the twentieth MOS tube, the drain of the twentieth MOS tube is electrically connected to the second resistor, and the gates of the nineteenth MOS tube and the twentieth MOS tube are both electrically connected to the current mirror circuit; wherein the current mirror circuit is used to mirror the current with a zero temperature coefficient to the sixth current mirror branch, and provide a bias voltage for the nineteenth MOS tube and the twentieth MOS tube.

12. A method for generating a bias voltage, characterized in that: Applied to the bias voltage generating circuit according to any one of claims 1 to 11, the bias voltage generating method comprises: The current mirror circuit generates a preset first current and a second current and mirrors them to the temperature coefficient adjustment circuit; wherein the first current is a current with a positive temperature coefficient, and the second current is a current with a zero temperature coefficient; The temperature coefficient trimming circuit generates a first resistance value according to a first trimming control instruction, and generates a first voltage according to the first resistance value, the first current and the second current; The reference voltage trimming circuit generates a third current according to the second trimming control instruction, and generates a second voltage according to the third current and a preset second resistance value; The operational amplifier circuit generates a bias voltage according to the first voltage and the second voltage; wherein the bias voltage is used as a control voltage of a subsequent circuit.

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