Real-time data read-write method of on-chip logic analyzer and related device

Abstract

The invention relates to the field of data processing, in particular to a real-time data read-write method of an on-chip logic analyzer and a related device. The method comprises the following steps: receiving first data collected by a trigger unit in real time; storing the first data into a first buffer area in a write state at present, and analyzing and transmitting the second data through a second buffer area in a read state at present; if the residual storage space in the first buffer area is lower than the storage capacity threshold value, switching the first buffer area from the write state to the read state, and switching the second buffer area from the read state to the write state; and analyzing and transmitting the first data through the first buffer area switched to the read state, and storing the third data received after switching to the second buffer area in the write state at present, so as to realize real-time data reading and writing of the on-chip logic analyzer. According to the method, the integrity of on-chip signals can be guaranteed, the accuracy of analysis results is improved, the debugging time can be greatly shortened, and the debugging efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a triggering method of a logic analyzer and a related device. Background Art

[0002] As integrated circuit (IC) design becomes increasingly complex, the functionality and performance requirements of on-chip systems are also constantly improving, which poses severe challenges to signal capture and analysis technology.

[0003] On-Chip Logic Analyzer (OCLA) is a special tool integrated into an integrated circuit (IC) and is designed specifically for digital system debugging and fault diagnosis. It helps engineers understand the logical and timing relationships of various signals in the system by capturing and displaying the logic level status of the digital system in real time. Compared with traditional external logic analyzers, on-chip logic analyzers have unique advantages and application areas.

[0004] As the complexity of integrated circuit design continues to increase, traditional on-chip logic analyzers have difficulty tracking complete on-chip signals in a timely manner due to their limited read and write speeds. The integrity of on-chip signals further affects the accuracy of the analysis results. In addition, due to the limited read and write speeds of on-chip logic analyzers, traditional on-chip logic analyzers can often only perform offline analysis after data is generated, and cannot provide immediate data feedback, which reduces debugging efficiency and prolongs the IC development cycle.

[0005] Therefore, it is urgent to design a technical solution to solve the technical problems existing in the trigger unit in the related technology. Summary of the invention

[0006] In view of the technical problems existing in the prior art, the present application provides a real-time data reading and writing method and related devices of an on-chip logic analyzer to ensure the integrity of on-chip signals, improve the accuracy of analysis results, and perform online real-time debugging, which greatly shortens the debugging time, improves debugging efficiency, and effectively shortens the IC development cycle.

[0007] In a first aspect, an embodiment of the present application provides a real-time data reading and writing method of an on-chip logic analyzer, wherein the on-chip logic analyzer comprises at least: a trigger unit, a ping-pong buffer, wherein the ping-pong buffer is provided with a first buffer and a second buffer; the method comprises: Receiving first data collected in real time by a trigger unit; storing the first data in a first buffer currently in a write state, and analyzing and transmitting the second data through a second buffer currently in a read state; the first data and the second data are continuously collected by the trigger unit; Detecting the remaining storage space of the first buffer; If the remaining storage space in the first buffer is lower than a storage capacity threshold, switching the first buffer from a write state to a read state, and switching the second buffer from a read state to a write state; the storage capacity threshold is dynamically configured based on data processing requirements of the on-chip logic analyzer; The first data is analyzed and transmitted by switching the first buffer to a read state, and the third data received after switching is stored in a second buffer currently in a write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0008] In a second aspect, an embodiment of the present application provides an on-chip logic analyzer, the on-chip logic analyzer at least comprising: a trigger unit, a ping-pong buffer, wherein the ping-pong buffer is provided with a first buffer and a second buffer; the ping-pong buffer is configured to receive first data collected in real time by the trigger unit; the first data is stored in the first buffer currently in a write state, and the second data is analyzed and transmitted through the second buffer currently in a read state; the first data and the second data are continuously collected by the trigger unit; The trigger unit is configured to detect the remaining storage space in the first buffer; if the remaining storage space in the first buffer is lower than a storage capacity threshold, the first buffer is switched from a write state to a read state, and the second buffer is switched from a read state to a write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer; The ping-pong buffer is configured to analyze and transmit the first data by switching to the first buffer in the read state, and store the third data received after the switching in the second buffer currently in the write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0009] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: at least one processor, memory, and input-output unit; The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the real-time data reading and writing method of the on-chip logic analyzer of the first aspect.

[0010] In a fourth aspect, a computer-readable storage medium is provided, which includes instructions. When the instructions are executed on a computer, the computer executes the real-time data reading and writing method of the on-chip logic analyzer of the first aspect.

[0011] The present application provides a real-time data reading and writing method and related device of an on-chip logic analyzer. In this technical solution, first, the first data collected in real time by the trigger unit is received. Then, the first data is stored in the first buffer currently in the write state, and the second data is analyzed and transmitted through the second buffer currently in the read state; the first data and the second data are continuously collected by the trigger unit. Then, the remaining storage space of the first buffer is detected. If the remaining storage space in the first buffer is lower than the storage capacity threshold, the first buffer is switched from the write state to the read state, and the second buffer is switched from the read state to the write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer. Finally, the first data is analyzed and transmitted by the first buffer switched to the read state, and the third data received after the switch is stored in the second buffer currently in the write state, so as to realize the real-time data reading and writing of the on-chip logic analyzer.

[0012] The technical solution of the present application can capture more on-chip signals in a timely manner through the alternating read and write state switching of multiple buffers (such as the first buffer and the second buffer), avoiding signal loss, thereby ensuring the integrity of the on-chip signals and improving the accuracy of the analysis results. In addition, through the real-time switching of the buffer, the data can be analyzed and transmitted at the same time as it is generated, realizing instant data feedback without waiting for offline analysis results, greatly shortening the debugging time, improving debugging efficiency, and effectively shortening the IC development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a flowchart of a real-time data reading and writing method of an on-chip logic analyzer according to an embodiment of the present application; Figure 2 It is a schematic diagram of the principle of a real-time data reading and writing method of an on-chip logic analyzer according to an embodiment of the present application; Figure 3 is a structural schematic diagram of an on-chip logic analyzer according to an embodiment of the present application; Figure 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application; Figure 5 It is a structural schematic diagram of a medium device according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0015] On-Chip Logic Analyzer (OCLA) is a special tool integrated into an integrated circuit (IC) and is designed specifically for digital system debugging and fault diagnosis. It helps engineers understand the logical and timing relationships of various signals in the system by capturing and displaying the logic level status of the digital system in real time. Compared with traditional external logic analyzers, on-chip logic analyzers have unique advantages and application areas.

[0016] In related technologies, as the complexity of integrated circuit design continues to increase, traditional on-chip logic analyzers have difficulty tracking complete on-chip signals in a timely manner due to limited read and write speeds. The integrity of on-chip signals further affects the accuracy of analysis results. In addition, limited by the read and write speeds of on-chip logic analyzers, traditional on-chip logic analyzers can often only perform offline analysis after data is generated, and cannot provide immediate data feedback, which reduces debugging efficiency and prolongs the IC development cycle.

[0017] In order to solve at least one technical problem in the related art, an embodiment of the present application provides a real-time data reading and writing method of an on-chip logic analyzer and a related device.

[0018] In the technical solution provided by the present application, first, the first data collected in real time by the trigger unit is received. Then, the first data is stored in the first buffer currently in the write state, and the second data is analyzed and transmitted through the second buffer currently in the read state; the first data and the second data are continuously collected by the trigger unit. Next, the remaining storage space of the first buffer is detected. If the remaining storage space in the first buffer is lower than the storage capacity threshold, the first buffer is switched from the write state to the read state, and the second buffer is switched from the read state to the write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer. Finally, the first data is analyzed and transmitted by switching the first buffer to the read state, and the third data received after the switch is stored in the second buffer currently in the write state, so as to realize the real-time data reading and writing of the on-chip logic analyzer.

[0019] The technical solution of the present application solves the problem of limited read and write speed of traditional on-chip logic analyzers by switching the read and write states of multiple buffers (such as the first buffer and the second buffer) alternately. In the traditional solution, it is difficult to fully track the on-chip signals due to the limited read and write speed. In this solution, when one buffer is writing data, the other buffer can analyze and transmit data at the same time, greatly improving the data reading and writing efficiency. For example, in a high-speed data acquisition scenario, more on-chip signals can be captured in a timely manner, avoiding signal loss, thereby ensuring the integrity of the on-chip signals and improving the accuracy of the analysis results.

[0020] Secondly, traditional on-chip logic analyzers can only perform offline analysis due to read and write speed issues, and cannot provide engineers with data feedback in a timely manner. In this solution, through real-time switching of the buffer, data can be analyzed and transmitted at the same time as it is generated, achieving instant data feedback. Engineers can obtain analysis results in real time and quickly determine whether the logical relationship and timing relationship of each signal in the system are normal. For example, during the development of integrated circuits, once a problem occurs, engineers can immediately debug based on real-time feedback data without waiting for offline analysis results, which greatly shortens the debugging time and improves debugging efficiency, thereby effectively shortening the IC development cycle.

[0021] Finally, the storage capacity threshold in this solution can be dynamically configured based on the data processing requirements of the on-chip logic analyzer. Different integrated circuit designs have different data processing requirements. For example, some complex designs may require higher storage capacity to cope with sudden large amounts of data acquisition, while some simple designs have relatively low storage capacity requirements. This solution can flexibly adjust the storage capacity threshold according to actual data processing requirements. When the data processing requirements increase, the storage capacity threshold is appropriately increased to ensure that the buffer has enough space to store data; when the data processing requirements are small, the storage capacity threshold is lowered to optimize resource utilization, so that the on-chip logic analyzer can better adapt to different application scenarios and data processing requirements.

[0022] The technical solution of the present application can capture more on-chip signals in a timely manner through the alternating read and write state switching of multiple buffers (such as the first buffer and the second buffer), avoiding signal loss, thereby ensuring the integrity of the on-chip signals and improving the accuracy of the analysis results. In addition, through the real-time switching of the buffer, the data can be analyzed and transmitted at the same time as it is generated, realizing instant data feedback without waiting for offline analysis results, greatly shortening the debugging time, improving debugging efficiency, and effectively shortening the IC development cycle.

[0023] The real-time data reading and writing scheme of the on-chip logic analyzer provided in the embodiment of the present application can also be executed by an electronic device, which can be a server, a server cluster, or a cloud server. The electronic device can also be a terminal device such as a mobile phone, a computer, a tablet computer, a wearable device, or a dedicated device (such as a dedicated terminal device with a real-time data reading and writing method system of an on-chip logic analyzer, etc.). These electronic devices can also be equipped with the chips introduced in the above embodiments. Alternatively, these electronic devices can also be installed with a service program for executing the real-time data reading and writing scheme of the on-chip logic analyzer.

[0024] Figure 1 A flowchart of a real-time data reading and writing method of an on-chip logic analyzer provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method comprises the following steps: Step 101, receiving first data collected in real time by a trigger unit; Step 102, storing the first data in a first buffer currently in a write state, and analyzing and transmitting the second data through a second buffer currently in a read state; Step 103, detecting the remaining storage space of the first buffer; Step 104, if the remaining storage space in the first buffer is lower than the storage capacity threshold, the first buffer is switched from a write state to a read state, and the second buffer is switched from a read state to a write state; Step 105 , analyzing and transmitting the first data by switching to the first buffer in the read state, and storing the third data received after the switching in the second buffer currently in the write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0025] The embodiment of the present application is applied to an on-chip logic analyzer. The on-chip logic analyzer at least includes the following structures: a trigger unit and a ping-pong buffer.

[0026] Furthermore, a first buffer and a second buffer are provided in the ping-pong buffer. The ping-pong buffer plays a key role in the on-chip logic analyzer, wherein the first buffer and the second buffer provided are core components for realizing efficient data processing. The two buffers work together to realize continuous data collection and real-time processing. In the initial state, the first buffer is set as a write buffer for receiving the first data collected in real time by the trigger unit. At the same time, the second buffer is used as a read buffer to analyze and transmit the second data collected and stored therein before. This parallel operation greatly improves the efficiency of data processing and avoids the drawback that the traditional single buffer cannot read and write at the same time.

[0027] As data is continuously written, the remaining storage space of the first buffer can be continuously detected. Once the remaining storage space is lower than the storage capacity threshold dynamically configured based on the data processing requirements of the on-chip logic analyzer, the states of the two buffers will switch. At this time, the first buffer changes from the write state to the read state, and begins to analyze and transmit the previously stored first data, while the second buffer switches from the read state to the write state to receive the newly collected third data.

[0028] Through this alternating working mode, the first buffer and the second buffer ensure the continuity of data collection, and there will be no data loss or interruption due to buffer state switching. At the same time, the real-time processing function is also realized, providing engineers with instant data feedback, which helps to quickly locate and solve problems in digital systems, improve the debugging efficiency in the integrated circuit development process, and shorten the development cycle.

[0029] In an on-chip logic analyzer, due to the huge differences in different integrated circuit development scenarios and application requirements, a static fixed storage capacity threshold is difficult to meet diverse situations. In an embodiment of the present application, further optionally, the storage capacity threshold can be dynamically configured based on the data processing requirements of the on-chip logic analyzer, so that it can be flexibly adjusted according to the current data processing requirements of the on-chip logic analyzer.

[0030] For example, when debugging a complex digital system, if there are a large number of high-frequency changing signals in the system and the data generation rate is extremely fast, the storage capacity threshold can be increased to prevent data overflow and loss of key information. In this way, the first buffer or the second buffer can reserve more space to ensure that the data generated at high speed can be stored completely without missing any important on-chip signals. On the contrary, when performing relatively simple digital system fault diagnosis, the signal changes smoothly and the data volume is small, lowering the storage capacity threshold can effectively save valuable on-chip storage resources. These released resources can be used for other functional modules that are more in need, improving the resource utilization efficiency of the overall system.

[0031] In addition, as the development of integrated circuits progresses, the emphasis and requirements for data processing at different stages are also changing. In the early stages of development, you may pay more attention to long-term signal acquisition, and at this time, you can appropriately increase the storage capacity threshold; in the later optimization stage, the focus may shift to the precise analysis of key signals in a specific period of time, so lowering the storage capacity threshold and combining it with precise trigger events can make the analysis more targeted. In short, dynamically configuring the storage capacity threshold greatly enhances the ability of on-chip logic analyzers to cope with complex and changing development environments. Further, the trigger unit includes at least a custom storage array. Specifically, the trigger unit uses the effective bit mask to filter out the effective data bits that are really concerned from the input data, filters out irrelevant data bits, reduces the amount of data to be processed subsequently, and improves the pertinence of the analysis. For example, for a wide-bit data, when only some of the key bits are concerned, this module can be used to implement it. The custom storage array is used to temporarily store the data processed by the effective bit mask. Further optionally, the array works according to the first-in-first-out principle, can cache data to a certain extent, wait for comparison with the pattern mask and subsequent processing, and prevent data loss or untimely processing. The trigger unit stores the data flag bit corresponding to the trigger event through the pattern mask, compares it with the data temporarily stored in the custom storage array, determines whether the trigger event is met, and then generates a control signal to control the ping-pong buffer. Under the control signal generated by the pattern mask comparison result in the trigger unit, the ping-pong buffer stores the target input data that meets the cache requirements, plays the role of data caching and transfer, and ensures that the data can be transmitted to the host computer in an orderly and stable manner. The host computer receives the data from the ping-pong buffer and performs subsequent analysis, display and other operations to help users intuitively understand the data collected by the on-chip logic analyzer.

[0032] See also Figure 2 In the schematic diagram of the structure of the on-chip logic analysis shown in the figure, the input data first enters the effective bit mask module in the trigger logic unit (i.e., the trigger unit), and the processed data flows into the FIFO (i.e., the custom storage array). The input data in the FIFO will be compared with the pattern mask, and the control signal generated according to the comparison result will control the data storage in the ping-pong buffer. Furthermore, the ping-pong buffer is connected to the host computer, and the data stored in the ping-pong buffer is used as the basis for data analysis by the host computer.

[0033] Exemplarily, two independent buffers are configured in the on-chip logic analyzer, named memory A and memory B. During initialization, memory A is set as a write buffer and memory B is set as a read buffer. The write logic of memory A is controlled by a trigger logic unit. When memory A is full, it automatically switches to memory B for write operation, and starts reading and processing the data in memory A. Conversely, when memory B is full, it switches back to memory A for write operation, and reads and processes the data in memory B. When reading and processing the data in memory A or memory B, the data is packaged and communicated with the host computer through the PCIe protocol.

[0034] In the embodiment of the present application, in the on-chip logic analyzer application scenario of the embodiment of the present application, after the data in the first buffer and the second buffer are read and processed, the data is packaged and communicated with the host computer using the PCIe (Peripheral Component Interconnect Express) protocol.

[0035] PCIe is a high-speed serial computer expansion bus standard that uses high-speed differential signal pairs for data transmission, supports multi-channel parallel transmission, and can achieve high-speed and reliable data communication. A high-speed data transmission channel is built between the on-chip logic analyzer and the host computer to ensure that data can be quickly and accurately transmitted from the on-chip device to the host computer for further analysis.

[0036] Specifically, before transmitting the data in the first buffer and the second buffer through PCIe, the system will preliminarily organize the data. According to the data type, acquisition timestamp and other information, the relevant data will be classified to prepare for subsequent packaging. A header is added to each data packet, which contains basic information of the data packet, such as the starting address of the data, the length of the data packet, the data type, the checksum information, etc. After receiving the data packet, the host computer can accurately identify and process the data packet by parsing the header information. According to the specifications of the PCIe protocol, the organized data and header information are encapsulated into a PCIe data packet. The PCIe data packet has a specific format and structure, including a transaction layer data packet (TLP), a data link layer data packet (DLLP), etc., to ensure the reliability and integrity of the data during transmission. If the amount of data is large, the data will be divided into multiple smaller data packets for transmission. Each data packet has independent header information, which is convenient for the host computer to receive and reorganize.

[0037] PCIe has a very high data transmission rate, and its different versions support different bandwidths. For example, PCIe3.0x16 channels can provide up to 16GB / s bandwidth, which can meet the needs of fast transmission of large amounts of data from the on-chip logic analyzer, greatly improving the efficiency of data transmission from the on-chip device to the host computer. The design of the PCIe protocol makes the data transmission delay low, and can transmit the collected and processed data to the host computer in time, providing engineers with instant data feedback, which helps to quickly debug the system and diagnose faults. The PCIe protocol has a complete error detection and correction mechanism, such as cyclic redundancy check (CRC), which can effectively detect and correct errors that may occur during data transmission, and ensure the reliability and accuracy of data transmission. PCIe is a widely used standard interface, and most computers and servers support the PCIe interface. Therefore, the on-chip logic analyzer can be easily connected and communicated with various host computers, with good compatibility and versatility.

[0038] In addition to the PCIe protocol, support for other high-speed data transmission protocols can also be added, such as USB4, Thunderbolt, etc. In this way, the most suitable transmission protocol can be selected according to different application scenarios and the interface type of the host computer, thereby improving the compatibility and efficiency of data transmission.

[0039] In the process of data transmission, data pre-fetching technology is used to predict the data that the host computer may need and take it out of the buffer and prepare it for transmission. This can reduce the time the host computer waits for data and improve the real-time performance of data transmission.

[0040] In an embodiment of the present application, a trigger unit is provided with a plurality of trigger modes for the ping-pong buffer; the plurality of trigger modes include: a front trigger mode, a middle trigger mode, and a rear trigger mode. The data caching method of the ping-pong buffer in the front trigger mode is: the first target data bit in the input data before the mode mask is used as the first data. The data caching method of the ping-pong buffer in the middle trigger mode is: the second target data bit in the input data from before the mode mask to after the mode mask is used as the first data. The data caching method of the ping-pong buffer in the rear trigger mode is: the three target data bits in the input data after the mode mask are used as the first data.

[0041] As an optional embodiment, the pattern mask is used to indicate a data flag bit corresponding to a trigger event; the trigger event is associated with a data analysis process performed by the on-chip logic analyzer. Based on this, the pattern mask is dynamically configured based on a data jump form, and the data jump form includes: at least one of a data change value, a data change trend, a data change amplitude, a data timing, and a data repetition number.

[0042] In the embodiment of the present application, the trigger unit sets multiple trigger modes and dynamically configures the mode mask. In the on-chip logic analyzer data processing, the first target data bit in the input data before the mode mask is used as the first data, which allows engineers to capture data before the trigger event occurs. For example, when analyzing the signal changes at the moment of power-on of the circuit, relevant data can be recorded in advance, which helps to deeply understand the status of the system startup phase and avoid missing key information.

[0043] In the medium trigger mode, the data before and after the pattern mask is used as the first data, which can fully record the signal change process before and after the trigger event. For example, when analyzing a signal pulse, it can not only obtain the stable state before the pulse arrives, but also capture the changes during and after the pulse, providing sufficient data for comprehensive analysis of signal characteristics.

[0044] In post-trigger mode, the third target data bit after the pattern mask is used as the first data, and the focus can be on the system response after the trigger event occurs. For example, when studying the recovery process after a system failure, this mode can accurately collect relevant data after the failure occurs, making it easier to locate the problem and evaluate the system recovery capability.

[0045] The pattern mask is dynamically configured based on the data jump form, covering data change value, trend, amplitude, timing, number of repetitions, etc. This dynamic configuration enables the trigger unit to flexibly adjust the trigger event according to different data analysis requirements. For example, when focusing on the rapid change of the signal, the pattern mask can be dynamically adjusted according to the amplitude of the data change to ensure that the key signal can be captured in time. For periodic signals, the pattern mask is configured according to the number of data repetitions to accurately identify the periodic characteristics of the signal. This not only improves the pertinence and accuracy of data acquisition, but also reduces unnecessary data storage, improves the working efficiency of the on-chip logic analyzer, and provides strong support for the debugging and fault diagnosis of complex digital systems.

[0046] As an optional embodiment, before receiving the first data collected in real time by the trigger unit in step 101, the input data can also be collected in real time by the trigger unit; the corresponding data bits to be analyzed are marked in the input data using a valid bit number mask; the data bits to be analyzed are compared to see whether they match the pattern mask to obtain a matching result of the data bits to be analyzed; and according to the matching result and / or the data caching mode in which the trigger unit is located, the data storage process of the ping-pong buffer is controlled by the trigger unit, and the first data in the input data that meets the caching requirements is sent to the ping-pong buffer.

[0047] Specifically, in this optional embodiment, the trigger unit plays a key pre-processing role in the data processing flow of the on-chip logic analyzer. Before receiving the first data collected by the trigger unit in real time, the trigger unit first collects the input data in real time. In this process, the effective bit mask is used to mark the corresponding data bits to be analyzed in the input data. The effective bit mask is like a "precision locator" that can filter out the valuable parts for subsequent analysis from a large amount of input data, avoid invalid processing of irrelevant data, and greatly improve data processing efficiency. Then, these marked data bits to be analyzed are compared with the pattern mask to obtain a matching result. The pattern mask represents the data flag bit corresponding to the trigger event, which is dynamically configured based on the data jump form, such as data change value, trend, amplitude, etc. Through this comparison, it can be accurately determined whether the key part of the input data is consistent with the set trigger event. Then, according to the matching result and the data caching mode (such as front trigger, middle trigger, and post trigger mode) in which the trigger unit is located, the trigger unit controls the data storage process of the ping-pong buffer. If the matching result meets the trigger event and is in a specific data caching mode, the trigger unit will send the first data in the input data that meets the caching requirements to the ping-pong buffer. For example, in the medium trigger mode, when the data bit to be analyzed matches the pattern mask, the trigger unit will store the relevant data from before to after the pattern mask as the first data that meets the cache requirements into the ping-pong buffer, providing a reliable data basis for subsequent data processing and analysis, ensuring that the on-chip logic analyzer can work accurately and efficiently.

[0048] Furthermore, in the application scenario of the on-chip logic analyzer, the custom storage array and the ping-pong buffer in the trigger unit are set as a multi-level first-in-first-out storage array (FIFO), and the corresponding FIFO depth and number of layers can be dynamically configured based on the trigger mode of the trigger unit. The following is a detailed introduction.

[0049] The multi-level FIFO in the custom storage array is used to temporarily store data after the effective bit mask processing. Each level of FIFO can be regarded as an independent data storage queue, and the data flows in each level of FIFO in turn according to the first-in-first-out principle. This multi-level structure can increase the data cache capacity and provide more intermediate stages for data processing, which is convenient for complex pattern detection and data processing operations.

[0050] The multi-level FIFO of the ping-pong buffer is mainly used to store target input data that meets the cache requirements. It works in conjunction with the FIFO of the custom storage array. When the data in the custom storage array meets the trigger event, the data will be transferred to the FIFO of the ping-pong buffer for storage. The multi-level structure of the ping-pong buffer can realize continuous storage and processing of data, improving the efficiency and stability of data storage.

[0051] Based on the aforementioned multi-level structure, the FIFO depth configuration in the pre-trigger mode can be that data for a period of time before the trigger event occurs needs to be stored. Therefore, the FIFO depth of the custom storage array and the ping-pong buffer needs to be configured according to the length of the historical data you want to trace back. For example, if you want to record the data of 100 clock cycles before the trigger event, the FIFO depth must be set to at least 100. This ensures that when the trigger event occurs, the previous relevant data can be fully obtained. The FIFO layer configuration in the pre-trigger mode can be configured according to the complexity of data processing and the analysis requirements of the data. If more complex pattern detection is required, it may be necessary to increase the number of FIFO layers so that different processing and analysis can be performed at different levels. For example, preliminary data screening is performed in the first-level FIFO, and more refined pattern matching is performed in the second-level FIFO.

[0052] The FIFO depth configuration in the medium trigger mode can be that the medium trigger mode needs to record the data before and after the trigger event occurs. Therefore, the configuration of the FIFO depth should take into account the amount of data that needs to be stored before and after the trigger event. For example, if you want to record the data of 50 clock cycles before the trigger event and 50 clock cycles after the trigger event, then the FIFO depth must be set to at least 100. At the same time, the FIFO depth can be further adjusted according to the configurable additional storage length. Similarly, the number of layers is configured according to the needs of data processing and analysis. In order to fully analyze the entire process of the trigger event, more layers may be required for data processing and storage at different stages. For example, key data before, during, and after the trigger are stored in different layers for subsequent detailed comparison and analysis.

[0053] The FIFO depth configuration in post-trigger mode can be to focus on data storage after the trigger event occurs. The FIFO depth can be configured based on the length of time you want to observe the post-trigger data. For example, if you want to record data 200 clock cycles after the trigger event, then the FIFO depth is set to 200. In addition, factors such as the time it takes for the ping-pong buffer to be full and the data input rate need to be considered to ensure that the critical post-trigger data can be fully stored. At the same time, the number of layers can be configured based on the processing requirements for the post-trigger data. If you need to perform multi-stage processing and analysis on the post-trigger data, such as preliminary screening of the data first, and then detailed pattern analysis, you can increase the number of FIFO layers.

[0054] Therefore, by dynamically configuring the FIFO depth and number of layers based on the trigger mode, the performance of the storage array and buffer can be flexibly adjusted according to different debugging and analysis requirements. In different application scenarios, it can quickly adapt to various trigger events and data processing requirements, improving the versatility and adaptability of the on-chip logic analyzer. In addition, it can avoid the problem of resource waste or shortage caused by fixed configuration. When a large amount of data storage is not required, the FIFO depth and number of layers can be reduced to save the storage resources of the chip; when complex data needs to be processed and in-depth analysis is required, the corresponding configuration can be added to ensure that the actual needs can be met. In summary, setting the custom storage array and ping-pong buffer as a multi-level FIFO and dynamically configuring its depth and number of layers based on the trigger mode can provide the on-chip logic analyzer with more flexible and efficient data storage and processing capabilities to meet diverse debugging and analysis needs.

[0055] Further optionally, the ping-pong buffer is configured as a multi-level first-in-first-out storage array FIFO; the FIFO depth and number of layers corresponding to the first buffer and the second buffer in the ping-pong buffer are dynamically configured based on the real-time reading and writing speed of the ping-pong buffer.

[0056] Specifically, during the real-time reading and writing of data, the reading and writing speeds change all the time. When the data writing speed increases, if the current FIFO depth is insufficient, data is easily accumulated and overflows. At this time, the system can automatically increase the depth of the FIFO corresponding to the first buffer or the second buffer according to the high-speed writing speed monitored in real time. For example, by expanding the storage unit through hardware circuits, or adjusting the storage mapping using software algorithms, the FIFO can accommodate more data to ensure the smooth progress of the write operation. Similarly, if the data reading speed increases, the number of FIFO layers can be appropriately increased to meet the demand for fast reading. Multi-layer FIFOs can process data in parallel and accelerate the reading process. For example, the original single-layer FIFO is expanded to a double-layer, the upper layer processes the recently written data, and the lower layer processes the earlier data, so that the data can be read out more efficiently and reduce the reading delay. On the other hand, when the reading and writing speed decreases, dynamically reducing the FIFO depth and number of layers can release unnecessary storage resources and avoid resource waste. For example, reducing the number of layers of an overly deep FIFO can save chip area and power consumption and improve resource utilization. This dynamic configuration based on real-time read and write speeds allows the first and second buffers of the ping-pong buffer to flexibly adapt to changes in data flow and always maintain efficient read and write performance, ensuring that the on-chip logic analyzer can stably and efficiently complete data collection, storage and processing tasks under different workloads.

[0057] Further optionally, the storage space capacity occupied by each of the first buffer zone and the second buffer zone in the ping-pong buffer zone is proportional to the corresponding real-time data transmission rate of each in the current state.

[0058] Specifically, when the data transmission rate changes, this mechanism of dynamically allocating storage space can effectively cope with it. For example, if the first buffer is currently in a data writing state and the real-time data writing rate rises sharply, it means that more data needs to be stored per unit time. At this time, the system will automatically increase the storage space capacity occupied by the first buffer based on the proportional relationship between the two. The implementation method can be to dynamically adjust the address allocation of the storage area through the hardware circuit, or to re-plan the ownership of the memory block using the software algorithm, so that the first buffer can obtain more storage resources to meet the needs of high-speed data writing and prevent data from being lost due to insufficient storage space. On the contrary, if the second buffer is in a data reading state and the real-time data reading rate is accelerated, it indicates that data needs to be extracted from the buffer faster. According to the proportional principle, the system will increase the storage space capacity of the second buffer accordingly. This enables the buffer to accommodate more data to be read, reduces data waiting time, improves data reading efficiency, and thus improves the fluency of the entire data processing process. When the data transmission rate decreases, the storage space capacity occupied by the buffer will also decrease accordingly. This can avoid too much storage space being idle, improve the overall utilization of storage resources, and reduce hardware costs and power consumption. By dynamically adjusting the storage space capacity according to the real-time data transmission rate, the first buffer and the second buffer can flexibly adapt to different working scenarios, ensuring the stable and efficient operation of the on-chip logic analyzer, and providing solid support for the debugging and optimization of digital systems.

[0059] Further optionally, the ping-pong buffer can be configured as a multi-level first-in-first-out storage array (FIFO). The FIFO depth and number of layers corresponding to the first buffer and the second buffer in the ping-pong buffer can be dynamically configured based on the data processing requirements of the on-chip logic analyzer and the trigger mode of the trigger unit.

[0060] Specifically, the ping-pong buffer is set as a multi-level first-in-first-out storage array (FIFO), and its depth and number of layers are dynamically configurable, which greatly improves the flexibility and adaptability of the on-chip logic analyzer. In terms of data processing requirements, when faced with a large number of high-speed changing on-chip signals in complex digital systems, if the amount of data increases dramatically, the FIFO depth can be increased to store more data to prevent data overflow. At the same time, according to the complexity of data processing, the number of layers can be appropriately increased. For example, when data of different types or priorities need to be processed in layers, the multi-layer structure can better meet the needs and improve data processing efficiency.

[0061] The trigger mode of the trigger unit also affects the configuration of the FIFO. If it is in the pre-trigger mode or post-trigger mode, in order to accurately capture the required data, the FIFO depth can be appropriately deepened to ensure that the key data before and after the trigger event can be fully recorded. In the medium trigger mode, if you pay attention to the data changes in the interval corresponding to the trigger event, you can adjust the number of layers and depth of the FIFO according to the estimated amount of data in the interval. For example, if it is expected that there will be a lot of data in this interval, the number of layers can be increased to process data in different time periods in parallel and improve the overall processing speed. Through this dynamic configuration based on data processing requirements and trigger modes, the multi-level FIFO in the ping-pong buffer can efficiently realize continuous data acquisition and processing in different application scenarios, provide more reliable and accurate data support for on-chip logic analyzers, and help engineers debug and diagnose digital systems more quickly and accurately.

[0062] Optionally, more levels of buffers are added based on the first buffer and the second buffer to form a multi-level ping-pong structure. For example, four buffers are set to provide more flexible data processing capabilities in more complex scenarios. When one buffer is processing data, other buffers can continue to collect data, further reducing the waiting time for data processing and improving the continuity of data processing.

[0063] For example, adding four buffers on the basis of two-level ping-pong buffers can greatly enhance the flexibility of data processing in complex scenarios. When the digital system is running, the rhythm of data acquisition and processing is complex and changeable. When one buffer is busy with data processing, such as data parsing, format conversion, and transmission to external devices, the other three buffers can be engaged in data acquisition at the same time. This parallel operation mode greatly reduces the waiting time for data processing. For example, in high-speed data acquisition scenarios, traditional ping-pong buffers may have processing gaps that cause data acquisition to stagnate briefly. The four-level ping-pong structure can further ensure the continuity of data acquisition, making data processing as smooth as flowing water, greatly improving processing continuity, and providing a solid guarantee for the stable operation of the system.

[0064] Further optionally, the size of the buffer is dynamically adjusted according to the actual data acquisition rate and processing requirements. For example, when the data acquisition rate suddenly increases, the capacity of the first buffer and the second buffer is automatically increased to avoid data overflow. When the data acquisition rate is low, the buffer size is reduced to save storage resources.

[0065] For example, the actual data acquisition rate is not constant. When the data acquisition rate increases suddenly, such as when a large number of signals burst out in the system, the buffer can be automatically expanded. Through hardware circuit or software algorithm control, the number of storage units in the buffer is increased or its address mapping range is adjusted to prevent data from overflowing and losing due to insufficient space. For example, the address range of the buffer is adjusted by modifying the address mapping table. When the buffer needs to be expanded, the address mapping can be reallocated to include the originally unused address space in the addressing range of the buffer, thereby increasing the effective storage capacity of the buffer. Furthermore, the data is divided into multiple segments for storage, and the address mapping of the segment is dynamically adjusted according to the usage of the buffer. When a segment is full, the subsequent data is automatically stored in the new segment, and the address mapping information is updated to ensure continuous storage and effective management of the data. Conversely, when the data acquisition rate is low, the buffer size is actively reduced to release excess storage resources. These resources can be reallocated to other urgently needed system modules, effectively improving the resource utilization of the entire on-chip system, so that the system can run efficiently under different data traffic.

[0066] As an optional embodiment, before writing the data into the buffer, an efficient data compression algorithm is used to compress the data. This can reduce the storage space required for the buffer, and when the data is transmitted to the host computer, it can also reduce the amount of data transmitted and improve the transmission efficiency. For example, for some periodic or regular data, a lossless compression algorithm can be used for compression.

[0067] Set different priorities for different types of data. When the buffer space is limited, high-priority data is processed and stored first to ensure that important data is not lost. For example, data for system critical signals can be set to high priority, while data for some auxiliary signals can be set to low priority.

[0068] In the embodiment of the present application, the trigger logic unit can be further optimized as an adaptive trigger logic. It can automatically adjust the trigger event according to the real-time characteristics of the collected data. For example, when the frequency of data changes suddenly increases, the trigger threshold is automatically lowered to capture the data changes more timely.

[0069] In addition to the existing trigger logic, support for multiple trigger sources is added. For example, triggering can be performed not only based on specific data values, but also based on multiple conditions such as the rate of change and periodicity of the data, thus improving the flexibility and applicability of the logic analyzer.

[0070] In the embodiment of the present application, a parallel processing architecture is introduced, and multiple processing units are set in the on-chip logic analyzer to process data in different buffers at the same time. For example, one processing unit is responsible for processing data in memory A, and another processing unit is responsible for processing data in memory B, which can greatly improve the speed of data processing.

[0071] Optionally, an intelligent management system is constructed to monitor and manage the entire on-chip logic analyzer in real time. It can automatically detect the system's operating status, buffer usage, data transmission rate, etc., and automatically adjust and optimize according to the detection results to improve the stability and reliability of the system.

[0072] In the embodiment of the present application, input data refers to a data stream related to the function to be monitored and analyzed from inside or outside the chip. These data can be of various types, such as binary data transmitted in a digital circuit, digital representation corresponding to an analog signal after analog-to-digital conversion, etc. For example, in a processor chip, instruction data, operation data, etc. transmitted on the processor internal bus can be used as input data for an on-chip logic analyzer. In a communication chip, data packet data transmitted in a communication link can also become input data. It covers all data information generated or received during the operation of the chip that needs to be monitored and analyzed.

[0073] In the embodiment of the present application, the effective digit mask is a binary number used to filter the key data bits in the input data. Its bit width is the same as the bit width of the input data, and the attention to the corresponding bit in the input data is indicated by setting "1" and "0" in the mask. When a certain bit in the mask is "1", it means that the corresponding bit in the input data is the effective data bit that the user really cares about; if it is "0", it means that the bit is a bit that can be ignored in the current analysis. For example, if the input data is 32 bits, and the user only cares about the data of bits 8-15, the effective digit mask can be set to 000000001111111100000000000000000. When the on-chip logic analyzer is working, the input data is logically ANDed with the effective digit mask to obtain the filtered data containing only the effective data bits, thereby reducing the amount of data to be processed later and focusing on key information for analysis.

[0074] In the embodiment of the present application, the mode mask is used to indicate the data flag bit corresponding to the trigger event. Here, the trigger event is associated with the data analysis process performed by the on-chip logic analyzer. That is, the trigger event is a key event that triggers a data jump and needs to be monitored in the data analysis process performed by the on-chip logic analyzer.

[0075] Specifically, the pattern mask is a binary number whose bit width is usually the same as the bit width of the input data. It is like a "data key" used to filter out data that meets specific requirements. Each bit in the mask corresponds to the corresponding bit of the input data. When a bit in the pattern mask is set to a specific value (such as "1" or "0"), it means that when judging the trigger event, the corresponding bit of the input data must match it; if it is set to a wildcard (such as "X"), it means that the specific value of this bit does not need to be paid attention to when judging. For example, for 32-bit input data, if the pattern mask is 1010XXXX1100XXXX, it means paying attention to the 1st, 2nd, 5th, 6th, 9th, and 10th bits of the input data, and requiring the 1st, 2nd, 9th, and 10th bits to be 1, 0, 1, and 0 respectively, while other bits marked with "X" are not strictly required when triggering judgments.

[0076] Trigger events refer to key events that users want to focus on monitoring or analyzing during the operation of the chip. These events can be varied, for example, triggering when a certain value or a group of certain values ​​appear on a specific data line, such as a specific memory address appears on the processor's address bus, or a key instruction code appears on the data bus. For example, triggering when a signal changes from a low level to a high level, or from a high level to a low level, such as the rising or falling edge of a clock signal, the valid / invalid state switching of a control signal, etc. For example, triggering when the data in multiple consecutive clock cycles meets a pre-set pattern, such as the continuous appearance of a data sequence such as "ABC". For example, for a chip containing a state machine, it is triggered when the state machine enters a specific state to analyze the operation of the chip in that state.

[0077] Thus, the occurrence of a trigger event is the "switch" that starts the data analysis process. Once the pattern mask matches the input data, indicating that a trigger event has occurred, the on-chip logic analyzer will begin to collect, store, and analyze relevant data according to the preset process. For example, after detecting a specific data pattern match, it will start recording all relevant data for a period of time before and after the trigger, so as to conduct a subsequent in-depth analysis of the background, process, and impact of the event.

[0078] Different trigger events correspond to different data analysis focuses. For example, if the trigger event is a change in a control signal, the data analysis process may focus on checking the values ​​of related registers before and after the signal changes, the synchronous changes of other signals, etc., to determine whether the control signal is working properly and its impact on the entire system; if the trigger event is an abnormal data value on the data bus, the data analysis process will analyze the source of the data value, the transmission path, and the impact on subsequent data processing.

[0079] In addition, users can define different trigger events by setting different pattern masks according to specific debugging and analysis needs, and then customize the corresponding data analysis process. At different stages of chip design or when troubleshooting different types of problems, the pattern mask and the corresponding analysis process can be flexibly adjusted, so that the on-chip logic analyzer can adapt to a variety of analysis tasks and improve the efficiency of debugging and troubleshooting.

[0080] In the embodiment of the present application, first, by marking the data bits to be analyzed in the input data through the effective digit mask, it is possible to focus on the key data part and avoid processing a large amount of irrelevant data. This can reduce the amount of data processing, improve the speed and efficiency of data processing, and significantly improve the analysis efficiency, especially when processing wide-bit data or data containing a large amount of redundant information. For example, for a 128-bit data, if you only care about 32 bits of key data, the use of the effective digit mask can directly locate these 32 bits without processing the entire 128-bit data.

[0081] Secondly, the pattern mask is used to indicate the data flag corresponding to the trigger event, and the trigger event is associated with the data analysis process. This allows users to flexibly set the trigger event according to specific analysis needs to meet different debugging and analysis scenarios. No longer limited to fixed trigger events, it can more accurately capture data related to the target event, improving the adaptability and practicality of the logic analyzer. For example, in different chip designs, different pattern masks can be set to trigger data caching according to the chip's functions and possible problems.

[0082] In addition, since the trigger event is associated with the data analysis process performed by the on-chip logic analyzer, this technical solution can adapt to diverse data analysis needs. Whether it is the verification of chip functions, performance evaluation or troubleshooting, accurate and useful data can be obtained by setting appropriate mode masks and data caching methods, providing strong support for in-depth data analysis.

[0083] Furthermore, according to the matching results and the data caching mode of the trigger unit, the data storage process of the custom storage array and the ping-pong buffer is controlled. This enables the target input data that meets the caching requirements to be accurately stored in the ping-pong buffer, avoiding unnecessary data storage and saving storage resources. At the same time, different data caching modes (such as pre-trigger, mid-trigger, post-trigger, etc.) can be effectively controlled and managed to ensure the integrity and accuracy of the data. For example, in the mid-trigger mode, the relevant data before and after the trigger event can be accurately stored according to the matching results.

[0084] It is understandable that the combination of custom storage arrays and ping-pong buffers, as well as precise control of the data storage process, can optimize the use of storage resources, avoid the waste or shortage of storage resources that may occur in traditional methods, enable storage resources to be more reasonably allocated and used, and improve the overall performance and stability of the system.

[0085] It can be further understood that the embodiments of the present application do not rely on a specific chip architecture or data type, and can be applied to a variety of different on-chip logic analyzers, with strong versatility. Whether processing simple digital signals or complex mixed signals, efficient data caching and analysis can be achieved by adjusting parameters such as the effective bit mask and the mode mask, thereby expanding the application scope of the logic analyzer.

[0086] The following describes the specific implementation methods of each step with examples.

[0087] In step 101, first data collected in real time by a trigger unit is received.

[0088] As an optional embodiment, before receiving the first data collected in real time by the trigger unit in step 101, the first buffer can also be set to a write state and the second buffer can be set to a read state; according to the real-time data transmission conditions and real-time debugging requirements of the on-chip logic analyzer, the start timing of the first buffer and the second buffer is dynamically configured so that the first buffer and the second buffer can cooperate to realize real-time reading and writing of the trigger unit.

[0089] In the embodiment of the present application, the start time of the first buffer zone in the write state is earlier than the start time of the second buffer zone in the read state.

[0090] During the operation of the on-chip logic analyzer, precise control of the start-up timing of the first and second buffers is a key step in improving system performance.

[0091] Before receiving the first data collected in real time by the trigger unit, the first buffer is set to the write state and the second buffer is set to the read state. This is the basic setting of the system data processing flow. Dynamically configuring their startup timing according to the real-time data transmission conditions and real-time debugging requirements of the on-chip logic analyzer allows the system to flexibly adapt to different working scenarios.

[0092] For example, when the data transmission rate is high and the debugging requirements focus on quickly capturing initial data, the first buffer in the write state is started in advance. This means that it can start receiving data collected by the trigger unit earlier, use its write state to store data in time, and retain the original information for subsequent analysis. Since the first buffer is started early, it can collect data efficiently at the early stage of data generation, avoiding data loss due to startup delays.

[0093] The second buffer in the read state starts relatively late because when data collection starts, there may not be enough data to read and analyze. After the first buffer accumulates a certain amount of data, the second buffer is started for reading. At this time, the data read is more complete and valuable for analysis.

[0094] In actual applications, if the real-time debugging needs focus on the continuous processing of data, the time difference between the start-up timing of the two buffers can be appropriately adjusted. When a certain amount of data is written to the first buffer and reaches a stable state, the second buffer is immediately started to read the data, so that the two work together to achieve real-time reading and writing of the trigger unit. This collaborative mechanism ensures the continuity of data acquisition and processing. The first buffer focuses on capturing data in a timely manner, and the second buffer reads and analyzes the stored data at the right time, effectively improving the on-chip logic analyzer's processing efficiency of the trigger unit's real-time data, providing strong support for accurate debugging of digital systems.

[0095] It is worth noting that when adjusting the buffer start timing, it is necessary to ensure that data will not be lost due to improper start time settings. For example, if the first buffer in the write state is started too late, important data collected earlier by the trigger unit may be missed. If the second buffer in the read state is started too early, incomplete or invalid data may be read. In addition, it is necessary to ensure that the data is transmitted coherently between the two buffers. After dynamically configuring the start timing, it should be ensured that the order and relevance of the data are not destroyed during the process from writing to reading from the first buffer to the second buffer, so that the logical and timing relationship between the data can be accurately analyzed later. The configuration of the start timing should match the data processing capability of the on-chip logic analyzer. If the buffer is started too quickly, the amount of data exceeds the processing capability of the system, which may cause system overload, slow processing speed, or even errors. If the start is too slow, the overall efficiency of the system will be reduced. Minimize the system delay introduced by the dynamic configuration of the start timing. Frequent adjustment of the start time may cause additional delays in the system when switching the buffer state, affecting the real-time performance of data processing, so it needs to be optimized during configuration. Be able to respond to changes in real-time data transmission conditions and debugging requirements in a timely manner. When the data transmission rate changes suddenly or the debugging focus shifts, the buffer startup timing should be adjusted quickly to meet the real-time requirements. The startup timing should be configured in combination with the trigger event of the trigger unit. For example, after the trigger event occurs, it is necessary to ensure that the buffer can be started in time to accurately capture and process relevant data.

[0096] Further optionally, in the above steps, dynamically configuring the start timing of the first buffer and the second buffer according to the real-time data transmission conditions and real-time debugging requirements of the on-chip logic analyzer includes: Determine the storage space capacity and storage space structure of each of the first buffer and the second buffer; determine the read and write time difference between the first buffer and the second buffer according to the real-time data transmission condition, the real-time debugging requirement, and the storage space capacity and storage space structure of each of the first buffer and the second buffer; configure the start timing of each of the first buffer and the second buffer based on the read and write time difference.

[0097] Specifically, we first need to determine the storage space capacity and structure of the first and second buffers. The storage space capacity needs to be determined based on the amount of data that the system may process. If a large amount of continuous data is expected, the capacity must be large enough to prevent data overflow. The storage space structure involves whether to use simple linear storage or more complex hierarchical storage, etc., which depends on the characteristics of the data and processing requirements. Next, the read and write time difference between the two is determined based on the real-time data transmission conditions, real-time debugging requirements, and the determined buffer storage space capacity and structure. For example, when the real-time data transmission rate is high and the real-time debugging requirement is to quickly process new data, if the first buffer has a large capacity and the structure is conducive to fast writing, the time difference from its startup to the start of reading in the second buffer can be appropriately shortened. If the data transmission rate is unstable, it is also necessary to dynamically adjust the time difference in combination with the characteristics of the buffer structure to ensure the consistency and efficiency of data processing. Finally, the start timing of each of the two buffers is configured based on the determined read and write time difference. According to the calculated time difference, the time when the first buffer starts writing data and the time when the second buffer starts reading data after that are accurately set to ensure that data flows in an orderly manner between the two buffers, realize efficient real-time reading and writing of trigger unit data, and improve the overall performance of the on-chip logic analyzer.

[0098] In step 102, the first data is stored in a first buffer currently in a write state, and the second data is analyzed and transmitted through a second buffer currently in a read state. Further, the first data and the second data are continuously collected by the trigger unit.

[0099] The first data is quickly stored in the first buffer which is currently in the write state. The first buffer is temporarily stored. In simple terms, the first buffer is specifically responsible for receiving and temporarily storing the latest collected data. At the same time, the second buffer which is currently in the read state is also actively working to analyze and transmit the second data. It is worth noting that the first data and the second data are continuously collected by the trigger unit, which ensures the consistency and integrity of the data.

[0100] In this process, the status of the two buffers is clearly divided, one focuses on data writing, and the other is responsible for data analysis and transmission. Parallel operation greatly improves data processing efficiency. For example, when debugging a complex digital system, the trigger unit continuously collects a large amount of signal data, and the first buffer stores the latest first data in a timely manner to retain the original information for subsequent in-depth analysis. The second buffer parses the previously stored second data, extracts key features, and transmits them to the host computer or other processing modules through a high-speed interface, helping engineers quickly grasp the system operation status and accurately locate problems. This data processing method based on the ping-pong buffer mechanism ensures that the on-chip logic analyzer can efficiently and stably process real-time collected data, providing solid support for the development and debugging of integrated circuits.

[0101] As an optional embodiment, in step 102, after the first data is stored in the first buffer that is currently in a write state, and the second data is analyzed and transmitted through the second buffer that is currently in a read state, the read and write status data of the first buffer and the second buffer can also be collected in real time; the read and write status data at least includes: the read and write rates, data transmission rate, and transmission delay of the first buffer and the second buffer respectively; the read and write status data is input into the buffer prediction model to predict the read and write status prediction values ​​of the first buffer and the second buffer within a preset time period in the future; based on the read and write status prediction values, the predicted read and write time difference between the first buffer and the second buffer is determined; based on the predicted read and write time difference, the state switching timing of the first buffer and the second buffer is optimized.

[0102] Specifically, during the operation of the on-chip logic analyzer, after the first data is stored in the first buffer in the write state and the second data is analyzed and transmitted through the second buffer in the read state, a series of subsequent operations are aimed at optimizing the buffer performance. First, the read and write status data of the first and second buffers are collected in real time, covering their respective read and write rates, data transmission rates, and transmission delays. These data reflect the current working conditions of the buffers. Then, these read and write status data are input into the buffer prediction model, which will analyze based on historical data and algorithms to predict the predicted read and write status values ​​of the first and second buffers within a preset time in the future, such as predicting the changes in read and write rates within a period of time in the future. Then, based on these predicted values, the predicted read and write time difference between the two buffers is determined, that is, it is estimated when in the future one buffer will finish writing data and the other buffer will start reading data. Finally, based on this predicted read and write time difference, the state switching timing of the first and second buffers is optimized to avoid problems such as incoherent data processing, low efficiency or data loss due to untimely switching, and ensure that the system can be prepared in advance according to the predicted situation, so that the first and second buffers can work efficiently and collaboratively in different working scenarios, and improve the data processing capability and overall performance of the on-chip logic analyzer.

[0103] For example, the trigger unit collects data during the operation of the processor in real time, stores the first data in the first buffer in the write state, and analyzes the second data collected before in the second buffer in the read state, and transmits the analyzed data to the host computer through the PCIe protocol. Specifically, the read and write status data of the first buffer and the second buffer are collected in real time, including their respective read and write rates, data transmission rates, and transmission delays. For example, when the processor performs complex computing tasks, the write rate of the first buffer reaches 100MB / s, the read and transfer rates of the second buffer are 80MB / s, and the transmission delay is 100 microseconds; in the standby state, the write rate of the first buffer drops to 10MB / s, the read and transfer rates of the second buffer are 8MB / s, and the transmission delay is 50 microseconds. Then, these read and write status data are input into the buffer prediction model. Assuming that the preset duration is 100 milliseconds, the model predicts that in the next 100 milliseconds, the processor will switch from the complex computing task to the standby state, the write rate of the first buffer will gradually decrease to 15MB / s, and the read and transfer rates of the second buffer will decrease to 12MB / s. Finally, based on these predicted values, the predicted read and write time difference between the first buffer and the second buffer is determined. Originally, at a high data generation rate, the state switching time interval between the two buffers is 10 milliseconds. After prediction, at a low data generation rate, the state switching time interval can be extended to 50 milliseconds.

[0104] Based on this predicted read-write time difference, the state switching timing between the first buffer and the second buffer is optimized. When a downward trend in data generation rate is detected, the state switching time is adjusted in advance to avoid system overhead caused by frequent switching and improve overall efficiency.

[0105] In step 103, the remaining storage space of the first buffer is detected.

[0106] During the operation of the on-chip logic analyzer, the first buffer is mainly responsible for storing the first data collected by the trigger unit in real time. In order to ensure the continuity of data storage and the stable operation of the system, it is necessary to perform real-time detection on the remaining storage space of the first buffer.

[0107] For example, a counter is set at the data write end of the first buffer. Whenever new data is written to the buffer, the counter value is increased by 1. The remaining storage space can be obtained by subtracting the current value of the counter from the total capacity of the buffer (the total number of storage units). A synchronous counter can be used, which is driven by the write clock signal. When the write enable signal is valid, the counter is increased by 1 for each write clock pulse. The number of bits of the counter needs to be determined according to the total capacity of the buffer. For example, if the total capacity of the buffer is 2 nIf there are n storage units, then the counter needs n bits.

[0108] The advantages are simple implementation, fast response, and the ability to track the number of used storage cells in real time. The limitations are that the counter itself may take up certain hardware resources, and in some complex write modes, additional logic may be required to ensure the accuracy of the counter.

[0109] For example, an address pointer is set on the address bus of the buffer to indicate the address of the current written data. At the same time, the starting address and the end address of the buffer are stored in the register. By comparing the value of the address pointer with the end address, the remaining storage space can be calculated. When data is written, the address pointer increments with the write operation. The system can continuously compare the size relationship between the address pointer and the end address through a comparator. The remaining storage space can be calculated by subtracting the value of the current address pointer from the end address. In this way, the information of the address bus can be directly used without the need for an additional counter. The limitation is that it is necessary to ensure that the update of the address pointer is synchronized with the data write operation, otherwise the calculation result may be inaccurate.

[0110] For example, in an operating system or an embedded system, a memory manager is used to manage the memory allocation and release of the first buffer. The memory manager maintains a data structure to record the usage of the buffer, including allocated memory blocks and free memory blocks. Data structures such as linked lists or bitmaps can be used to record the usage of the buffer. For example, when a linked list is used, each node represents a memory block, including the starting address, size, and whether the memory block has been allocated. When data is written, the memory manager allocates the corresponding memory block as needed and updates the information of the linked list. By traversing the linked list, the remaining free memory block size can be calculated. In this way, it is highly flexible and can adapt to different memory allocation strategies and write modes. The limitation is that the response speed of the software implementation is relatively slow, which may be affected by the system load.

[0111] For example, some status flags are set in the software to record the usage of the buffer. For example, a flag can be set to indicate whether the buffer is full, and another flag can be set to indicate the number of storage units used. When data is written, the software will update the values ​​of these flags. For example, each time a data unit is written, the flag of the number of storage units used is increased by 1. By reading the values ​​of these flags, the remaining storage space can be calculated.

[0112] In step 104, if the remaining storage space in the first buffer is lower than the storage capacity threshold, the first buffer is switched from a write state to a read state, and the second buffer is switched from a read state to a write state. Further, the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer.

[0113] Specifically, when it is detected that the remaining storage space in the first buffer is lower than the storage capacity threshold, the system will perform a buffer state switching operation. The storage capacity threshold here is not fixed, but is dynamically configured based on the data processing requirements of the on-chip logic analyzer. If the current data acquisition rate is fast, or the subsequent data processing process has high requirements for data integrity, the storage capacity threshold will be increased accordingly, so that more space can be reserved for the first buffer to store data and avoid data loss. Conversely, if the data acquisition rate is slow, the threshold can be appropriately lowered to improve the utilization of storage resources. Once the remaining storage space is lower than the threshold, the system will switch the first buffer from the write state to the read state, and the second buffer from the read state to the write state. This state switching can be achieved through hardware control signals or software instructions to ensure that the functions of the two buffers can be smoothly converted.

[0114] In step 105, the first data is analyzed and transmitted by switching to the first buffer in the read state, and the third data received after the switching is stored in the second buffer currently in the write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0115] It can be understood that after completing the buffer state switching, the system enters a new data processing stage. The first buffer in the read state begins to analyze and transmit the first data stored previously. The analysis process may include operations such as decoding, filtering, and feature extraction of the data to obtain useful information. The transmission is to send the analyzed data to the host computer or other processing equipment through a suitable interface (such as PCIe protocol) for further processing and analysis. At the same time, the second buffer in the write state begins to receive new data, that is, the third data collected by the trigger unit. The second buffer will store these data in sequence to prepare for the next round of data processing. In this way, the first buffer and the second buffer perform read and write operations alternately, realizing the real-time data reading and writing function of the on-chip logic analyzer, and ensuring the continuity and efficiency of data acquisition and processing.

[0116] In the embodiment of the present application, by switching between the read and write states of multiple buffers (such as the first buffer and the second buffer), more on-chip signals can be captured in time, avoiding signal loss, thereby ensuring the integrity of the on-chip signals and improving the accuracy of the analysis results. In addition, by switching the buffers in real time, data can be analyzed and transmitted at the same time as they are generated, achieving instant data feedback without waiting for offline analysis results, greatly shortening the debugging time, improving debugging efficiency, and effectively shortening the IC development cycle.

[0117] In another embodiment of the present application, an on-chip logic analyzer is also provided. Figure 3 The on-chip logic analyzer at least includes: a trigger unit and a ping-pong buffer, wherein the ping-pong buffer is provided with a first buffer and a second buffer.

[0118] The ping-pong buffer is configured to receive first data collected in real time by a trigger unit; store the first data in a first buffer currently in a write state, and analyze and transmit the second data through a second buffer currently in a read state; the first data and the second data are continuously collected by the trigger unit; The trigger unit is configured to detect the remaining storage space in the first buffer; if the remaining storage space in the first buffer is lower than a storage capacity threshold, the first buffer is switched from a write state to a read state, and the second buffer is switched from a read state to a write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer; The ping-pong buffer is configured to analyze and transmit the first data by switching to the first buffer in the read state, and store the third data received after the switching in the second buffer currently in the write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0119] Further optionally, the trigger unit is provided with a plurality of trigger modes for the ping-pong buffer; the plurality of trigger modes include: a front trigger mode, a middle trigger mode, and a rear trigger mode; the data caching method of the ping-pong buffer in the front trigger mode is: the first target data bit in the input data before the mode mask is used as the first data; the data caching method of the ping-pong buffer in the middle trigger mode is: the second target data bit in the input data from before the mode mask to after the mode mask is used as the first data; the data caching method of the ping-pong buffer in the rear trigger mode is: the three target data bits in the input data after the mode mask are used as the first data.

[0120] Further optionally, the pattern mask is used to indicate a data flag corresponding to a trigger event; the trigger event is associated with a data analysis process executed by the on-chip logic analyzer; the pattern mask is dynamically configured based on a data transition form, and the data transition form includes: at least one of a data change value, a data change trend, a data change amplitude, a data timing, and a number of data repetitions.

[0121] Further optionally, the trigger unit, before the ping-pong buffer receives the first data collected in real time by the trigger unit, is further configured to: The input data is collected in real time; corresponding data bits to be analyzed are marked in the input data using a valid bit number mask; the data bits to be analyzed are compared to see whether they match the pattern mask to obtain a matching result of the data bits to be analyzed; according to the matching result and / or the data caching mode of the trigger unit, the data storage process of the ping-pong buffer is controlled by the trigger unit, and the first data in the input data that meets the caching requirements is sent to the ping-pong buffer.

[0122] Further optionally, the trigger unit, before the ping-pong buffer receives the first data collected in real time by the trigger unit, is further configured to: The first buffer is set to a write state, and the second buffer is set to a read state; according to the real-time data transmission conditions and real-time debugging requirements of the on-chip logic analyzer, the start timing of the first buffer and the second buffer is dynamically configured so that the first buffer and the second buffer cooperate to realize real-time reading and writing of the trigger unit.

[0123] Further optionally, the trigger unit dynamically configures the start timing of the first buffer and the second buffer according to the real-time data transmission condition and real-time debugging requirement of the on-chip logic analyzer, and is configured as follows: Determine the storage space capacity and storage space structure of each of the first buffer and the second buffer; determine the read and write time difference between the first buffer and the second buffer according to the real-time data transmission condition, the real-time debugging requirement, and the storage space capacity and storage space structure of each of the first buffer and the second buffer; configure the start timing of each of the first buffer and the second buffer based on the read and write time difference.

[0124] Further optionally, the start time of the first buffer zone in the write state is earlier than the start time of the second buffer zone in the read state.

[0125] Further optionally, the ping-pong buffer further includes a prediction unit, which is further configured to: after the ping-pong buffer stores the first data in a first buffer currently in a write state and analyzes and transmits the second data through a second buffer currently in a read state: The read and write status data of the first buffer and the second buffer are collected in real time; the read and write status data at least include: the read and write rate, data transmission rate and transmission delay of the first buffer and the second buffer respectively; the read and write status data are input into the buffer prediction model to predict the read and write status prediction values ​​of the first buffer and the second buffer within a preset time period in the future; based on the read and write status prediction values, the predicted read and write time difference between the first buffer and the second buffer is determined; based on the predicted read and write time difference, the state switching timing of the first buffer and the second buffer is optimized.

[0126] Further optionally, the ping-pong buffer is configured as a multi-level first-in-first-out storage array FIFO; the FIFO depth and number of layers corresponding to the first buffer and the second buffer in the ping-pong buffer are dynamically configured based on the real-time reading and writing speed of the ping-pong buffer.

[0127] Further optionally, the storage space capacity occupied by each of the first buffer zone and the second buffer zone in the ping-pong buffer zone is proportional to the corresponding real-time data transmission rate of each in the current state.

[0128] The system can implement various steps in the above method embodiment, which will not be expanded here.

[0129] The on-chip logic analyzer provided in the embodiment of the present application can not only ensure the integrity of on-chip signals and improve the accuracy of analysis results, but also greatly shorten the debugging time and improve the debugging efficiency.

[0130] See also Figure 4 , Figure 4 This is a schematic diagram of an electronic device provided in an embodiment of the present application. Figure 4 As shown, an embodiment of the present application provides an electronic device 500, including a memory 510, a processor 520, and a computer program 511 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, the following steps are implemented: receiving first data collected by a trigger unit in real time; storing the first data in a first buffer currently in a write state, and analyzing and transmitting the second data through a second buffer currently in a read state; the first data and the second data are continuously collected by the trigger unit; detecting the remaining storage space of the first buffer; if the remaining storage space in the first buffer is lower than the storage capacity threshold, switching the first buffer from a write state to a read state, and switching the second buffer from a read state to a write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer; analyzing and transmitting the first data through the first buffer switched to a read state, and storing the third data received after the switch in the second buffer currently in a write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0131] See also Figure 5 , Figure 5 A schematic diagram of an embodiment of a computer-readable storage medium provided in an embodiment of the present application. Figure 5As shown, this embodiment provides a computer-readable storage medium 600, on which computer program information 611 is stored. When the computer program information 611 is executed by the processor, the following steps are implemented: receiving first data collected in real time by a trigger unit; storing the first data in a first buffer currently in a write state, and analyzing and transmitting the second data through a second buffer currently in a read state; the first data and the second data are continuously collected by the trigger unit; detecting the remaining storage space of the first buffer; if the remaining storage space in the first buffer is lower than the storage capacity threshold, switching the first buffer from a write state to a read state, and switching the second buffer from a read state to a write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer; analyzing and transmitting the first data through the first buffer switched to a read state, and storing the third data received after the switch in the second buffer currently in a write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

[0132] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. It should be understood by those skilled in the art that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. Although the preferred embodiments of the present application have been described, once the technical personnel in the field know the basic creative concept, they can make additional changes and modifications to these embodiments. Therefore, the attached claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. In this way, if these modifications and variations of the present application belong to the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A real-time data reading and writing method for an on-chip logic analyzer, characterized in that: The on-chip logic analyzer at least comprises: a trigger unit, a ping-pong buffer, wherein the ping-pong buffer is provided with a first buffer and a second buffer; the method comprises: Receiving first data collected in real time by a trigger unit; storing the first data in a first buffer currently in a write state, and analyzing and transmitting the second data through a second buffer currently in a read state; the first data and the second data are continuously collected by the trigger unit; Detecting the remaining storage space of the first buffer; If the remaining storage space in the first buffer is lower than a storage capacity threshold, switching the first buffer from a write state to a read state, and switching the second buffer from a read state to a write state; the storage capacity threshold is dynamically configured based on data processing requirements of the on-chip logic analyzer; The first data is analyzed and transmitted by switching the first buffer to a read state, and the third data received after switching is stored in a second buffer currently in a write state, so as to realize real-time data reading and writing of the on-chip logic analyzer.

2. The real-time data reading and writing method of the on-chip logic analyzer according to claim 1, characterized in that: The trigger unit is provided with a plurality of trigger modes for the ping-pong buffer; the plurality of trigger modes include: a front trigger mode, a middle trigger mode, and a rear trigger mode; The data caching method of the ping-pong buffer in the front trigger mode is: taking the first target data bit before the mode mask in the input data as the first data; The data caching method of the ping-pong buffer in the medium trigger mode is: taking the second target data bit from before the mode mask to after the mode mask in the input data as the first data; The data caching method of the ping-pong buffer in the post-trigger mode is: three target data bits after the mode mask in the input data are used as the first data.

3. The real-time data reading and writing method of the on-chip logic analyzer according to claim 2, characterized in that: The mode mask is used to indicate the data flag bit corresponding to the trigger event; the trigger event is a key event that triggers data jump and needs to be monitored in the data analysis process performed by the on-chip logic analyzer; The mode mask is dynamically configured based on a data transition form, and the data transition form includes at least one of a data change value, a data change trend, a data change amplitude, a data timing, and a data repetition number.

4. The real-time data reading and writing method of the on-chip logic analyzer according to claim 3, characterized in that: Before receiving the first data collected in real time by the trigger unit, the method further includes: Collecting the input data in real time through the trigger unit; Using a valid digit mask to mark the corresponding data bits to be analyzed in the input data; Comparing whether the data bit to be analyzed matches the pattern mask to obtain a matching result of the data bit to be analyzed; According to the matching result and / or the data cache mode of the trigger unit, the data storage process of the ping-pong buffer is controlled by the trigger unit, and the first data in the input data that meets the cache requirement is sent to the ping-pong buffer.

5. The real-time data reading and writing method of the on-chip logic analyzer according to claim 1, characterized in that: Before receiving the first data collected in real time by the trigger unit, the method further includes: Setting the first buffer to a write state and the second buffer to a read state; According to the real-time data transmission conditions and real-time debugging requirements of the on-chip logic analyzer, the start timing of the first buffer and the second buffer are dynamically configured so that the first buffer and the second buffer cooperate to realize real-time reading and writing of the trigger unit.

6. The real-time data reading and writing method of the on-chip logic analyzer according to claim 5, characterized in that: The method of dynamically configuring the start timing of the first buffer and the second buffer according to the real-time data transmission condition and the real-time debugging requirement of the on-chip logic analyzer includes: Determine the storage space capacity and storage space structure of the first buffer and the second buffer respectively; Determine the read and write time difference between the first buffer and the second buffer according to the real-time data transmission condition, the real-time debugging requirement, and the storage space capacity and storage space structure of the first buffer and the second buffer respectively; The start timings of the first buffer and the second buffer are configured based on the read-write time difference.

7. The real-time data reading and writing method of the on-chip logic analyzer according to claim 6, characterized in that: The start time of the first buffer zone in the write state is earlier than the start time of the second buffer zone in the read state.

8. The real-time data reading and writing method of the on-chip logic analyzer according to claim 6, characterized in that: After storing the first data in the first buffer currently in the write state and analyzing and transmitting the second data through the second buffer currently in the read state, the method further includes: Collecting the read and write status data of the first buffer and the second buffer in real time; the read and write status data at least includes: the read and write rate, data transmission rate, and transmission delay of the first buffer and the second buffer respectively; Inputting the read / write status data into a buffer prediction model to predict the read / write status prediction values ​​of the first buffer and the second buffer within a preset time period in the future; Determining a predicted read / write time difference between the first buffer and the second buffer based on the read / write state prediction value; Based on the predicted read-write time difference, the state switching timing between the first buffer and the second buffer is optimized.

9. The real-time data reading and writing method of the on-chip logic analyzer according to claim 1, characterized in that: The ping-pong buffer is configured as a multi-level first-in-first-out storage array FIFO; The FIFO depth and number of layers corresponding to the first buffer and the second buffer in the ping-pong buffer are dynamically configured based on the real-time reading and writing speed of the ping-pong buffer.

10. The real-time data reading and writing method of the on-chip logic analyzer according to claim 9, characterized in that: The storage space capacity occupied by the first buffer and the second buffer in the ping-pong buffer is proportional to the corresponding real-time data transmission rate in the current state.

11. An on-chip logic analyzer, characterized in that: The on-chip logic analyzer at least comprises: a trigger unit, a ping-pong buffer, wherein the ping-pong buffer is provided with a first buffer and a second buffer; The ping-pong buffer is configured to receive the first data collected in real time by the trigger unit; store the first data in the first buffer currently in the write state, and analyze and transmit the second data through the second buffer currently in the read state; the first data and the second data are obtained by continuous collection by the trigger unit; analyze and transmit the first data through the first buffer switched to the read state, and store the third data received after the switching in the second buffer currently in the write state, so as to realize the real-time data reading and writing of the on-chip logic analyzer; The trigger unit is configured to detect the remaining storage space in the first buffer; if the remaining storage space in the first buffer is lower than the storage capacity threshold, the first buffer is switched from the write state to the read state, and the second buffer is switched from the read state to the write state; the storage capacity threshold is dynamically configured based on the data processing requirements of the on-chip logic analyzer.

Images