Superconducting integrated circuit and electronic product

Abstract

The invention provides a superconducting integrated circuit and an electronic product. The superconducting integrated circuit comprises a logic chip, a substrate and a bump structure, a superconducting logic circuit is arranged on the logic chip, and a bias network is arranged on the upper surface of the substrate; wherein the logic chip and the bump structure are arranged on the upper surface of the substrate, and a bias current feeding point on the upper surface of the superconducting logic circuit is electrically connected with the bias network through the bump structure. According to the invention, adverse effects on circuit performance caused by on-chip collection of current are avoided, and the stability of the circuit is improved; the problems that in the prior art, an inductor layout is large in occupied area, and large-scale circuit wiring is difficult are solved.

Description

Technical Field

[0001] The present invention relates to the field of superconducting technology, and in particular to a superconducting integrated circuit and an electronic product. Background Art

[0002] Rapid Single Flux Quantum (RSFQ) is a circuit technology based on superconducting materials. It has attracted much attention for its extremely high operating frequency, low power consumption and strong anti-interference ability. Especially in the post-Moore era, it is considered to be one of the most promising new computing technologies. RSFQ circuit is the earliest SFQ method. Compared with traditional CMOS devices, RSFQ circuit can achieve extremely low signal delay and stability required for low-temperature working environment in superconducting environment, so it shows significant advantages in high-performance computing and low-temperature quantum technology. In the current design of large-scale RSFQ circuits, bias current is usually connected to the logic circuit through the bias line on the chip. However, all devices in the RSFQ circuit are laid on the same substrate. It is difficult to completely avoid the current concentration phenomenon in the connection area between the bias line and the logic circuit in design and layout. The current tends to gather in these connection areas. This concentrated current will generate a magnetic field, which will have an adverse effect on the performance of the entire circuit.

[0003] Energy-efficient Single Flux Quantum (ERSFQ) is a low-power version of the RSFQ circuit. It uses a superconducting inductor and an overdamped Josephson junction in series to form an L-JJ bias structure to replace the bias resistor in the bias network of the RSFQ circuit, eliminating a large amount of static power consumption generated by the resistor in the bias network, reducing the overall power consumption by one to two orders of magnitude. However, the L-JJ bias network structure requires a superconducting inductor with a large inductance value to suppress the current fluctuation in the bias network. A large superconducting inductor will not only occupy a large layout area under the existing process and reduce the circuit integration, but also cause circuit wiring difficulties, leading to current aggregation problems. At present, some research on the placement of superconducting inductors is mainly focused on developing a new multi-layer process to increase the number of process layers and reduce the impact of inductors on circuit wiring and integration. However, this new multi-layer process is difficult to develop, the chip preparation cycle is long, and it is difficult to ignore the self-inductance and mutual inductance of the inductor.

[0004] Therefore, how to overcome the problems of large layout area, current concentration, high process difficulty, and inductance effect that cannot be ignored in superconducting integrated circuits has become one of the urgent issues to be solved by technical personnel in this field.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a superconducting integrated circuit and an electronic product to solve the problems of large layout area, current concentration and inductance affecting circuit performance in the prior art superconducting integrated circuit.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a superconducting integrated circuit, which at least comprises:

[0008] A logic chip, a substrate and a bump structure; a superconducting logic circuit is arranged on the logic chip, and a bias network is arranged on the upper surface of the substrate;

[0009] The logic chip and the bump structure are arranged on the upper surface of the substrate, and the bias current feeding point on the upper surface of the superconducting logic circuit is electrically connected to the bias network through the bump structure.

[0010] Optionally, when the superconducting integrated circuit is a fast single flux quantum circuit, the superconducting logic circuit includes N logic units, and the bias current feeding point of each logic unit is connected to a corresponding bump structure; N is a natural number greater than or equal to 1.

[0011] More optionally, the bias network includes M bias resistors, where M is a natural number greater than or equal to 1 and less than or equal to N; when M is greater than or equal to 2, one end of each bias resistor is connected to the bias voltage, and the other end is connected to the corresponding bump structure.

[0012] More optionally, the resistance of the bias resistor is K times the resistance of the corresponding logic unit, where K is a number greater than 0 and less than 1.

[0013] Optionally, when the superconducting integrated circuit is a high-efficiency single-flux quantum circuit, the superconducting logic circuit includes P logic units, and the logic chip is further provided with P bias Josephson junctions and Q feeding Josephson transmission lines, where P and Q are both natural numbers greater than or equal to 1;

[0014] The bias current feed point of the logic unit is connected to the bump structure via a corresponding bias Josephson junction;

[0015] The bias current feeding point of the feeding Josephson transmission line is connected to the corresponding bump structure.

[0016] More optionally, the bias network includes S superconducting inductors, where S is a natural number greater than or equal to 1 and less than or equal to P; when S is greater than or equal to 2, one end of each superconducting inductor is connected to the bias voltage, and the other end is connected to the corresponding bump structure.

[0017] More optionally, the logic chip is further provided with P shunt resistors, each shunt resistor being connected in parallel at two ends of a corresponding biased Josephson junction, so that the damping of the biased Josephson junction is less than 1.

[0018] More optionally, the ratio of the bias current of the feeding Josephson transmission line to the bias current of the superconducting logic circuit is 1:2 to 1:1.

[0019] Optionally, a vertical projection of the logic chip on the substrate at least partially overlaps with a region where the bias network is located.

[0020] More optionally, the height of the bump structure is not less than half of the height of the logic chip.

[0021] To achieve the above-mentioned object and other related objects, the present invention further provides an electronic product, characterized in that the electronic product at least includes: the above-mentioned superconducting integrated circuit.

[0022] As described above, the superconducting integrated circuit and electronic product of the present invention have the following beneficial effects:

[0023] 1. The superconducting integrated circuit and electronic product of the present invention stack the logic layer and bias layer of the superconducting integrated circuit, thereby realizing the vertical expansion of the chip. When designing large-scale superconducting integrated circuits, the use of the superconducting integrated circuit and electronic product of the present invention can overcome the problem of strong magnetic fields generated by on-chip current collection, reduce the interference of the magnetic field on the circuit, and improve the stability of the circuit.

[0024] 2. When the present invention designs a large-scale ERSFQ circuit, it can solve the problem of large layout area occupied and overall wiring difficulty caused by large inductors, so that the existing process can be directly used to design and tape out large-scale ERSFQ circuits, avoiding the problems of long development cycle and high process difficulty caused by the development of new multi-layer processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a schematic structural diagram of a superconducting integrated circuit of the present invention.

[0026] Figure 2 Another schematic diagram of the structure of the superconducting integrated circuit of the present invention is shown.

[0027] Figure 3 Shown is a schematic structural diagram of the superconducting logic circuit of the present invention.

[0028] Figure 4 Shown is another structural schematic diagram of the superconducting integrated circuit of the present invention.

[0029] Figure 5 Shown is another structural schematic diagram of the superconducting integrated circuit of the present invention.

[0030] Figure 6 Shown is a structural schematic diagram of the logic chip of the present invention.

[0031] Figure 7 Shown is the IV characteristic curve of an overdamped junction.

[0032] Figure 8 Shown is the IV characteristic curve of an underdamped junction.

[0033] Fig. 9 Shown is a schematic structural diagram of the superconducting logic circuit and the biased Josephson junction of the present invention.

[0034] Fig.10 Shown is a schematic structural diagram of the fed Josephson transmission line of the present invention.

[0035] Fig.11 Shown is a schematic structural diagram of the substrate of the present invention.

[0036] Component number description

[0037] 1 Superconducting integrated circuits

[0038] 11 Logic Chip

[0039] 111 Superconducting Logic Circuit

[0040] 112 Biased Josephson Junction

[0041] 113-fed Josephson transmission line

[0042] 12 substrate

[0043] 121 Bias Network

[0044] 13 Bump structure DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] See also Figures 1 to 11It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] In order to solve the above problems, the present invention provides a superconducting integrated circuit, which includes: a logic chip, a substrate and a bump structure; a superconducting logic circuit is arranged on the logic chip, and a bias network is arranged on the upper surface of the substrate; wherein the logic chip and the bump structure are arranged on the upper surface of the substrate, and the bias current feeding point on the upper surface of the superconducting logic circuit is electrically connected to the bias network through the bump structure; thereby, the superconducting logic circuit and the bias network are arranged on different dielectric layers to achieve the purpose of avoiding current concentration, and when there is a large inductance in the bias network, the influence of the self-inductance and mutual inductance of the inductance on the logic circuit can also be overcome.

[0048] Furthermore, the vertical projection of the logic chip on the substrate at least partially overlaps with the area where the bias network is located, thereby reducing the layout area. The superconducting integrated circuit of the present invention is specifically described below.

[0049] Embodiment 1

[0050] like Figure 1 and Figure 2 As shown, this embodiment provides a superconducting integrated circuit 1, which includes: a logic chip 11, a substrate 12 and a bump structure 13; wherein the superconducting integrated circuit 1 is a fast single flux quantum circuit (RSFQ).

[0051] like Figure 1 and Figure 2 As shown, a superconducting logic circuit 111 is provided on the logic chip 11 .

[0052] Specifically, in this embodiment, the superconducting logic circuit 111 includes N logic units, where N is a natural number greater than or equal to 1; the bias current feeding point of the logic unit is connected to the corresponding bump structure 13, that is, the logic unit obtains the corresponding bias current from the corresponding bump structure 13. The logic unit is composed of logic gates and transmission lines; the transmission line is connected between the logic gates and is used for signal transmission between the logic gates; the logic gates include but are not limited to AND and XOR, which are not described one by one here, and more complex logic structures can be constructed through different combinations; the transmission line includes but is not limited to JTL (Josephson Junction Transmission Line) and PTL (Passive Transmission Line), which are not described one by one here, and the main function of the transmission line is to ensure that the signal can be transmitted stably and quickly in the superconducting logic circuit 111 to keep the timing of the logic operation correct.

[0053] As an example, Figure 3 As shown, the superconducting logic circuit 111 includes a series structure of three confluence buffer units, and each confluence buffer unit includes a logic gate and a transmission line, which are not described one by one here. Among them, the input terminal AI1 of the first confluence buffer unit CB1 is connected to the input signal, the input terminal BI1 is grounded, and the output terminal AO1 is connected to the input terminal AI2 of the second confluence buffer unit CB2; the input terminal BI2 of the second confluence buffer unit CB2 is grounded, and the output terminal AO2 is connected to the input terminal AI3 of the third confluence buffer unit CB3; the input terminal BI3 of the third confluence buffer unit CB3 is grounded, and the output terminal AO3 outputs the output signal. Each confluence buffer unit has a bias current feeding point IB, and the bias current feeding point IB is connected to the corresponding bump structure 13, and the corresponding bias current is obtained through the bump structure 13. Of course, in actual use, the superconducting logic circuit 111 can be a logic circuit formed by connecting any RSFQ units, not limited to this embodiment.

[0054] like Figure 1 and Figure 2 As shown, a bias network 121 is disposed on the upper surface of the substrate 12 .

[0055] Specifically, in this embodiment, the bias network 121 includes M bias resistors, where M is a natural number greater than or equal to 1 and less than or equal to N; it is used to distribute the bias current, provide accurate current support for each unit in the logic chip 11, and ensure that each unit can perform logical operations and signal processing according to the design requirements. When each logic unit in the superconducting logic circuit 111 shares the same bias current, only one bias resistor needs to be set in the bias network 121; the bias resistor generates a corresponding bias current based on the bias voltage, and the size of the bias resistor can be set as required. When the number of bias currents required in the superconducting logic circuit 111 is greater than or equal to 2, a corresponding number of bias resistors (that is, M is greater than or equal to 2) are set in the bias network 121, one end of each bias resistor is connected to the bias voltage, and the other end is respectively connected to the corresponding bump structure 13; each bias resistor has a different resistance value, and generates a corresponding bias current under the action of the bias voltage to achieve different current distribution effects.

[0056] Specifically, as another implementation method of the present invention, the resistance of each bias resistor is set to K times the resistance of the corresponding logic unit, K is a number greater than 0 and less than 1, including but not limited to 1 / 2, 1 / 3, 1 / 4; thereby realizing low-voltage electrical design (LV-RSFQ circuit); that is, by reducing the resistance of the bias resistor, the same bias current can be obtained while using a smaller bias voltage.

[0057] It should be noted that the design of the bias network 121 can be flexibly adjusted according to different types of superconducting integrated circuits to construct bias networks with various structures to meet specific requirements of different circuits, and is not limited to this embodiment.

[0058] like Figure 1 and Figure 2 As shown, bump structures 13 are disposed on substrate 12 and serve as physical and electrical connection points.

[0059] Specifically, the bump structure 13 is made of conductive material and has a certain height difference, which is used to realize the electrical connection between the superconducting logic circuit and the bias network; at the same time, the physical distance between the bias current lead of the superconducting logic circuit and the bias current lead of the bias network is increased, thereby reducing the current aggregation; and through the air layer between the bias current lead of the superconducting logic circuit and the bias current lead of the bias network, the current aggregation is further reduced (or even avoided), ensuring that the performance of the superconducting integrated circuit 1 is not affected. As an example, the height of the bump structure 13 is not less than half the height of the logic chip 11, including but not limited to being the same as the height of the logic chip 11, or higher than the logic chip 11; in actual use, the height of the bump structure 13 is set according to actual needs, and the aggregation between the bias current leads can be reduced.

[0060] In the present invention, the logic chip 11 is disposed on the upper surface of the substrate 12, and the electrical connection between the superconducting logic circuit 111 and the bias network 121 is realized through the bump structure 13. As an example, Figure 1 As shown, the logic chip 11 and the bias network 121 are respectively arranged on both sides of the bump structure 13, and the two do not overlap; the bottom of each bump structure 13 is connected to the bias network 121, and the top is connected to the superconducting logic circuit 111. As another example, Figure 2 As shown, the vertical projection of the logic chip 11 on the substrate 12 at least partially overlaps with the area where the bias network 121 is located. In this example, the logic chip 11 and the bias network 121 are arranged on the same side of the bump structure 13. Similarly, the bottom of each bump structure 13 is connected to the bias network 121, and the top is connected to the superconducting logic circuit 111. The bias current lead of the superconducting logic circuit 111 and the bias current lead of the bias network 121 are isolated by an air layer; by stacking the superconducting logic circuit 111 and the bias network 121 in the vertical direction, the layout size can be further reduced, and it will not cause great restrictions on the wiring; in actual use, each bump structure 13 can be distributed at any position outside the area where the logic chip 11 and the bias network 121 are located, for example, on the left and right sides of the area where the logic chip 11 and the bias network 121 are located, which will not be described one by one here. As another example, the logic chip 11 can be divided into multiple parts, each part is separated from each other, and different parts can be arranged at appropriate positions as needed.

[0061] Embodiment 2

[0062] like Figure 4-5 As shown, this embodiment provides a superconducting integrated circuit 1, which is different from the first embodiment in that the superconducting integrated circuit 1 is an energy-efficient single flux quantum circuit (ERSFQ).

[0063] like Figure 6 As shown, in this embodiment, the superconducting logic circuit 111 includes P logic units, and the logic units include logic gates and transmission lines, which are not described one by one here. P bias Josephson junctions 112 and Q feeding Josephson transmission lines 113 are also provided on the logic chip 11; P and Q are both natural numbers greater than or equal to 1. Among them, one end of each bias Josephson junction 1b is connected to the bias current feeding point of the corresponding logic unit 1a, and the other end is connected to the corresponding bump structure 13 (that is, the bias current feeding point of the logic unit 1a is connected to the bump structure 13 via the corresponding bias Josephson junction), which is used to regulate the current in the logic unit 1a. The bias current feeding point of the feeding Josephson transmission line 1c is connected to the corresponding bump structure 13, which is used to stabilize the voltage on the power supply bus and keep the bias current of the logic unit constant. In this embodiment, P and Q are both set to 3. In actual use, the values ​​of P and Q can be set as needed, and the values ​​of P and Q can be different.

[0064] Furthermore, the biased Josephson junction achieves current regulation through its IV characteristics (resistance changes at the critical current), such as Figure 7 The IV characteristics of an overdamped junction are shown in Figure 8 The IV characteristic of the underdamped junction is shown. When the current flowing through the biased Josephson junction is greater than the critical current value Ic, the biased Josephson junction enters the resistive state from the superconducting state. In this embodiment, the biased Josephson junction is an overdamped junction, and the damping coefficient is less than 1 to prevent the additional power dissipation caused by the hysteresis effect of the biased Josephson junction after the ERSFQ circuit is finished working. As an example, P shunt resistors are also provided on the logic chip 11, and each shunt resistor is connected in parallel at both ends of the corresponding biased Josephson junction so that the damping of the biased Josephson junction is less than 1; in actual use, any method that can adjust the damping of the biased Josephson junction to less than 1 is applicable to the present invention, and is not limited to this embodiment.

[0065] Furthermore, the ratio of the bias current of the feeding Josephson transmission line 113 to the bias current of the superconducting logic circuit 111 is set to 1:2 to 1:1, preferably 1:2.

[0066] As an example, Fig. 9 As shown, the superconducting logic circuit 111 includes a series structure of three bus buffer units, namely, a first bus buffer unit CB1, a second bus buffer unit CB2, and a third bus buffer unit CB2. For the specific structure, see the first embodiment, which will not be described one by one here; similarly, in other embodiments, the superconducting logic circuit 111 can be a logic circuit formed by connecting any ERSFQ units, not limited to this embodiment. Accordingly, three bias Josephson junctions are provided; wherein, one end of the first bias Josephson junction J1 is connected to the first bus buffer unit CB1, and the other end is connected to the corresponding bump structure 13; one end of the second bias Josephson junction J2 is connected to the second bus buffer unit CB2, and the other end is connected to the corresponding bump structure 13; one end of the third bias Josephson junction J3 is connected to the first bus buffer unit CB3, and the other end is connected to the corresponding bump structure 13. By adjusting the parameters of the bias Josephson junction and the bias network, a reasonable current distribution from the power supply bus to the feeding point can be achieved.

[0067] As an example, Fig.10As shown, the feeding Josephson transmission line includes a series structure of three two-junction delayed Josephson transmission line units, wherein the input end AI1 of the first Josephson transmission line unit JTL1 is connected to the input signal, and the output end AO1 is connected to the input end AI2 of the second Josephson transmission line unit JTL2; the output end AO2 of the second Josephson transmission line unit JTL2 is connected to the input end AI3 of the third Josephson transmission line unit JTL3; the output end AO3 of the third Josephson transmission line unit JTL3 outputs the output signal. Each Josephson transmission line unit has a bias current feeding point IB, and the bias current feeding point IB is connected to the corresponding bump structure 13, and the corresponding bias current is obtained through the bump structure 13. In actual use, the feeding Josephson transmission line can be selected according to the scale of the ERSFQ logic circuit, and the appropriate number of Josephson transmission line units are selected to form a series structure, which is not limited to this embodiment.

[0068] like Figure 4 and Figure 5 As shown, in this embodiment, the bias network 121 includes S superconducting inductors, S is a natural number greater than or equal to 1 and less than or equal to P; it is used to perform the first current distribution during the power-on process of the ERSFQ circuit (subsequent current distribution is performed by the bias Josephson junction), and the superconducting inductor and the bias Josephson structure form an L-JJ bias structure. When each unit (logic unit, feeding Josephson transmission line) in the logic chip 11 shares the same bias current, only one superconducting inductor needs to be set in the bias network 121; the superconducting inductor generates a corresponding bias current based on the bias voltage, and the size of the superconducting inductor can be set as required. When the number of bias currents required in the logic chip 11 is greater than or equal to 2, a corresponding number of superconducting inductors (that is, S is greater than or equal to 2) are set in the bias network 121, one end of each superconducting inductor is connected to the bias voltage, and the other end is respectively connected to the corresponding bump structure 13; each superconducting inductor has a different inductance, and generates a corresponding bias current under the action of the bias voltage to achieve different current distribution effects. As an example, the bump structures 13 are arranged in a row, and the superconducting inductors are arranged on the same side of the bump structures 13. As another example, Fig.11 As shown, the bump structures 13 are arranged in two rows, the superconducting inductors are divided into two groups, and the bump structures 13 in each row are alternately distributed in each group of superconducting inductors.

[0069] like Figure 4 and Figure 5 As shown, each bump structure 13 serves as a connection point between the bias network 121 and the bias current feeding point of the bias Josephson junction 112 or the feeding Josephson transmission line 113 .

[0070] In the present invention, the logic chip 11 is disposed on the upper surface of the substrate 12, and the electrical connection between the logic chip 11 and the bias network 121 is realized through the bump structure 13. As an example, Figure 4As shown, the logic chip 11 and the bias network 121 are respectively arranged on both sides of the bump structure 13; as another example, Figure 5 As shown, the vertical projection of the logic chip 11 on the substrate 12 at least partially overlaps with the area where the bias network 121 is located; see Example 1. In actual use, each bump structure 13 can be distributed at any position outside the area where the logic chip 11 and the bias network 121 are located, which will not be described one by one here. As another example, the logic chip 11 can be divided into multiple parts, and each part is separated from each other, for example, Figure 6 The superconducting logic circuit 111 and the biased Josephson junction 112 are the first part, and the feeding Josephson transmission line 113 is the second part; the bias network 121 is as shown in Fig.11 As shown, the first part of the logic chip 11 is overlapped with the corresponding group of superconducting inductors, and the second part of the logic chip 11 is overlapped with the corresponding group of superconducting inductors, so as to further reduce the layout area.

[0071] The other structures are the same as those in the first embodiment and will not be described in detail here.

[0072] It should be noted that the superconducting integrated circuit 1 of the present invention is not limited to RSFQ and ERSFQ, and is applicable to any superconducting circuit that requires biasing, and is not limited to the examples listed in this embodiment.

[0073] The present invention further provides an electronic product, which includes: the superconducting integrated circuit 1 of the present invention.

[0074] The present invention arranges the logic chip and the bias network on the substrate in layers, realizes the design of large-scale superconducting integrated circuits under the existing process, avoids the adverse effect of current collection on the chip on circuit performance during large-scale SFQ circuit design, reduces the dependence on new process development, and avoids the high cost and time investment brought about by the development of difficult processes.

[0075] In summary, the present invention provides a superconducting integrated circuit and electronic product, including: a logic chip, a substrate and a bump structure; a superconducting logic circuit is arranged on the logic chip, and a bias network is arranged on the upper surface of the substrate; wherein the logic chip and the bump structure are arranged on the upper surface of the substrate, and the bias current feeding point on the upper surface of the superconducting logic circuit is electrically connected to the bias network through the bump structure. The present invention avoids the adverse effect of the current collection on the chip on the circuit performance, improves the stability of the circuit, and solves the problem of large area occupied by the inductor layout and difficulty in large-scale circuit wiring under the prior art. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A superconducting integrated circuit, characterized in that: The superconducting integrated circuit at least comprises: A logic chip, a substrate and a bump structure; a superconducting logic circuit is arranged on the logic chip, and a bias network is arranged on the upper surface of the substrate; The logic chip and the bump structure are arranged on the upper surface of the substrate, and the bias current feeding point on the upper surface of the superconducting logic circuit is electrically connected to the bias network through the bump structure.

2. The superconducting integrated circuit according to claim 1, characterized in that: When the superconducting integrated circuit is a fast single flux quantum circuit, the superconducting logic circuit includes N logic units, and the bias current feeding point of each logic unit is connected to the corresponding bump structure; N is a natural number greater than or equal to 1.

3. The superconducting integrated circuit according to claim 2, characterized in that: The bias network includes M bias resistors, where M is a natural number greater than or equal to 1 and less than or equal to N; when M is greater than or equal to 2, one end of each bias resistor is connected to a bias voltage, and the other end is respectively connected to a corresponding bump structure.

4. The superconducting integrated circuit according to claim 3, characterized in that: The resistance of the bias resistor is K times the resistance of the corresponding logic unit, where K is a number greater than 0 and less than 1.

5. The superconducting integrated circuit according to claim 1, characterized in that: When the superconducting integrated circuit is a high-efficiency single-flux quantum circuit, the superconducting logic circuit includes P logic units, and the logic chip is further provided with P bias Josephson junctions and Q feeding Josephson transmission lines, where P and Q are both natural numbers greater than or equal to 1; The bias current feed point of the logic unit is connected to the bump structure via a corresponding bias Josephson junction; The bias current feeding point of the feeding Josephson transmission line is connected to the corresponding bump structure.

6. The superconducting integrated circuit according to claim 5, characterized in that: The bias network includes S superconducting inductors, where S is a natural number greater than or equal to 1 and less than or equal to P; when S is greater than or equal to 2, one end of each superconducting inductor is connected to a bias voltage, and the other end is connected to a corresponding bump structure.

7. The superconducting integrated circuit according to claim 5 or 6, characterized in that: P shunt resistors are also arranged on the logic chip, and each shunt resistor is connected in parallel to two ends of a corresponding biased Josephson junction, so that the damping of the biased Josephson junction is less than 1.

8. The superconducting integrated circuit according to claim 5 or 6, characterized in that: The ratio of the bias current of the feeding Josephson transmission line to the bias current of the superconducting logic circuit is 1:2 to 1:

1.

9. The superconducting integrated circuit according to claim 1, characterized in that: A vertical projection of the logic chip on the substrate at least partially overlaps with a region where the bias network is located.

10. The superconducting integrated circuit according to claim 1 or 9, characterized in that: The height of the bump structure is not less than half of the height of the logic chip.

11. An electronic product, characterized in that: The electronic product at least comprises: a superconducting integrated circuit as described in any one of claims 1-10.

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