Control circuit, display screen and method for reducing electromagnetic interference noise of TFT LCD (Thin Film Transistor Liquid Crystal Display) display screen drive

Abstract

The invention provides a control circuit applied to TFT LCD display screen drive to reduce EM noise, which at least comprises a polarity exchange circuit (2), an EM noise control module (1) and N columns of first channel loads 31, second channel loads 32, S3... SN, and the adjacent first channel loads (31) and second channel loads (32) are used as a group of basic working units; a first NMOS switch tube (CSP1) and a second NMOS switch tube (CSP2) are respectively grounded at the positions of intermediate nodes EX1P and EX2P of the polarity exchange circuit (2), and grid electrodes of all positive polarity channel NMOS discharge tubes in N columns of first channel loads 31, second channel loads 32, S3... SN are connected together; a first PMOS switch tube (CSN1) and a second PMOS switch tube (CSN2) are respectively grounded at positions of intermediate nodes EXN1 and EXN2 of the polarity exchange circuit (2), and grid electrodes of all negative polarity channel PMOS discharge tubes in N columns of first channel loads 31, second channel loads 32, S3... SN are connected together. According to the invention, soft discharge and hard discharge are well fused to reach the optimal level.

Description

Technical Field

[0001] The present invention belongs to the field of chips, and specifically, relates to display driver chips, especially the field of TFT_LCD chips, and in particular to chip control applied to TFT_LCD display screens, and in particular to a control circuit for reducing electromagnetic interference (EMI) noise during the driving process of a TFT_LCD display screen and a corresponding control method for reducing electromagnetic interference (EMI) noise. Background Art

[0002] At present, in the process of TFT_LCD screen display driving, in order to avoid the problem of polarity aging of liquid crystal molecules due to maintaining the same flip angle for a long time, it is necessary to periodically exchange the voltage polarity on the liquid crystal molecules with positive and negative polarities, that is, the driving source (source) changes the direction of the electric field on each pixel through polarity exchange control, so that the liquid crystal molecules periodically change the flip direction and angle. However, in actual driving display, in order to reduce driving power consumption and solve the problem of device withstand voltage, before the pixel point performs polarity exchange, it is generally necessary to discharge the voltage on the channel load (channel) to 0V to the ground, and then drive the channel load (channel) to the grayscale voltage with opposite polarity by the driving buffer (source buffer). However, due to the large parasitic capacitance on the channel load (channel), a large discharge peak current will be generated during the discharge of the channel load (channel) to the ground, and a large electromagnetic interference noise (EMI) will be generated on the display screen, becoming the main source of electromagnetic interference (EMI) noise in TFT_LCD display driving.

[0003] At present, there are two main ways to discharge the channel load:

[0004] (1) Hard discharge of the switch tube: A MOS tube that discharges to ground is connected to the MOS tube path with the source polarity exchanged. Sometimes a current limiting resistor is connected in series with the discharge MOS tube to limit the current. When the channel load needs to discharge to ground, the MOS tube that discharges to ground of the channel load is directly turned on to achieve the discharge of the channel load to ground.

[0005] (2) Switch tube maximum current limiting discharge: Based on the hard discharge of the switch tube, the maximum value of the channel load discharge current is limited. The implementation method is that when the channel load is discharging, the start-up gate voltage of the discharge MOS tube is clamped to a voltage far lower than the power supply. At this time, the MOS is equivalent to a linear resistor with a large resistance. When the channel load is discharging, the maximum discharge current flowing through the discharge tube is limited to below the set current value.

[0006] There are many defects in the existing technology, such as:

[0007] (1) Hard discharge of the switch tube: The discharge speed of this discharge method to the ground is very fast, but the discharge current peak will be very large. At the moment when the discharge MOS tube is turned on, the voltage on the channel load is at the maximum voltage state, and the conduction impedance of the discharge MOS tube is at the minimum state. When the discharge tube is turned on, a large current peak will be generated. Specifically, when the positive and negative channel discharge tubes are turned on, the voltage on the positive channel load will generate a positive current from the channel load to the ground, and the voltage on the negative channel load will generate a negative current from the channel load to the ground. Due to the asymmetry of the absolute value of the voltage on the positive and negative channel loads, the different types of positive and negative channel load discharge tubes, and the differences in the control circuits of the positive and negative channel load discharge tubes themselves, it is very easy to cause the discharge peak currents of the positive and negative channel loads to be not only large, but also easy to misalign in time and cannot offset each other, thereby generating a large electromagnetic interference (EMI) noise.

[0008] (2) Maximum current limiting discharge: This solution is an improvement and optimization of the hard discharge of the switch tube. Its biggest feature is that it limits the discharge peak current of the positive and negative channel loads (channels). In the discharge from the channel to the ground, the discharge peak current is limited to a lower level, and the currents of the positive and negative channel loads (channels) offset each other, which can reduce the electromagnetic interference (EMI) noise to a certain extent. However, this solution has the disadvantages of slow discharge speed and long discharge time, and the electromagnetic interference noise (EMI) is not ideal.

[0009] In the prior art, there has always been a need to better solve the impact caused by electromagnetic interference (EMI) noise, but there is no better and more efficient technical solution. Summary of the invention

[0010] In view of the technical defects existing in the prior art, the purpose of the present invention is to provide a control circuit for reducing EMI noise in a TFT_LCD display screen drive, which is used to reduce the EMI noise of the display screen drive in the TFT_LCD display screen, and is characterized in that it at least includes a polarity exchange circuit 2, an EMI noise control module 1, and N columns of first channel loads 31, second channel loads 32, S3...SN, and the adjacent first channel loads 31 and second channel loads 32 are used as a group of basic working units; wherein the polarity exchange circuit 2 provides a positive voltage drive for the first channel load 31 through a positive polarity drive buffer, and provides a negative voltage drive for the second channel load 32 through the control of a negative polarity drive buffer; wherein the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 are connected to the ground at the intermediate nodes EX1_P and EX2_P of the polarity exchange circuit 2, respectively. , used for positive polarity channel load to discharge to ground, and the gates of all positive polarity channel NMOS discharge tubes in the N columns of first channel load 31, second channel load 32, S3...SN are connected together; the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 are connected to the ground at the intermediate nodes EX_N1 and EX_N2 of the polarity exchange circuit 2, respectively, for negative polarity channel load to discharge to ground, and the gates of all negative polarity channel PMOS discharge tubes in the N columns of first channel load 31, second channel load 32, S3...SN are connected together; wherein, the S3...SN represents channel load. Specifically, those skilled in the art understand that the S3...SN represents a channel load that is the same or similar to the first channel load 31 and the second channel load 32, for example, S3 is the same as the first channel load 31, S4 is the same as the second channel load 32, and so on.

[0011] Preferably, the EMI noise control module 1 at least includes a first EMI noise control submodule, a first EMI noise control submodule EMI_P, and a second EMI control submodule EMI_N. The output end OUTP_EM I of the first EMI noise control submodule EMI_P connects the gates of the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 together for control, and the output end OUTN_EM I of the second EMI control submodule EMI_N connects the gates of the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 together for control.

[0012] Preferably, the first EM I noise control submodule first EM I noise control submodule EM I_P at least includes a current mirror current replication circuit, an output terminal voltage clamping circuit, and an output current modulation circuit, wherein the output terminal voltage clamping circuit is used to limit the minimum voltage value of the output terminal OUTP_EM I so that it is not lower than the voltage clamping value; the output current modulation circuit is used to adjust the size of the output current of the output terminal so that the output current is controlled to slowly charge and discharge the gate of the discharge tube.

[0013] Preferably, the current mirror current replication circuit at least includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, and a fourth MOS tube M4. The gate and drain of the first MOS tube M1 are connected, and the gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2. The second MOS tube M2 replicates the current of the first MOS tube M1. The drain of the second MOS tube M2 is connected to the drain of the third MOS tube M3. The gate and drain of the third MOS tube M3 are connected. The gate of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4. The fourth MOS tube M4 replicates the current of the third MOS tube M3. The output terminal voltage clamp circuit at least includes a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, and an eighth MOS tube M8. The gate and drain of the fifth MOS tube M5 are connected, the gate and drain of the sixth MOS tube M6 are connected, and the drain of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6. The drain of the sixth MOS tube M6 is connected to the fourth MOS tube M4. The drain voltage of the sixth MOS tube M6 is about two threshold voltages higher than GND. Then, the gate of the eighth MOS tube M8 is connected to the drain of the sixth MOS tube M6. The source of the eighth MOS tube M8 is connected to the output terminal OUTP_EM I is connected, then the OUTP_EM I voltage is clamped at a threshold voltage approximately higher than GND; the output current modulation circuit at least includes a third MOS tube M3, a ninth MOS tube M9, and a tenth MOS tube M10, the gate of the tenth MOS tube M10 is connected to the drain of the ninth MOS tube M9, the source of the ninth MOS tube M9 is connected to the gate of the third MOS tube M3, and by controlling the opening and closing of the ninth MOS tube M9, the tenth MOS tube M10 copies the current of the third MOS tube M3 according to the first tube size ratio.

[0014] Preferably, the tube size ratio of the tenth MOS tube M10 to the third MOS tube is N1:1, which is expressed as a first tube size ratio, and the value range of N1 is between 1 and 30.

[0015] Preferably, the second EMI noise control submodule EMI_N at least includes a current mirror current replication circuit, an output terminal voltage clamping circuit, and an output current modulation circuit, wherein the output terminal voltage clamping circuit is used to limit the maximum voltage of the output terminal OUTN_EMI so that it is not higher than the voltage clamping value, and the output current modulation circuit is used to adjust the size of the output current of the output terminal so that the output current is controlled to slowly charge and discharge the gate of the discharge tube.

[0016] Preferably, the current mirror current replication circuit at least includes a fourteenth MOS tube M14 and a fifteenth MOS tube M15, wherein the gate of the fourteenth MOS tube M14 is connected to the drain, and the gate of the fifteenth MOS tube M15 is connected to the gate of the fourteenth MOS tube M14, and the fifteenth MOS tube M15 replicates the current of the fourteenth MOS tube M14; the output end voltage clamping circuit at least includes a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, and a twentieth MOS tube M20. , by connecting the gate and drain of the seventeenth MOS tube M17, the gate and drain of the eighteenth MOS tube M18, the gate and drain of the nineteenth MOS tube M19, the source of the seventeenth MOS tube M17 and the positive power supply voltage VDDS, the drain voltage of the nineteenth MOS tube M19 is about three threshold voltages lower than the positive power supply voltage, and then connecting the gate of the twenty-first MOS tube M21 and the drain of the nineteenth MOS tube M19, the source of the twenty-first MOS tube M21 and the output terminal OUTN_EM I is connected, and the OUTN_EM I voltage is clamped at about two threshold voltages lower than the positive power supply voltage; the output current modulation circuit at least includes a fourteenth MOS tube M14, a twenty-second MOS tube M22, and a twenty-sixth MOS tube M26, the gate of the twenty-sixth MOS tube M26 is connected to the drain of the twenty-second MOS tube M22, the gate of the fourteenth MOS tube M14 is connected to the source of the twenty-second MOS tube M22, and by controlling the opening and closing of the twenty-second MOS tube M22, the twenty-sixth MOS tube M26 replicates the current of the fourteenth MOS tube M14 according to the second tube size ratio.

[0017] Preferably, the tube size ratio of the twenty-sixth MOS tube M26 to the fourteenth MOS tube M14 is N2:1, which is expressed as a second tube size ratio, and the value range of N2 is between 1 and 30.

[0018] According to another aspect of the present invention, there is provided a novel TFT_LCD display screen for reducing EMI noise, characterized in that it comprises the above-mentioned control circuit.

[0019] According to another aspect of the present invention, a control method for a novel TFT-LCD display screen for reducing EMI noise is provided, which is used to reduce the EMI noise of the display screen driving in the above TFT-LCD display screen, and is characterized in that it comprises at least the following steps:

[0020] a. First, when the channel load enters the discharge stage, the lower clamp circuit enables the discharge tube of the first channel load 31 to quickly enter the critical open state, and the upper clamp circuit enables the discharge tube of the second channel load 32 to quickly enter the critical open state;

[0021] b. The first EM I noise control submodule EM I_P and the second EM I control submodule EM I_N simultaneously output a small current whose magnitude is modulated respectively, so as to slowly charge and discharge the discharge tube gates of the positive polarity channel load and the negative polarity channel load, and the discharge currents of the first channel load 31 and the second channel load 32 change from small to large, and the two discharge currents have opposite polarities and are equal in magnitude;

[0022] c. The discharge current of the first channel load 31 and the second channel load 32 changes from small to large. When the discharge current reaches the maximum value, the soft discharge stage is completed. At this time, the soft discharge function is turned off, and the hard discharge switches M11 and M24 are respectively and simultaneously turned on in the first EM I noise control submodule EM I_P and the second EM I control submodule EM I_N, so that the discharge tube gates of the first channel load 31 and the second channel load 32 are quickly pulled to the power supply voltage, and the positive and negative channel load voltages are quickly discharged to GND.

[0023] Preferably, after the positive and negative channel load voltages are discharged to GND, the discharge path of the first channel load 31 to the ground is turned off, and the first channel load 31 is positively pre-charged, while the discharge path of the second channel load 32 to the ground remains open until the pre-charging of the first channel load 31 is completed and then turned off.

[0024] Preferably, the positive polarity drive buffer and the negative polarity drive buffer enable OP_EN state is high, PS1, PS3 and NS1, NS3 are high, PS2, PS4 and NS2, NS4 are low, and CS_GND1 P, CS_GND2P and CS_GND1 N, CS_GND2N are all low; the positive polarity drive buffer and the negative polarity drive buffer drive the first channel load 31 through PS1 and PS3 to display a positive voltage, and the negative polarity drive buffer drives the second channel load 32 through NS1 and NS3 to display a negative voltage. After a row of drive display is completed, the positive polarity drive buffer and the negative polarity drive buffer enable EN change from high to low, the positive polarity drive buffer and the negative polarity drive buffer stop working, and the positive polarity drive buffer output terminal OUT_P and the negative polarity drive buffer output terminal OUT_N are in a suspended state. For this step, you can refer to Figure 1 to be realized.

[0025] Preferably, after completing the driving of the first channel load 31 and the second channel load 32, the first NMOS switch tube CSP1, the second NMOS switch tube CSP2 and the first PMOS switch tube CSN1, the second PMOS switch tube CSN2 are slowly opened under the control of the EM I control circuit to perform controlled discharge to the ground for the first channel load 31 and the second channel load 32; for the positive polarity first channel load 31, the first EM I noise control submodule EM I_P circuit input signal CS_GND1 P changes from a low level to a high level, and CS_GND2P remains at a low level unchanged, at this time M7 and M9 are turned on, and M11, M12, and M13 are turned off, M5, M6, and M8 clamp the output OUTP_EM I voltage, and M8 quickly pulls up the EM I_OUP voltage by an NMOS threshold voltage Vthn, so that the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 are weakly opened, and at the same time M1 and M2, M3 and M10 form a current mirror structure, and OUTP_EM I is controlled by M10. I continuously injects a modulated small current ip, so that the gate voltages of the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 slowly increase, the voltage of the first channel load 31 slowly decreases, and the discharge current slowly increases from small to large.

[0026] Preferably, for the second channel load 32, the second EM I control submodule EM I_N circuit input signal CS_GND1 N changes from a low level to a high level, and CS_GND2N remains at a low level. At this time, M16, M20, and M22 are turned on, and M23, M24, and M25 are turned off. M17, M18, and M19 clamp the output OUTN_EM I. M21 quickly pulls down the EM I_OUN voltage by a PMOS threshold voltage Vthp, so that the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 are weakly turned on. At the same time, M14 and M15, M14 and M26 form a current mirror structure, and a small current in with a modulated size is continuously drawn from OUTN_EM I through M26, so that the gate voltages of the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 slowly decrease, the voltage of the second channel load 32 slowly increases, and the discharge current slowly increases from small to large.

[0027] Preferably, as the gate voltages of the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 slowly increase, and the gate voltages of the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 slowly decrease, the positive polarity first channel load 31 injects a positive current ip to the ground, and the negative polarity second channel load 32 injects a negative current in to the ground, and the currents ip and in slowly change from small to large and in opposite directions, and the EMI noises generated by the two positive and negative polarity first channel loads 31 and the second channel loads 32 cancel each other out; as the channel loads slowly discharge, the voltage of the positive polarity channel S1 slowly decreases and approaches GND, and the voltage of the second channel load 32 slowly increases and approaches GND, and the discharge currents ip and in gradually increase. By adjusting the sizes of N1 and N2, the discharge currents ip and in reach the maximum current peaks at the same time, so as to achieve the maximum cancellation of the channel load discharge current EMI noise.

[0028] Preferably, after the discharge currents ip and in of the first channel load 31 and the second channel load 32 reach the maximum value at the same time, ip and in stop increasing and start to decrease; at this time, in the first EM I noise control submodule EM I_P module, the control signal CS_GND1P changes from a high level to a low level, and at the same time, CS_GND2P changes from a low level to a high level, and in the first EM I noise control submodule EM I_P module, M7, M9, and M11 are turned off, and M12 is turned on, and the gate of the M10 tube is pulled down to AGND, so that the M10 tube is fully turned on to pull the OUTP_EM I voltage up to AVDD, and the NMOS discharge tube, i.e., the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2, are fully turned on to discharge to the ground with maximum capacity, and the voltage of the first channel load 31 is quickly pulled to GND, completing the discharge function of the first channel load 31; in the second EM I control submodule EM I_N, the control signal CS_GND1 N changes from a high level to a low level, and at the same time CS_GND2N changes from a low level to a high level. In the second EM I control submodule EM I_N, M20, M22, and M23 are turned off, and M24 is turned on. The gate of the M26 tube is pulled down to the VDDS voltage, so that the M26 tube is fully turned on to pull the OUTN_EM I voltage down to AVCL. The first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 are fully turned on to discharge to the ground with maximum capacity, and the voltage of the second channel load 32 is quickly pulled to GND, completing the discharge function of the second channel load 32.

[0029] Preferably, after the voltage of the first channel load 31 and the second channel load 32 is discharged to GND, the control signal CS_GND2P changes from a high level to a low level, and the ground discharge NMOS tube, i.e., the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2, is turned off; then the polarity exchange circuits PS2 and PS4 are controlled to change from a low level to a high level to be turned on, and PS1 and PS3 are controlled to change from a high level to a low level to be turned off, so as to select a negative polarity drive channel for the first channel load 31, and the polarity exchange circuits NS2 and NS4 are controlled to change from a low level to a high level to be turned on, and NS1 and NS3 are controlled to change from a high level to a low level to be turned off, so as to select a positive polarity drive channel for the second channel load 32, and the process is completed. The polarity of the channel load is exchanged; thereafter, the positive polarity second channel load 32 is precharged to the VCI voltage. After completing the precharging function, the control signal CS_GND2N changes from a high level to a low level, and the ground discharge PMOS tube, namely the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 are turned off, and the enable OP_EN of the positive polarity drive buffer and the negative polarity drive buffer changes from a low level to a high level. The positive polarity drive buffer drives the second channel load 32 to display a positive voltage through PS2 and PS4, and the negative polarity drive buffer drives the first channel load 31 to display a negative voltage through NS2 and NS4, and enters the drive display of the next line cycle.

[0030] This patent aims at the traditional channel load (channel) to ground hard switch discharge mode, which has the disadvantages of large discharge peak current, poor mutual offset between positive and negative channel load (channel) discharge current, and poor compatibility between discharge speed and electromagnetic interference (EMI) noise. It invents a channel load (channel) to ground soft discharge solution with slowly changing current limiting resistor and dynamically controllable discharge current, which integrates soft discharge and hard discharge well. It can not only reduce electromagnetic interference (EMI) noise well, and achieve a balance between discharge speed and electromagnetic interference (EMI) noise, but also can be flexibly adjusted according to different application requirements to achieve the best level. This technical solution is efficient, low in cost compared with the existing technology, easy to apply, and easy to effectively promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0032] Figure 1 A circuit diagram of a control circuit for reducing EMI noise in a TFT_LCD display screen drive according to a specific embodiment of the present invention is shown;

[0033] Figure 2A circuit diagram of a first EM I noise control submodule and a first EM I noise control submodule EM I_P in a control circuit for reducing EM I noise in a TFT_LCD display screen drive according to a first embodiment of the present invention is shown;

[0034] Figure 3 A circuit diagram of a second EM I control submodule EM I_N in a control circuit for reducing EM I noise in a TFT_LCD display screen drive according to a first embodiment of the present invention is shown;

[0035] Figure 4 A schematic diagram of discharge waveforms and control signals in a control method for a novel TFT_LCD display screen for reducing EM I noise according to a first embodiment of the present invention is shown;

[0036] Figure 5 A schematic diagram showing a comparison between a current peak value and a normal discharge current peak value of a control method for a novel TFT_LCD display screen for reducing EMI noise according to a specific embodiment of the present invention; and

[0037] Figure 6 A circuit diagram of a control circuit for reducing EMI noise in a TFT_LCD display screen drive according to another specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0038] In order to better illustrate the technical solution of the present invention, the present invention is further described below in conjunction with the accompanying drawings.

[0039] refer to Figure 1 , Figure 2 , Figure 3 as well as Figure 6Those skilled in the art understand that, in a preferred embodiment, the first EM I noise control submodule EM I_P at least includes a current mirror current copy circuit composed of a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, and a fourth MOS tube M4, the gate of the first MOS tube M1 is connected to the drain, the gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, M2 copies the M1 current, the drain of the second MOS tube M2 is connected to the drain of the third MOS tube M3, the gate of the third MOS tube M3 is connected to the drain, the gate of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4, and M4 copies the M3 current; the fourth MOS tube M4, the fifth MOS tube M5, the fifth MOS tube M6, the fifth MOS tube M7, the fifth MOS tube M8, the fifth MOS tube M9, the fifth MOS tube M10, the fifth MOS tube M11, the fifth MOS tube M12, the fifth MOS tube M13, the fifth MOS tube M14, the fifth MOS tube M15, the fifth MOS tube M16, the fifth MOS tube M17, the fifth MOS tube M18, the fifth MOS tube M19, the fifth MOS tube M20, the fifth MOS tube M21, the fifth MOS tube M22, the fifth MOS tube M3 The output terminal voltage clamp circuit is composed of the MOS tube M5, the sixth MOS tube M6, and the eighth MOS tube M8. The gate and drain of the fifth MOS tube M5 are connected, the gate and drain of the sixth MOS tube M6 are connected, the drain of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6, the drain of the sixth MOS tube M6 is connected to M4, the drain voltage of the sixth MOS tube M6 is about two threshold voltages higher than GND, and then the gate of the eighth MOS tube M8 is connected to the drain of the sixth MOS tube M6, and the source of M8 is connected to the output terminal OUTP_EMI, then OUTP_EMI The I voltage is clamped at a threshold voltage approximately higher than GND; an output current modulation circuit composed of a third MOS tube M3, a ninth MOS tube M9, and a tenth MOS tube M10, and some simple logic control circuits are used to realize the control of soft discharge and hard discharge. The gate of the tenth MOS tube M10 is connected to the drain of the M9 tube, and the source of the M9 tube is connected to the gate of the third MOS tube M3. By controlling the opening and closing of M9, M10 copies the current of M3 in proportion to the size.The tube size ratio of the tenth MOS tube M10 to M3 is N1:1, the size of N1 depends on the number N of channel loads and the sizes of the discharge tubes CSN1 and CSN2, as well as the size of the parasitic capacitance on the gate wiring of the control discharge tubes CSN1 and CSN2, and the value range of N1 is between 1 and 30; the second EMI noise control submodule EMI_N at least includes a current mirror current replication circuit composed of a fourteenth MOS tube M14 and a fifteenth MOS tube M15, the gate of the fourteenth MOS tube M14 is connected to the drain, and the gate of the fifteenth MOS tube M15 is connected to the gate of the fourteenth MOS tube M14, and M15 replicates the current of M14; the output terminal voltage clamp circuit composed of the seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19, and the twentieth MOS tube M20, through the The gate of the seventeenth MOS tube M17 is connected to the drain, the gate of the eighteenth MOS tube M18 is connected to the drain, the gate of the nineteenth MOS tube M19 is connected to the drain, the source of the seventeenth MOS tube M17 is connected to the positive power supply voltage VDDS, the drain voltage of the nineteenth MOS tube M19 is about three threshold voltages lower than the positive power supply voltage, and then the gate of the twenty-first MOS tube M21 is connected to the drain of the nineteenth MOS tube M19, and the source of the twenty-first MOS tube M21 is connected to the output terminal OUTN_EMI. The OUTN_EMI voltage is clamped at about two threshold voltages lower than the positive power supply voltage; the output current modulation circuit composed of the fourteenth MOS tube M14, the twenty-second MOS tube M22, and the twenty-sixth MOS tube M26, and some simple logic control circuits are used to realize the control of soft discharge and hard discharge. The gate of the twenty-sixth MOS tube M26 is connected to the drain of the twenty-second MOS tube M22, and the gate of the fourteenth MOS tube M14 is connected to the source of the twenty-second MOS tube M22. By controlling the opening and closing of M22, M26 copies the current of M14 according to the size ratio. The tube size ratio of M26 to M14 is N2:1. The size of N2 depends on the number N of channel loads and the sizes of the discharge tubes CSP1 and CSP2, as well as the size of the parasitic capacitance on the gate wiring of the discharge tubes CSP1 and CSP2. The value range of N2 is between 1 and 30.

[0040] Furthermore, refer to Figure 1 as well as Figure 6 , which shows the circuit structure of the control circuit applied to TFT_LCD display screen driving to reduce EMI noise, namely including:

[0041] 1. Main circuit module composition:

[0042] (1) Logic control and level conversion module: The main function is to process the digital timing control signals D2A_AUX_GND, D2A_CSP_GND, and D2A_CSNAUX_GND through logic processing, and then perform level conversion, and finally generate a suitable voltage domain signal to the subsequent CTR_EMI module, where D2A_AUX_GND is the control signal for the start of soft discharge, D2A_CSP_GND is the control signal for the control of the positive channel to start hard discharge, and D2A_CSN_GND is the control signal for the control of the negative channel to start hard discharge;

[0043] (2) CTR_EM I module: It is the core circuit of this patent. There is only one module, which consists of the first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N. It directly controls the gate of all channel load (hereinafter referred to as: channa l) discharge tubes; the first EMI noise control submodule EMI_P generates a CSP_GND signal to provide a gate control voltage for all positive channel discharge tubes (NMOS), and the second EMI noise control submodule EMI_N generates a CSN_GND signal to provide a gate control voltage for all negative channel discharge tubes (PMOS). When the channa l needs to be discharged to the ground, a controllable soft discharge is performed under the slow control of CSP_GND and CSP_GND. The circuit structures of the first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N are as follows: Figure 2 and Figure 3 As shown;

[0044] (3) Polarity exchange circuit and channa l load: The polarity exchange circuit is mainly composed of polarity exchange MOS tube and ground discharge MOS tube. In order to realize soft discharge control, the connection relationship between the discharge tubes is improved. The gates of the two discharge tubes (NMOS) corresponding to the output of the positive amplifier (OP) are connected together and directly controlled by CSP_GND. The gates of the two discharge tubes (PMOS) corresponding to the output of the negative amplifier (OP) are connected together and directly controlled by CSN_GND. By directly connecting the control signal with the gate of the discharge tube MOS, the controlled discharge of all channa l by two signals is realized; the other part is the load model of the channa l, which is a typical third-order channa l RC load model.

[0045] Further, refer to Figure 1 , Figure 4 as well as Figure 5Those skilled in the art will appreciate that in the control method for a new TFT-LCD display screen for reducing EMI noise, the control process for reducing EMI noise can be completed in the following manner:

[0046] (1) Before t1: The source finishes driving the previous row, the source amplifier (OP) stops working, and starts to enter the next row porch stage;

[0047] (2) t1-t2: From t1, the next row porch phase begins. At this time, the channel needs to discharge to ground. In digital timing control, the D2A_AUX_GND signal first changes to 1, indicating that the circuit begins to enter the controlled soft discharge phase.

[0048] First, in the first EM I noise control submodule EM I_P, the gate voltage of the fifth MOS tube M5 is clamped at 2VTH by the sixth MOS tube M6 and the seventh MOS tube M7, and the CSP_GND voltage is quickly charged by M5 from 0V to near the VTH voltage, so that the discharge tube of the positive channel can quickly enter the open state; in the second EM I noise control submodule EM I_N, the gate of the 20th MOS tube M20 is clamped at the VDDS-3VTH voltage by the 21st MOS tube M21, the 22nd MOS tube M22, and the 23rd MOS tube M23 (the substrate bias effect of the negative channel discharge tube PMOS is considered here), and the CSN_GND voltage is quickly discharged by M20 from the VDDS voltage to near VDDS-1.5*VTH, so that the discharge tube of the negative channel can quickly enter the open state;

[0049] Then, in the first EM I noise control submodule EM I_P, the eighth MOS tube M8 is turned off, the ninth MOS tube M9 is turned on, the gate of the tenth MOS tube M10 is connected to the VBP voltage, the tenth MOS tube M10 and the third MOS tube M3 form a current mirror to charge CSP_GND with a constant small current, so that the CSP_GND voltage rises slowly, the conduction impedance of the positive channa l discharge tube NMOS changes slowly from large to small, and the positive channa l slowly discharges the voltage; in the second EM I noise control submodule EM I_N, the seventeenth MOS tube M17 is turned off, the sixteenth MOS tube M16 is turned on, the gate of the eighteenth MOS tube M18 is connected to the VBN voltage, the eighteenth MOS tube M18 and the fourteenth MOS tube M14 form a current mirror to discharge CSN_GND with a constant small current, so that the CSN_GND voltage drops slowly, the conduction impedance of the negative channa l discharge tube PMOS changes slowly from large to small, and the negative channa l slowly discharges the voltage;

[0050] (3) t2-t3: As the channa l discharges, the channa l voltage gradually decreases. When the positive and negative channa l voltages drop to a smaller value, the discharge currents of the positive and negative channa l (i.e., the first channel load 31 and the second channel load 32) begin to decay. In order to save discharge time, the discharge tubes of the positive and negative channa l need to be fully opened to accelerate the discharge speed of the channa l, that is, M11 in the first EM I noise control submodule EM I_P is opened to quickly pull CSP_GND to the VSP power supply voltage, the positive channa l discharge tube is fully opened to quickly discharge, the nineteenth MOS tube M19 in the second EM I noise control submodule EM I_N is opened to quickly pull CSN_GND to the VSN power supply voltage, and the negative channa l discharge tube is fully opened to quickly discharge.

[0051] (4) After t3: Entering this stage, the discharge of channa l to ground has been completed, and the voltage of positive and negative channa l is 0V. At this time, it is necessary to turn off the discharge path of positive channa l to ground, and precharge the positive channa l in the positive direction. The discharge path of negative channa l to ground remains open until the precharge of positive channa l is completed and then closed. Then the source enters the display driving stage of the next row.

[0052] refer to Figure 5 , which is the comparison result of the two modes when the positive and negative channels are discharged to the ground, S <1> , S <2> are the voltages on the positive channa l and the negative channa l respectively.

[0053] (1) When the channa l enters the discharge stage, i.e., at time t1, the voltage on the channa l is the maximum. In the traditional hard discharge mode, the discharge tube is directly turned on by the power supply voltage. At this time, the channa l voltage is the maximum and the VGS voltage of the discharge tube is the maximum (i.e., the on-resistance of the discharge tube is the minimum). The positive and negative channa l will generate very large peak currents I p (peak) and In (peak) at the moment the discharge tube is turned on. As shown in the figure, since the gate control signals of the positive and negative channa l discharge tubes are generated by circuits in different voltage domains and are affected by the inherent transmission delay difference and corner of the circuit, it is actually difficult for the positive and negative channa l discharge tubes to be turned on at the same time. This inevitably leads to the peak currents I p (peak) and In (peak) of the positive and negative channa l being misaligned in time and unable to cancel each other, thereby generating a large EMI noise. In addition, it should be considered that in the TFT_LCD display driver, the negative grayscale voltage is often significantly smaller than the positive grayscale voltage, i.e., when the channa l is discharged, I p (peak) will be more than twice as large as In (peak). In other words, the positive and negative channa l l The discharge peak current cannot be completely offset. Based on these two reasons, the EM I noise will be very large in the traditional hard discharge mode;

[0054] (2) The soft discharge mode of the present invention, when the channa l enters the discharge moment, i.e., moment t1, in order to save discharge time, the discharge tube will be quickly driven to a weakly turned-on state. At this time, the on-resistance is very large, and the discharge current changes slowly from small to large, and no channa l current discharge spike will be generated. Even if the positive and negative channa l discharge tubes are affected by the inherent transmission delay difference and corner of the circuit and cannot be turned on at the same time, since the discharge current is small and smooth, no obvious EMI noise will appear. As the channa l discharges to the ground, i.e., the t1-t2 time period, the channa l voltage gradually decreases, the discharge tube gate voltage gradually increases, the on-resistance decreases, and the discharge current gradually increases. Since the positive and negative channa l discharge currents have a very smooth change curve, the two can offset each other well, minimizing the EMI noise. When the channa l voltage is set to a certain value, the discharge current has begun to decay significantly, and the channa l The voltage on channa l also decreases significantly, indicating that the discharge current has exceeded the maximum value, and the discharge tube conduction impedance is already relatively small, that is, at time t2. At this time, in order to speed up the discharge speed, the discharge tube is fully opened through the control signal, and the positive and negative channa l begin to discharge at the maximum capacity. Since the channa l voltage is already in a relatively low voltage state, there will be no large current peak when the discharge tube is fully opened, that is, no large EM I noise will be generated.

[0055] (3) The time period t1-t2 is called the soft discharge stage, and the time period t2-t3 is called the hard discharge stage. In actual work, the two time periods can be flexibly adjusted through digital registers. If the requirements for EM I noise are high, the time period t1-t2 can be lengthened, the time period t12-t3 can be shortened, or even the time period t2-t3 can be cancelled to allow the channel to perform full soft discharge. If the requirements for discharge speed are high, the time period t1-t2 can be shortened, the time period t2-t3 can be lengthened, or even the time period t1-t2 can be cancelled to allow the channel to perform full hard discharge. In short, it can be flexibly adjusted according to different specifications of glass and different application requirements to achieve the most ideal EM I noise level.

[0056] (4) Through simulation comparison, it is found that the soft discharge scheme of channa l to ground proposed in this patent can reduce EMI noise by 3 to 4 times compared with the traditional hard switch discharge of channa l to ground, and the effect improvement is very obvious.

[0057] Furthermore, in a preferred embodiment, the above control process can also be completed in the following manner:

[0058] First, step a is performed. When the channel load enters the discharge stage, the lower clamping circuit enables the discharge tube of the first channel load 31 to quickly enter the critical open state, and the upper clamping circuit enables the discharge tube of the second channel load 32 to quickly enter the critical open state;

[0059] Then, step b is entered. The first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N simultaneously output a small current with a modulated magnitude, so as to slowly charge and discharge the discharge tube gates of the positive polarity channel load 31 and the negative polarity channel load 32, so that the discharge tubes of the first channel load 31 and the second channel load 32 are slowly opened for discharge at the same time, and the discharge currents of the first channel load 31 and the second channel load 32 change from small to large, and the discharge currents have opposite polarities and equal magnitudes, so as to achieve the purpose of mutual cancellation of EMI noises;

[0060] Then execute step c. The discharge current of the first channel load 31 and the second channel load 32 changes from small to large. When the discharge current reaches the maximum value, the soft discharge stage is completed. At this time, the soft discharge function is turned off, and the hard discharge switches M11 and M24 are respectively and simultaneously turned on in the first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N, so that the gates of the discharge tubes of the first channel load 31 and the second channel load 32 are quickly pulled to the power supply voltage, the discharge switch tube is fully turned on, the on-resistance becomes minimum, and the positive and negative channel load voltages are quickly discharged to GND;

[0061] Finally, step d is entered. When the positive and negative channel load voltages are discharged to GND, the channel load discharge phase is completed. At this time, the discharge path of the first channel load 31 to the ground is turned off, and the first channel load 31 is positively pre-charged, while the discharge path of the second channel load 32 to the ground remains open until the pre-charging of the first channel load 31 is completed and then closed.

[0062] Further, those skilled in the art understand that referring to Figure 1 In the above process, the positive polarity drive buffer and the negative polarity drive buffer enable OP_EN state are high level, PS1, PS3 and NS1, NS3 are high level, PS2, PS4 and NS2, NS4 are low level, and CS_GND1 P, CS_GND2P and CS_GND1 N, CS_GND2N are all low level state; the positive polarity drive buffer drives the channel load S1 through PS1 and PS3 to display a positive voltage, and the negative polarity drive buffer drives the channel load S2 through NS1 and NS3 to display a negative voltage. After one line of drive display is completed, the positive polarity drive buffer and the negative polarity drive buffer enable EN change from high level to low level, the positive polarity drive buffer and the negative polarity drive buffer stop working, and no longer provide drive to the first channel load 31 and the second channel load 32, and the output terminals OUT_P and OUT_N of the positive polarity drive buffer and the negative polarity drive buffer are in a suspended state.

[0063] Further, those skilled in the art understand that referring to Figure 2 , Figure 3In the above process, after the driving of the first channel load 31 and the second channel load 32 is completed, the first discharge switch tube CSP1 (hereinafter referred to as: CSP1), the second discharge switch tube CSP2 (hereinafter referred to as: CSP2) and the third discharge switch tube CSN1 (hereinafter referred to as: CSN1), the second PMOS switch tube CSN2 (hereinafter referred to as: CSN2) are slowly opened under the control of the EMI control circuit to perform controlled discharge to the ground for the first channel load 31 and the second channel load 32; for the positive polarity path load S1, the first EMI noise control submodule EMI_P circuit input signal CS_GND1P changes from a low level to a high level, and CS_GND2P remains at a low level. At this time, M7 and M9 are turned on, and M11, M12, and M13 are turned off. M5, M6, and M8 clamp the output OUTP_EM I voltage, and M8 quickly turns EM I The I_OUP voltage pulls up an NMOS threshold voltage Vthn, allowing CSP1 and CSP2 to turn on slightly. At the same time, M1, M2, M3 and M10 form a current mirror structure, and a small current ip with a modulated size is continuously injected into OUTP_EM I through M10, so that the gate voltages of CSP1 and CSP2 slowly increase, the voltage of the first channel load 31 slowly decreases, and the discharge current slowly increases from small to large; for the second channel load 32 (i.e., the negative polarity channel load), the second EM I noise control submodule EM I_N circuit input signal CS_GND1 N changes from low level to high level, and CS_GND2N remains at a low level. At this time, M16, M20, and M22 are turned on, and M23, M24, and M25 are turned off. M17, M18, and M19 clamp the output OUTN_EM I, and M21 quickly clamps the EM The I_OUN voltage pulls down a PMOS threshold voltage Vthp, allowing CSN1 and CSN2 to be slightly turned on. At the same time, M14 and M15, M14 and M26 form a current mirror structure, and a modulated small current in is continuously drawn from OUTN_EM I through M26, so that the gate voltages of CSN1 and CSN2 slowly decrease, the voltage of the second channel load 32 slowly increases, and the discharge current slowly increases from small to large.

[0064] Those skilled in the art understand that the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) are NMOS tubes that discharge to ground; and the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) are PMOS tubes that discharge to ground.

[0065] Furthermore, refer to Figure 2 , Figure 3As the gate voltages of the tubes CSP1 and CSP2 increase slowly, and the gate voltages of the tubes CSN1 and CSN2 decrease slowly, the positive polarity first channel load 31 injects a positive current ip to the ground, and the negative polarity second channel load 32 injects a negative current in to the ground, and the currents ip and in change slowly from small to large and in opposite directions, and the EMI noises generated by the two positive and negative polarity first channel loads 31 and the second channel loads 32 cancel each other out; as the channel loads discharge slowly, the voltage of the positive polarity channel S1 decreases slowly and approaches GND, and the voltage of the second channel load 32 increases slowly and approaches GND, and the discharge currents ip and in gradually increase. By adjusting the sizes of N1 and N2, the discharge currents ip and in reach the maximum current peaks at the same time, so as to achieve the maximum cancellation of the channel load discharge current EMI noise.

[0066] Further, refer to Figure 2 , Figure 3 , Figure 4 , when the discharge currents ip and in of the first channel load 31 and the second channel load 32 reach the maximum value at the same time, ip and in stop increasing and start decreasing; at this time, in the first EM I noise control submodule EM I_P, the control signal CS_GND1 P changes from a high level to a low level, and at the same time CS_GND2P changes from a low level to a high level, in the first EM I noise control submodule EM I_P, M7, M9, and M11 are turned off, and M12 is turned on, and the gate of the M10 tube is pulled down to AGND, so that the M10 tube is fully turned on to pull the OUTP_EM I voltage up to AVDD, and the NMOS discharge tubes CSP1 and CSP2 are fully turned on to discharge to the ground with the maximum capacity, and the voltage of the first channel load 31 is quickly pulled to GND, completing the discharge function of the first channel load 31 (i.e., the positive channel load); in the second EM I noise control submodule EM I_N, the control signal CS_GND1 N changes from a high level to a low level, and at the same time CS_GND2N changes from a low level to a high level, and the second EM I noise control submodule EM I_N In I_N, M20, M22, and M23 are closed, and M24 is opened, and the gate of M26 is pulled down to the VDDS voltage, so that M26 is fully opened to pull the OUTN_EM I voltage down to AVCL, and the PMOS discharge tubes CSN1 and CSN2 are fully opened to discharge to the ground with maximum capacity, and the voltage of the second channel load 32 is quickly pulled to GND, completing the discharge function of the negative second channel load 32.

[0067] refer to Figure 4, technicians in this field understand that the loads of different screen channels vary greatly, the discharge rates are different, and the time required for the discharge current to reach the peak value is different. In chip testing, it is necessary to adjust the pulse width of CS_GND1 P and CS_GND1 N according to the load weight of different screens to achieve the minimum EM I noise.

[0068] Furthermore, after the voltage of the first channel load 31 and the second channel load 32 is discharged to GND, the control signal CS_GND2P changes from a high level to a low level, and the ground discharge NMOS tubes CSP1 and CSP2 are turned off; then the polarity exchange circuits PS2 and PS4 are controlled to change from a low level to a high level to be turned on, and PS1 and PS3 are controlled to change from a high level to a low level to be turned off, and the negative polarity drive channel is selected for the first channel load 31, and the polarity exchange circuits NS2 and NS4 are controlled to change from a low level to a high level to be turned on, and NS1 and NS3 are controlled to change from a high level to a low level to be turned off, and the positive polarity drive channel is selected for the second channel load 32. The polarity exchange of the channel load is completed; thereafter, the positive polarity second channel load 32 is precharged to the VCI voltage. After the precharge function is completed, the control signal CS_GND2N changes from a high level to a low level, and the ground discharge PMOS tubes CSN1 and CSN2 are turned off. The enable OP_EN of the positive polarity drive buffer and the negative polarity drive buffer changes from a low level to a high level. The positive buffer drives the second channel load 32 to display a positive voltage through PS2 and PS4, and the negative buffer drives S1 to display a negative voltage through NS2 and NS4, and enters the drive display of the next line cycle.

[0069] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A control circuit for reducing EMI noise in a TFT_LCD display screen driver, which is used to reduce the EMI noise in a TFT_LCD display screen driver, and is characterized in that: The device at least comprises a polarity exchange circuit (2), an EMI noise control module (1), and N columns of first channel loads (31), second channel loads (32), S3…SN, and takes adjacent first channel loads (31) and second channel loads (32) as a group of basic working units; The polarity exchange circuit (2) provides a positive voltage drive for the first channel load (31) through a positive polarity drive buffer, and provides a negative voltage drive for the second channel load (32) through control of a negative polarity drive buffer; Wherein, at the positions of the middle nodes EX1_P and EX2_P of the polarity exchange circuit (2), a first NMOS switch tube (CSP1) and a second NMOS switch tube (CSP2) are respectively connected to the ground for discharging the positive polarity channel load to the ground, and the gates of all the positive polarity channel NMOS discharge tubes in the N columns of the first channel load (31), the second channel load (32), S3...SN are connected together; at the positions of the middle nodes EX_N1 and EX_N2 of the polarity exchange circuit (2), a first PMOS switch tube (CSN1) and a second PMOS switch tube (CSN2) are respectively connected to the ground for discharging the negative polarity channel load to the ground, and the gates of all the negative polarity channel PMOS discharge tubes in the N columns of the first channel load (31), the second channel load (32), S3...SN are connected together; Wherein, the S3...SN represents the channel load.

2. The control circuit according to claim 1, characterized in that: The EMI noise control module (1) comprises at least a first EMI noise control submodule (first EMI noise control submodule EMI_P) and a second EMI control submodule (EMI_N), wherein the output end OUTP_EMI of the first EMI noise control submodule (first EMI noise control submodule EMI_P) connects the gates of the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) together for control, and the output end OUTN_EMI of the second EMI control submodule (EMI_N) connects the gates of the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) together for control.

3. The control circuit according to claim 2, characterized in that: The first EMI noise control submodule (first EMI noise control submodule EMI_P) includes at least a current mirror current replication circuit, an output terminal voltage clamping circuit, and an output current modulation circuit, wherein the output terminal voltage clamping circuit is used to limit the minimum voltage value of the output terminal OUTP_EMI so that it is not lower than the voltage clamping value; the output current modulation circuit is used to adjust the size of the output current of the output terminal so that the output current is controlled to slowly charge and discharge the gate of the discharge tube.

4. The control circuit according to claim 3, characterized in that: The current mirror current replication circuit at least comprises a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), and a fourth MOS tube (M4); the gate of the first MOS tube (M1) is connected to the drain, the gate of the first MOS tube (M1) is connected to the gate of the second MOS tube (M2), the second MOS tube (M2) replicates the current of the first MOS tube (M1), the drain of the second MOS tube (M2) is connected to the drain of the third MOS tube (M3), the gate of the third MOS tube (M3) is connected to the drain, the gate of the third MOS tube (M3) is connected to the gate of the fourth MOS tube (M4), and the fourth MOS tube (M4) replicates the current of the third MOS tube (M3); The output terminal voltage clamping circuit at least comprises a fourth MOS tube (M4), a fifth MOS tube (M5), a sixth MOS tube (M6), and an eighth MOS tube (M8). The gate of the fifth MOS tube (M5) is connected to the drain, the gate of the sixth MOS tube (M6) is connected to the drain, the drain of the fifth MOS tube (M5) is connected to the source of the sixth MOS tube (M6), the drain of the sixth MOS tube (M6) is connected to the fourth MOS tube (M4), the drain voltage of the sixth MOS tube (M6) is about two threshold voltages higher than GND, and then the gate of the eighth MOS tube (M8) is connected to the drain of the sixth MOS tube (M6), and the source of the eighth MOS tube (M8) is connected to the output terminal OUTP_EMI, so that the OUTP_EMI voltage is clamped at a threshold voltage about one threshold voltage higher than GND. The output current modulation circuit at least comprises a third MOS tube (M3), a ninth MOS tube (M9), and a tenth MOS tube (M10); the gate of the tenth MOS tube (M10) is connected to the drain of the ninth MOS tube (M9); the source of the ninth MOS tube (M9) is connected to the gate of the third MOS tube (M3); by controlling the opening and closing of the ninth MOS tube (M9), the tenth MOS tube (M10) replicates the current of the third MOS tube (M3) according to the first tube size ratio.

5. The control circuit according to claim 4, characterized in that: The tube size ratio of the tenth MOS tube (M10) to the third MOS tube is N1:1, which is expressed as a first tube size ratio, and the value range of N1 is between 1 and 30.

6. The control circuit according to any one of claims 2 to 5, characterized in that: The second EMI noise control submodule (EMI_N) at least includes a current mirror current replication circuit, an output voltage clamping circuit, and an output current modulation circuit, wherein the output voltage clamping circuit is used to limit the maximum voltage of the output terminal OUTN_EMI so that it is not higher than the voltage clamping value, and the output current modulation circuit is used to adjust the size of the output current of the output terminal so that the output current is controlled to slowly charge and discharge the gate of the discharge tube.

7. The control circuit according to claim 6, characterized in that: The current mirror current replication circuit at least comprises a fourteenth MOS tube (M14) and a fifteenth MOS tube (M15), wherein the gate of the fourteenth MOS tube (M14) is connected to the drain, and the gate of the fifteenth MOS tube (M15) is connected to the gate of the fourteenth MOS tube (M14), and the fifteenth MOS tube (M15) replicates the current of the fourteenth MOS tube (M14); The output terminal voltage clamping circuit at least comprises a seventeenth MOS tube (M17), an eighteenth MOS tube (M18), a nineteenth MOS tube (M19), and a twentieth MOS tube (M20), wherein the gate of the seventeenth MOS tube (M17) is connected to the drain, the gate of the eighteenth MOS tube (M18) is connected to the drain, the gate of the nineteenth MOS tube (M19) is connected to the drain, the source of the seventeenth MOS tube (M17) is connected to the positive power supply voltage VDDS, the drain voltage of the nineteenth MOS tube (M19) is about three threshold voltages lower than the positive power supply voltage, and then the gate of the twenty-first MOS tube (M21) is connected to the drain of the nineteenth MOS tube (M19), and the source of the twenty-first MOS tube (M21) is connected to the output terminal OUTN_EMI, so that the OUTN_EMI voltage is clamped at about two threshold voltages lower than the positive power supply voltage; The output current modulation circuit at least comprises a fourteenth MOS tube (M14), a twenty-second MOS tube (M22), and a twenty-sixth MOS tube (M26); the gate of the twenty-sixth MOS tube (M26) is connected to the drain of the twenty-second MOS tube (M22); the gate of the fourteenth MOS tube (M14) is connected to the source of the twenty-second MOS tube (M22); by controlling the opening and closing of the twenty-second MOS tube (M22), the twenty-sixth MOS tube (M26) replicates the current of the fourteenth MOS tube (M14) according to the second tube size ratio.

8. The control circuit according to claim 7, characterized in that: The tube size ratio of the twenty-sixth MOS tube (M26) to the fourteenth MOS tube (M14) is N2:1, which is expressed as a second tube size ratio, and the value range of N2 is between 1 and 30.

9. A new TFT_LCD display screen for reducing EMI noise, characterized in that: Comprising a control circuit according to any one of claims 1 to 8.

10. A control method for a new TFT_LCD display screen for reducing EMI noise, which is used to reduce the display screen driving EMI noise in the TFT_LCD display screen according to claim 9, characterized in that: At least the following steps are included: a. First, when the channel load enters the discharge stage, the lower clamping circuit enables the discharge tube of the first channel load (31) to quickly enter the critical open state, and the upper clamping circuit enables the discharge tube of the second channel load (32) to quickly enter the critical open state; b. The first EMI noise control submodule (the first EMI noise control submodule EMI_P) and the second EMI control submodule (EMI_N) simultaneously output a small current whose magnitude is modulated respectively, so as to slowly charge and discharge the discharge tube gates of the positive polarity channel load and the negative polarity channel load, and the discharge currents of the first channel load (31) and the second channel load (32) change from small to large, and the two discharge currents have opposite polarities and equal magnitudes; c. The discharge current of the first channel load (31) and the second channel load (32) changes from small to large. When the discharge current reaches the maximum value, the soft discharge stage is completed. At this time, the soft discharge function is turned off, and the hard discharge switches M11 and M24 are respectively and simultaneously turned on in the first EMI noise control submodule (the first EMI noise control submodule EMI_P) and the second EMI control submodule (EMI_N), so that the discharge tube gates of the first channel load (31) and the second channel load (32) are quickly pulled to the power supply voltage, and the positive and negative channel load voltages are quickly discharged to GND. d. When the positive and negative channel load voltages are discharged to GND, the discharge path of the first channel load (31) to the ground is turned off, and the first channel load (31) is positively precharged, while the discharge path of the second channel load (32) to the ground remains open until the precharging of the first channel load (31) is completed and then turned off.

11. The control method according to claim 10, characterized in that: The positive polarity drive buffer and the negative polarity drive buffer enable OP_EN state is high level, PS1, PS3 and NS1, NS3 are high level, PS2, PS4 and NS2, NS4 are low level, and CS_GND1 P, CS_GND2P and CS_GND1 N, CS_GND2N are all low level state; the positive polarity drive buffer and the negative polarity drive buffer drive the first channel load (31) through PS1 and PS3 to display a positive voltage, and the negative polarity drive buffer drives the second channel load (32) through NS1 and NS3 to display a negative voltage. After one line of driving display is completed, the positive polarity drive buffer and the negative polarity drive buffer enable EN change from high level to low level, the positive polarity drive buffer and the negative polarity drive buffer stop working, and the output end OUT_P of the positive polarity drive buffer and the output end OUT_N of the negative polarity drive buffer are in a suspended state.

12. The control method according to claim 10 or 11, characterized in that: After driving the first channel load (31) and the second channel load (32), the first NMOS switch tube (CSP1), the second NMOS switch tube (CSP2) and the first PMOS switch tube (CSN1), the second PMOS switch tube (CSN2) are slowly opened under the control of the EMI control circuit to perform controlled discharge to the ground for the first channel load (31) and the second channel load (32); for the positive polarity first channel load (31), the first EMI noise control submodule (EMI_P) circuit input signal CS_GND1 P changes from a low level to a high level, and CS_GND2P remains at a low level. At this time, M7 and M9 are turned on, and M11, M12, and M13 are turned off. M5, M6, and M8 clamp the output OUTP_EMI. M8 quickly pulls up the EMI_OUP voltage by an NMOS threshold voltage Vthn, so that the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) are slightly turned on. At the same time, M1 and M2, M3 and M10 form a current mirror structure, and a small current ip with a modulated size is continuously injected into OUTP_EMI through M10, so that the gate voltages of the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) are slowly increased, the voltage of the first channel load (31) is slowly decreased, and the discharge current is slowly increased from small to large.

13. The control method according to claim 12, characterized in that: For the second channel load (32), the second EMI control submodule (EMI_N) circuit input signal CS_GND1 N changes from low level to high level, and CS_GND2N remains at a low level. At this time, M16, M20, and M22 are turned on, and M23, M24, and M25 are turned off. M17, M18, and M19 clamp the output OUTN_EMI. M21 quickly pulls down the EMI_OUN voltage by a PMOS threshold voltage Vthp, so that the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) are slightly turned on. At the same time, M14 and M15, M14 and M26 form a current mirror structure, and a small current in modulated by magnitude is continuously drawn from OUTN_EMI through M26, so that the gate voltages of the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) slowly decrease, the voltage of the second channel load (32) slowly increases, and the discharge current slowly increases from small to large.

14. The control method according to any one of claims 10 to 13, characterized in that: As the sub-gate voltages of the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) slowly increase, and the sub-gate voltages of the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) slowly decrease, the positive polarity first channel load (31) injects a positive current ip into the ground, and the negative polarity second channel load (32) injects a negative current in into the ground, and the currents ip and in slowly change from small to large and in opposite directions, the EMI noises generated by the two positive and negative polarity first channel loads (31) and second channel loads (32) are offset against each other; As the channel load slowly discharges, the voltage of the positive polarity channel S1 slowly decreases and approaches GND, the voltage of the second channel load 32 slowly increases and approaches GND, and the discharge currents ip and in gradually increase. By adjusting the sizes of N1 and N2, the discharge currents ip and in reach the maximum current peaks at the same time to achieve maximum cancellation of the channel load discharge current EMI noise.

15. The control method according to any one of claims 10 to 14, characterized in that: When the discharge currents ip and in of the first channel load (31) and the second channel load (32) reach their maximum values ​​at the same time, ip and in stop increasing and start decreasing; at this time, in the first EMI noise control submodule (first EMI noise control submodule EMI_P), the control signal CS_GND1P changes from a high level to a low level, and at the same time, CS_GND2P changes from a low level to a high level; in the first EMI noise control submodule (first EMI noise control submodule EMI_P), M7, M9, and M11 are turned off, and M12 is turned on, and the gate of the M10 tube is pulled down to AGND, so that the M10 tube is fully turned on to pull the OUTP_EMI voltage up to AVDD; the NMOS discharge tube, i.e., the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2), are fully turned on to discharge to the ground with maximum capacity, and the voltage of the first channel load (31) is quickly pulled to GND, thereby completing the discharge function of the first channel load (31).

16. The control method according to claim 15, characterized in that: In the second EMI control submodule (EMI_N), the control signal CS_GND1N changes from a high level to a low level, and at the same time, CS_GND2N changes from a low level to a high level. In the second EMI control submodule (EMI_N), M20, M22, and M23 are turned off, and M24 is turned on. The gate of the M26 tube is pulled down to the VDDS voltage, so that the M26 tube is fully turned on to pull the OUTN_EMI voltage down to AVCL. The first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) are fully turned on to discharge to the ground with maximum capacity, and the voltage of the second channel load (32) is quickly pulled to GND, completing the discharge function of the second channel load (32).

17. The control method according to any one of claims 10 to 16, characterized in that: After the voltage of the first channel load (31) and the second channel load (32) is discharged to GND, the control signal CS_GND2P changes from a high level to a low level, and the ground discharge NMOS tubes, i.e., the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) are turned off; then, the polarity exchange circuits PS2 and PS4 are controlled to change from a low level to a high level to be turned on, and PS1 and PS3 are controlled to change from a high level to a low level to be turned off, so as to select a negative polarity drive channel for the first channel load (31), and the polarity exchange circuits NS2 and NS4 are controlled to change from a low level to a high level to be turned on, and NS1 and NS3 are controlled to change from a high level to a low level to be turned off, so as to select a positive polarity drive channel for the second channel load (32), and the pass is completed. The polarity of the channel load is exchanged; thereafter, the positive polarity second channel load (32) is precharged to the VCI voltage. After the precharging function is completed, the control signal CS_GND2N changes from a high level to a low level, the ground discharge PMOS tube, i.e., the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) are turned off, and the enable OP_EN of the positive polarity drive buffer and the negative polarity drive buffer changes from a low level to a high level. The positive polarity drive buffer drives the second channel load (32) to display a positive voltage through PS2 and PS4, and the negative polarity drive buffer drives the first channel load (31) to display a negative voltage through NS2 and NS4, and enters the next line cycle of drive display.

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