Silicon bridge chip packaging method and structure

Abstract

The invention provides a silicon bridge chip packaging method and a silicon bridge chip packaging structure, which can reduce the manufacturing cost and improve the heat dissipation effect of a packaging body. A silicon through hole and a first dielectric substance layer are manufactured on the first surface of a silicon wafer, a groove is manufactured by avoiding the silicon through hole, a silicon bridge chip is mounted in the groove, a rewiring layer is arranged on the first surface of the silicon wafer, and the silicon bridge chip is packaged by the rewiring layer. Welding salient points are arranged on the rewiring layer, and the welding salient points are connected to the silicon bridge chip through lines on the rewiring layer; at least two chips are connected with the welding bumps, so that the chips are connected through the silicon bridge chip, the first surface of the silicon wafer is subjected to plastic packaging, the second surface, away from the silicon bridge chip, of the silicon wafer is thinned until the bottom of the silicon through hole is exposed, then a second dielectric substance layer is manufactured, and metal bumps are arranged; and thinning the plastic packaging layer on the first surface of the silicon wafer to expose the back surface of the chip, cutting the silicon wafer into single packaging bodies, inversely welding the single packaging bodies on the first surface of the substrate through the metal bumps, and arranging solder balls on the second surface of the substrate.

Description

Technical Field

[0001] The invention relates to the field of semiconductor chip packaging, and specifically demonstrates a silicon bridge chip packaging method and structure. Background Art

[0002] Using silicon bridge chips to connect two chips, such as SoC and HBM chips, has become a new trend in 2.5D packaging in the industry. Compared with silicon adapters, silicon bridge chip technology can not only retain the ability of high-density integrated packaging, but also significantly reduce packaging costs. At present, the mainstream silicon bridge chip packaging in the industry is to embed the silicon bridge chip into the plastic package. This silicon bridge chip packaging structure faces many disadvantages, such as: it needs to be plastic-sealed twice, the process cost is high, and the heat dissipation of the plastic package itself is not good; this packaging technology produces TMV (Through Mold Via) copper pillars, and due to the limitation of process capabilities, the diameter of the copper pillars is difficult to be reduced to less than 40um. Summary of the invention

[0003] In view of the above problems, the present invention provides a silicon bridge chip packaging method and structure, which can reduce the process cost and improve the heat dissipation effect of the package body.

[0004] The technical solution is as follows: a silicon bridge chip packaging method, comprising the following steps:

[0005] Step 1: providing a silicon wafer, making a through silicon via on a first surface of the silicon wafer, and making a first dielectric layer on the same surface of the silicon wafer, wherein the through silicon via is filled with a conductive material;

[0006] Step 2: making a groove on the first surface of the silicon wafer avoiding the through silicon via, wherein the groove is adapted to the silicon bridge chip;

[0007] Step 3: Mounting the silicon bridge chip into the groove to fill the gap between the silicon bridge chip and the groove;

[0008] Step 4: a redistribution layer is provided on the first surface of the silicon wafer, and welding bumps are provided on the redistribution layer, wherein the welding bumps are connected to the silicon bridge chip through the circuits on the redistribution layer;

[0009] Step 5: Connect at least two chips to the solder bumps so that the chips are connected via a silicon bridge chip;

[0010] Step 6: Fill the gap between the chip and the redistribution layer, and perform plastic sealing on the first surface of the silicon wafer;

[0011] Step 7: thinning the second surface of the silicon wafer away from the silicon bridge chip until the bottom of the through silicon via is exposed, and then forming a second dielectric layer on the second surface of the silicon wafer;

[0012] Step 8: Arranging a metal bump on the second surface of the silicon wafer, wherein the metal bump is connected to the bottom of the through silicon via; thinning the plastic sealing layer on the first surface of the silicon wafer so that the back side of the chip is exposed;

[0013] Step nine: Cut the reconstructed wafer obtained in step eight into single packages, and reversely solder them to the first surface of the substrate through metal bumps to fill the gap between the single package and the substrate, and set solder balls on the second surface of the substrate.

[0014] Furthermore, in step one, the through silicon via is manufactured by TVS process; when manufacturing the first dielectric layer, a dielectric layer is simultaneously manufactured in the through silicon via, and then filled with conductive material, and the conductive material forms a solid copper column in the through silicon via.

[0015] Furthermore, in step 2, the groove is made on the first surface of the silicon wafer avoiding the through silicon via by photolithography and dry etching processes, and the size of the groove is slightly larger than the size of the silicon bridge chip, so that there is a gap between the silicon bridge chip and the groove.

[0016] Furthermore, in step three, the bottom of the silicon bridge chip is fixed to the bottom of the groove through a DAF film, and the gap between the silicon bridge chip and the groove is filled with insulating glue or dry film insulating material.

[0017] Furthermore, in step five, the micro-bumps of the chip and the soldering bumps on the redistribution layer are physically connected and electrically interconnected by flip-chip soldering.

[0018] Furthermore, in step six, before the first surface of the silicon wafer is plastic-sealed, the gap between the chip and the redistribution layer is filled with underfill glue.

[0019] Further, in step seven, the second surface of the silicon wafer away from the silicon bridge chip is thinned by mechanical grinding and chemical mechanical polishing, a second dielectric layer is formed on the second surface by silicon dry etching and PECVD, and then the copper pillar is exposed by chemical mechanical polishing again;

[0020] Furthermore, in step eight, the metal bumps are first manufactured by a C4 process, and then the plastic encapsulation layer on the first surface of the silicon wafer is thinned by a grinding process.

[0021] A silicon bridge chip packaging structure, characterized in that the silicon bridge chip packaging structure is prepared by the above-mentioned silicon bridge chip packaging method, and the silicon bridge chip packaging structure includes:

[0022] At least two chips;

[0023] A silicon bridge chip, used to connect the chips;

[0024] A silicon wafer, wherein a groove is provided on the silicon wafer, wherein the silicon bridge chip is mounted in the groove, a redistribution layer is provided on the first surface of the silicon wafer, and welding bumps are provided on the redistribution layer, wherein the welding bumps are connected to the silicon bridge chip through the circuit on the redistribution layer, and the chip is connected to the welding bumps, and a plastic sealing layer is provided on the chip;

[0025] A metal bump is arranged on the second surface of the silicon wafer; a through silicon via is arranged on the silicon wafer, the through silicon via is filled with a conductive material, one end of the through silicon via is connected to the metal bump, and the other end of the through silicon via is connected to the redistribution layer.

[0026] The silicon chip is welded on the first surface of the substrate through metal bumps, and solder balls are arranged on the second surface of the substrate.

[0027] Furthermore, a first dielectric layer is arranged on the first surface of the silicon wafer, a redistribution layer is arranged on the first dielectric layer, a dielectric layer is arranged in the silicon through hole, a conductive material is located on the inner side of the dielectric layer, a second dielectric layer is arranged on the second surface of the silicon wafer, and the metal bump passes through the second dielectric layer to contact the conductive material in the silicon through hole.

[0028] Furthermore, the bottom of the silicon bridge chip is fixed to the bottom of the groove through a DAF film, and a filler is filled in the gap between the silicon bridge chip and the groove. Before setting the plastic sealing layer, bottom filling glue is also set to fill the gap between the chip and the redistribution layer, and glue is set to fill the gap between the silicon wafer and the substrate.

[0029] The silicon bridge chip packaging method and structure of the present invention, by opening a groove on the silicon wafer and mounting the silicon bridge chip into the groove, reduces the traditional two-time plastic sealing process to one time, and only needs to perform plastic sealing once on the first surface of the silicon wafer, which significantly reduces the process cost. The thermal expansion coefficient CTE of the silicon wafer is lower than that of the plastic sealing material, which is beneficial to reducing the warpage value of the wafer and can improve the reliability and stability of the package. The thermal conductivity of the silicon wafer is higher than that of the plastic sealing material, which is beneficial to improving the heat dissipation effect of the silicon bridge chip. In the present invention, by arranging metal bumps on the silicon wafer and connecting TSV copper pillars, the heat dissipation path is optimized, the heat dissipation performance of the package is improved, and the back side of the chip is exposed by thinning the back side of the silicon wafer, which further improves the heat dissipation effect.

[0030] The copper pillars made by the TSV silicon through-via process in the present invention can control the diameter of the copper pillars within a wide range, and can be easily achieved from 10um to 100um, breaking through the limitation of the traditional TMV process on the diameter of the copper pillars and improving the high-density integration capability of the package; the silicon bridge chip packaging method of the present invention does not require temporary bonding and debonding processes, effectively saving the costs of temporary bonding and debonding equipment, temporary bonding glue and glass carriers, simplifying the process flow and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of a silicon wafer provided in an embodiment;

[0032] Figure 2 This is a schematic diagram of the structure of the intermediate product obtained by step 1 of the method in the embodiment;

[0033] Figure 3 This is a schematic diagram of the structure of the intermediate product obtained by step 2 of the method in the embodiment;

[0034] Figure 4 This is a schematic diagram of the structure of the intermediate product obtained by step three of the method in the embodiment;

[0035] Figure 5 This is a schematic diagram of the structure of the intermediate product obtained by step 4 of the method in the embodiment;

[0036] Figure 6 This is a schematic diagram of the structure of the intermediate product obtained by step five of the method in the embodiment;

[0037] Figure 7 This is a schematic diagram of the structure of the intermediate product obtained by step six of the method in the embodiment;

[0038] Figure 8 This is a schematic diagram of the structure of the intermediate product obtained by step seven of the method in the embodiment;

[0039] Fig. 9 This is a schematic diagram of the structure of the intermediate product obtained by step eight of the method in the embodiment;

[0040] Fig.10 is a schematic diagram of the structure of the package body obtained through step nine of the method in the embodiment; DETAILED DESCRIPTION

[0041] In an embodiment of the present invention, a silicon bridge chip packaging method is provided, comprising the following steps:

[0042] Step 1: See Figure 1 A silicon wafer 1 is provided, a through silicon via 2 is formed on a first surface of the silicon wafer, and a first dielectric layer 3 is formed on the same surface of the silicon wafer 2, the through silicon via is filled with a conductive material, and the semi-finished product obtained by step 1 is shown in FIG. Figure 2 ;

[0043] Step 2: See Figure 3 , forming a groove 4 on the first surface of the silicon wafer 1 avoiding the through silicon via 2, wherein the groove 4 is adapted to the silicon bridge chip 5;

[0044] Step 3: See Figure 4 , mounting the silicon bridge chip 5 into the groove 4, and filling the gap 502 between the silicon bridge chip 5 and the groove 4 with a filler;

[0045] Step 4: See Figure 5 , a redistribution layer 6 is provided on the first surface of the silicon wafer 1, and welding bumps 601 are provided on the redistribution layer 6, and the welding bumps 601 are connected to the silicon bridge chip 5 through the circuit on the redistribution layer 6;

[0046] Step 5: See Figure 6 , connecting the two chips 7 with the solder bumps 601, so that the chips 7 are connected through the silicon bridge chip 5. In the embodiment, the two chips 7 are chips of different types;

[0047] Step 6: See Figure 7 , fill the gap between the chip 7 and the redistribution layer 6 with underfill glue 8, and then perform plastic sealing on the first surface of the silicon wafer 1 to form a plastic sealing layer 9;

[0048] Step 7: See Figure 8 , thinning the second surface of the silicon wafer 1 away from the silicon bridge chip 6 until the bottom of the through silicon via 2 is exposed, and then forming a second dielectric layer 10 on the second surface of the silicon wafer 1;

[0049] Step 8: See Fig. 9 , a metal bump 11 is arranged on the second surface of the silicon wafer 1, and the metal bump 11 is connected to the bottom of the through silicon via 2; the plastic sealing layer 9 on the first surface of the silicon wafer 1 is thinned so that the back side of the chip 7 is exposed;

[0050] Step 9: Cut the reconstructed wafer obtained in step 8 into individual packages, and reversely solder them to the first surface of the substrate 12 through the metal bumps 11, fill the gap between the individual packages and the substrate 12 with glue 13, and set solder balls 14 on the second surface of the substrate 12. The resulting package can be seen in FIG. Fig.10 .

[0051] Traditional silicon bridge packaging requires two plastic sealing processes, one for the silicon bridge chip and the other for the chip, which results in high manufacturing costs. The method in the embodiment is used to open a groove in the silicon wafer and mount the silicon bridge chip into the groove, thereby reducing one plastic sealing process and reducing process costs. Traditional silicon bridge packaging uses two plastic sealing processes, and the thermal conductivity of the plastic sealing material is low, which makes it difficult to effectively dissipate the heat inside the package, which will affect the working stability and life of the chip. The use of silicon wafers in the embodiment reduces the use of plastic sealing materials. The thermal conductivity of silicon wafers is higher than that of plastic sealing materials, which is conducive to improving the heat dissipation effect of silicon bridge chips. For the semiconductor field, good heat dissipation performance is crucial to improving product performance and extending service life. In addition, through the use of silicon wafers, the thermal expansion coefficient CTE of silicon is lower than that of plastic sealing materials, which helps to reduce the warpage value of the wafer and improve the flatness and reliability of the package.

[0052] The entire process flow in implementation does not require temporary bonding and debonding processes, saves the cost of temporary bonding and debonding equipment, temporary bonding glue and glass carrier, simplifies the process steps, and reduces production costs.

[0053] In a specific implementation of the present invention, in step 1, a through silicon via is manufactured on a silicon wafer by a TVS (Through Silicon Via) process, the sidewall of the through silicon via structure is a dielectric layer 201, and a first dielectric layer 3 is manufactured on the same side of the through silicon via 2 of the silicon wafer 1 to provide an insulating basis for the subsequent redistribution layer; when manufacturing the first dielectric layer 3, a dielectric layer 201 is also manufactured in the through silicon via 2 at the same time, and the material of the first dielectric layer 3 is usually consistent with the material of the dielectric layer 301 in the through silicon via, and the material of the dielectric layer is usually an insulating material such as silicon oxide and silicon nitride; then a conductive material is filled in the through silicon via 2, and the conductive material is copper, and the conductive material forms a solid copper column in the through silicon via.

[0054] Due to the limitation of process capability, the diameter of TMV copper pillars made by traditional methods is difficult to be less than 40um, which limits the further improvement of interconnection density. In practice, the copper pillars made by TSV silicon through-via process can control the diameter of copper pillars in a wide range, which can be easily achieved from 10um-100um. This breaks through the limitation of traditional TMV process on copper pillar diameter and can improve the high-density integration capability of packaging.

[0055] In a specific implementation of the present invention, in step two, a groove 4 is made on the first surface of the silicon wafer avoiding the through silicon via by photolithography and dry etching processes. The size of the groove 4 is slightly larger than the size of the silicon bridge chip 5, so that there is a gap between the silicon bridge chip 5 and the groove 4, ensuring that the silicon bridge chip can be smoothly embedded and there is an appropriate gap for filling the insulating material.

[0056] In a specific implementation of the present invention, in step three, the prepared silicon bridge chip 5 is mounted inside the groove 4, the bottom of the silicon bridge chip 5 is fixed to the bottom of the groove 4 through the DAF film 501, and the gap between the silicon bridge chip 5 and the groove 4 is filled by dispensing, screen printing or laminating dry film to ensure mechanical stability and electrical isolation. The material for filling the gap 502 can be insulating glue or dry film insulating material. By embedding the silicon bridge chip 5 into the pre-made groove 4, the entire packaging process reduces one plastic sealing, greatly simplifies the manufacturing process, reduces production costs, and significantly reduces process steps and material consumption compared to the traditional method that requires two plastic sealings;

[0057] In step 4, a redistribution layer 6 is provided on the first surface of the silicon wafer 1, and welding bumps 601 are provided on the redistribution layer 6. The welding bumps 601 are connected to the silicon bridge chip 5 through the circuits on the redistribution layer 6, so as to facilitate the connection of subsequent chips.

[0058] In step five, the micro-bumps 701 of chip 7 are physically connected and electrically interconnected with the solder bumps 601 on the redistribution layer by flip-chip welding, so that the chips 7 can be efficiently connected through the silicon bridge chip 5. There are at least two chips 7, or three or more chips of different types, which may be logic chips, HBM, I / O, etc.

[0059] In step six, before the first surface of the silicon wafer 1 is plastic-sealed, the gap between the chip 6 and the redistribution layer 7 is filled with bottom-fill glue 8, and then the first surface of the silicon wafer 1 is plastic-sealed to form a plastic-sealing layer 9; the bottom-fill glue 8 can buffer stress and block water and oxygen, thereby enhancing the integrity and sealing of the package. The entire reconstructed wafer is plastic-sealed, and the plastic-sealing layer 9 can protect the chip and serve as a carrier for subsequent processing of the reconstructed wafer. In practice, only one plastic-sealing is required to complete the entire packaging process, which simplifies the process flow and reduces the process cost;

[0060] In step seven, the second surface of the silicon wafer away from the silicon bridge chip is thinned by mechanical grinding and chemical mechanical polishing until the bottom of the silicon through hole 2 is exposed, and then the second dielectric layer 10 is formed on the second surface by silicon dry etching and PECVD. The second dielectric layer 10 is usually an insulating material such as silicon oxide and silicon nitride. After that, the copper pillar in the silicon through hole 2 is exposed by chemical mechanical polishing again.

[0061] In step eight, a metal bump is first made by the C4 process, and the metal bump 11 is connected to the bottom of the through silicon via 2 to form a stable electrical connection. By integrating the silicon bridge chip, the redistribution layer, the welding bump and the metal bump on the silicon carrier, an integrated connection between the chips is achieved, the packaging structure is simplified, and the overall performance of the package is improved; then, the plastic sealing layer 9 on the first surface of the silicon wafer is thinned by a grinding process, so that the back side of the chip 7 is exposed, and the heat dissipation effect is further improved;

[0062] Finally, in step nine, the reconstructed wafer obtained in step eight is cut into single packages, and reversely soldered to the first surface of the substrate 12 through the metal bumps 11, and the gap between the single package and the substrate 12 is filled with glue 13, which can buffer stress and block water and oxygen; solder balls 14 are set on the second surface of the substrate 12 for mounting the PCB board. The embodiment provides a flexible substrate connection method to facilitate the integration and application of the package. The final package is completed.

[0063] See Fig.10 In an embodiment of the present invention, a silicon bridge chip packaging structure is further provided. The silicon bridge chip packaging structure can be prepared by the above-mentioned silicon bridge chip packaging method. The silicon bridge chip packaging structure includes:

[0064] At least two chips 7, where the chips 7 may be chips of different types;

[0065] Silicon bridge chip 5, used to connect chips;

[0066] A silicon wafer 1 is provided with a groove 4, a silicon bridge chip 5 is mounted in the groove 4, a redistribution layer 6 is provided on the first surface of the silicon wafer 1, a welding bump 601 is provided on the redistribution layer 6, the welding bump 601 is connected to the silicon bridge chip 5 through the line on the redistribution layer 5, a chip 7 is connected to the welding bump 601, and a plastic sealing layer 9 is provided on the chip 7;

[0067] A metal bump 11 is disposed on the second surface of the silicon wafer 1; a through silicon via 2 is disposed on the silicon wafer 1, and a copper column is filled in the through silicon via 2, one end of the through silicon via 2 is connected to the metal bump 11, and the other end of the through silicon via 2 is connected to the redistribution layer 6;

[0068] The substrate 12, the silicon chip 1 is soldered on the first surface of the substrate 12 through the metal bumps 11, and the solder balls 13 are arranged on the second surface of the substrate 12 for mounting the PCB board.

[0069] In addition, in one embodiment, a first dielectric layer 3 is provided on the first surface of the silicon wafer, a redistribution layer 6 is provided on the first dielectric layer 3, a dielectric layer 201 is provided in the through silicon via 2, a copper pillar is located on the inner side of the dielectric layer 201, a second dielectric layer 10 is made on the second surface of the silicon wafer 1, and a metal bump 11 passes through the second dielectric layer 10 to contact the copper pillar in the through silicon via.

[0070] In one embodiment, the bottom of the silicon bridge chip 5 is fixed to the bottom of the groove 4 through a DAF film 501 .

[0071] In one embodiment, a filler is filled in the gap 502 between the silicon bridge chip 5 and the groove 4. Before setting the plastic encapsulation layer 9, a bottom fill glue 8 is set to fill the gap between the chip 6 and the redistribution layer 7. In addition, glue 13 is set to fill the gap between the silicon wafer 1 and the substrate 12. This can also enhance the mechanical strength between the chip and the redistribution layer, and between the single package and the substrate, thereby improving the overall stability of the package.

[0072] The silicon bridge chip packaging structure in the embodiment solves the problems of poor heat dissipation and complex process caused by multiple plastic sealing in the prior art. Silicon wafers are used to replace plastic sealing materials, so that the package body only needs to be plastic sealed once, which saves process cost and time compared with the two plastic sealing in the prior art; the excellent low CTE and high thermal conductivity physical properties of silicon wafers are utilized to solve the heat dissipation and warping problems in the prior art; the silicon through vias set by the TSV process in the embodiment break through the limitations of the prior art and realize flexible control of the copper column diameter. In the embodiment, the gap is filled with bottom fill glue to enhance the mechanical strength between the chip and the redistribution layer, and between the single package body and the substrate, which can improve the overall stability of the package body.

[0073] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention.

[0074] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A silicon bridge chip packaging method, characterized in that: The following steps are involved: Step 1: providing a silicon wafer, making a through silicon via on a first surface of the silicon wafer, and making a first dielectric layer on the same surface of the silicon wafer, wherein the through silicon via is filled with a conductive material; Step 2: making a groove on the first surface of the silicon wafer avoiding the through silicon via, wherein the groove is adapted to the silicon bridge chip; Step 3: Mounting the silicon bridge chip into the groove to fill the gap between the silicon bridge chip and the groove; Step 4: a redistribution layer is provided on the first surface of the silicon wafer, and welding bumps are provided on the redistribution layer, wherein the welding bumps are connected to the silicon bridge chip through the circuits on the redistribution layer; Step 5: Connect at least two chips to the solder bumps so that the chips are connected via a silicon bridge chip; Step 6: Fill the gap between the chip and the redistribution layer, and perform plastic sealing on the first surface of the silicon wafer; Step 7: thinning the second surface of the silicon wafer away from the silicon bridge chip until the bottom of the through silicon via is exposed, and then forming a second dielectric layer on the second surface of the silicon wafer; Step 8: Arrange a metal bump on the second surface of the silicon wafer, wherein the metal bump is connected to the bottom of the through silicon via; thin the plastic sealing layer on the first surface of the silicon wafer so that the back side of the chip is exposed; Step nine: Cut the reconstructed wafer obtained in step eight into single packages, and reversely solder them to the first surface of the substrate through metal bumps to fill the gap between the single package and the substrate, and set solder balls on the second surface of the substrate.

2. A silicon bridge chip packaging method according to claim 1, characterized in that: In step one, a through silicon via is fabricated by a TVS process; when the first dielectric layer is fabricated, a dielectric layer is also fabricated in the through silicon via, and then a conductive material is filled therein, wherein the conductive material is copper, to form a solid copper column in the through silicon via.

3. The silicon bridge chip packaging method according to claim 1, characterized in that: In step 2, the groove is made on the first surface of the silicon wafer avoiding the through silicon via by photolithography and dry etching processes. The size of the groove is slightly larger than the size of the silicon bridge chip, so that there is a gap between the silicon bridge chip and the groove.

4. The silicon bridge chip packaging method according to claim 1, characterized in that: In step three, the bottom of the silicon bridge chip is fixed to the bottom of the groove through a DAF film, and the gap between the silicon bridge chip and the groove is filled with insulating glue or dry film insulating material.

5. The silicon bridge chip packaging method according to claim 1, characterized in that: In step five, the micro-bumps of the chip and the soldering bumps on the redistribution layer are physically connected and electrically interconnected by flip-chip soldering.

6. The silicon bridge chip packaging method according to claim 1, characterized in that: In step six, before the first surface of the silicon wafer is plastic-sealed, the gap between the chip and the redistribution layer is filled with underfill glue.

7. The silicon bridge chip packaging method according to claim 21, characterized in that: In step seven, the second surface of the silicon wafer away from the silicon bridge chip is thinned by mechanical grinding and chemical mechanical polishing, a second dielectric layer is formed on the second surface by silicon dry etching and PECVD, and then the copper pillar is exposed by chemical mechanical polishing again; In step eight, metal bumps are first manufactured by a C4 process, and then the plastic encapsulation layer on the first surface of the silicon wafer is thinned by a grinding process.

8. A silicon bridge chip packaging structure, characterized in that: The silicon bridge chip packaging structure comprises: At least two chips; A silicon bridge chip, used to connect the chips; A silicon wafer, wherein a groove is arranged on the silicon wafer, wherein the silicon bridge chip is mounted in the groove, a redistribution layer is arranged on the first surface of the silicon wafer, a welding bump is arranged on the redistribution layer, the welding bump is connected to the silicon bridge chip through a line on the redistribution layer, the chip is connected to the welding bump, and a plastic sealing layer is arranged on the chip; a metal bump is arranged on the second surface of the silicon wafer; a through silicon via is arranged on the silicon wafer, wherein the through silicon via is filled with a conductive material, one end of the through silicon via is connected to the metal bump, and the other end of the through silicon via is connected to the redistribution layer; The silicon chip is welded on the first surface of the substrate through metal bumps, and solder balls are arranged on the second surface of the substrate.

9. The silicon bridge chip packaging structure according to claim 8, characterized in that: A first dielectric layer is also arranged on the first surface of the silicon wafer, a redistribution layer is arranged on the first dielectric layer, a dielectric layer is arranged in the silicon through hole, a conductive material is located on the inner side of the dielectric layer, a second dielectric layer is arranged on the second surface of the silicon wafer, and the metal bump passes through the second dielectric layer to contact the conductive material in the silicon through hole.

10. The silicon bridge chip packaging structure according to claim 8, characterized in that: The bottom of the silicon bridge chip is fixed to the bottom of the groove through a DAF film, and a filler is filled in the gap between the silicon bridge chip and the groove. Before setting the plastic sealing layer, bottom filling glue is also set to fill the gap between the chip and the redistribution layer, and glue is set to fill the gap between the silicon chip and the substrate.

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