Chip package and manufacturing method thereof

Abstract

A chip package includes a bearing portion, an electronic component, a plurality of solders and a filling adhesive. The bearing part is provided with a first side wall and comprises a circuit structure layer and an insulating layer. The circuit structure layer is arranged on the insulating layer, and the first side wall exposes the circuit structure layer and the insulating layer. The electronic component is arranged on the circuit structure layer, and a gap is reserved between the electronic component and the circuit structure layer. The solders are arranged in the gap and are connected with the electronic component and the circuit structure layer. The filling glue covers the circuit structure layer and the side edge of the electronic component, fills the gap, and is provided with a top surface and a second side wall. The second side wall surrounds and is connected with the top surface and is flush with the first side wall, and the top surface extends from the side edge of the electronic component to the second side wall. The chip package has a relatively thin overall thickness, and is beneficial to the development trend of thinning at present.

Description

Technical Field

[0001] The present invention relates to a chip package and a manufacturing method thereof, and in particular to a chip package including a filling glue and a manufacturing method thereof. Background Art

[0002] Existing chip packages usually include a chip, a carrier, a molding compound, and an underfill. Generally speaking, the chip, the underfill, and the molding compound are all disposed on the carrier, wherein the bottom surface of the chip faces the carrier, and the underfill is disposed between the bottom surface and the carrier. The molding compound will cover the entire chip and the underfill, that is, the top surface and the side of the chip are covered by the molding compound, so that the thickness of the molding compound is greater than the thickness of the chip. In other words, the overall thickness of the existing chip package includes not only the thickness of the chip, but also the thickness of the portion of the molding compound located on the top surface of the chip. Summary of the invention

[0003] At least one embodiment of the present invention provides a chip package that can have a relatively thin thickness and is conducive to the development trend of thinning chip packages.

[0004] The chip package provided by at least one embodiment of the present invention includes a carrier, a first electronic component, a plurality of first solders and a filling glue. The carrier has a first side wall and includes a first circuit structure layer and a first insulating layer, wherein the first circuit structure layer is arranged on the first insulating layer, and the first side wall exposes the first circuit structure layer and the first insulating layer. The first electronic component is arranged on the first circuit structure layer, wherein there is a gap between the first electronic component and the first circuit structure layer. These first solders are arranged in the gap and connect the first electronic component and the first circuit structure layer. The filling glue covers the sides of the first circuit structure layer and the first electronic component and fills the gap, wherein the filling glue has a top surface and a second side wall. The second side wall surrounds and connects the top surface and is flush with the first side wall, and the top surface extends from the side of the first electronic component to the second side wall.

[0005] In at least one embodiment of the present invention, the filling glue further has an angle, and the angle is located between the top surface and the second side wall and is greater than 90 degrees.

[0006] In at least one embodiment of the present invention, the distance between the top surface and the carrying portion decreases from the side edge of the first electronic component toward the second side wall.

[0007] In at least one embodiment of the present invention, the top surface is a concave curved surface.

[0008] In at least one embodiment of the present invention, the first electronic component has an upper surface and a lower surface, and the side surrounds and connects the upper surface and the lower surface, wherein the filling glue connects the edge of the upper surface, and the first solders connect the lower surface.

[0009] In at least one embodiment of the present invention, the chip package further includes an electromagnetic shielding layer, wherein the electromagnetic shielding layer conformally covers the first electronic component, the first sidewall of the carrying portion, the top surface of the filling glue, and the second sidewall.

[0010] In at least one embodiment of the present invention, the supporting part further includes a first chip, a second chip, an adhesive layer and a second circuit structure layer. The first chip is disposed in the first insulating layer and electrically connected to the first circuit structure layer. The second chip is disposed in the first insulating layer, wherein the first chip is located between the second chip and the first circuit structure layer. The adhesive layer is disposed between the first chip and the second chip, and bonds the back of the first chip to the back of the second chip. The second circuit structure layer is electrically connected to the second chip, wherein the second chip is located between the first chip and the second circuit structure layer, and the first insulating layer is sandwiched between the first circuit structure layer and the second circuit structure layer.

[0011] In at least one embodiment of the present invention, the chip package further includes a second electronic component, wherein the second electronic component is disposed on the second circuit structure layer.

[0012] In at least one embodiment of the present invention, the supporting portion further comprises at least one conductive column disposed in the first insulating layer and between the first circuit structure layer and the second circuit structure layer, wherein the conductive column connects the first circuit structure layer and the second circuit structure layer.

[0013] In at least one embodiment of the present invention, the at least one conductive column includes a first conductive sub-column and a second conductive sub-column. The first conductive sub-column is connected to the second circuit structure layer. The second conductive sub-column is stacked on the first conductive sub-column and connects the first conductive sub-column and the first circuit structure layer, wherein the second conductive sub-column is located between the first conductive sub-column and the first circuit structure layer, and the diameter of the first conductive sub-column is not equal to the diameter of the second conductive sub-column.

[0014] In at least one embodiment of the present invention, the chip package further includes a second electronic component, wherein the second electronic component is disposed on the first circuit structure layer.

[0015] In at least one embodiment of the present invention, the above-mentioned supporting part also includes a first chip, a second chip, a second circuit structure layer, a third circuit structure layer, a fourth circuit structure layer, a second insulating layer and a plurality of second solders. The first chip is arranged in the first insulating layer and is electrically connected to the first circuit structure layer. The first insulating layer is sandwiched between the first circuit structure layer and the second circuit structure layer. The first insulating layer is located between the second insulating layer and the first electronic component. The second chip is arranged in the second insulating layer. The third circuit structure layer is arranged on the second insulating layer. The fourth circuit structure layer is electrically connected to the second chip, wherein the second insulating layer is sandwiched between the third circuit structure layer and the fourth circuit structure layer. These second solders are sandwiched between the second circuit structure layer and the third circuit structure layer, and connect the second circuit structure layer and the third circuit structure layer.

[0016] In at least one embodiment of the present invention, the above-mentioned supporting part further includes at least one first conductive column and at least one second conductive column. The first conductive column is arranged in the first insulating layer and is located between the first circuit structure layer and the second circuit structure layer, wherein the first conductive column connects the first circuit structure layer and the second circuit structure layer. The second conductive column is arranged in the second insulating layer and is located between the third circuit structure layer and the fourth circuit structure layer, wherein the second conductive column connects the third circuit structure layer and the fourth circuit structure layer.

[0017] The manufacturing method of the chip package provided by at least one embodiment of the present invention includes the following steps. An initial bearing portion is formed, which includes a first circuit structure layer and a first insulating layer, wherein the first circuit structure layer is disposed on the first insulating layer. Thereafter, at least one first electronic component is installed on the first circuit structure layer, wherein a gap exists between the first electronic component and the first circuit structure layer. After the first electronic component is installed on the first circuit structure layer, a filling material is formed on the first circuit structure layer, wherein the filling material covers the side of the first electronic component and fills the gap. After the filling material is formed, the filling material and the initial bearing portion are cut to form at least one bearing portion and at least one filling glue disposed on the at least one bearing portion.

[0018] In at least one embodiment of the present invention, the manufacturing method further comprises forming an electromagnetic shielding layer after cutting the filling material and the initial carrying portion, wherein the electromagnetic shielding layer covers the first electronic component, the carrying portion and the filling glue.

[0019] In at least one embodiment of the present invention, the step of forming the initial carrier portion includes forming a second circuit structure layer on the carrier substrate. Thereafter, at least one conductive column is formed on the second circuit structure layer. At least one first chip and at least one second chip are arranged on the second circuit structure layer, wherein the back of the first chip and the back of the second chip are bonded to each other through an adhesive layer. After forming the conductive column, the first chip and the second chip, a first insulating layer is formed on the second circuit structure layer, wherein the first insulating layer covers the conductive column, the first chip and the second chip. Thereafter, a first circuit structure layer is formed on the first insulating layer.

[0020] In at least one embodiment of the present invention, the manufacturing method further comprises removing the carrier substrate after forming the first circuit structure layer.

[0021] In at least one embodiment of the present invention, the step of forming a conductive column includes forming a first photoresist pattern on the second circuit structure layer. Then, using the first photoresist pattern as a mask, at least one first conductive sub-column is formed on the second circuit structure layer. After forming the first conductive sub-column, a second photoresist pattern is formed on the first photoresist pattern and the first conductive sub-column, wherein the second photoresist pattern exposes the first conductive sub-column. Then, using the second photoresist pattern as a mask, at least one second conductive sub-column is formed on the first conductive sub-column.

[0022] Based on the above, since the filling glue does not cover the upper surface of the first electronic component, the chip package is made to have a thinner overall thickness, which is conducive to the development trend of thinning chip packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A is a cross-sectional schematic diagram of a chip package according to at least one embodiment of the present invention.

[0024] Figure 1B yes Figure 1A An enlarged schematic diagram of the middle dotted frame 1B.

[0025] Figures 2A to 2G yes Figure 1A A cross-sectional schematic diagram of a method for manufacturing a chip package in FIG.

[0026] Figure 3A is a cross-sectional schematic diagram of a chip package according to at least one embodiment of the present invention.

[0027] Figure 3B yes Figure 3A A cross-sectional schematic diagram of a chip package manufacturing method at one stage.

[0028] Figure 4A is a cross-sectional schematic diagram of a chip package according to at least one embodiment of the present invention.

[0029] Figure 4Bis a cross-sectional schematic diagram of a chip package according to at least one embodiment of the present invention.

[0030] Figure 5 is a cross-sectional schematic diagram of a chip package according to at least one embodiment of the present invention.

[0031] Figure 6 is a cross-sectional schematic diagram of a chip package according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0032] In the following text, in order to clearly present the technical features of this case, the dimensions (such as length, width, thickness, area or depth) of the elements (such as layers, films, substrates and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the sizes and shapes presented by the elements, but should cover the sizes, shapes and deviations of the two caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, while the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of this case are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the claims of this case.

[0033] Secondly, the words "about", "approximately" or "substantially" that appear in the content of this case not only cover the numerical values ​​and numerical ranges that are clearly recorded, but also cover the permissible deviation range that can be understood by technicians in the technical field of the invention, where this deviation range can be determined by the error generated during measurement, and this error is caused by, for example, the limitations of the measurement system or process conditions. In addition, "about" can mean within one or more standard deviations of the above numerical values, such as ±30%, ±20%, ±10% or ±5%. The words "about", "approximately" or "substantially" that appear in this text can select an acceptable deviation range or standard deviation based on optical properties, etching properties, mechanical properties or other properties, and not just one standard deviation can be applied to all properties such as the above optical properties, etching properties, mechanical properties and other properties.

[0034] Figure 1A is a cross-sectional view of a chip package according to at least one embodiment of the present invention. Figure 1A The chip package 10 includes a first electronic component 11 and a carrier 100, wherein the first electronic component 11 is disposed on the carrier 100. Figure 1AIn the illustrated embodiment, the carrier 100 includes a first circuit structure layer 111 and a first insulating layer 121, wherein the first circuit structure layer 111 is disposed on the first insulating layer 121. In addition, the carrier 100 has a first sidewall 101, and the first sidewall 101 exposes the first circuit structure layer 111 and the first insulating layer 121. Figure 1A shown.

[0035] The first electronic element 11 is disposed on the first circuit structure layer 111 and is electrically connected to the first circuit structure layer 111, so the first circuit structure layer 111 is located between the first electronic element 11 and the first insulating layer 121. The first circuit structure layer 111 may be a redistribution layer (RDL), so the first circuit structure layer 111 may include at least one circuit layer and at least one insulating layer (both are not shown). Figure 1A ). The first insulating layer 121 may be a ceramic layer or a polymer material layer, wherein the polymer material layer is, for example, a resin layer. In addition, the first insulating layer 121 may have photosensitive properties. For example, the first insulating layer 121 may be a photosensitive dielectric material (Photo-Imageable Dielectric, PID).

[0036] exist Figure 1A In the illustrated embodiment, the chip package 10 further includes a plurality of first solders S1, wherein the first solders S1 are disposed between the first electronic component 11 and the first circuit structure layer 111, and connect the first electronic component 11 and the first circuit structure layer 111, so that the first electronic component 11 can be electrically connected to the first circuit structure layer 111 through the first solders S1. In addition, the first solders S1 can support the first electronic component 11, so that a gap G1 exists between the first electronic component 11 and the first circuit structure layer 111, wherein the first solders S1 are disposed in the gap G1.

[0037] exist Figure 1A In the embodiment shown, the first electronic component 11 may be a packaged component. Specifically, the first electronic component 11 may include a carrier 11c and a chip component 11d, wherein the chip component 11d is mounted on the carrier 11c, and the chip component 11d may be an unpackaged die or a packaged chip. In addition, in other embodiments, the first electronic component 11 may also be an unpackaged die. In other words, Figure 1A The carrier 11c shown can be omitted, and the unpackaged chip component 11d can be directly connected to these first solders S1, so that the chip component 11d can be electrically connected to the first circuit structure layer 111 only through the first solders S1 without the carrier 11c.

[0038] It is worth mentioning that in other embodiments, the first electronic component 11 may be a multi-chip package (Multi-Chip Package), such as a system-in-Package (SiP). Therefore, the first electronic component 11 may include at least two chips, wherein the aforementioned chips may be packaged components or unpackaged dies. Therefore, the number of chips (such as packaged components or unpackaged dies) included in the first electronic component 11 may be multiple, not limited to only one.

[0039] The chip package 10 further includes a filler 15, wherein the filler 15 covers the surface of the first circuit structure layer 111 and the first electronic component 11 and fills the gap G1, and the filler 15 can be a bottom filler, not a molding material. The first electronic component 11 has an upper surface U11, a lower surface L11 and a side S11, wherein the upper surface U11 and the lower surface L11 are opposite to each other, and the side S11 surrounds and connects the upper surface U11 and the lower surface L11. Figure 1A From the perspective of FIG. 1 , the chip element 11 d has an upper surface U11 , and the carrier 11 c has a lower surface L11 , wherein the side S11 includes the side of both the chip element 11 d and the carrier 11 c , and the first solders S1 are connected to the lower surface L11 .

[0040] The filling glue 15 covers at least a portion of the side S11 of the first electronic component 11. Figure 1A For example, the filling glue 15 can completely cover the side S11 of the first electronic component 11, so that the filling glue 15 surrounds the first electronic component 11, but does not cover the upper surface U11. In other words, the filling glue 15 will connect the edge of the upper surface U11 of the first electronic component 11. The filling glue 15 has a top surface 15t and a second side wall 15s, wherein the second side wall 15s is flush with the first side wall 101. The second side wall 15s surrounds and connects the top surface 15t. Since the filling glue 15 does not cover the upper surface U11 of the first electronic component 11, the top surface 15t of the filling glue 15 surrounds the upper surface U11 and extends from the side S11 of the first electronic component 11 to the second side wall 15s.

[0041] The filling glue 15 has an angle A1 between the top surface 15t and the second side wall 15s, wherein the angle A1 is greater than 90 degrees. The distance between the top surface 15t and the supporting portion 100 decreases from the side edge S11 of the first electronic component 11 toward the second side wall 15s, so the top surface 15t is an inclined surface. Figure 1A As shown. Figure 1AIn the embodiment shown, the top surface 15t may be a concave curved surface. In other embodiments, the top surface 15t may be a flat surface. An angle A2 between the top surface 15t and the side S11 may be less than 90 degrees, wherein the angle A2 is the contact angle between the filling glue 15 and the side S11 of the first electronic component 11. In addition, Figure 1A The dashed line in represents a tangent line of the top surface 15 t , wherein the dashed line of the angle A1 extends from the edge of the second side wall 15 s , and the dashed line of the angle A2 extends from the side S11 (eg, the edge of the side S11 ).

[0042] exist Figure 1A In the illustrated embodiment, the carrier 100 further includes a plurality of chips: a first chip 132 and a second chip 133. The first chip 132 and the second chip 133 are both disposed in the first insulating layer 121, wherein the first chip 132 is electrically connected to the first circuit structure layer 111, and the first chip 132 is located between the second chip 133 and the first circuit structure layer 111. In addition, similar to the first electronic component 11, at least one of the first chip 132 and the second chip 133 can be a packaged component or an unpackaged die.

[0043] The carrier 100 further includes an adhesive layer 134, wherein the adhesive layer 134 is disposed between the first chip 132 and the second chip 133, and adheres the back of the first chip 132 and the back of the second chip 133, so that the first chip 132 and the second chip 133 can be combined with each other. In addition, the adhesive layer 134 is an insulator, so the first chip 132 and the second chip 133 cannot be electrically connected to each other through the adhesive layer 134.

[0044] The carrier portion 100 also includes a second circuit structure layer 112 electrically connected to a second chip 133, wherein the second chip 133 can be electrically connected to the second circuit structure layer 112 via solder (not shown). The second chip 133 is located between the first chip 132 and the second circuit structure layer 112, so the first chip 132 is located between the second chip 133 and the first electronic component 11. The first insulating layer 121 is sandwiched between the first circuit structure layer 111 and the second circuit structure layer 112. Therefore, the first chip 132 and the second chip 133 disposed in the first insulating layer 121 will be located between the first circuit structure layer 111 and the second circuit structure layer 112. In addition, the gap (not shown) between the second chip 133 and the second circuit structure layer 112 can be filled with bottom filler UF2, such as Figure 1A shown.

[0045] The carrier portion 100 further includes at least one conductive column 113. Figure 1AFor example, the carrier 100 includes a plurality of conductive pillars 113, and the conductive pillars 113 are disposed in the first insulating layer 121. Each conductive pillar 113 may be cylindrical and substantially have a fixed diameter. The conductive pillars 113 are located between the first circuit structure layer 111 and the second circuit structure layer 112, and connect the first circuit structure layer 111 and the second circuit structure layer 112.

[0046] In this way, each conductive column 113 can electrically connect the first circuit structure layer 111 and the second circuit structure layer 112, so that the first circuit structure layer 111 and the second circuit structure layer 112 can be electrically connected to each other through the conductive column 113. In addition, the first electronic component 11, the first chip 132 and the second chip 133 can be electrically connected to each other by using the first circuit structure layer 111, the second circuit structure layer 112 and the conductive column 113, so that electrical signals can be transmitted between the first electronic component 11, the first chip 132 and the second chip 133.

[0047] It should be noted that in Figure 1A In the illustrated embodiment, the carrier 100 includes a plurality of conductive pillars 113. However, in other embodiments, the number of conductive pillars 113 included in the carrier 100 may be only one. Figure 1A The conductive pillars 113 shown are merely examples and are not intended to limit the number of conductive pillars 113 included in the carrier portion 100 .

[0048] Secondly, in Figure 1A In the embodiment shown, the carrier 100 is a package including at least one chip (such as a first chip 132 and a second chip 133), but in other embodiments, the carrier 100 may also be a carrier board or a circuit board without any chip or die. Figure 1A The carrier 100 shown is only for illustration and is not limited to a chip package.

[0049] The second wiring structure layer 112 may also be a redistribution layer (RDL), so the second wiring structure layer 112 may also include at least one wiring layer and at least one insulating layer (neither of which is shown). In at least one embodiment, the number of wiring layers of the first wiring structure layer 111 and the second wiring structure layer 112 may be the same. However, in other embodiments, the difference between the number of wiring layers of the first wiring structure layer 111 and the second wiring structure layer 112 may be used to avoid or weaken the warpage of the carrier 100 caused by thermal expansion. Therefore, the number of wiring layers of the first wiring structure layer 111 and the second wiring structure layer 112 may be different.

[0050] In at least one embodiment, the thickness of the insulating layer or the thickness of the circuit layer of the first circuit structure layer 111 and the second circuit structure layer 112 may be substantially the same. When the thickness of the insulating layer or the thickness of the circuit layer is substantially the same, within the allowable tolerance range, the thickness of the insulating layer or the thickness of the circuit layer of the first circuit structure layer 111 and the second circuit structure layer 112 may be slightly different. In addition, in other embodiments, the thickness of the insulating layer or the thickness of the circuit layer of the first circuit structure layer 111 and the second circuit structure layer 112 may also be significantly different to avoid or weaken the warping of the carrier 100 caused by the difference in thermal expansion coefficient.

[0051] The chip package 10 may further include at least one second electronic component, wherein the second electronic component may be disposed in at least one of the first circuit structure layer 111 and the second circuit structure layer 112. Figure 1A For example, the chip package 10 includes a plurality of second electronic components 141 and 142 , wherein the second electronic components 141 are disposed on the first circuit structure layer 111 , and the second electronic components 142 are disposed on the second circuit structure layer 112 .

[0052] from Figure 1A From the perspective of the embodiment, the second electronic component 141 is located on the upper surface of the first circuit structure layer 111, and the second electronic component 142 is located on the lower surface of the second circuit structure layer 112, wherein the second electronic component 141 is located in the gap G1 and is covered by the filling glue 15. The second electronic component 141 can be welded on the first circuit structure layer 111, wherein the gap (not shown) between the second electronic component 141 and the first circuit structure layer 111 can be filled with the bottom filling glue UF1. In addition, at least one of these second electronic components 141 and 142 can be a passive component, such as a resistor, a capacitor, or an inductor.

[0053] The chip package 10 further includes an electromagnetic shielding layer 16, wherein the electromagnetic shielding layer 16 conformally covers the first electronic component 11, the first side wall 101 of the carrier 100, the top surface 15t and the second side wall 15s of the filling glue 15, so that the electromagnetic shielding layer 16 and the second circuit structure layer 112 cover the first electronic component 11, the first chip 132 and the second chip 133. In addition, the electromagnetic shielding layer 16 can be a metal layer, such as a copper metal layer, and the electromagnetic shielding layer 16 can have a relatively thin thickness 16t, such as between 1 micrometer and 5 micrometers.

[0054] Figure 1B yes Figure 1A The enlarged schematic diagram of the dotted box 1B in the middle. Figure 1A and Figure 1B ,exist Figure 1BIn the illustrated embodiment, the first circuit structure layer 111 includes multiple circuit layers 111g, 111w and multiple insulation layers 111i, wherein the circuit layers 111g, 111w and insulation layers 111i are stacked on each other, and each insulation layer 111i is sandwiched between two adjacent layers of the circuit layers 111g and 111w.

[0055] The electromagnetic shielding layer 16 is connected to and contacts the circuit layer 111g, wherein the circuit layer 111g is a ground layer, which is, for example, a ground plane. Specifically, one side of the circuit layer 111g is exposed to the first side wall 101, so that the electromagnetic shielding layer 16 covering the first side wall 101 can contact and connect the circuit layer 111g. In this way, the electromagnetic shielding layer 16 is electrically connected to the circuit layer 111g and grounded, so that the electromagnetic shielding layer 16 effectively shields electromagnetic waves. In addition, the electromagnetic shielding layer 16 is only electrically connected to the circuit layer 111g, but is not electrically connected to the circuit layer 111w for transmitting electrical signals, so as to avoid a short circuit between the circuit layer 111w and the electromagnetic shielding layer 16.

[0056] It should be noted that, in other embodiments, the circuit layer 111w included in the first circuit structure layer 111 may be only one layer, and may not include any ground layer, so that the electromagnetic shielding layer 16 is not electrically connected to the first circuit structure layer 111. Figure 1B The disclosed electromagnetic shielding layer 16 and the first circuit structure layer 111 are only for illustration, and do not limit the number of circuit layers 111 w and 111 g in the first circuit structure layer 111 .

[0057] Based on the above, since the filling glue 15 does not cover the upper surface U11 of the first electronic component 11, and the electromagnetic shielding layer 16 has a relatively thin thickness 16t, the chip package 10 can have a thinner overall thickness compared to the existing common chip packages, so that the chip package 10 is conducive to thinning, thereby meeting the development trend of existing electronic devices.

[0058] Secondly, from Figure 1A From the perspective of the structure, the filler 15 has a certain content and occupies a considerable proportion in the entire chip package 10, so that the filler 15 affects the warping of the chip package 10. Therefore, the content of the filler 15 can be adjusted, or a filler 15 with a suitable thermal expansion coefficient can be selected to avoid or weaken the warping of the chip package 10. In addition, the filler 15 can also be doped with a heat dissipation material to help the chip package 10 dissipate heat, thereby maintaining or improving the performance of the chip package 10.

[0059] Figures 2A to 2G yes Figure 1A A cross-sectional schematic diagram of a method for manufacturing a chip package in FIG. Figure 2AIn the manufacturing method of the chip package 10, first, a second circuit structure layer 112 is formed on a carrier substrate 20. The carrier substrate 20 may be a rigid substrate, such as a glass plate or a metal plate, and the circuit layer of the second circuit structure layer 112 may be formed by an additive method, a semi-additive method, or a subtractive method.

[0060] exist Figure 2A In the illustrated embodiment, the dimensions (eg, length, width, or area) of the carrier substrate 20 and the second circuit structure layer 112 may be equivalent to the dimensions of a circuit panel or a substrate strip. Figure 2A The sizes of the carrier substrate 20 and the second circuit structure layer 112 are both significantly larger than the size of a single chip package 10 .

[0061] It should be noted that in other embodiments, the sizes of the carrier substrate 20 and the second circuit structure layer 112 may be equivalent to the size of the substrate unit, so the sizes of the carrier substrate 20 and the second circuit structure layer 112 may be significantly smaller than the size of the circuit board or the substrate strip. In addition, in this embodiment, a release layer 21 may be first formed on the carrier substrate 20. Then, the second circuit structure layer 112 is formed on the release layer 21, so that the carrier substrate 20 can be peeled off from the second circuit structure layer 112 in the subsequent process.

[0062] See also Figure 2B Then, at least one conductive column 113 is formed on the second wiring structure layer 112. Figure 2B For example, a plurality of conductive pillars 113 are formed on the second circuit structure layer 112. Since the number of conductive pillars 113 included in the carrier 100 of other embodiments may be only one, Figure 2B In the steps shown, only one conductive pillar 113 may be formed on the second wiring structure layer 112 .

[0063] In the process of forming the conductive pillars 113, a seed layer and a patterned mask layer 22 may be sequentially formed on the second circuit structure layer 112. The seed layer is a metal film and has a relatively thin thickness, so it is not shown in the drawings. The seed layer may be formed by deposition. For example, the seed layer may be formed by physical vapor deposition (PVD) such as sputtering or evaporation.

[0064] The patterned mask layer 22 may be a photoresist pattern after exposure and development, so the patterned mask layer 22 has one or more openings 22h, wherein the openings 22h partially expose the seed layer. The patterned mask layer 22 may have a multi-layer structure. Figure 2B For example, the patterned mask layer 22 may include a first photoresist pattern 22a and a second photoresist pattern 22b, wherein the first photoresist pattern 22a is located between the second photoresist pattern 22b and the carrier substrate 20, and the opening 22h extends through the first photoresist pattern 22a and the second photoresist pattern 22b. In this embodiment, the first photoresist pattern 22a is formed by one exposure and development process, and the second photoresist pattern 22b is formed by another exposure and development process, that is, the opening 22h is formed by two exposure and development processes.

[0065] It should be noted that in other embodiments, the patterned mask layer 22 may only have a single-layer structure. Figure 2B The second photoresist pattern 22b in the patterned mask layer 22 may be omitted, so the opening 22h may be formed by only one exposure and development process. In another embodiment, the patterned mask layer 22 may also include three or more layers of photoresist patterns, so the opening 22h may be formed by at least three exposure and development processes. Afterwards, the conductive pillar 113 is formed on the second circuit structure layer 112 using the patterned mask layer 22 as a mask, wherein the conductive pillar 113 may be formed by electroplating using the above-mentioned seed layer.

[0066] It is worth mentioning that in the present embodiment, the conductive pillar 113 is formed by using a seed layer and a patterned mask layer 22. However, in other embodiments, the conductive pillar 113 may also be formed without any seed layer and patterned mask layer 22. Specifically, the conductive pillar 113 may be a finished metal pillar, such as a copper pillar, and the conductive pillar 113 may be directly disposed on the second circuit structure layer 112, wherein the conductive pillar 113 may be welded to the circuit layer of the second circuit structure layer 112, so that the conductive pillar 113 is electrically connected to the second circuit structure layer 112.

[0067] See also Figure 2C After forming the conductive pillars 113, the patterned mask layer 22 and the seed layer are removed, wherein the seed layer can be removed by etching, such as micro-etching. Then, at least one first chip 132 and at least one second chip 133 are disposed on the second circuit structure layer 112, wherein the back of the first chip 132 and the back of the second chip 133 can be bonded to each other through the adhesive layer 134.

[0068] Since the sizes of the carrier substrate 20 and the second circuit structure layer 112 are equivalent to the size of the circuit board or the substrate strip, the second circuit structure layer 112 can accommodate multiple first chips 132 and multiple second chips 133. In other words, at least one first chip 132 and at least one second chip 133 can be set on the second circuit structure layer 112. After the first chip 132 and the second chip 133 are set on the second circuit structure layer 112, a gap (not marked) will be formed between the second chip 133 and the second circuit structure layer 112. At this time, the bottom filler UF2 can be filled in the aforementioned gap.

[0069] See also Figure 2D After forming the conductive pillars 113, the first chips 132 and the second chips 133, a first insulating layer 121 is formed on the second circuit structure layer 112. The first insulating layer 121 covers all the conductive pillars 113, all the first chips 132 and all the second chips 133, so the size of the first insulating layer 121 is also equivalent to the size of the circuit board or the substrate strip. However, in other embodiments, the sizes of the carrier substrate 20 and the second circuit structure layer 112 can also be equivalent to the size of the substrate unit, so the size of the first insulating layer 121 can also be equivalent to the size of the substrate unit, and the first insulating layer 121 can only cover one first chip 132 and one second chip 133.

[0070] Afterwards, a first circuit structure layer 111 is formed on the first insulating layer 121 to form an initial bearing portion 100i. The circuit layer of the first circuit structure layer 111 (eg Figure 1B The method for forming the circuit layer 111w in the circuit structure layer 112 may be the same as the method for forming the circuit layer of the second circuit structure layer 112, and will not be described again. The initial carrier 100i includes the first circuit structure layer 111, the first insulating layer 121, the conductive pillar 113, the first chip 132 and the second chip 133. The size of the initial carrier 100i may be equivalent to the size of the circuit board or the substrate strip. Alternatively, the size of the initial carrier 100i may also be equivalent to the size of the substrate unit.

[0071] See also Figure 2E After forming the first circuit structure layer 111, the carrier substrate 20 is removed. In the present embodiment, the carrier substrate 20 can be peeled off from the second circuit structure layer 112 through the release layer 21, wherein the release layer 21 can be dissociated by laser or heating to peel the carrier substrate 20 from the second circuit structure layer 112. In other embodiments, the carrier substrate 20 can be a metal plate and can be removed by etching, wherein the second circuit structure layer 112 can be directly formed on the surface of the carrier substrate 20 without forming any release layer 21 on the carrier substrate 20. In other words, FIG. 2A to FIG. 2D The release layer 21 shown may be omitted.

[0072] See also Figure 2E , then, at least one first electronic component 11 and at least one second electronic component 141 are installed on the first circuit structure layer 111, wherein the first electronic component 11 and the second electronic component 141 can be disposed on the first circuit structure layer 111 by flip chip method, and the gap between the second electronic component 141 and the first circuit structure layer 111 can be filled with bottom filler UF1. Therefore, the first electronic component 11 can be disposed on the first circuit structure layer 111 by using a plurality of first solders S1.

[0073] Since the size of the initial carrier 100i can be equivalent to the size of the circuit board or substrate strip, the first circuit structure layer 111 of the initial carrier 100i can provide at least one first electronic component 11 and at least one second electronic component 141 for installation. In addition, after the first electronic component 11 is installed on the first circuit structure layer 111, there will be a gap G1 between the first electronic component 11 and the first circuit structure layer 111, such as Figure 2E shown.

[0074] See also Figure 2F Then, a filling material 15i is formed on the first circuit structure layer 111, wherein the filling material 15i completely covers the upper surface of the initial bearing portion 100i. The filling material 15i may be a glue material and covers all the side edges S11 of the first electronic component 11, wherein the filling material 15i further fills the gap G1, such as Figure 2F shown.

[0075] In this embodiment, the filling material 15i may completely cover the side S11 of the first electronic component 11, so that the filling material 15i surrounds the first electronic component 11 and connects to the edge of the upper surface U11 of the first electronic component 11, but does not cover the upper surface U11. In other embodiments, the filling material 15i may not completely cover the side S11 of the first electronic component 11, that is, the filling material 15i covers a portion of the side S11, but does not cover the other portions of the side S11. Therefore, the filling material 15i may not connect to the edge of the upper surface U11.

[0076] After forming the filling material 15i, the filling material 15i and the initial carrier 100i are cut. Since the size of the initial carrier 100i may be equivalent to the size of the circuit board or the substrate strip, the initial carrier 100i may be cut into a plurality of carriers 100 and a plurality of filling glues 15 disposed on the carrier 100. After cutting the filling material 15i and the initial carrier 100i, a plurality of chip packages 10 may be formed. In addition, the size of the initial carrier 100i may also be equivalent to the size of the substrate unit, so the cut initial carrier 100i may only form one carrier 100 and one filling glue 15, that is, only form one chip package 10.

[0077] See also Figure 2F and Figure 2G Before cutting the filling material 15i, the filling material 15i may be solidified so that the cutter 29 can smoothly cut the filling material 15i. Figure 2F The dashed line shown represents the cutting path of the cutter 29. Since both the filling material 15i and the initial bearing portion 100i are cut by the cutter 29, after the cutter 29 cuts the filling material 15i and the initial bearing portion 100i, the second side wall 15s will be cut flush with the first side wall 101. In addition, in other implementations, other means may be used to cut the filling material 15i, such as laser cutting. Therefore, the use of the cutter 29 to cut the filling material 15i is not limited.

[0078] See also Figure 2G After cutting the filling material 15i and the initial carrier 100i, an electromagnetic shielding layer 16 can be formed, wherein the electromagnetic shielding layer 16 covers the first electronic component 11, the carrier 100 and the filling glue 15. The electromagnetic shielding layer 16 can be formed by physical vapor deposition (PVD), wherein the aforementioned physical vapor deposition is, for example, sputtering or evaporation. Therefore, the electromagnetic shielding layer 16 can conformally cover the upper surface U11 of the first electronic component 11, the first side wall 101 of the carrier 100, the top surface 15t and the second side wall 15s of the filling glue 15.

[0079] See also Figure 1A and Figure 2G Since the angle A1 is greater than 90 degrees and the top surface 15t is an inclined surface, the metal material is advantageously deposited on the top surface 15t of the filling glue 15 during physical vapor deposition (e.g., sputtering), so that the electromagnetic shielding layer 16 can fully cover the upper surface U11 of the first electronic component 11, the first side wall 101 of the carrier 100, the top surface 15t of the filling glue 15, and the second side wall 15s. In this way, the electromagnetic shielding layer 16 can effectively shield electromagnetic waves to reduce or avoid interference of electromagnetic waves on the first electronic component 11, the first chip 132, and the second chip 133.

[0080] After forming the electromagnetic shielding layer 16, a plurality of second solders S2 and a plurality of second electronic components 142 may be disposed on the lower surface of the second circuit structure layer 112 to form a Figure 1A In the chip package 10 shown, the second solders S2 enable the chip package 10 to be mounted on an external circuit board (not shown) so that the chip package 10 is electrically connected to the external circuit board.

[0081] It is worth mentioning that in the above embodiment, the second solder S2 and the second electronic component 142 are disposed on the lower surface of the second circuit structure layer 112 after the electromagnetic shielding layer 16 is formed. However, in other embodiments, the second solder S2 and the second electronic component 142 may be disposed on the lower surface of the second circuit structure layer 112 first. Then, the electromagnetic shielding layer 16 is formed. Therefore, Figure 1A and Figure 2G The disclosed embodiment does not limit the order of forming the electromagnetic shielding layer 16 and disposing the second solder S2 and the second electronic component 142 .

[0082] Figure 3A is a cross-sectional view of a chip package according to at least one embodiment of the present invention. Figure 3A The chip package 30 of the present embodiment is similar to the aforementioned chip package 10. For example, the chip package 30 also includes a filler 15, a first electronic component 11 and a carrier 300, and the carrier 300 includes a first chip 132, a second chip 133, a first circuit structure layer 111, a second circuit structure layer 112, a first insulating layer 121 and a plurality of second electronic components 141 and 142. The differences between the chip packages 30 and 10 are described below, and the same features of the chip packages 30 and 10 are basically not repeated.

[0083] Different from the chip package 10, the carrier portion 300 includes at least one conductive pillar 313, wherein the conductive pillar 313 is different from the conductive pillar 113. Figure 3A For example, the carrier 300 includes a plurality of conductive pillars 313, wherein each conductive pillar 313 includes a first conductive sub-pillar C1 and a second conductive sub-pillar C2, and the first conductive sub-pillar C1 is connected to the second line structure layer 112. In addition, in other embodiments, the carrier 300 may include only one conductive pillar 313. Alternatively, the carrier 300 may include at least one conductive pillar 113 and at least one conductive pillar 313. Therefore, Figure 3A This is only an example and does not limit the shape and number of the conductive pillars 313 .

[0084] The second conductive sub-pillar C2 is stacked on the first conductive sub-pillar C1 and connects the first conductive sub-pillar C1 and the first circuit structure layer 111, so the second conductive sub-pillar C2 is located between the first conductive sub-pillar C1 and the first circuit structure layer 111. Through these conductive pillars 313, the first circuit structure layer 111 and the second circuit structure layer 112 can be electrically connected to each other.

[0085] from Figure 3A From the perspective of FIG. 3 , in the same conductive column 313 , the diameter of the first conductive sub-column C1 is not equal to the diameter of the second conductive sub-column C2 . Figure 3AFor example, in the outermost conductive pillars 313, the diameter of the second conductive sub-pillar C2 is greater than the diameter of the first conductive sub-pillar C1, and the second conductive sub-pillar C2 protrudes from the side of the first conductive sub-pillar C1. In the innermost conductive pillars 313, the diameter of the second conductive sub-pillar C2 is smaller than the diameter of the first conductive sub-pillar C1, and the first conductive sub-pillar C1 protrudes from the side of the second conductive sub-pillar C2. Therefore, each conductive pillar 313 has a significantly different diameter.

[0086] It is worth mentioning that in Figure 3A In the illustrated embodiment, the diameters of the first conductive sub-pillars C1 are not equal to each other, and the diameters of the second conductive sub-pillars C2 are not equal to each other. However, in other embodiments, the diameters of the first conductive sub-pillars C1 may be equal to each other, and the diameters of the second conductive sub-pillars C2 may be equal to each other, wherein the diameter of the first conductive sub-pillars C1 is not equal to the diameter of the second conductive sub-pillars C2. Therefore, the diameter of each second conductive sub-pillar C2 may be greater than the diameter of the first conductive sub-pillar C1. Alternatively, the diameter of each second conductive sub-pillar C2 may be smaller than the diameter of the first conductive sub-pillar C1.

[0087] Figure 3B yes Figure 3A A cross-sectional view of a manufacturing method of a chip package in one stage. Figure 3B The formation methods of the conductive pillars 313 and 113 are similar, but the difference is that the patterned mask layer 32 used to form the conductive pillars 313 is different from the aforementioned patterned mask layer 22. In addition, Figure 3B The disclosed steps can be performed by forming a seed layer on the second circuit structure layer 112 (eg Figure 2A as shown).

[0088] The formation of the conductive pillar 313 may include the following steps. First, a first photoresist pattern 32a is formed on the second circuit structure layer 112, wherein the first photoresist pattern 32a partially exposes a seed layer (not shown) on the second circuit structure layer 112. Next, at least one first conductive sub-pillar C1 is formed on the second circuit structure layer 112 using the first photoresist pattern 32a as a mask, wherein the first conductive sub-pillar C1 may be formed by electroplating using the seed layer.

[0089] After forming the first conductive sub-pillars C1, a second photoresist pattern 32b is formed on the first photoresist pattern 32a and the first conductive sub-pillars C1, wherein the second photoresist pattern 32b exposes the first conductive sub-pillars C1. Next, the second conductive sub-pillars C2 are formed on the first conductive sub-pillars C1 using the second photoresist pattern 32b as a mask, wherein the second conductive sub-pillars C2 can also be formed by electroplating using the first conductive sub-pillars C1.

[0090] The first photoresist pattern 32a and the second photoresist pattern 32b each have a plurality of openings H3a and H3b, wherein the diameters of at least two of the openings H3a and H3b are not equal, so that the diameter of the first conductive column C1 is not equal to the diameter of the second conductive column C2. Figure 3A and Figure 3B In addition, in this embodiment, the first conductive sub-pillar C1 and the second conductive sub-pillar C2 of the same conductive pillar 313 may be substantially coaxial. However, in other embodiments, the first conductive sub-pillar C1 and the second conductive sub-pillar C2 of the same conductive pillar 313 may also be significantly non-coaxial.

[0091] It is worth mentioning that both the first photoresist pattern 32a and the second photoresist pattern 32b are developed photoresist layers, so the steps of forming both the first photoresist pattern 32a and the second photoresist pattern 32b include exposure and development. In other words, the method for forming the conductive pillar 313 disclosed in the above embodiment includes two exposures and two developments. However, in other embodiments, the conductive pillar 313 can also be formed by only one development.

[0092] Specifically, two exposed photoresist layers may be sequentially formed on the second circuit structure layer 112. Then, the two photoresist layers are developed to form Figure 3B The first photoresist pattern 32a and the second photoresist pattern 32b are shown. Therefore, the first photoresist pattern 32a and the second photoresist pattern 32b having openings H3a and H3b can be formed after the same development process. Afterwards, the seed layer on the second circuit structure layer 112 is electroplated to form the first conductive sub-column C1 and the second conductive sub-column C2, wherein the first conductive sub-column C1 and the second conductive sub-column C2 can be formed in the same electroplating process. The aforementioned two photoresist layers can both be positive photoresist layers or negative photoresist layers. Alternatively, the two photoresist layers can be a positive photoresist layer and a negative photoresist layer, respectively.

[0093] Figure 4A is a cross-sectional view of a chip package according to at least one embodiment of the present invention. Figure 4A The chip package 40 of the present embodiment is similar to the aforementioned chip package 10, wherein the chip package 40 and 10 include the same or similar components. For example, the chip package 40 includes a first electronic component 11, a filler 15, an electromagnetic shielding layer 16, second electronic components 141 and 142, and a carrier 400. The differences between the chip packages 40 and 10 are described below, and the same features of the chip packages 40 and 10 are basically not repeated.

[0094] The carrier 400 includes a first circuit structure layer 111, a second circuit structure layer 412, a third circuit structure layer 413, a fourth circuit structure layer 414, a first insulating layer 421, a second insulating layer 422, a first chip 132, and a second chip 133, wherein the second circuit structure layer 412, the third circuit structure layer 413, and the fourth circuit structure layer 414 are all redistribution layers, and each includes at least one circuit layer and at least one insulating layer (not shown). Figure 4A ).

[0095] The number of circuit layers of the four circuit structure layers 111 to 414 may be the same, and the thickness of the insulating layer or the circuit layer of the four circuit structure layers may be substantially the same. Alternatively, the number of circuit layers of the four circuit structure layers 111 to 414 may be different for at least two of them, and the thickness of the insulating layer or the circuit layer of at least two of them may be significantly different, so as to avoid or weaken the warping of the carrier 400 caused by the difference in thermal expansion coefficient.

[0096] The first chip 132 is disposed in the first insulating layer 421 and is electrically connected to the first circuit structure layer 111. The first insulating layer 421 is sandwiched between the first circuit structure layer 111 and the second circuit structure layer 412, and is located between the second insulating layer 422 and the first electronic element 11. The second chip 133 is disposed in the second insulating layer 422, wherein the upper surface of the second chip 133 may be covered by the second insulating layer 422.

[0097] The second chip 133 is electrically connected to the fourth circuit structure layer 414 and can be electrically connected to the fourth circuit structure layer 414 through solder (not shown), wherein the gap (not shown) between the second chip 133 and the fourth circuit structure layer 414 can be filled with bottom filler UF2, such as Figure 4A The third circuit structure layer 413 is disposed on the second insulating layer 422 , and the second insulating layer 422 is sandwiched between the third circuit structure layer 413 and the fourth circuit structure layer 414 .

[0098] The carrier 400 further includes a plurality of second solders S42, wherein the second solders S42 are sandwiched between the second circuit structure layer 412 and the third circuit structure layer 413, and connect the second circuit structure layer 412 and the third circuit structure layer 413. Thus, the second circuit structure layer 412 and the third circuit structure layer 413 can be electrically connected to each other through the second solders S42.

[0099] The carrier 400 may further include a filling layer 45 and a plurality of third solders S43. The filling layer 45 fills the gap between the second circuit structure layer 412 and the third circuit structure layer 413 and covers the second solders S42. The third solders S43 are disposed on the lower surface of the fourth circuit structure layer 414, and the third solders S43 may be the same as the aforementioned second solders S2, wherein the third solders S43 enable the chip package 40 to be mounted on an external circuit board (not shown) and electrically connected to the external circuit board.

[0100] The carrier portion 400 further includes at least one first conductive column 431 and at least one second conductive column 432. The first conductive column 431 is disposed in the first insulating layer 421 and is located between the first circuit structure layer 111 and the second circuit structure layer 412, wherein the first conductive column 431 connects the first circuit structure layer 111 and the second circuit structure layer 412, so that the first circuit structure layer 111 and the second circuit structure layer 412 are electrically connected to each other. The second conductive column 432 is disposed in the second insulating layer 422 and is located between the third circuit structure layer 413 and the fourth circuit structure layer 414, wherein the second conductive column 432 connects the third circuit structure layer 413 and the fourth circuit structure layer 414, so that the third circuit structure layer 413 and the fourth circuit structure layer 414 are electrically connected to each other.

[0101] Through the first circuit structure layer 111, the second circuit structure layer 412, the third circuit structure layer 413, the fourth circuit structure layer 414, these second solders S42, these first conductive columns 431 and these second conductive columns 432, the first electronic component 11, the first chip 132 and the second chip 133 can be electrically connected to each other so that electrical signals can be transmitted between the first electronic component 11, the first chip 132 and the second chip 133.

[0102] It is worth mentioning that in Figure 4A In the illustrated embodiment, the second chip 133 is electrically connected to the fourth circuit structure layer 414 through solder (not shown), wherein bottom filler UF2 is filled between the second chip 133 and the fourth circuit structure layer 414. However, in other embodiments, the second chip 133 may be directly electrically connected to the fourth circuit structure layer 414 without solder, wherein no bottom filler UF2 may be present between the second chip 133 and the fourth circuit structure layer 414.

[0103] Figure 4B is a cross-sectional view of a chip package according to at least one embodiment of the present invention. Figure 4B The chip package 40' of the present embodiment is similar to the aforementioned chip package 40, and only the differences between the chip packages 40' and 40 are described below. The same features of the chip packages 40' and 40 are basically not described again.

[0104] Specifically, the chip package 40' includes a carrier portion 400', wherein the carrier portion 400' is connected to the aforementioned Figure 4A The carrier 400 shown in FIG. 4 is similar to the carrier 400 shown in FIG. For example, the carrier 400' and 400 also include some of the same components, such as the second chip 133, the first chip 132 and the second insulating layer 422. Different from the aforementioned carrier 400, the carrier 400' does not include the bottom filler UF2, so the second chip 133 is directly electrically connected to the fourth circuit structure layer 414 without solder. In addition, the carrier 400' also includes an adhesive layer 134, wherein the adhesive layer 134 is sandwiched between the back of the second chip 133 and the third circuit structure layer 413, and bonds the back of the second chip 133 and the third circuit structure layer 413, as shown in FIG. Figure 4B shown.

[0105] Figure 5 is a cross-sectional view of a chip package according to at least one embodiment of the present invention. Figure 5 The chip package 50 of the present embodiment is similar to the aforementioned chip package 10, wherein the chip package 50 and the chip package 10 include the same or similar components. The difference between the chip package 50 and the chip package 10 is that the filling glue 55 included in the chip package 50 does not completely cover the side edge S11 of the first electronic component 11. Figure 5 For example, the filling glue 55 covers a portion of the side edge S11 , but does not cover other portions of the side edge S11 close to the upper surface U11 .

[0106] It can be seen that the filling glue 55 will not connect to the upper surface U11 of the first electronic component 11, and the first electronic component 11 will protrude from the top surface 55t of the filling glue 55. Secondly, the electromagnetic shielding layer 56 not only covers the upper surface U11 of the first electronic component 11, but also covers part of the side edge S11. Figure 5 In addition, in this embodiment, the filling glue 55 covers the entire side of the carrier 11c and part of the side of the chip element 11d. However, in other embodiments, the filling glue 55 may cover part of the side of the carrier 11c but not the side of the chip element 11d.

[0107] Similar to the aforementioned chip package 10, the electromagnetic shielding layer 56 can be formed by physical vapor deposition (e.g., sputtering or evaporation), and conformally covers the upper surface U11 and the side S11 of the first electronic component 11, the first side wall 101 of the carrier 100, and the top surface 55t and the second side wall 55s of the filling glue 55. The material of the filling glue 55 is the same as that of the aforementioned filling glue 15, and the top surface 55t of the filling glue 55 is also an inclined surface, which can be a flat surface or a concave curved surface.

[0108] Therefore, during the physical vapor deposition (e.g., sputtering) process, since the top surface 55t is an inclined surface, the metal material is advantageously deposited on the top surface 55t of the filling glue 55. Therefore, the electromagnetic shielding layer 56 can fully cover the upper surface U11 of the first electronic component 11, the first side wall 101 of the carrier 100, the top surface 55t and the second side wall 55s of the filling glue 55. In this way, the electromagnetic shielding layer 56 can effectively shield electromagnetic waves to reduce or avoid interference of electromagnetic waves on the first electronic component 11, the first chip 132 and the second chip 133.

[0109] Figure 6 is a cross-sectional view of a chip package according to at least one embodiment of the present invention. Figure 6 The chip package 60 of this embodiment is similar to Figure 4A The chip package 40 is a chip package 60, and the chip package 60 and the chip package 40 also include the same or similar components, such as the first chip 132, the second chip 133 and the filling glue 15. The differences between the chip packages 60 and 40 are mainly introduced below, and the same features of the two are basically not repeated.

[0110] In this embodiment, the active surface 132a of the first chip 132 and the active surface 133a of the second chip 133 face each other, that is, the first chip 132 and the second chip 133 are arranged face to face with each other, wherein the active surfaces 132a and 133a refer to the chip surfaces where the pads (not shown) are present. Figure 6 See Figure 4A and Figure 6 , which is different from the chip package 60, Figure 4A In the embodiment of the present invention, the active surface 132a of the first chip 132 and the active surface 133a ( Figure 4A Not marked) are facing each other, that is, Figure 4A The first chip 132 and the second chip 133 are arranged back to back with each other.

[0111] The chip package 60 includes a first circuit structure layer 111, a second circuit structure layer 614, and a third circuit structure layer 613, wherein the first circuit structure layer 111, the second circuit structure layer 614, and the third circuit structure layer 613 can all be redistribution layers, and the third circuit structure layer 613 is located between the first circuit structure layer 111 and the second circuit structure layer 614. In addition, the chip package 60 also includes at least one first conductive column 631 and at least one second conductive column 632.

[0112] The first conductive pillar 631 is disposed in the first insulating layer 621 and is located between the first circuit structure layer 111 and the third circuit structure layer 613, and the first conductive pillar 631 connects the first circuit structure layer 111 and the third circuit structure layer 613, so that the first circuit structure layer 111 and the third circuit structure layer 613 are electrically connected to each other. The second conductive pillar 632 is disposed in the second insulating layer 622 and is located between the third circuit structure layer 613 and the second circuit structure layer 614, wherein the second conductive pillar 632 connects the third circuit structure layer 613 and the second circuit structure layer 614, so that the third circuit structure layer 613 and the second circuit structure layer 614 are electrically connected to each other.

[0113] The chip package 60 includes a first insulating layer 621 and a second insulating layer 622, wherein the first insulating layer 621 is disposed between the first circuit structure layer 111 and the third circuit structure layer 613, and the second insulating layer 622 is disposed between the second circuit structure layer 614 and the third circuit structure layer 613. The first chip 132 is disposed in the first insulating layer 621 and is electrically connected to the third circuit structure layer 613. The second chip 133 is disposed in the second insulating layer 622 and is electrically connected to the third circuit structure layer 613, wherein the third circuit structure layer 613 is sandwiched between the first chip 132 and the second chip 133, and the active surfaces 132a and 133a both face the third circuit structure layer 613.

[0114] From this we can see that Figure 4A and Figure 6 In the embodiment, the first chip 132 and the second chip 133 can be arranged back to back with each other (eg Figure 4A as shown) or facing each other (as shown Figure 6 However, it should be noted that in other embodiments, the active surface 132a of the first chip 132 and the active surface 133a of the second chip 133 may face the same direction. For example, the active surfaces 132a and 133a both face the first electronic component 11, or face away from the first electronic component 11. Therefore, the first chip 132 and the second chip 133 are not limited to being disposed face to face or back to back.

[0115] also, Figure 6 The third circuit structure layer 613 in the embodiment can be replaced by Figure 4A The second circuit structure layer 412, the third circuit structure layer 413, the second solder S42 and the filling layer 45. Figure 4A The second circuit structure layer 412, the third circuit structure layer 413, the second solder S42 and the filling layer 45 in the embodiment may also be replaced by Figure 6 The third circuit structure layer 613 in FIG. Figure 6 The third circuit structure layer 613 in the Figure 4A The chip package 40 is Figure 4A The second circuit structure layer 412, the third circuit structure layer 413, the second solder S42 and the filling layer 45 in the embodiment can also be applied to Figure 6 A chip package 60 is provided.

[0116] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.

[0117]

Explanation of symbols

[0118] 1B: Virtual frame

[0119] 10, 30, 40, 40', 50: chip package

[0120] 11: First electronic component

[0121] 11c: Carrier board

[0122] 11d: Chip components

[0123] 15, 55: Filling glue

[0124] 15i: Filling material

[0125] 15s, 55s: Second side wall

[0126] 15t, 55t: Top surface

[0127] 16, 56: Electromagnetic shielding layer

[0128] 16t:Thickness

[0129] 20: Carrier substrate

[0130] 21: Release layer

[0131] 22, 32: Patterned mask layer

[0132] 22a, 32a: first photoresist pattern

[0133] 22b, 32b: second photoresist pattern

[0134] 22h, H3a, H3b: Open

[0135] 29: Knife

[0136] 45: Filling layer

[0137] 100, 300, 400, 400': load-bearing part

[0138] 100i: Initial load bearing part

[0139] 101: first side wall

[0140] 111: first circuit structure layer

[0141] 111g, 111w: circuit layer

[0142] 111i: Insulation layer

[0143] 112, 412, 614: Second line structure layer

[0144] 113, 313: Conductive column

[0145] 121, 421, 621: first insulating layer

[0146] 132: First chip

[0147] 132a, 133a: Active surface

[0148] 133: Second chip

[0149] 134: Adhesive layer

[0150] 141, 142: second electronic component

[0151] 413, 613: Third line structure layer

[0152] 414: Fourth line structure layer

[0153] 422, 622: second insulating layer

[0154] 431, 631: first conductive column

[0155] 432, 632: second conductive column

[0156] A1, A2: Angle

[0157] C1: First conductive column

[0158] C2: Second conductive column

[0159] G1: Clearance

[0160] L11: Lower surface

[0161] S1: First solder

[0162] S2, S42: Second solder

[0163] S11: Side

[0164] S43: Third solder

[0165] U11: Top surface

[0166] UF1, UF2: bottom filling.

Claims

1. A chip package, characterized in that: include: The carrying portion has a first side wall and includes a first circuit structure layer and a first insulating layer, wherein the first circuit structure layer is disposed on the first insulating layer, and the first side wall exposes the first circuit structure layer and the first insulating layer; A first electronic component is disposed on the first circuit structure layer, wherein a gap exists between the first electronic component and the first circuit structure layer; A plurality of first solders are disposed in the gap and connect the first electronic element and the first circuit structure layer; as well as A filling glue covers the first circuit structure layer and the side of the first electronic component and fills the gap, wherein the filling glue has a top surface and a second side wall, the second side wall surrounds and connects the top surface and is flush with the first side wall, and the top surface extends from the side of the first electronic component to the second side wall.

2. The chip package according to claim 1, wherein: The filling glue also has an included angle, which is located between the top surface and the second side wall and is greater than 90 degrees.

3. The chip package according to claim 1, wherein: The distance between the top surface and the carrying portion decreases from the side edge of the first electronic component toward the second side wall.

4. The chip package according to claim 1, wherein: The top surface is a concave curved surface.

5. The chip package according to claim 1, wherein: The first electronic component has an upper surface and a lower surface, and the side surrounds and connects the upper surface and the lower surface, wherein the filling glue connects the edge of the upper surface, and the plurality of first solders connect the lower surface.

6. The chip package according to claim 1, wherein: It also includes an electromagnetic shielding layer, wherein the electromagnetic shielding layer conformally covers the first electronic component, the first side wall of the carrying portion, the top surface of the filling glue, and the second side wall.

7. The chip package according to claim 1, wherein: The bearing portion further comprises: A first chip is disposed in the first insulating layer and electrically connected to the first circuit structure layer; A second chip is disposed in the first insulating layer, wherein the first chip is located between the second chip and the first circuit structure layer; An adhesive layer is disposed between the first chip and the second chip and bonds the back of the first chip to the back of the second chip; and The second circuit structure layer is electrically connected to the second chip, wherein the second chip is located between the first chip and the second circuit structure layer, and the first insulating layer is sandwiched between the first circuit structure layer and the second circuit structure layer.

8. The chip package according to claim 7, wherein: Also included is a second electronic component, wherein the second electronic component is disposed on the second circuit structure layer.

9. The chip package according to claim 7, wherein: The bearing portion further comprises: At least one conductive column is disposed in the first insulating layer and located between the first circuit structure layer and the second circuit structure layer, wherein the at least one conductive column connects the first circuit structure layer and the second circuit structure layer.

10. The chip package according to claim 9, wherein: The at least one conductive column comprises: A first conductive column connected to the second circuit structure layer; and The second conductive sub-column is stacked on the first conductive sub-column and connects the first conductive sub-column and the first circuit structure layer, wherein the second conductive sub-column is located between the first conductive sub-column and the first circuit structure layer, and the diameter of the first conductive sub-column is not equal to the diameter of the second conductive sub-column.

11. The chip package according to claim 1, wherein: It also includes a second electronic component, wherein the second electronic component is arranged on the first circuit structure layer.

12. The chip package according to claim 1, wherein: The bearing portion further comprises: A first chip is disposed in the first insulating layer and electrically connected to the first circuit structure layer; A second circuit structure layer, wherein the first insulating layer is sandwiched between the first circuit structure layer and the second circuit structure layer; a second insulating layer, wherein the first insulating layer is located between the second insulating layer and the first electronic element; A second chip is disposed in the second insulating layer, A third circuit structure layer is disposed on the second insulating layer; a fourth circuit structure layer electrically connected to the second chip, wherein the second insulating layer is sandwiched between the third circuit structure layer and the fourth circuit structure layer; and A plurality of second solders are sandwiched between the second circuit structure layer and the third circuit structure layer, and connect the second circuit structure layer and the third circuit structure layer.

13. The chip package according to claim 12, wherein: The bearing portion further comprises: At least one first conductive column is disposed in the first insulating layer and located between the first circuit structure layer and the second circuit structure layer, wherein the at least one first conductive column connects the first circuit structure layer and the second circuit structure layer; and At least one second conductive column is disposed in the second insulating layer and located between the third circuit structure layer and the fourth circuit structure layer, wherein the at least one second conductive column connects the third circuit structure layer and the fourth circuit structure layer.

14. A method for manufacturing a chip package, characterized in that: include: forming an initial bearing portion, wherein the initial bearing portion comprises a first circuit structure layer and a first insulating layer, and the first circuit structure layer is disposed on the first insulating layer; At least one first electronic component is installed on the first circuit structure layer, wherein there is a gap between the at least one first electronic component and the first circuit structure layer; After the at least one first electronic component is installed on the first circuit structure layer, a filling material is formed on the first circuit structure layer, wherein the filling material covers the side of the at least one first electronic component and fills the gap; and After forming the filling material, the filling material and the initial carrying portion are cut to form at least one carrying portion and at least one filling glue disposed on the at least one carrying portion.

15. The method for manufacturing a chip package according to claim 14, wherein: Also includes: After the filling material and the initial carrying portion are cut, an electromagnetic shielding layer is formed, wherein the electromagnetic shielding layer covers the at least one first electronic component, the at least one carrying portion and the at least one filling glue.

16. The method for manufacturing a chip package according to claim 14, wherein: The steps of forming the initial bearing portion include: forming a second circuit structure layer on the carrier substrate; forming at least one conductive column on the second circuit structure layer; At least one first chip and at least one second chip are arranged on the second circuit structure layer, wherein the back of the first chip and the back of the second chip are bonded to each other through an adhesive layer; After forming the at least one conductive column, the at least one first chip and the at least one second chip, forming a first insulating layer on the second circuit structure layer, wherein the first insulating layer covers the at least one conductive column, the at least one first chip and the at least one second chip; and The first circuit structure layer is formed on the first insulating layer.

17. The method for manufacturing a chip package according to claim 16, wherein: Also includes: After the first circuit structure layer is formed, the carrier substrate is removed.

18. The method for manufacturing a chip package according to claim 16, wherein: The step of forming the at least one conductive pillar comprises: forming a first photoresist pattern on the second circuit structure layer; Using the first photoresist pattern as a mask, forming at least one first conductive sub-pillar on the second circuit structure layer; After forming the at least one first conductive sub-pillar, forming a second photoresist pattern on the first photoresist pattern and the at least one first conductive sub-pillar, wherein the second photoresist pattern exposes the at least one first conductive sub-pillar; and Using the second photoresist pattern as a mask, at least one second conductive sub-pillar is formed on the at least one first conductive sub-pillar.

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