An open-drain output driver circuit with constant voltage slew rate

Abstract

This invention discloses a constant voltage slew rate open-drain output driver circuit, relating to the field of electronic equipment technology. It addresses the problem in existing technologies that require an additional bandgap reference module to provide a reference current that does not change with power supply voltage and operating temperature, and where the constant slew rate is entirely determined by the performance of the reference current itself. The circuit includes: a pull-up path, a pull-down path, an overflow path, and a driver transistor, all acting on the target node. A current-sensing resistor is connected in series in the pull-up path. The current-sensing resistor is used to detect the path current in real time and feeds it back as a voltage to the gate-source voltage of the corresponding switch in the overflow path, controlling the degree of current shunting from the overflow path to the pull-up path and maintaining a limited and constant voltage slew rate. The closed-loop control proposed in this invention has the advantages of precise control and strong anti-interference capability, efficiently achieving a constant voltage slew rate at the open-drain output port, thereby improving the reliability and electromagnetic compatibility of the communication bus.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and more particularly to an open-drain output driver circuit with a constant voltage slew rate. Background Technology

[0002] In modern electronic devices and communication systems, open-drain outputs are widely used on various communication buses such as 1-WIRE, I2C, and I3C. Therefore, the open-drain output port driver circuit is an indispensable and important component in the entire interface circuit. A higher slew rate and steeper signal edges on the communication bus result in more high-frequency components, which means more electromagnetic interference (EMI) is generated, thus affecting the operation of surrounding chips. Furthermore, for bus systems like 1-WIRE, which typically have long wiring lengths, excessively steep signal edges can also cause overshoot and ringing. If the communication signal can achieve a limited and constant slew rate, the reliability and electromagnetic compatibility of the communication bus can be effectively improved.

[0003] Therefore, there is an urgent need to provide a simpler and more efficient open-drain output driver circuit with constant voltage slew rate. Summary of the Invention

[0004] The purpose of this invention is to provide an open-drain output driver circuit with constant voltage slew rate to solve the problem in the prior art that an additional bandgap reference module is required to provide a reference current that does not change with the power supply voltage and operating temperature, and the constant slew rate capability is entirely determined by the performance of the reference current itself.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, the present invention provides an open-drain output driver circuit with a constant voltage slew rate, comprising:

[0007] All of these affect the pull-up path, pull-down path, overflow path, and driver transistor of the target node;

[0008] A second resistor is connected in series in the pull-up path; the second resistor is a current sensing resistor; the second resistor is used to detect the current in the path in real time and feed it back as the gate-source voltage of the corresponding switch in the overflow path in the form of voltage, thereby controlling the degree of current shunting of the overflow path to the pull-up path and maintaining a limited and constant voltage slew rate.

[0009] Optionally, the pull-up path includes a first switch, a first resistor, and a second resistor; the first resistor and the second resistor are connected in series between the first switch and the target node;

[0010] The pull-down path includes a second switch; the gate of the first switch is connected to the gate of the second switch.

[0011] The overflow path includes a first switching transistor, a first resistor, and a fourth switching transistor; one end of the first resistor is connected to the first switching transistor, and the other end of the first resistor is connected to the fourth switching transistor.

[0012] The driving transistor includes a third switching transistor and a Miller capacitor; the gate of the third switching transistor is connected to the target node, one end of the Miller capacitor is connected to the gate of the third switching transistor, and the other end of the Miller capacitor is connected to the drain of the third switching transistor.

[0013] Optionally, the node voltage of the target node is the gate voltage of the driving transistor, used to control the turn-on degree of the driving transistor.

[0014] Optionally, if the data input of the open-drain output driver circuit is logic 1, the first switch is turned off and the second switch is turned on; the target node discharges through the pull-down path until it becomes ground voltage, and the third switch is turned off; at this time, the open-drain output port exhibits a high-impedance state, and the bus voltage will be pulled up to the power supply voltage by the external pull-up resistor.

[0015] Optionally, if the data input is logic 0, the second switch is turned off and the first switch is turned on; the target node is charged through the pull-up path until it becomes the power supply voltage, so as to turn on the third switch. At this time, the open-drain output port behaves as a low-impedance path to ground, and the bus voltage will be pulled down to near the ground voltage by the internal driver transistor.

[0016] Optionally, when a reference current is not used to provide the path current of the pull-up path, the path current of the pull-up path varies with the power supply voltage and operating temperature. At low temperature and high voltage, the path current of the pull-up path increases by a factor of two; at high temperature and low voltage, the path current of the pull-up path decreases by a factor of two.

[0017] Optionally, if the current in the pull-up path is too large, the fourth switch is turned on, and the overflow path is opened.

[0018] Optionally, when the current in the pull-up path increases, the gate-source voltage of the fourth switch also increases, the on-resistance of the fourth switch as a switch decreases, the current diverted by the overflow path increases, and the degree of slowdown in the charging speed of the target node also increases.

[0019] Optionally, when the current diverted by the overflow path is greater than the preset current value, the current in the pull-up path decreases, the voltage across the second resistor decreases, the gate-source voltage of the fourth switch decreases, the on-resistance of the fourth switch as a switch increases, the current diverted by the overflow path decreases, and the degree of slowdown on the charging speed of the target node is weakened.

[0020] Compared with existing technologies, this invention provides a constant voltage slew rate open-drain output driver circuit, comprising: a pull-up path, a pull-down path, an overflow path, and a driving transistor, all acting on the target node; a current-sensing resistor is connected in series in the pull-up path; the current-sensing resistor is used to detect the path current in real time and feed it back as the gate-source voltage of the corresponding switch in the overflow path in voltage form, thereby controlling the degree of current shunting of the overflow path to the pull-up path and maintaining a limited and constant voltage slew rate. This invention uses a current-sensing resistor connected in series in the pull-up path to detect the path current in real time and feeds back the sensing result as the gate-source voltage of the fourth switch in voltage form, thereby controlling the degree of current shunting of the overflow path to the pull-up path, ultimately achieving a limited and constant voltage slew rate; it eliminates the need for an additional bandgap reference module to provide reference current, and also eliminates the need for any comparators or switch arrays, thus effectively saving layout area and reducing chip cost. Furthermore, the closed-loop control proposed in this invention has the advantages of precise control and strong anti-interference capability, efficiently achieving a constant voltage slew rate at the open-drain output port, thereby improving the reliability and electromagnetic compatibility of the communication bus. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 This is a schematic diagram of a conventional open-drain output driver without slew rate limitations.

[0023] Figure 2 This is a schematic diagram of an open-drain output driver circuit in the prior art;

[0024] Figure 3 This is a schematic diagram of an open-drain output driver circuit with constant voltage slew rate provided by the present invention.

[0025] Figure label:

[0026] 1-Pull-up path, 2-Pull-down path, 3-Overflow path, 4-Driver transistor, M1-First switch transistor, M2-Second switch transistor, M3-Third switch transistor, M4-Fourth switch transistor, R1-First resistor, R2-Second resistor, C-Miller capacitor, G-Target node. Detailed Implementation

[0027] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0028] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0029] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0030] Conventional open-drain output drivers without slew rate limitations, such as Figure 1 As shown, the input signal, after passing through an inverter, directly controls the gate voltage of driver transistor 4. Existing slew rate limiting techniques include... Figure 2 As shown, a reference current is used as the pull-up path 1 of the inverter. The voltage rise of the drive transistor 4 is controlled by charging the capacitor with a constant current, thereby limiting the voltage slew rate of the open-drain output signal to a constant value. The advantage of this scheme is that the slew rate is limited and constant. The disadvantage is that an additional bandgap reference module is needed to provide a reference current that does not change with the power supply voltage and operating temperature, and the ability to maintain a constant slew rate is entirely determined by the performance of the reference current itself.

[0031] To address the problems in the prior art, this invention provides an open-drain output driver circuit with a constant voltage slew rate. The solutions provided in the embodiments of this specification will now be described in conjunction with the accompanying drawings:

[0032] This invention provides an open-drain output driver circuit with a constant voltage slew rate. For example... Figure 3 As shown, it may include:

[0033] All of these are applied to the pull-up path 1, pull-down path 2, overflow path 3, and drive transistor 4 of the target node G;

[0034] A second resistor R2 is connected in series in the pull-up path 1; the second resistor R2 is a current sensing resistor; the second resistor R2 is used to detect the current in the path in real time and feed it back as the gate-source voltage of the corresponding switch in the overflow path 3 in the form of voltage, thereby controlling the degree of current shunting of the overflow path 3 to the pull-up path 1 and maintaining a limited and constant voltage slew rate.

[0035] based on Figure 3 The structural diagram is shown below. The embodiments in this specification can further refine the open-drain output driver circuit with constant voltage slew rate provided by the present invention, which will be described below.

[0036] The pull-up path 1 includes a first switch M1, a first resistor R1, and a second resistor R2; the first resistor R1 and the second resistor R2 are connected in series between the first switch M1 and the target node G.

[0037] The first switching transistor M1 can be a PMOS switching transistor, the first resistor R1 can be a current limiting resistor, and the second resistor R2 can be a current sensing resistor.

[0038] The pull-down path 2 includes a second switch M2; the gate of the first switch M1 is connected to the gate of the second switch M2.

[0039] The second switch M2 can be an NMOS switch.

[0040] The overflow path 3 includes a first switch M1, a first resistor R1, and a fourth switch M4; one end of the first resistor R1 is connected to the first switch M1, and the other end of the first resistor R1 is connected to the fourth switch M4.

[0041] The fourth switch M4 can be a PMOS switch.

[0042] The driving transistor 4 includes a third switching transistor M3 and a Miller capacitor C; the gate of the third switching transistor M3 is connected to the target node G, one end of the Miller capacitor C is connected to the gate of the third switching transistor M3, and the other end of the Miller capacitor C is connected to the drain of the third switching transistor M3.

[0043] The number of switching transistors and resistors in the above structure can be increased or decreased according to actual needs. Among them, the fourth switching transistor M4 can be a PMOS switching transistor, a transistor, a switch, a voltage-controlled switch, a voltage-controlled resistor, etc.

[0044] Therefore, as Figure 3 As shown, the simple and efficient closed-loop control circuit provided by this invention includes: a pull-up path 1, a pull-down path 2, an overflow path 3, and a driving transistor 4. The pull-up path 1 consists of a PMOS switch (first switch M1), a current-limiting resistor (first resistor R1), and a current-sensing resistor (second resistor R2). The pull-down path 2 consists of an NMOS switch (second switch M2). The overflow path 3 consists of a PMOS switch (first switch M1), a current-limiting resistor (first resistor R1), and a PMOS switch (fourth switch M4). The driving transistor 4 consists of a PMOS switch (third switch M3) and a Miller capacitor C. The pull-up path 1, pull-down path 2, and overflow path 3 all act on the target node G, whose voltage is the gate voltage of the driving transistor 4, and are responsible for controlling the turn-on degree of the driving transistor 4.

[0045] Figure 3 In the structure, a current sensing resistor (second resistor R2) is added to the pull-up path 1 to detect the path current in real time and feed back the sensing result as the gate-source voltage of the fourth switch M4 in the form of voltage, thereby controlling the degree of current shunting of the overflow path 3 to the pull-up path 1, and finally achieving a limited and constant voltage slew rate.

[0046] By adding a fourth switch M4 to overflow path 3, closed-loop control can be achieved. No additional bandgap reference module is needed to provide the reference current, nor are any comparators or switch arrays required, thus effectively saving layout area and reducing chip cost.

[0047] Furthermore, regarding the above Figure 3 The circuit structure and its corresponding working principle are as follows:

[0048] If the data input is logic 1, then the first switch M1 is turned off and the second switch M2 is turned on. The target node G will discharge through pull-down path 2 until it reaches ground voltage gnd, thereby turning off the third switch M3. At this time, the open-drain output port exhibits a high-impedance state, and the bus voltage will be pulled up to the power supply voltage Vdd by the external pull-up resistor. The rise time of the bus voltage in this process is entirely determined by the external pull-up resistor and the load capacitance, and this invention does not impose any restrictions on this process.

[0049] If the data input is logic 0, then the second switch M2 is turned off and the first switch M1 is turned on. The target node G will be charged through pull-up path 1 until it reaches the power supply voltage Vdd, thereby turning on the third switch M3. At this time, the open-drain output port exhibits a low-impedance path to ground, and the bus voltage will be pulled down to near the ground voltage Gnd by the internal driver transistor 4 (fourth switch M4). The bus voltage drop time in this process is mainly determined by the charging speed of the target node G. The present invention limits the voltage slew rate of this process.

[0050] Without using a reference current to provide the path current of pull-up path 1, the path current varies significantly with the power supply voltage and operating temperature: at low temperature and high voltage, the current increases exponentially; while at high temperature and low voltage, the current decreases exponentially. This invention uses a current-sensing resistor connected in series in pull-up path 1 to detect the path current in real time, and feeds back the sensing result as a voltage to the gate-source voltage of the fourth switch M4, thereby controlling the degree of current shunting from the overflow path 3 to pull-up path 1, ultimately achieving a limited and constant voltage slew rate.

[0051] If the current in pull-up path 1 is too large, the fourth switch M4 will turn on, and overflow path 3 will conduct, creating a direct current path from Vdd to Gnd and diverting some of the current from pull-up path 1, thus slowing down the charging speed of the target node G. Furthermore, the larger the current in pull-up path 1, the larger the gate-source voltage of the fourth switch M4 will be, the smaller the on-resistance of the fourth switch M4 as a switch, and the larger the current diverted by overflow path 3, thus increasing the slowdown on the charging speed of the target node G. Conversely, when the current diverted by overflow path 3 is too large, the current in pull-up path 1 decreases, the voltage across the current sensing resistor (second resistor R2) decreases, i.e., the gate-source voltage of the fourth switch M4 decreases, the on-resistance of the fourth switch M4 as a switch increases, and the current diverted by overflow path 3 also decreases, thus weakening the slowdown on the charging speed of the target node G. This negative feedback process achieves closed-loop control of the voltage slew rate, thereby maintaining a constant voltage slew rate.

[0052] Therefore, the open-drain output driver circuit with constant voltage slew rate provided by the present invention can achieve at least the following technical effects:

[0053] 1) The present invention provides a simple and efficient circuit structure. By adding a fourth switch M4 to the circuit, closed-loop control can be achieved. No additional bandgap reference module is needed to provide the reference current, nor are any comparators or switch arrays required, thus effectively saving layout area and reducing chip cost.

[0054] 2) This invention is based on closed-loop control with negative feedback. Compared with the open-loop control of traditional technical solutions, the closed-loop control proposed in this invention has the advantages of precise control and strong anti-interference ability.

[0055] 3) This invention can achieve a constant voltage slew rate at the open-drain output port in a simple and efficient manner, thereby improving the reliability and electromagnetic compatibility of the communication bus.

[0056] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0057] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A constant voltage slew rate open-drain output driver circuit, characterized in that, include: All of these affect the pull-up path, pull-down path, overflow path, and driver transistor of the target node; A second resistor is connected in series in the pull-up path; the second resistor is a current sensing resistor; the second resistor is used to detect the current in the path in real time and feed it back as the gate-source voltage of the corresponding switch in the overflow path in the form of voltage, thereby controlling the degree of current shunting of the overflow path to the pull-up path and maintaining a limited and constant voltage slew rate. The pull-up path includes a first switch, a first resistor, and a second resistor; the first resistor and the second resistor are connected in series between the first switch and the target node. The source of the first switching transistor is connected to the power supply voltage Vdd, the drain of the first switching transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the target node. The pull-down path includes a second switch; the gate of the first switch is connected to the gate of the second switch; the drain of the second switch is connected to the target node, and the source of the second switch is grounded (gnd). The overflow path includes a first switch, a first resistor, and a fourth switch; one end of the first resistor is connected to the first switch, and the other end of the first resistor is connected to the fourth switch; the other end of the first resistor is connected to the source of the fourth switch, the drain of the fourth switch is grounded (gnd), and the gate of the fourth switch is connected to the second end of the second resistor. The driving transistor includes a third switching transistor and a Miller capacitor; the gate of the third switching transistor is connected to the target node, one end of the Miller capacitor is connected to the gate of the third switching transistor, and the other end of the Miller capacitor is connected to the drain of the third switching transistor; the source of the third switching transistor is grounded (gnd). When the pull-up path current is not provided by a reference current, the pull-up path current varies with the power supply voltage and operating temperature. At low temperature and high voltage, the pull-up path current increases exponentially; at high temperature and low voltage, the pull-up path current decreases exponentially.

2. The open-drain output driver circuit with constant voltage slew rate according to claim 1, characterized in that, The node voltage of the target node is the gate voltage of the driving transistor, which is used to control the turn-on degree of the driving transistor.

3. The open-drain output driver circuit with constant voltage slew rate according to claim 2, characterized in that, If the data input of the open-drain output driver circuit is logic 1, then the first switch is turned off and the second switch is turned on; the target node discharges through the pull-down path until it becomes ground voltage, and the third switch is turned off. At this time, the open-drain output port exhibits a high-impedance state, and the bus voltage will be pulled up to the power supply voltage by the external pull-up resistor.

4. The open-drain output driver circuit with constant voltage slew rate according to claim 2, characterized in that, If the data input is logic 0, the second switch is turned off and the first switch is turned on; the target node is charged through the pull-up path until it becomes the power supply voltage, so as to turn on the third switch. At this time, the open-drain output port behaves as a low-impedance path to ground, and the bus voltage will be pulled down to near the ground voltage by the internal driver transistor.

5. The open-drain output driver circuit with constant voltage slew rate according to claim 2, characterized in that, If the current in the pull-up path is too large, the fourth switch will be turned on, and the overflow path will be opened.

6. The open-drain output driver circuit with constant voltage slew rate according to claim 2, characterized in that, When the current in the pull-up path increases, the gate-source voltage of the fourth switch also increases, the on-resistance of the fourth switch as a switch decreases, the current diverted by the overflow path increases, and the degree of slowdown in the charging speed of the target node also increases.

7. The open-drain output driver circuit with constant voltage slew rate according to claim 2, characterized in that, When the current diverted by the overflow path exceeds the preset current value, the current in the pull-up path decreases, the voltage across the second resistor decreases, the gate-source voltage of the fourth switch decreases, the on-resistance of the fourth switch as a switch increases, the current diverted by the overflow path decreases, and the slowdown on the charging speed of the target node is weakened.

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