High-frequency quartz wafer manufacturing method and high-frequency quartz wafer

Abstract

The invention relates to the technical field of semiconductor preparation processes, in particular to a high-frequency quartz wafer manufacturing method and a high-frequency quartz wafer, folding force is applied to the back surface of a wafer, and the force is guided at a folding point of the front surface, so that directional expansion of cracks is promoted. The design is based on a specific conversion relation between the wafer thickness and corrosion process parameters, under the condition that the corrosion parameters are certain, by changing the transverse spacing, the V-shaped angle, the V-shaped corrosion width and the shading spacing of the corrosion patterns, the method can be flexibly applied to manufacturing of wafers with different thicknesses, especially ultra-high-frequency thin products (the thickness is smaller than or equal to 20 microns), and the production efficiency of the ultra-high-frequency thin products is improved. According to the utility model, good overall structural strength can be kept, the wafer can be easily separated from the wafer, the wafer is effectively prevented from being damaged or unnecessarily protruded, the overall performance of the wafer is ensured, the requirements of subsequent processing and transportation are met, the production reliability and efficiency are ensured, and the technical problem of ultrahigh frequency wafer production is solved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor preparation technology, and in particular to a high-frequency quartz wafer manufacturing method and a high-frequency quartz wafer. Background Art

[0002] With the development of the 5G market, quartz resonators are also moving towards higher frequencies (quartz wafers are becoming thinner and thinner). How to mass-produce high-frequency chips is a technical problem that needs to be solved urgently.

[0003] When processing the packaging process of quartz resonator chips, separating individual chips from the quartz wafer is a key step. Usually, it is necessary to use a folding machine to automatically or manually separate the individual chips from the wafer. However, in this process, the chips may be defective or have unnecessary protrusions, which affects the reliability and performance of the final product. In addition, when designing the folding method, the structural strength of the chip must be considered at the same time, especially for high-frequency chips (thin chips). If the structural strength is too strong, the chip is not easy to fold or it will be obviously defective or protruding when folded vigorously, thus affecting the subsequent processing of the chip and the overall performance of the chip; if the structural strength is too weak, the chip will fall off with a slight force, which is not convenient for subsequent processing and transportation of the chip. Therefore, it is a key problem to ensure that the structure of the high-frequency chip is reasonable, and to ensure that the performance of the final product is stable and conducive to subsequent processing and transportation after folding. Summary of the invention

[0004] The object of the present invention is to provide a high-frequency quartz wafer manufacturing method and a quartz wafer, so as to solve the problems that the wafer has low structural strength, is easy to fall, and is damaged or has protrusions of excess material during the separation process.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions: A method for manufacturing a high-frequency quartz wafer comprises the following steps: S1. Process the quartz to the target thickness and coat the front and back surfaces of the quartz with a two-layer film structure. The bottom layer is chromium with a thickness of 5 to 50 nm and the top layer is gold with a thickness of ≥100 nm. S2, the front side of the quartz is coated with a photosensitive photoresist material, and the wafer area is exposed to pattern. The photolithography processes the wafer pattern and the folding area at the same time, and the back side is coated with photoresist and hardened for protection; S3, using a gold etching solution and a chromium etching solution in sequence to etch the area exposed by the photoresist to expose the quartz sheet; S4, stripping and removing the photoresist on the surface of the quartz wafer; S5, using an etching solution to etch the quartz wafer, etching the metal etched exposed area downward, and processing the folded area while etching out the wafer pattern; S6. After the etching is completed, use gold or chromium etching solution to remove the metal on the surface of the quartz sheet; S7. Fold the chip off the wafer.

[0006] A further technical solution is that the folded area is etched in turn with a gold etching solution and a chromium etching solution to expose the photoresist, and the etching shape is a V-shape rotated 90 degrees, wherein the wafer thickness is directly proportional to the height and width of a single V-shaped pattern, and the wafer thickness is inversely proportional to the spacing between two V-shaped patterns in the same direction and the spacing between two V-shaped patterns in the opposite direction.

[0007] A further technical solution is that in step S3, the gold etching solution is usually an aqueous solution prepared with iodine and potassium iodide, and the chromium etching solution is an aqueous solution prepared with nitric acid and ammonium cerium nitrate.

[0008] A further technical solution is that the photoresist stripping and removal in step S4 is carried out by plasma stripping or chemical stripping.

[0009] A further technical solution is that in step S5, the etching solution contains hydrofluoric acid, a corrosion inhibitor and a surfactant, and the etching time is affected by the thickness of the wafer.

[0010] A further technical solution is that in step S6, the gold etching solution is an aqueous solution prepared from iodine and potassium iodide, and the chromium etching solution is an aqueous solution prepared from nitric acid and ammonium cerium nitrate.

[0011] A high-frequency quartz wafer is manufactured by adopting a high-frequency quartz wafer manufacturing method.

[0012] Compared with the prior art, the present invention has at least one of the following beneficial effects: 1. The chip folding design provided by the present invention is to apply a folding force on the back of the wafer and guide the force at the folding point on the front to promote the directional expansion of cracks. The design is based on the specific conversion relationship between the chip thickness and the etching process parameters. Under certain etching parameter conditions, by changing the lateral spacing of the etching pattern, the V-shaped angle, the V-shaped etching width, and the shading spacing, it can be flexibly applied to the production of chips of different thicknesses, especially ultra-high frequency thin products (thickness ≤ 20μm), which can maintain good overall structural strength, thereby meeting the needs of subsequent processing and transportation, ensuring production reliability and efficiency, and solving a technical problem in the production of ultra-high frequency chips.

[0013] 2. In practical applications, the quartz chip design provided by the method can not only easily separate the chip from the wafer, but also effectively avoid defects or unnecessary protrusions on the chip, thereby ensuring the overall performance of the chip.

[0014] 3. In addition, this method does not add any additional wafer processing steps, does not increase the complexity of the wafer structure, reduces production difficulty and cost, and improves production qualification rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is the wafer folding pattern arrangement method 1 in the present invention.

[0016] Figure 2 This is the wafer folding pattern arrangement method 2 in the present invention.

[0017] Figure 3 This is the wafer folding pattern arrangement method 3 in the present invention.

[0018] Figure 4 It is a schematic diagram of the wafer folding protrusion in the present invention.

[0019] Figure 5 It is a schematic diagram of the chip folding defect in the present invention.

[0020] Figure 6 This is a schematic diagram of a wafer falling due to slight force in the present invention.

[0021] Figure 7 It is a schematic diagram showing the folding area in the present invention.

[0022] Figure 8 It is a schematic diagram of the folding area in the present invention.

[0023] Fig. 9 Another schematic diagram showing the folding area in the present invention.

[0024] Fig.10 Schematic diagram of the frequency response characteristics of a chip without notches / protrusions at different temperatures.

[0025] Fig.11 Schematic diagram of the frequency response characteristics of a chip with a slight notch or protrusion at different temperatures.

[0026] Fig.12 Schematic diagram of the frequency response characteristics of a chip with an obvious notch or protrusion at different temperatures.

[0027] Fig.13 A single V-shaped diagram of a chip. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] Embodiment 1: refer to Figures 1 to 13 As shown, a method for manufacturing a high-frequency quartz wafer is disclosed, comprising the following steps: S1. Process the quartz to the target thickness and coat the front and back surfaces of the quartz with a two-layer film structure. The bottom layer is chromium with a thickness of 5 to 50 nm and the top layer is gold with a thickness of ≥100 nm. S2, the front side of the quartz is coated with a photosensitive photoresist material, and the wafer area is exposed to pattern. The photolithography processes the wafer pattern and the folding area at the same time, and the back side is coated with photoresist and hardened for protection; S3, using a gold etching solution and a chromium etching solution in sequence to etch the area exposed by the photoresist to expose the quartz sheet; S4, stripping and removing the photoresist on the surface of the quartz wafer; S5, using an etching solution to etch the quartz wafer, etching the metal etched exposed area downward, and processing the folded area while etching out the wafer pattern; S6. After the etching is completed, use gold or chromium etching solution to remove the metal on the surface of the quartz sheet; S7. Fold the chip off the wafer.

[0030] When processing the packaging process of quartz resonator chips, separating individual chips from the quartz wafer is a key step. Usually, a chip folding machine is used to automatically or manually separate the individual chips from the wafer. However, during this process, the chips may be damaged or have unnecessary protrusions (such as Figure 4 and Figure 5 In addition, the structural strength of the wafer must be considered when designing the folding method, especially for high-frequency wafers (thin wafers). If the structural strength is too strong, the wafer will be difficult to fold or will be easily damaged or bulged (such as Figure 4 and Figure 5 As shown), the subsequent processing of the chip and the overall performance of the chip are affected; if the structural strength is too weak, the chip will fall off when subjected to a slight force (as shown Figure 6 As shown), it is not convenient for subsequent processing and transportation of the wafer.

[0031] In the present invention, a folding force is applied to the back of the wafer, and the force is guided at the folding point on the front side to promote the directional expansion of cracks. The design is based on a specific conversion relationship between wafer thickness and etching process parameters. Under certain etching parameter conditions, by changing the lateral spacing of the etching pattern, the V-shaped angle, the V-shaped etching width, and the light shielding spacing, it can be flexibly applied to the production of wafers of different thicknesses, especially ultra-high frequency thin products (thickness ≤ 20μm), which can maintain good overall structural strength, thereby meeting the needs of subsequent processing and transportation, ensuring production reliability and efficiency, and solving a technical problem in ultra-high frequency wafer production.

[0032] The specific conversion relationship between wafer thickness and etching process parameters is as follows: etching time = K1*wafer thickness / etching rate; K1 value is between 2.4 and 3.4. The etching rate is adjusted by solution ratio, temperature, solution flow rate, crystal rotation speed, etc., and the etching rate is controlled between 0.2 and 0.5 μm / min.

[0033] Specifically, the three-dimensional morphology after corrosion is controlled by controlling the shape and size of the corrosion area. The morphology forms a groove with a certain depth to guide the action of external force, so that the crack expands along a predetermined path, and finally achieves the effect of neatly breaking the wafer off from the wafer.

[0034] like Figure 1 Shown and Fig.12 As shown, the corrosion area is a black area, and there are folded areas at both ends of the wafer surface. The folded areas will be corroded in the subsequent wafer etching process, and the corroded shape is a V-shape rotated 90 degrees. Figure 1 The distance between two V-shaped patterns in the same direction (i.e. Figure 1 As shown in the mark A), the width of a single V-shaped pattern (i.e. Figure 1 As shown by the mark D in the figure), the distance between the two reverse V-shaped patterns (i.e. Figure 1 The height of a single V-shaped pattern (i.e. Figure 1 (As shown in the mark C in the figure), the design is mainly affected by the thickness of the wafer. The wafer thickness is proportional to the height and width of a single V-shaped pattern, and the wafer thickness is inversely proportional to the spacing between two V-shaped patterns in the same direction and the spacing between two reverse V-shaped patterns. For wafers with a thickness of 5~50μm, the height of a single V-shaped pattern ranges from 5~50um, the width of a single V-shaped pattern ranges from 5~20um, the spacing between two V-shaped patterns in the same direction is basically 0.5~2 times the width of a single V-shaped pattern, and the spacing between two reverse V-shaped patterns is greater than the width of a single V-shaped pattern, ranging from 0~30μm. After the etching process, these patterns will form a V-shaped groove of about 5~25μm. The depth of the V-groove is affected by the height of a single V-shaped pattern, the width of a single V-shaped pattern and the parameters of the etching process. The process is controlled so that the depth of the processed V-groove is less than half the thickness of the wafer.

[0035] All values ​​affect the overall structural strength of the chip. The larger the distance between two V-shaped patterns in the same direction and the distance between two V-shaped patterns in opposite directions, the greater the structural strength. The larger the height of a single V-shaped pattern and the width of a single V-shaped pattern, the greater the V-groove depth and the smaller the structural strength of the chip.

[0036] The folding pattern is arranged in a V-shaped pattern that is rotated 90 degrees so that the V mouth faces right. There is no reverse V-shaped pattern, such as Figure 2As shown; or the V-shaped graphic area is divided into two parts, the left part of the V-shaped is rotated 90 degrees so that the V-mouth faces right, and the right part of the V-shaped is rotated 270 degrees so that the V-mouth faces left. The number of V-shaped graphics in the left and right parts should be roughly the same, such as Figure 1 and Figure 3 The specific number and arrangement of V-shaped patterns can be adjusted according to the thickness and width of the wafer to ensure that the wafer is intact after folding and reaches a certain structural strength before folding, which is conducive to subsequent processing and transportation.

[0037] In practical applications, the quartz chip design provided in this embodiment can not only easily separate the chip from the wafer, but also effectively avoid chip defects or unnecessary protrusions, thereby ensuring the overall performance of the chip. For example, when a chip with a nominal frequency of 76.8MHz has no notches / protrusions, the chip has good frequency response characteristics at different temperatures, showing that the main frequency is stable, the parasitic frequency is small and weak, such as Fig.10 As shown in the figure, when there is a slight notch or protrusion on the chip (notch / protrusion size ≈ 15μm), the frequency response characteristics of the chip at different temperatures are poor, which is manifested as many and strong parasitic frequencies and a certain deviation of the main frequency, such as Fig.11 As shown in the figure, when there is an obvious notch or protrusion on the chip (notch / protrusion size ≈ 25μm), the frequency response characteristics of the chip at different temperatures are worse, which is manifested as more and stronger parasitic frequencies, poor main frequency stability, and large offset, such as Fig.12 shown.

[0038] Specifically, in step S3, the gold etching solution is usually an aqueous solution prepared with iodine and potassium iodide, and the chromium etching solution is an aqueous solution prepared with nitric acid and ammonium cerium nitrate. Here, the gold etching solution is usually an aqueous solution prepared with iodine and potassium iodide, which is a conventionally prepared solution, and the chromium etching solution is an aqueous solution prepared with nitric acid and ammonium cerium nitrate, which is also a conventionally prepared solution.

[0039] The quartz sheet is exposed by etching the region exposed by the photoresist using a gold etching solution and a chromium etching solution in sequence.

[0040] In step S4, the photoresist stripping and removal adopts plasma stripping or chemical stripping method, which is a conventional stripping method and will not be described in detail here.

[0041] In step S5, the etching solution contains hydrofluoric acid, corrosion inhibitors and surfactants. The etching time is affected by the thickness of the wafer, and the specific influence is etching time = K* wafer thickness / corrosion rate; wherein the K value is between 2.4 and 3.4. The etching rate is adjusted by the solution ratio, temperature, flow rate, etc., and is roughly controlled between 0.2 and 0.5 μm / min. The cross-section of the wafer under this etching process is trapezoidal in the long side direction and parallelogram-like in the short side direction. The side edges are all primary crystal edges, which helps the product to obtain better electrical performance indicators. In addition, this etching process has little damage to the gold mask, and a wafer with almost no corrosion pits can be obtained. Figure 7 , Figure 8 and Fig. 9 shown.

[0042] In step S6, the gold etching solution is an aqueous solution prepared by iodine and potassium iodide, and the chromium etching solution is an aqueous solution prepared by nitric acid and ammonium cerium nitrate. At this time, the folded area is shown as Figure 7 Left part and Figure 8 shown.

[0043] After the corrosion is completed, gold and chromium etching solutions are used to chemically react with the metal on the surface of the quartz sheet, thereby removing the metal on the surface of the quartz sheet. At this time, the folded area appears as follows: Figure 7 Right part and Fig. 9 As shown, it can be found that there is almost no obvious protrusion or defect in the wafer folding area, ensuring the integrity of the wafer.

[0044] Embodiment 2: A high-frequency quartz wafer is manufactured by the method in the above-mentioned embodiment 1. The wafer not only has a certain structural strength and is not easy to fall, but also will not be damaged or have excess material protruding during the separation process, thereby ensuring that subsequent processing steps can be carried out smoothly and obtaining a product with stable performance.

[0045] Although the present invention is described herein with reference to a number of illustrative embodiments of the present invention, it will be appreciated that those skilled in the art may devise many other modifications and implementations that fall within the scope and spirit of the principles disclosed herein. More specifically, within the scope of the present disclosure, drawings, and claims, a variety of variations and modifications may be made to the components and / or layout of the subject combination layout. In addition to the variations and modifications made to the components and / or layout, other uses will also be apparent to those skilled in the art.

Claims

1. A method for manufacturing a high-frequency quartz wafer, characterized in that: The following steps are involved: S1. Process the quartz to the target thickness and coat the front and back surfaces of the quartz with a two-layer structure, the bottom layer is chromium with a thickness of 5 to 50 nm, and the top layer is gold with a thickness of ≥100 nm; S2. Coat the front side of the quartz with a photosensitive photoresist material, perform pattern exposure on the wafer area, and process the wafer pattern while processing the folding area, and coat the back side with photoresist and harden the film for protection; S3. Use gold etching solution and chromium etching solution to etch the area exposed by the photoresist in turn to expose the quartz sheet; S4. Remove the photoresist on the surface of the quartz wafer by stripping off; S5. Use etching liquid to etch the quartz wafer, etch the metal exposed area downwards, and process the folding area while etching out the chip pattern; S6. After the etching is completed, use gold and chromium etching liquid to remove the metal on the surface of the quartz wafer; S7. Fold the chip off the wafer.

2. The method for manufacturing a high-frequency quartz wafer according to claim 1, characterized in that: The folded area is etched in turn using gold etching solution and chromium etching solution to etch the area exposed by the photoresist, and the etching shape is a V-shape rotated 90 degrees, wherein the wafer thickness is directly proportional to the height and width of a single V-shaped pattern, and the wafer thickness is inversely proportional to the spacing between two V-shaped patterns in the same direction and the spacing between two V-shaped patterns in the opposite direction.

3. The method for manufacturing a high-frequency quartz wafer according to claim 1, characterized in that: In step S3, the gold etching solution is usually an aqueous solution prepared with iodine and potassium iodide, and the chromium etching solution is an aqueous solution prepared with nitric acid and ammonium cerium nitrate.

4. The method for manufacturing a high-frequency quartz wafer according to claim 1, characterized in that: In step S4, the photoresist is stripped and removed by plasma stripping or chemical stripping.

5. The method for manufacturing a high-frequency quartz wafer according to claim 1, characterized in that: In step S5, the etching solution contains hydrofluoric acid, corrosion inhibitor and surfactant, and the etching time is affected by the thickness of the wafer.

6. The method for manufacturing a high-frequency quartz wafer according to claim 1, characterized in that: In step S6, the gold etching solution is an aqueous solution prepared from iodine and potassium iodide, and the chromium etching solution is an aqueous solution prepared from nitric acid and ammonium cerium nitrate.

7. A high frequency quartz wafer, characterized in that: The high-frequency quartz wafer is manufactured by the high-frequency quartz wafer manufacturing method described in any one of claims 1-6.

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