High-linearity self-bias numerical control attenuator with switched capacitor compensation phase

Abstract

The invention discloses a high-linearity self-bias numerical control attenuator with a switched capacitor compensation phase. Comprising a radio frequency signal input port Rfin, a radio frequency signal output port Rfout, a digital control level V1, a digital control level V2, a reference path series transistor group, a first attenuation path series transistor group, a second attenuation path series transistor group, a first attenuation resistor Rs, a second attenuation resistor RP1, a third attenuation resistor RP2, a first transistor and a second transistor. Phase compensation is carried out through turn-off stray capacitance of the first transistor and the second transistor, the linearity is improved by generating equivalent negative bias voltage at the two ends of the transistors through the bias resistor, an additional negative voltage generation circuit is not needed, and power consumption is reduced.

Description

Technical Field

[0001] The invention relates to the field of digital controlled attenuators, and in particular to a high linearity self-biased digital controlled attenuator with switched capacitor phase compensation. Background Art

[0002] As an integrated circuit that can control signal gain, digital attenuators are widely used in receiver circuits of wireless systems such as radar and communications. In order to ensure that the channel inside the receiver is not blocked by large-amplitude signals, the signal amplitude needs to be controlled. As an intermediate module of the receiver circuit, the attenuator is usually required to have high linearity to ensure that the signal is not compressed. In addition, excellent return loss, high attenuation accuracy and low additional phase shift are all key requirements for the attenuator.

[0003] Compared with variable gain amplifiers (active attenuators), digitally controlled attenuators have low power consumption, high linearity, and wider operating bandwidth. Variable gain amplifiers have static power consumption, while the static power consumption of digitally controlled attenuators is almost zero. Compared with traditional silicon processes, devices made of gallium arsenide process have lower on-resistance and higher linearity, making them more suitable for designing attenuators. The static power consumption of digitally controlled attenuators comes from their bias circuits, mainly from negative voltage generation circuits, such as Buck circuits or oscillators, which are heavily dependent on negative voltage generation circuits and need to be improved. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a high-linearity self-biased digitally controlled attenuator with switched capacitor phase compensation, which does not require a negative voltage generating circuit, achieves good switching characteristics, and improves linearity.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a high linearity self-biased digital controlled attenuator with switched capacitor phase compensation, comprising: a radio frequency signal input port Rf in , RF signal output port Rf out , digital control level V1, digital control level V2, reference path series transistor group, first attenuation path series transistor group, second attenuation path series transistor group, first attenuation resistor Rs, second attenuation resistor R P1 , the third attenuation resistor R P2 , a first transistor and a second transistor, wherein:

[0006] The reference path series transistor group includes a plurality of reference path transistors, the sources and drains of the plurality of reference path transistors are sequentially connected in series, and the source of the corresponding reference path transistor whose first end is not connected to the drain is connected to the RF signal input port Rf inThe drain of the corresponding reference path transistor that is not connected to the source at the end of the reference path series transistor group is connected to the RF signal output port Rf out Connected;

[0007] A first gate suspension resistor is connected between the gate of the reference path transistor and the digital control level V1, and a first bias resistor is provided between the connection point between the source and drain of two adjacent reference path transistors and the digital control level V2;

[0008] The first attenuation resistor Rs is connected to the RF signal input port Rf in With RF signal output port Rf out between;

[0009] The first attenuation path series transistor group includes a plurality of first attenuation path transistors, the sources and drains of the plurality of first attenuation path transistors are sequentially connected in series, and the drain of the corresponding first attenuation path transistor whose head end is not connected to the source of the first attenuation path series transistor group is connected to the RF signal input port Rf in The first attenuation path series transistor group end not connected to the drain corresponds to the source of the first attenuation path transistor and the second attenuation resistor R P1 The head end is connected;

[0010] The second attenuation path series transistor group includes a plurality of second attenuation path transistors, the sources and drains of the plurality of second attenuation path transistors are sequentially connected in series, and the drain of the corresponding second attenuation path transistor whose head end is not connected to the source of the second attenuation path series transistor group is connected to the RF signal output port Rf out The second attenuation path series transistor group end not connected to the drain is connected to the source of the corresponding second attenuation path transistor and the third attenuation resistor R P2 The head end is connected;

[0011] A second gate suspension resistor is provided between the gate of the first attenuation path transistor and the digital control level V2, and a third gate suspension resistor is provided between the gate of the second attenuation path transistor and the digital control level V2;

[0012] A second bias resistor is provided between the connection point between the source and drain of two adjacent first attenuation path transistors and the digital control level V1, and a third bias resistor is provided between the connection point between the source and drain of two adjacent second attenuation path transistors and the digital control level V1;

[0013] The gates of the first transistor and the second transistor are respectively connected to the digital control level V1, and the drain of the first transistor is connected to the second attenuation resistor R P1 The drain of the second transistor is connected to the third attenuation resistor R P2The first and second transistors are connected to each other at the beginning and the phase compensation is performed by using the off parasitic capacitance of the first and second transistors, which reduces the error caused by process fluctuations. Compared with MIM capacitor compensation, a smaller and more accurate capacitance value can be achieved.

[0014] In a preferred embodiment of the present invention, the second attenuation resistor R P1 The tail end is grounded.

[0015] In a preferred embodiment of the present invention, the third attenuation resistor R P2 The tail end is grounded.

[0016] In a preferred embodiment of the present invention, sources of the first transistor and the second transistor are grounded.

[0017] In a preferred embodiment of the present invention, the attenuator is adjusted to switch between the reference path and the attenuation path by controlling the digital control level V1 and the digital control level V2 to switch between high and low levels.

[0018] In a preferred embodiment of the present invention, at the RF signal input port Rf in With RF signal output port Rf out When the characteristic impedance Z0 is connected, the first attenuation resistor Rs and the second attenuation resistor R P1 And the third attenuation resistor R P2 The resistance value is:

[0019]

[0020] Wherein, L is the required attenuation and the characteristic impedance Z0 is 50Ω.

[0021] The source-drain voltage Vds of each transistor determines whether the transistor operates in the triode region or the saturation region. In the saturation region, Id no longer changes with the change of Vds, and the maximum source-drain voltage that the N transistors in series can withstand is N*Vds, which greatly improves the 1dB compression point of the entire circuit, thereby achieving high linearity.

[0022] IP1dB∝(V GS -V TH )≤N*V ds

[0023] Where IP1dB is the 1dB compression point, which is defined as the input power corresponding to a 1dB drop in gain. GS is the gate-source voltage of the transistor, V TH is the threshold voltage of the transistor, V ds is the drain-source voltage of the transistor.

[0024] The beneficial effects of the present invention are as follows: the present invention provides a high linearity self-biased digital controlled attenuator with switched capacitor phase compensation, wherein each source and drain connection of the series transistors is connected to another gate voltage V of the current series transistor group through a bias resistor. G Complementary digital control levels can obtain better switching characteristics, thereby significantly improving the linearity of the circuit. While improving the linearity of the circuit, no additional negative voltage generation circuit is required, further reducing the power consumption of the digitally controlled attenuator. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0026] Figure 1 It is a structural schematic diagram of a preferred embodiment of a high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation according to the present invention;

[0027] Figure 2 is the equivalent circuit diagram of the attenuator when the reference path is turned on;

[0028] Figure 3 is the equivalent circuit diagram of the attenuator when the attenuation path is turned on;

[0029] Figure 4 The attenuation variation curves of the conventional attenuator and the attenuator of the present invention with respect to the frequency;

[0030] Figure 5 The curves of the conventional attenuator and the attenuator of the present invention at 1 dB compression point vary with frequency. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] See also Figure 1 to Figure 5 , the embodiment of the present invention includes:

[0033] like Figure 1 The high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation shown in the figure comprises: a radio frequency signal input port Rf in , RF signal output port Rf out, digital control level V1, digital control level V2, reference path series transistor group A1, first attenuation path series transistor group A2, second attenuation path series transistor group A3, first attenuation resistor Rs, second attenuation resistor R P1 , the third attenuation resistor R P2 , a first transistor M10 and a second transistor M11, wherein:

[0034] The reference path series transistor group A1 includes a reference path transistor M1, a reference path transistor M2 and a reference path transistor M3. The sources and drains of the reference path transistors M1, M2 and M3 are sequentially connected in series to form a reference path. The source of the reference path transistor M1 is connected to the RF signal input port Rf in The drain of the reference path transistor M3 is connected to the RF signal output port Rf out Connected;

[0035] A first gate suspension resistor is connected between the gate of the reference path transistor and the digital control level V1. Specifically, Figure 1 As shown, a first gate suspension resistor R1 is connected between the reference path transistor M1 and the digital control level V1, a first gate suspension resistor R2 is connected between the reference path transistor M2 and the digital control level V1, and a first gate suspension resistor R3 is connected between the reference path transistor M3 and the digital control level V1. The gate leakage current is reduced by the first gate suspension resistor, and the larger the resistance value, the better. In the present embodiment, the resistance value of the first gate suspension resistor is above 1 kΩ.

[0036] A first bias resistor is arranged between the source and drain connection of two adjacent reference path transistors and the digital control level V2. Specifically, a first bias resistor R10 is arranged between the source and drain connection of the reference path transistor M1 and the reference path transistor M2 and the digital control level V2, and a first bias resistor R11 is arranged between the source and drain connection of the reference path transistor M2 and the reference path transistor M3 and the digital control level V2. Due to the existence of the bias resistor, the transistors with bias resistors connected to the source and drain in the turned-off transistor group can achieve good turn-off, thereby improving the attenuator linearity.

[0037] Connect the first attenuation resistor Rs to the RF signal input port Rf in With RF signal output port Rf out The resistance of the first attenuation resistor Rs is:

[0038]

[0039] Wherein, L is the required attenuation and the characteristic impedance Z0 is 50Ω.

[0040] In this embodiment, the first attenuation path series transistor group A2 includes a first attenuation path transistor M4, a first attenuation path transistor M5 and a first attenuation path transistor M6, the sources and drains of the first attenuation path transistor M4, the first attenuation path transistor M5 and the first attenuation path transistor M6 are sequentially connected in series, and the drain of the first attenuation path transistor M4 is connected to the RF signal input port Rf in The source of the first attenuation path transistor M6 is connected to the second attenuation resistor R P1 The first end is connected to the second attenuation resistor R P1 The tail end is grounded.

[0041] The second attenuation resistor R P1 And the third attenuation resistor R P2 The resistance value is:

[0042]

[0043] The second attenuation path series transistor group A3 includes a second attenuation path transistor M7, a second attenuation path transistor M8 and a second attenuation path transistor M9, the sources and drains of the second attenuation path transistor M7, the second attenuation path transistor M8 and the second attenuation path transistor M9 are sequentially connected in series, and the drain of the second attenuation path transistor M7 is connected to the RF signal output port Rf out The source of the second attenuation path transistor M9 is connected to the third attenuation resistor R P2 The first end is connected to the third attenuation resistor R P2 The tail end is grounded.

[0044] The third attenuation resistor R P2 The resistance value is:

[0045]

[0046] like Figure 1 As shown, a second gate floating resistor R4 is provided between the gate of the first attenuation path transistor M4 and the digital control level V2, a second gate floating resistor R5 is provided between the gate of the first attenuation path transistor M5 and the digital control level V2, a second gate floating resistor R6 is provided between the gate of the first attenuation path transistor M6 and the digital control level V2, a third gate floating resistor R7 is provided between the gate of the second attenuation path transistor M7 and the digital control level V2, a third gate floating resistor R8 is provided between the gate of the second attenuation path transistor M8 and the digital control level V2, and a third gate floating resistor R9 is provided between the gate of the second attenuation path transistor M9 and the digital control level V2, which is beneficial to reducing gate leakage current.

[0047] A second bias resistor R12 is provided between the source and drain connection of the first attenuation path transistor M4 and the first attenuation path transistor M5 and the digital control level V1, a second bias resistor R13 is provided between the source and drain connection of the first attenuation path transistor M5 and the first attenuation path transistor M6 and the digital control level V1, a third bias resistor R14 is provided between the source and drain connection of the second attenuation path transistor M7 and the second attenuation path transistor M8 and the digital control level V1, and a third bias resistor R15 is provided between the source and drain connection of the second attenuation path transistor M8 and the second attenuation path transistor M9 and the digital control level V1.

[0048] In this embodiment, the first attenuation resistor Rs and the second attenuation resistor R P1 , the third attenuation resistor R P2 The first attenuation path series transistor group A2 and the second attenuation path series transistor group A3 form a Π-type structure, which has the advantages of broadband and large attenuation. The attenuation path is mainly composed of the first attenuation path series transistor group A2 and the second attenuation path series transistor group A3.

[0049] like Figure 1 As shown, the gates of the first transistor M10 and the second transistor M11 are connected to the digital control level V1 respectively, and the drain of the first transistor M10 is connected to the second attenuation resistor R P1 The drain of the second transistor M11 is connected to the third attenuation resistor R P2 The first and second transistors M10 and M11 are connected to each other, and the source electrodes of the first and second transistors M10 and M11 are grounded. The phase compensation is performed by using the off parasitic capacitance of the first and second transistors M10 and M11, which reduces the error caused by process fluctuations. Compared with MIM capacitance compensation, a smaller and more accurate capacitance value can be achieved.

[0050] By controlling the digital control level V1 and the digital control level V2 to switch between high and low levels, the attenuator is adjusted to switch between the reference path and the attenuation path. Each source and drain connection in the series transistor is connected to another gate voltage V of the current series transistor group through a bias resistor. G Complementary digital control levels are used to obtain better switching characteristics and linearity. For example, when the digital control level V2 connected to the gate of the first attenuation path transistor M5 is low, a bias voltage V1 is generated at both ends of the transistor. s =V1-IR 12.13 , V2=V G , V G is the transistor gate voltage, V d is the transistor drain voltage, V s is the transistor source voltage, V G 、Vd and V s When the following formula conditions are met, the transistor is turned off.

[0051] 0≤V G <V s , 0≤V G <V d ,V TH >0

[0052] V GS -V TH <0, transistor is turned off.

[0053] In addition to producing an equivalent negative bias effect at both ends of the transistor, the bias resistor can also provide a DC potential, which is equivalent to an AC virtual ground. In a series transistor, the source of one transistor is connected to the drain of another transistor.

[0054] In this embodiment, Rs, R P1 , R P2 The values ​​of are as follows:

[0055] Attenuation(dB) Rs(Ω) Rp1(Ω) Rp2(Ω) 8 52.84 116.14 116.14

[0056] like Figure 2 When the reference path is turned on, the transistors in the reference path are equivalent to three series-connected on-resistances R on1 , R on2 , R on3 The first attenuation path series transistor group A2 and the second attenuation path series transistor group A3 of the attenuation path are equivalent to the series connection of the parasitic capacitor and the open switch respectively.

[0057] Due to the existence of the equivalent negative bias voltage, the transistors in A2 and A3 are well turned off and can be equivalent to an open switch; at this time, the gates of the first transistor M10 and the second transistor M11 are connected to a high level and can be equivalent to a wire, and the second attenuation resistor R p1 , the third attenuation resistor R p2 Short to ground.

[0058] like Figure 3 When the attenuation path is turned on, the transistors in the reference path are equivalent to the series connection of the off capacitor and the open switch, and the attenuation path transistors are equivalent to the on-resistance R on4 , R on5 , R on6 , R on7 , R on8 , R on9 At the same time, the first transistor M10 and the second transistor M11 are turned off, which can be equivalent to being connected in parallel with the second attenuation resistor R p1 , the third attenuation resistor R p2 The capacitance C across thec1 , C c2 , which plays the role of phase compensation.

[0059] When a high-power signal passes through the attenuator structure, due to the presence of the parasitic capacitance Cgs (gate-source parasitic capacitance) and Cgd (gate-drain parasitic capacitance) of the switching transistor, the input signal is coupled to the gate through the parasitic capacitance. When the signal coupling reaches a certain level, the gate voltage of the switching transistor will be reduced, causing the turned-on transistor to enter the linear region or the turned-off transistor to enter the subthreshold region, thereby affecting the linearity of the entire structure.

[0060] The 1dB compression point can reflect the linearity of a structure, such as Figure 5 The 1dB compression point variation curves of the digital controlled attenuator of the present invention and the traditional structure attenuator within 0-20GHz are shown. The digital controlled attenuator of the present invention improves the 1dB compression point power within the broadband, proving that the structure has high linearity.

[0061] In summary, the present invention provides a high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation, wherein the digital control level V1 and the digital control level V2 are complementary levels and can both be positive values, such as 0 and 5, and each source and drain connection in the series transistor is connected to another gate voltage V of the current series transistor group through a bias resistor. G The complementary digital control level does not require a negative level to turn off the transistor, which is beneficial to reducing the power consumption of the digitally controlled attenuator.

[0062] The above are only embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation, characterized in that: include: RF signal input port Rf in , RF signal output port Rf out , digital control level V1, digital control level V2, reference path series transistor group, first attenuation path series transistor group, second attenuation path series transistor group, first attenuation resistor Rs, second attenuation resistor R P1 , the third attenuation resistor R P2 , a first transistor and a second transistor, wherein: The reference path series transistor group includes a plurality of reference path transistors, the sources and drains of the plurality of reference path transistors are sequentially connected in series, and the source of the corresponding reference path transistor whose first end is not connected to the drain is connected to the RF signal input port Rf in The drain of the corresponding reference path transistor that is not connected to the source at the end of the reference path series transistor group is connected to the RF signal output port Rf out Connected; A first gate suspension resistor is connected between the gate of the reference path transistor and the digital control level V1, and a first bias resistor is provided between the connection point between the source and drain of two adjacent reference path transistors and the digital control level V2; The first attenuation resistor Rs is connected to the RF signal input port Rf in With RF signal output port Rf out between; The first attenuation path series transistor group includes a plurality of first attenuation path transistors, the sources and drains of the plurality of first attenuation path transistors are sequentially connected in series, and the drain of the corresponding first attenuation path transistor whose head end is not connected to the source is connected to the RF signal input port Rf in The first attenuation path series transistor group end not connected to the drain corresponds to the source of the first attenuation path transistor and the second attenuation resistor R P1 The head end is connected; The second attenuation path series transistor group includes a plurality of second attenuation path transistors, the sources and drains of the plurality of second attenuation path transistors are sequentially connected in series, and the drain of the corresponding second attenuation path transistor whose head end is not connected to the source of the second attenuation path series transistor group is connected to the RF signal output port Rf out The second attenuation path series transistor group end not connected to the drain is connected to the source of the corresponding second attenuation path transistor and the third attenuation resistor R P2 The head end is connected; A second gate suspension resistor is provided between the gate of the first attenuation path transistor and the digital control level V2, and a third gate suspension resistor is provided between the gate of the second attenuation path transistor and the digital control level V2; A second bias resistor is provided between the connection point between the source and drain of two adjacent first attenuation path transistors and the digital control level V1, and a third bias resistor is provided between the connection point between the source and drain of two adjacent second attenuation path transistors and the digital control level V1; The gates of the first transistor and the second transistor are respectively connected to the digital control level V1, and the drain of the first transistor is connected to the second attenuation resistor R P1 The drain of the second transistor is connected to the third attenuation resistor R P2 The first and second transistors are connected to each other at their respective ends, and phase compensation is performed using the turn-off parasitic capacitance of the first transistor and the second transistor.

2. The high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation according to claim 1, characterized in that: The second attenuation resistor R P1 The tail end is grounded.

3. The high linearity self-biased digital controlled attenuator with switched capacitor phase compensation according to claim 1, characterized in that: The third attenuation resistor R P2 The tail end is grounded.

4. The high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation according to claim 1, characterized in that: Sources of the first transistor and the second transistor are grounded.

5. The high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation according to claim 1, characterized in that: By controlling the digital control level V1 and the digital control level V2 to switch between high and low levels, the attenuator is adjusted to switch between the reference path and the attenuation path.

6. The high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation according to claim 1, characterized in that: At the RF signal input port Rf in With RF signal output port Rf out When the characteristic impedance Z0 is connected, the first attenuation resistor Rs and the second attenuation resistor R P1 And the third attenuation resistor R P2 The resistance value is: Where L is the required attenuation.

7. The high linearity self-biased digitally controlled attenuator with switched capacitor phase compensation according to claim 6, characterized in that: The characteristic impedance Z0 is 50Ω.

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