Anti-snorkeling inverter circuit

Abstract

The invention relates to the field of integrated circuit design, in particular to an anti-latent-pass inverter circuit which comprises three NMOS (N-channel Metal Oxide Semiconductor) tubes MN1-MN3, three PMOS (P-channel Metal Oxide Semiconductor) tubes MP1-MP3, a diode D1 and a resistor R1, the phase inverter circuit has an anti-latent-pass function, the stability and safety of the whole circuit can be improved, and meanwhile the cost of circuit analysis can be saved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and in particular to an anti-sneak-through inverter circuit. Background Art

[0002] In the control systems of aerospace, military equipment and critical infrastructure, any flaw may lead to catastrophic consequences, and reliability is the key to ensuring safety. When the main circuit fails, by switching the power supply, the main circuit power is turned off, and the backup circuit power is powered on. The backup circuit can quickly take over to ensure the continuity and stability of the system. Sneak Circuit refers to an unexpected and potential current path in circuit design due to factors such as circuit complexity and wiring. This path is usually hidden under normal circuit function operation and will only be activated under specific conditions, such as circuit component failure, abnormal signal combination or external interference.

[0003] In the prior art, the input and output of the main circuit and the backup circuit are often connected together. Since multiple devices are connected in parallel, the backup circuit power supply is not powered on when the main circuit is operating. When there is an inverter at the output, the main circuit output can be connected to the backup circuit power supply in series with the backup circuit output port. The high level will enter the power supply through the substrate and the channel to affect the normally working devices, making the unpowered devices in a working state. Before circuits with high safety requirements are put into practical application, they usually undergo complex circuit analysis to exclude potential circuits.

[0004] Therefore, it is of great significance to study an inverter with anti-sneak-through function. Summary of the invention

[0005] In view of this, the present invention discloses an anti-sneak-through inverter circuit to solve the above problem; the circuit comprises:

[0006] Three NMOS tubes MN1~MN3, three PMOS tubes MP1~MP3, a diode D1, and a resistor R1; the connection method is: the source of MP1 is respectively connected to the source of MP2, the positive electrode of D1, the gate of MP3, and the gate of MN1 and serves as a power supply terminal; the gate of MP1 is respectively connected to the drain of MP2, the source of MP3, the drain of MN2, and the gate of MN3 and serves as an output terminal; the drain of MP1 is respectively connected to the drain of MN1, the drain of MP3, and the gate of MP2; the substrate of MP1 is respectively connected to one end of R1, the substrate of MP2, and the substrate of MP3; the source of MN1 is respectively connected to the gate of MN2 and the drain of MN3 and serves as an input terminal; the substrate of MN1 is grounded; the source of MN2 is respectively connected to the substrate of MN2, the substrate of MN3, and the source of MN3 and is grounded; the cathode of D1 is connected to the other end of R1.

[0007] The beneficial effects of the present invention include: by adopting the inverter circuit described in the present invention, the device can have an anti-sneak-through function when it is not powered on, thereby protecting the entire circuit, improving the stability and safety of the entire circuit, and saving circuit analysis costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A circuit diagram of the anti-creeping inverter circuit of the present invention when it is not working;

[0009] Figure 2 is an equivalent circuit diagram of an embodiment of the present invention when the power supply is powered on;

[0010] Figure 3 FIG. 4 is an equivalent circuit diagram of an embodiment of the present invention when the power supply is not powered on. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solution, characteristics and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0012] This embodiment includes an anti-sneak-through inverter circuit, specifically, including: 3 NMOS tubes MN1~MN3, 3 PMOS tubes MP1~MP3, 1 diode D1, and 1 resistor R1; further, the circuit diagram of this embodiment is as shown in Figure 1 As shown, A represents the input end, ZN represents the output end, VDD represents the power supply, VDD1 is a node introduced to facilitate the display of the circuit structure, and GND represents the ground.

[0013] Furthermore, the connection method is as follows: the source of MP1 is respectively connected to the source of MP2, the positive electrode of D1, the gate of MP3, and the gate of MN1 and serves as a power supply terminal; the gate of MP1 is respectively connected to the drain of MP2, the source of MP3, the drain of MN2, and the gate of MN3 and serves as an output terminal; the drain of MP1 is respectively connected to the drain of MN1, the drain of MP3, and the gate of MP2; the substrate of MP1 is respectively connected to one end of R1, the substrate of MP2, and the substrate of MP3; the source of MN1 is respectively connected to the gate of MN2 and the drain of MN3 and serves as an input terminal; the substrate of MN1 is grounded; the source of MN2 is respectively connected to the substrate of MN2, the substrate of MN3, and the source of MN3 and is grounded; the negative electrode of D1 is connected to the other end of R1.

[0014] When the power supply is not powered on and the voltage at the circuit output port is at a high level, the MP2 tube will be closed, preventing the high level from entering the power supply through the MP2 channel; the high level will enter the MP2 substrate, and the diode D1 will be in an anti-bias state, preventing the level from entering the power supply through the substrate.

[0015] Furthermore, when the power supply is powered on, the equivalent circuit of this embodiment is as follows: Figure 2 As shown, the circuit works as a common inverter: the voltage signal at the input end is the ground voltage or the power supply voltage, and the voltage signal at the output end is the power supply voltage or the ground voltage, and is inverted with the input signal.

[0016] Specifically, the gate voltage of MP3 is VDD, and the tube is in the off state; when the input signal A is VDD, the gate voltage of MN2 is VDD, and the tube is in the on state and pulls down the voltage of the output terminal ZN; since the gate voltage of MN1 is VDD, MN1 is in the off state; the gate of MP1 is connected to the output port ZN, and since ZN is at a low level, the MP1 tube is in the on state, thereby causing the gate voltage of MP2 to be pulled up to VDD, and MP2 is in the off state. At this time, when the input signal A is GND, MN1 is on, MP2 is on, MN2 is off, MP1 is off, MN3 is on, and the output signal is VDD.

[0017] Furthermore, when the circuit power supply is not powered on (VDD=0V) and the output is in a high level state, the equivalent circuit of this embodiment is as follows: Figure 3 shown.

[0018] Specifically, the gate voltage of MP3 is 0V, and the tube is in the on state. Since the substrates of MP1, MP2, and MP3 are connected to VDD through diodes, the diodes are in a reverse biased state, and the high level cannot be transmitted to VDD; at the same time, the gate and drain of MP2 and the gate and drain of MP1 are connected together, all in a high level state, and the sources of MP1 and MP2 are 0V, so MP1 and MP2 are in the off state. The high level cannot be transmitted to the power supply through the substrate and the channel, and the high level output of the inverter will not be transmitted to the power supply through the sneak path.

[0019] Furthermore, the sizes of MN2 and MP2 are calculated from the required driving current I, and the calculation formula is:

[0020]

[0021] Among them, W is the width of the MOS tube channel, L is the length of the MOS tube channel, I is the drain current of the MOS tube when the power supply is turned on, and C ox is the oxide layer capacitance per unit area of ​​the MOS tube, μ p is the hole mobility of the MOS tube, V DD is the power supply voltage, V th is the threshold voltage of the MOS tube.

[0022] Furthermore, the power supply terminal voltage is 1.8V, 3.3V or 5V.

[0023] Finally, it should be noted that the above only describes some embodiments of the present invention. For those skilled in the art, it is conceivable that various changes, modifications, substitutions and deformations may be made to these embodiments without departing from the principles and spirit of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents, and the above-mentioned actions should be covered within the scope of protection of the present invention.

Claims

1. An anti-sneak-through inverter circuit, characterized in that: It includes three NMOS tubes MN1 to MN3, three PMOS tubes MP1 to MP3, one diode D1, and one resistor R1; The connection method is as follows: the source of MP1 is respectively connected to the source of MP2, the positive electrode of D1, the gate of MP3, and the gate of MN1; the gate of MP1 is respectively connected to the drain of MP2, the source of MP3, the drain of MN2, and the gate of MN3; the drain of MP1 is respectively connected to the drain of MN1, the drain of MP3, and the gate of MP2; the substrate of MP1 is respectively connected to one end of R1, the substrate of MP2, and the substrate of MP3; the source of MN1 is respectively connected to the gate of MN2 and the drain of MN3; the substrate of MN1 is grounded; the source of MN2 is respectively connected to the substrate of MN2, the substrate of MN3, the source of MN3 and grounded; the negative electrode of D1 is connected to the other end of R1.

2. The anti-sneak-through inverter circuit according to claim 1, characterized in that: The source of MP1 serves as a power supply terminal, the gate of MP1 serves as an output terminal, and the substrate of MP1 serves as an input terminal.

3. The anti-sneak-through inverter circuit according to claim 1, characterized in that: The size of MN2 and MP2 is determined by the drive current I: Among them, W is the width of the MOS tube channel, L is the length of the MOS tube channel, I is the drain current of the MOS tube when the power supply is turned on, and C ox is the oxide layer capacitance per unit area of ​​the MOS tube, μ p is the hole mobility of the MOS tube, V DD is the power supply voltage, V th is the threshold voltage of the MOS tube.

4. The anti-sneak-through inverter circuit according to claim 1, characterized in that: When not powered on, the MP2 tube is in a closed state, which is used to prevent the current at the output end from entering the power supply through the substrate.

5. The anti-sneak-through inverter circuit according to claim 1, characterized in that: When powered on, the voltage signal at the input end is the ground voltage or the power supply end voltage, and the voltage signal at the output end is the power supply end voltage or the ground voltage, and is inversely proportional to the input signal.

6. The anti-sneak-through inverter circuit according to claim 4, characterized in that: The power supply voltage is 1.8V, 3.3V or 5V.

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