DVB-S2 high-speed parallel BCH code decoder and decoding method thereof

Abstract

The invention provides a DVB-S2 high-speed parallel BCH code decoder and a decoding method thereof. The decoder comprises an N-path parallel syndrome calculation module, an error polynomial calculation module, an N-path parallel Chien search module and an error correction module. The modules are used for carrying out N-path parallel syndrome calculation on a BCH code to be decoded to obtain a syndrome result; by utilizing an iBM algorithm, performing multiple iterative operations on the syndrome result, and determining an error position polynomial output result; based on the error position polynomial output result, using a small lookup table containing an initial value to determine whether the information position of the to-be-decoded BCH code has an error, and outputting a judgment result; and finally, outputting a high-speed parallel decoding result based on the to-be-decoded BCH code and the judgment result. According to the method, multi-bit parallel input and output data are adopted, and the error polynomial is calculated by using the iBM algorithm, so that the timeliness of the decoding process is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a DVB-S2 high-speed parallel BCH code decoder and a decoding method thereof. Background Art

[0002] The decoding process of BCH code generally includes several steps, namely finding the companion formula, finding the error polynomial and Qian's search. The calculation of Galois field is involved in all three steps. The commonly used method for this calculation is to make a lookup table of extended field elements, convert the multiplication of finite field into the addition and subtraction of its exponent, and write the extended field elements into the FPGA precompiled header file or the soft core part in the form of fixed constants, and then get the result by looking up the table.

[0003] Among them, when using pure FPGA to calculate the Galois Field, finite field multipliers can be used. The current commonly used method is to reuse the finite field multipliers in an iterative manner, integrate the iterative process into the decoding input data and output data process, and obtain high-order Galois Field elements in the process.

[0004] However, in the DVB-S2 protocol, BCH code decoding uses GF(2 16 ) and GF(2 14 ), two lookup tables of size 65535×16 and 16383×14 need to be made on FPGA. If static storage is used, due to the existence of multiple parallel decoding, multiple lookup tables need to be made repeatedly to ensure simultaneous reading and writing of multiple channels, which greatly occupies storage resources.

[0005] Moreover, for the finite field multiplier iteration method, when performing multi-way parallel decoding, the startup of the syndrome process requires some higher-order Galois field elements. At this time, if it is still obtained through pure iteration, a large number of iterations will be performed, which also consumes a long time and resources.

[0006] If the table lookup method is implemented using an SOC chip and stored in the soft core part, then because it usually performs serial processing, one instruction cycle requires multiple machine cycles to implement, and there is a propagation delay in the data exchange between the PS and PL ends, it is difficult to meet the real-time requirements of high-speed decoding. Summary of the invention

[0007] The present invention provides a DVB-S2 high-speed parallel BCH code decoder and a decoding method thereof, which are used to solve the defect of poor decoding timeliness in the prior art, and achieve the goal of effectively shortening the decoding time and improving the decoding efficiency.

[0008] The present invention provides a DVB-S2 high-speed parallel BCH code decoder, comprising: an N-way parallel syndrome calculation module, an error polynomial calculation module, an N-way parallel Qian's search module and an error correction module;

[0009] The input end of the N-way parallel syndrome calculation module is connected in parallel with the first input end of the error correction module, and then connected to the input end of the BCH code data to be decoded of DVB-S2, the output end of the N-way parallel syndrome calculation module is connected to the input end of the error polynomial calculation module, the output end of the error polynomial calculation module is connected to the input end of the N-way parallel Qian's search module, the output end of the N-way parallel Qian's search module is connected to the second input end of the error correction module, and the output end of the error correction module is connected to the decoding output end;

[0010] The N-way parallel syndrome calculation module is used to perform N-way parallel syndrome calculation on the BCH code to be decoded to obtain syndrome results;

[0011] The error polynomial calculation module is used to determine the error position polynomial output result by performing multiple iterative operations on the syndrome result using the iBM algorithm without inversion;

[0012] The N-way parallel Qian's search module is used to output the result based on the error position polynomial, use a small lookup table containing an initial value, and iteratively update the judgment by N bits one by one to determine whether an error occurs in the information position of the BCH code to be decoded, and output the judgment result;

[0013] The error correction module is used to output a high-speed parallel decoding result of the BCH code to be decoded based on the BCH code to be decoded and the judgment result.

[0014] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the error polynomial calculation module is specifically used for:

[0015] Calculate the correction term parameters required for each round of iteration according to the syndrome results corresponding to each round of iteration of the non-inversion iBM algorithm, and determine whether the correction term parameters are 0;

[0016] If the correction term parameter of any round of iteration is not 0, the coefficients of the current error polynomial are updated, and the updated error polynomial is used as the error pattern;

[0017] The difference between the updated error polynomial and the current error polynomial is calculated, and the difference is added to the correction term parameter calculation of the next round of iteration until the operation of all the syndrome results is completed, and the error position polynomial output result is output according to the error pattern.

[0018] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the algorithm flow of the non-inverse iBM algorithm is as follows:

[0019] Determine the initial value as μ(0) (x)=1,λ (0) (x)=1,l (0) =0,γ (k) =1(k≤0);

[0020] According to the following formula, calculate the correction parameter δ (k+1) :

[0021]

[0022] In the formula, Represents μ k (x) j The coefficient of the term, s represents the companion matrix in the iterative process, k represents the number of iterations, l represents the intermediate quantity, and the correction term parameter δ k and the intermediate quantity l act as judgment conditions in the iteration process;

[0023] According to the correction parameter δ (k+1) , the difference is calculated according to the following formula:

[0024] μ (k+1) (x) = γ (k) μ (k) (x)-δ (k+1) λ (k) (x)x;

[0025] Wherein, μ(x) represents the difference, γ k and λ(x) represent the iterative intermediate variables introduced to replace the inversion process;

[0026] According to the difference, update the coefficients of the current error polynomial according to the following rules:

[0027] If δ (k+1) ≠0 and 2l (k) ≤k, then:

[0028] λ (k+1) (x) = μ (k)

[0029] l (k+1) =k+1-l (k)

[0030] γ (k+1) =δ (k+1)

[0031] If δ (k+1) =0 or 2l (k) >k, then:

[0032] λ (k+1) (x) = xλ (k) (x)

[0033] l (k+1) = l (k)

[0034] γ (k+1) =γ (k)

[0035] Repeat the above calculation and update steps for multiple iterations until after 2t iterations, μ(x) = μ (2t) (x);

[0036] Since the first equation:

[0037]

[0038] and k is a non-zero constant, then the error location polynomial output result is obtained by solving the first equation;

[0039] The error polynomial σ(x) is expressed as:

[0040]

[0041] In the formula, σ 1 , σ 2 , ..., σ t represents the coefficients of the error polynomial, and the roots of the error polynomial are the inverses of the error positions.

[0042] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the N-way parallel Qian's search module is specifically used for:

[0043] Starting from the highest bit of the error position polynomial output result, the N-bit check code α is converted to i+N-1 , ..., α i+1 , α i ,i=nN,...,2N,0 inverse (α i+N-1 ) -1 =α, ..., (α i+1 ) -1 =α、(α i ) -1 =α, respectively substitute into the error position polynomial output results, and observe whether the error position polynomial output results are 0 in parallel. If the result corresponding to any bit is 0, it is determined that an error occurs in the bit, otherwise there is no error.

[0044] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the N-way parallel Qian's search module is also used for:

[0045] A small lookup table containing initial values ​​is prepared, and based on the small lookup table, in each round of calculation, a check code for the next round of check is obtained through iteration.

[0046] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the N-way parallel companion computing module is implemented by pure FPGA, and the N-way parallel companion computing module is specifically used for:

[0047] While receiving the codeword polynomial of the BCH code to be decoded, iterating through a finite field multiplier to obtain a finite field element at a corresponding position in a BCH code check matrix;

[0048] Horner's rule is used to decompose and synchronously perform N-bit calculations, and the BCH code check matrix and the corresponding positions of the code word polynomial are multiplied and accumulated to obtain the syndrome result at the next clock after the BCH code to be decoded is input.

[0049] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the BCH code check matrix is ​​expressed as:

[0050]

[0051] Wherein, H represents the BCH code check matrix, α represents the extended domain element, n represents the code length of the BCH code to be decoded, and t represents the maximum error correction number;

[0052] The syndrome result is expressed in a matrix as follows:

[0053] S=(s 1 ,s 2 ,s 3 ,…,s 2t );

[0054] In the formula, S represents the result matrix of the companion formula, where S 1 ,S 2 ,...,S 2t The syndrome results of multiplying the BCH code check matrix and the codeword polynomial are all in the form of extended domain elements;

[0055] The codeword polynomial of the BCH code to be decoded is expressed as:

[0056] R(x)=r n-1 x n-1 +r n-2 x n-2 +…+r 1 x 1 +r 0 ;

[0057] Wherein, R(x) represents the codeword polynomial, the codeword polynomial is the input signal, r n-1 ,r n-2 ,...,r 0 represents the polynomial coefficient, and x represents the polynomial variable;

[0058] The syndrome result can be obtained by solving the following formula:

[0059] S T =H·R T .

[0060] According to a DVB-S2 high-speed parallel BCH code decoder provided by the present invention, the error correction module is specifically used for:

[0061] If the judgment result is that an error exists, the N-bit BCH code currently being verified is flipped to achieve error correction, and the corrected data is output as the high-speed parallel decoding result.

[0062] A DVB-S2 high-speed parallel BCH code decoder provided by the present invention further includes a parameter configuration module for:

[0063] The configuration includes parameters for the order of the predefined polynomial factors in the BCH decoder, the maximum error correction capability code, and the word polynomial length.

[0064] The present invention also provides a DVB-S2 high-speed parallel BCH code decoding method, which is implemented by any of the above-mentioned DVB-S2 high-speed parallel BCH code decoders, and the method comprises:

[0065] Performing N-way parallel syndrome calculations on the BCH code to be decoded to obtain syndrome results;

[0066] Using the non-inverse iBM algorithm, by performing multiple iterative operations on the syndrome result, the error position polynomial output result is determined;

[0067] Based on the error position polynomial output result, using a small lookup table containing an initial value, by iteratively updating the judgment N bits at a time, determine whether an error occurs in the information position of the BCH code to be decoded, and output the judgment result;

[0068] Based on the BCH code to be decoded and the judgment result, a high-speed parallel decoding result of the BCH code to be decoded is output.

[0069] The DVB-S2 high-speed parallel BCH code decoder and decoding method provided by the present invention adopt multi-bit parallel input and output data, that is, the syndrome calculation is directly merged into the input data for multi-bit parallel calculation, and is directly output in parallel during the Qian search. At the same time, the calculation of the error polynomial uses the non-inverse BM algorithm (iBM algorithm), so that the total decoding time in the overall decoding process is compressed to much less than 1 / 2 of the input data time, successfully avoiding blocking and effectively improving the timeliness of the decoding process. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0071] Figure 1 A schematic diagram of the structure of a DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0072] Figure 2 A schematic diagram of the input and output timing of an error polynomial calculation module in a DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0073] Figure 3 A schematic diagram of the structure of a Qian's search circuit in a DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0074] Figure 4 A schematic diagram of the input and output timing of a decoder in a DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0075] Figure 5 A schematic diagram of the structure of a syndrome calculation circuit in a DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0076] Figure 6 A schematic diagram of the input and output timing of the syndrome calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0077] Figure 7 The present invention provides a flowchart of a DVB-S2 high-speed parallel BCH code decoding method. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0079] The present invention aims at the problem of poor timeliness of BCH code decoding in the prior art. By adopting multi-bit parallel input and output data, that is, directly merging the syndrome calculation into the input data for multi-bit parallel calculation, and directly outputting in parallel during Qian's search, and using the inverse-free BM algorithm (iBM algorithm) for the calculation of the error polynomial, the total decoding time in the overall decoding process is compressed to much less than 1 / 2 of the input data time, successfully avoiding blocking, and effectively improving the timeliness of the decoding process. The present invention will be specifically described and introduced through multiple embodiments below.

[0080] Figure 1 The present invention provides a structural diagram of a DVB-S2 high-speed parallel BCH code decoder, which is a DVB-S2 / DVB-S2X system BCH code high-speed parallel decoding FPGA decoder, which can be used to implement high-speed parallel decoding of BCH codes in DVB-S2 / DVB-S2X, such as Figure 1 As shown, the decoder includes an N-way parallel syndrome calculation module 101, an error polynomial calculation module 102, an N-way parallel Qian search module 103 and an error correction module 104. Among them:

[0081] After the input end of the N-way parallel syndrome calculation module 101 is connected in parallel with the first input end of the error correction module 104, it is connected to the input end of the BCH code data to be decoded of DVB-S2, the output end of the N-way parallel syndrome calculation module 101 is connected to the input end of the error polynomial calculation module 102, the output end of the error polynomial calculation module 102 is connected to the input end of the N-way parallel Qian's search module 103, the output end of the N-way parallel Qian's search module 103 is connected to the second input end of the error correction module 104, and the output end of the error correction module 104 is connected to the decoding output end.

[0082] The N-way parallel syndrome calculation module 101 is used to perform N-way parallel syndrome calculation on the BCH code to be decoded to obtain syndrome results;

[0083] The error polynomial calculation module 102 is used to determine the error position polynomial output result by performing multiple iterative operations on the syndrome result using the iBM algorithm without inversion;

[0084] The N-way parallel Qian's search module 103 is used to determine whether an error occurs in the information position of the BCH code to be decoded based on the error position polynomial output result, using a small lookup table containing an initial value, by iteratively updating the judgment N bits at a time, and output the judgment result;

[0085] The error correction module 104 is used for outputting a high-speed parallel decoding result of the BCH code to be decoded based on the BCH code to be decoded and the judgment result.

[0086] It can be understood that, Figure 1 As shown, the DVB-S2 high-speed parallel BCH code decoder of the present invention should at least include an N-way parallel syndrome calculation module 101, an error polynomial calculation module 102, an N-way parallel Qian's search module 103 and an error correction module 104. The connection relationship between these modules is also shown in FIG. Figure 1 As shown, they are respectively used to implement the processing flow of companion calculation, error polynomial calculation, Qian's search and error correction.

[0087] Specifically, when decoding the BCH code in the DVB-S2 protocol, the input data to be decoded, i.e., the BCH code to be decoded, is first stored in the data storage module in the error correction module 104 for subsequent reading. At the same time, the BCH code data to be decoded is sent to the N-way parallel syndrome calculation module 101 for syndrome calculation. When the input of the BCH code data to be decoded is completed, the syndrome calculation is also completed.

[0088] Secondly, the syndrome results output by the N-way parallel syndrome calculation module 101 are input to the error position polynomial calculation module, i.e., the error polynomial calculation module 102, and the error position polynomial is iteratively calculated. After 2t iterations, the result is output as the error position polynomial output result.

[0089] Then, the error position polynomial output result, i.e., the error position polynomial, is input into the N-way parallel Qian search module 103 for Qian search, starting from the high position, N bits by bit, such as 4 bits by bit, to determine whether an error occurs in the position of the information to be decoded, and output the decoding result in real time in combination with the data storage module in the error correction module 104. When the Qian search of the lowest bit is completed, the decoding is completed, and when the decoding is completed, all the decoding result data are output.

[0090] It should be understood that in the DVB-S2 protocol of the present invention, the BCH code is an outer code, the LDPC code is an inner code, and the BCH decoding is to solve the problem that when the LDPC decoding reaches the limit performance, there are a few uncorrectable errors (error leveling). As shown in Table 1, it is an error correction coding parameter table specified in the DVB-S2 protocol. In the present invention, the BCH decoding adopts a hard decision idea, which can stably correct all decoding errors within the maximum error correction capability.

[0091] Table 1, BCH error correction code parameter table in DVB-S2

[0092]

[0093]

[0094] BCH long code is defined in GF(2 16 ) field, the primitive polynomial is 1+x 2 +x 3 +x 5 +x 16 ; Short code is defined in GF(2 14 ), the primitive polynomial is 1+x+x 3 +x 5 +x 14 .

[0095] When decoding involves Galois field operations, a common method is to create and use an extended field element lookup table. However, considering that the lookup table required for the DVB-S2 protocol is too large, dynamic storage requires most hardware resources, and static storage will waste a lot of resources when performing parallel decoding. The present invention uses a Galois field universal multiplier.

[0096] Taking the long code as an example, first in GF(2 16 ) can be represented by a polynomial of degree less than 16 (here called 16-fold representation). When multiplying, the polynomial multiplication is first performed according to the conventional method to obtain an intermediate variable of degree not greater than 30.

[0097] Secondly, its primitive polynomial is expressed as 1+x 2 +x 3 +x 5 +x 16 , then x 16 =1+x 2 +x 3 +x 5 On this basis, x 16 to x 30 Transformed into a linear combination of natural bases. Substituting the result into the variables in the previous step, after combination cancellation, a 16-fold representation of the product of domain elements can be obtained. The circuit designed according to this logical relationship is a pure combinational logic circuit, which can get the output result in just one clock cycle. In the actual circuit, 256 AND gates and 633 XOR gates are used in one multiplier. The input and output interface description of the decoder is shown in Table 2.

[0098] Table 2, BCH code decoder interface description table

[0099]

[0100]

[0101] The DVB-S2 high-speed parallel BCH code decoder provided by the present invention adopts multi-bit parallel input and output data, that is, the syndrome calculation is directly merged into the input data for multi-bit parallel calculation, and is directly output in parallel during the Qian search. At the same time, the calculation of the error polynomial uses the inverse-free BM algorithm (iBM algorithm), so that the total decoding time in the overall decoding process is compressed to much less than 1 / 2 of the input data time, successfully avoiding blocking and effectively improving the timeliness of the decoding process.

[0102] According to the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the error polynomial calculation module is specifically used for:

[0103] Calculate the correction term parameters required for each round of iteration according to the syndrome results corresponding to each round of iteration of the non-inversion iBM algorithm, and determine whether the correction term parameters are 0;

[0104] If the correction term parameter of any round of iteration is not 0, the coefficients of the current error polynomial are updated, and the updated error polynomial is used as the error pattern;

[0105] The difference between the updated error polynomial and the current error polynomial is calculated, and the difference is added to the correction term parameter calculation of the next round of iteration until the operation of all the syndrome results is completed, and the error position polynomial output result is output according to the error pattern.

[0106] It can be understood that the algorithm used in the circuit of the error polynomial calculation module of the present invention is a non-inverse BM algorithm, that is, based on the obtained multiple syndrome results, iterative calculation is performed according to the iBM algorithm to obtain the error pattern.

[0107] Specifically, in each round of iterative operation, the correction term parameters required for iteration are calculated according to the syndrome results corresponding to the iteration of the error position polynomial algorithm. Then, it is determined whether the correction term parameters are zero. If the correction term parameters of any round of iteration are not zero, it means that there is a deviation. Then, the coefficients of the error polynomial are updated, and the updated error polynomial is used as the error pattern. At the same time, the difference between the updated error polynomial and the current error polynomial before the update is calculated, and the difference is added to the calculation of the correction term parameters of the next round of iteration.

[0108] In each round of iterative calculation of the error polynomial calculation module, the above calculation steps are repeatedly executed to calculate the syndrome results until the calculation of all syndrome results is completed, and then the error position polynomial output result is output according to the determined error pattern.

[0109] Among them, the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments is optional, and the algorithm flow of the non-inverse iBM algorithm is as follows:

[0110] Determine the initial value as μ (0) (x)=1,λ (0) (x)=1,l (0) =0,γ (k) =1(k≤0);

[0111] According to the following formula, calculate the correction parameter δ (k+1) :

[0112]

[0113] In the formula, μ j (k) Represents μ k (x) j The coefficient of the term, s represents the companion matrix in the iterative process, k represents the number of iterations, l represents the intermediate quantity, and the correction term parameter δ k and the intermediate quantity l act as judgment conditions in the iteration process;

[0114] According to the correction parameter δ (k+1) , the difference is calculated according to the following formula:

[0115] μ (k+1) (x) = γ (k) μ (k) (x)-δ (k+1) λ (k) (x)x;

[0116] Wherein, μ(x) represents the difference, γ k and λ(x) represent the iterative intermediate variables introduced to replace the inversion process;

[0117] According to the difference, update the coefficients of the current error polynomial according to the following rules:

[0118] If δ (k+1) ≠0 and 2l (k) ≤k, then:

[0119] λ (k+1) (x) = μ (k)

[0120] l (k+1) =k+1-l (k)

[0121] γ (k+1) =δ (k+1)

[0122] If δ(k+1) =0 or 2l (k) >k, then:

[0123] λ (k+1) (x) = xλ (k) (x)

[0124] l (k+1) = l (k)

[0125] γ (k+1) =γ (k)

[0126] Repeat the above calculation and update steps for multiple iterations until after 2t iterations, μ(x) = μ (2t) (x);

[0127] Since the first equation:

[0128]

[0129] and k is a non-zero constant, then the error location polynomial output result is obtained by solving the first equation;

[0130] The error polynomial σ(x) is expressed as:

[0131]

[0132] In the formula, σ 1 , σ 2 , ..., σ t represents the coefficients of the error polynomial, and the roots of the error polynomial are the inverses of the error positions.

[0133] It can be understood that if the error pattern is to be obtained directly, it is difficult to solve 2t unknowns from 2t equations. For this reason, the present invention introduces the error polynomial σ(x).

[0134]

[0135] The t roots of the error polynomial are the inverse of the error position. If the syndrome is known and the maximum number of errors is determined, the solution can be obtained. The commonly used method is the BM iterative decoding algorithm, but it contains the inversion operation of the finite field, which is not conducive to the implementation of the hardware algorithm. For this reason, the present invention proposes the above-mentioned non-inversion BM algorithm, namely the iBM algorithm. The input and output timing diagram of the iBM algorithm module is shown in FIG. Figure 2 As shown in FIG. 1 , it is a schematic diagram of the input and output timing of the error polynomial calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. The present invention divides the error polynomial solution process into a state machine for solving σ(x), μ(x), and re-updating information.(2t) (x) = kσ (2t) (x), and k is a non-zero constant, so μ(x) has the same root as the error polynomial and is also the reciprocal of the error position. In addition, the present invention adds γ (k) This iterative term eliminates the inversion step and is more conducive to hardware implementation.

[0136] It should be understood that in the DVB-S2 protocol, the maximum error correction capability required is t, and a maximum of 2t cycles are required. The total decoding clock cycle is in the order of hundreds of units. When the code length is the shortest, the error polynomial decoding time is less than 1 / 2 of the input data time, meeting the requirements of high-speed decoding.

[0137] Compared with the BM algorithm, the BM algorithm without inversion in the present invention adds a new iteration term γ (k) , the inverse step can be omitted, which is more conducive to hardware implementation. In the present invention, the solution process of the error polynomial is divided into several state machines for solving σ(x), μ(x), and re-updating information. The number of iterations required is twice the maximum error correction capability.

[0138] Wherein, the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments is optional, and the N-way parallel Qian search module is specifically used to: start from the highest bit of the error position polynomial output result, and convert the N-bit check code α i+N-1 , ..., α i+1 , α i ,i=nN,...,2N,0 inverse (α i+N-1 ) -1 =α, ..., (α i+1 ) -1 =α、(α i ) -1 =α, respectively substitute into the error position polynomial output results, and observe whether the error position polynomial output results are 0 in parallel. If the result corresponding to any bit is 0, it is determined that an error occurs in the bit, otherwise there is no error.

[0139] It can be understood that, considering that it is difficult to find roots in an extended domain in engineering, the idea of ​​the present invention using the Chien search method is to check each bit from the high bit and output each bit. The Chien search algorithm adopts the "root verification" method, which solves the problem that it is difficult to find roots for extended domain elements in engineering. The root-finding process starts from the high bit and checks each bit. To check the highest bit r n-1 If it is wrong, n-1 The inverse of (α n-1 ) -1 =α is substituted into the error polynomial and the result is observed to be 0. If it is 0, it means an error has occurred in that bit, otherwise there is no error.

[0140] To check the highest bit r n-1 Is it wrong? n-1 The corresponding check code α n-1 The inverse of (α n-1 ) -1 =αSubstitute the error polynomial into the output result σ(x), if

[0141] σ(α)=1+σ 1 α+σ 2 α 2 +…+σ v α v =0 (v≤t),

[0142] Description n-1 There is an error, otherwise it means r n-1 Correct.

[0143] The structure of Chien search circuit is as follows Figure 3 As shown in FIG. 1 , a schematic diagram of the structure of the Qian search circuit in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention is shown. When 4-way parallel calculation is adopted, each clock needs to calculate σ(α i ),σ(α i+1 ),σ(α i+2 ) and σ(α i+3 ), Chien searches for the value of 4 bits after each step of calculation, and makes a judgment. If the result is 0, it means that an error occurs in the bit, and the corresponding position in the data storage module is flipped, and the 4 bits are output together after flipping. Since the extended domain element lookup table required for the Galois field of the long code and the short code in DVB-S2 is too large, the present invention can choose to make a small lookup table containing the initial value, and obtain the elements required for the next step through iteration in each step of calculation.

[0144] The overall input and output timing of the decoder is as follows Figure 4 As shown, it is a schematic diagram of the input and output timing of the decoder in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. The decoding result starts to be output at the 2t+3th clock after the end of a frame of input data. Calculated from the completion of the input data, the total decoding time is n / 4 (n is the decoding code length) + 2t iterations (theoretical time upper limit is less than n / 4) + 1. Within the clock of 196MHz, the total decoding time is less than twice the time (n / 4) of inputting a frame of data, which effectively avoids the occurrence of blocking.

[0145] Among them, according to the DVB-S2 high-speed parallel BCH code decoder provided by the above embodiments, the N-way parallel Qian search module is also used to: make a small lookup table containing initial values, and based on the small lookup table, in each round of calculation, obtain the check code for the next round of verification through iteration.

[0146] It can be understood that the present invention determines the initial value by making a small-scale lookup table, and then performs iterative calculations through Galois field multipliers, and reuses multipliers between different steps, effectively reducing the occupation of hardware resources. The initial value is defined as α to α 4i After the current root test operation, the used α value is updated for the next step. In this way, the production of the entire extended domain element lookup table is converted into the use of multipliers. Since more multipliers are required during Chien search, the multipliers used in the previous two steps can be reused, thereby reducing resource consumption.

[0147] That is to say, considering that the Chien search algorithm and the process of finding the companion formula in the present invention have certain commonalities, the Chien search circuit of the present invention also incorporates the finite field multiplier iteration method into it, and also merges it into the process of outputting data. In addition, while using the finite field multiplier iteration method, a small-scale lookup table is used to determine the initial value, so it is possible to omit the process of finding the initial Galois field value through the multiplier and directly start the root test and add the output data. Since the extended domain elements used in each root test have regularity compared to the previous time, and the regularity is similar to the companion formula process, the Chien search circuit of the present invention reuses the multiplier and the lookup table used in the process of finding the companion formula, which reduces resource consumption to a certain extent.

[0148] The present invention combines the preparation of a small-scale lookup table with iteration, and can directly obtain the corresponding Galois field initial value each time, thereby accelerating the decoding speed. For example, in the case of 4-way parallel operation, the decoding time of the shortest code of the DVB-S2 protocol can be shortened by about 1 / 8.

[0149] According to the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the N-way parallel companion computing module is optionally implemented by pure FPGA, and the N-way parallel companion computing module is specifically used for:

[0150] While receiving the codeword polynomial of the BCH code to be decoded, iterating through a finite field multiplier to obtain a finite field element at a corresponding position in a BCH code check matrix;

[0151] Horner's rule is used to decompose and synchronously perform N-bit calculations, and the BCH code check matrix and the corresponding positions of the code word polynomial are multiplied and accumulated to obtain the syndrome result at the next clock after the BCH code to be decoded is input.

[0152] It can be understood that the N-way parallel circuit of the present invention can be described in detail by taking a 4-way parallel circuit as an example. The 4-way parallel syndrome calculation circuit is implemented by pure FPGA, and the solution of the syndrome is incorporated into the input data process using the finite field multiplier iteration method. While receiving the BCH code data to be decoded to form the codeword polynomial, the finite field elements of the corresponding positions in the check matrix are obtained by iteration, and the Horner's rule is used to decompose, and 4-bit calculations can be performed synchronously, and then the corresponding positions of the check matrix and the codeword polynomial are multiplied and accumulated, and the syndrome result can be obtained immediately at the next clock after the input data is completed.

[0153] In the present invention, the N-way parallel syndrome calculation module uses a finite field multiplier iteration and a method of determining an initial value using a small-scale lookup table. No index table of all the extended domain elements required is prepared, so no soft core or external storage chip is required. The initial value required to start iteration when calculating the syndrome has been stored in the small lookup table in advance, so it is not necessary to calculate the initial Galois field value through a multiplier and directly start inputting data plus syndrome iteration.

[0154] Among them, the DVB-S2 high-speed parallel BCH code decoder provided according to the above embodiments is optional, and the BCH code check matrix is ​​expressed as:

[0155]

[0156] Wherein, H represents the BCH code check matrix, α represents the extended domain element, n represents the code length of the BCH code to be decoded, and t represents the maximum error correction number;

[0157] The syndrome result is expressed in a matrix as follows:

[0158] S=(s 1 ,s 2 ,s 3 ,…,s 2t );

[0159] In the formula, S represents the result matrix of the companion formula, where S 1 ,S 2 ,...,S 2t The syndrome results of multiplying the BCH code check matrix and the codeword polynomial are all in the form of extended domain elements;

[0160] The codeword polynomial of the BCH code to be decoded is expressed as:

[0161] R(x)=r n-1 x n-1 +r n-2 x n-2 +…+r 1 x 1 +r0 ;

[0162] Wherein, R(x) represents the codeword polynomial, the codeword polynomial is the input signal, r n-1 ,r n-2 ,...,r 0 represents the polynomial coefficient, and x represents the polynomial variable;

[0163] The syndrome result can be obtained by solving the following formula:

[0164] S T =H·R T .

[0165] It can be understood that when the BCH code to be decoded is input, the BCH code to be decoded is formed into a receiving codeword polynomial R(x), and the BCH code check matrix H can be defined in advance as shown above. Then, when the two are known, it can be obtained according to S T =H·R T Obtain the companion polynomial S. In order to shorten the time for calculating the companion polynomial as much as possible, the iterative calculation of the companion polynomial is started at each clock of input data, and the iteration is completed when the last N bits of data are input.

[0166] According to Horner's law, the calculation formula of S can be converted into a nested form. When 4-bit data is input in parallel, 4-bit parallel calculation is also required when calculating the companion formula as follows:

[0167] s i =(……(r n-1 *α 3i +r n-2 *α 2i +r n-3 *α i +r n-4 )

[0168] *α 4i +r n-5 *α 3i ……+r 1 )*α i +r 0

[0169] Therefore, at each input clock, the corresponding α is superimposed according to the input 4-bit data. i to α 3i , its circuit structure is as follows Figure 5 The figure is a schematic diagram of the structure of the syndrome calculation circuit in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. In the Galois field, the addition is the exclusive OR of the 16-fold representation of the two, and then multiplied by α after superposition. 4iIn this way, the syndrome result can be output immediately at the next clock after the input data is completed, where i represents the i-th item in the syndrome. The final syndrome module input and output timing diagram is as follows: Figure 6 FIG. 1 is a schematic diagram of the input and output timing of the syndrome calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention.

[0170] Among them, the DVB-S2 high-speed parallel BCH code decoder provided according to the above embodiments is optional, and the error correction module is specifically used to: if the judgment result is that there is an error, flip the N-bit BCH code currently being verified to achieve error correction, and output the corrected data as the high-speed parallel decoding result.

[0171] It can be understood that the error detection and error correction circuits in the present invention are integrated into the data output process. Since an N-bit (e.g., 4-bit) parallel output mechanism is adopted, after each N-bit simultaneous root verification operation is performed, the N bits being tested are flipped according to the test results and directly output. After the entire codeword polynomial is tested, all data are also output.

[0172] Furthermore, based on the DVB-S2 high-speed parallel BCH code decoder provided according to the above embodiments, the DVB-S2 high-speed parallel BCH code decoder of the present invention also includes: a parameter configuration module, used to: configure parameters including the order of predefined polynomial factors in the BCH decoder, the maximum error correction capability code and the word polynomial length.

[0173] It can be understood that the DVB-S2 high-speed parallel BCH code decoder of the present invention also includes a corresponding parameter configuration module for configuring parameters of each module of the decoder, and executing the corresponding adjoint process, error polynomial solution process, Qian's search root test and error correction process according to the configuration parameters required by the corresponding system. The configured parameters include the order of the predefined polynomial factors in the BCH decoder (corresponding to the long and short code indication signal), the maximum error correction capability and the codeword polynomial length (corresponding to the data bit length, i.e., the information bit length plus the generator polynomial length), etc.

[0174] Based on the same inventive concept, the present invention further provides a DVB-S2 high-speed parallel BCH code decoding method according to the above embodiments, which realizes high-speed parallel decoding of BCH codes in DVB-S2 by applying the DVB-S2 high-speed parallel BCH code decoder provided by the above embodiments. Therefore, the description and definition in the DVB-S2 high-speed parallel BCH code decoder in the above embodiments can be used for understanding the relevant processing steps in the present invention, and the above embodiments can be specifically referred to, which will not be repeated here.

[0175] According to one embodiment of the present invention, the processing flow of the DVB-S2 high-speed parallel BCH code decoding method is as follows: Figure 7 FIG. 1 is a flow chart of a DVB-S2 high-speed parallel BCH code decoding method provided by the present invention. The method can be implemented by applying the DVB-S2 high-speed parallel BCH code decoder of each of the above embodiments, and specifically includes the following processing steps:

[0176] S701, performing N-way parallel syndrome calculation on the BCH code to be decoded to obtain syndrome results;

[0177] S702, using the iBM algorithm without inversion, by performing multiple iterative operations on the syndrome result, to determine an error position polynomial output result;

[0178] S703, based on the error position polynomial output result, using a small lookup table containing an initial value, by iteratively updating the judgment N bits at a time, determining whether an error occurs in the information position of the BCH code to be decoded, and outputting the judgment result;

[0179] S704: output a high-speed parallel decoding result of the BCH code to be decoded based on the BCH code to be decoded and the judgment result.

[0180] Specifically, the BCH code FPGA decoder module circuits are connected by ports. After the signal enters the decoder, it is input into the N-way parallel syndrome calculation module and the data storage module of the error correction module. The N-way parallel syndrome calculation module outputs the multiple syndrome results obtained in parallel to the error polynomial calculation module through multiple channels. The error polynomial calculation module inputs the error pattern into the N-way parallel Qian's search module, i.e., the Chien search module. In addition to its own finite field multiplier, the Chien search module also reuses the finite field multiplier and small-scale lookup table in the syndrome module. It judges whether the input codeword polynomial has an error through the finite field multiplier and the small-scale lookup table, and outputs the judgment result to the error correction module. The error correction module receives the codeword polynomial in the data storage module, and outputs the final data as the final high-speed parallel decoding result after error correction processing.

[0181] The DVB-S2 high-speed parallel BCH code decoding method provided by the present invention adopts multi-bit parallel input and output data, that is, the syndrome calculation is directly merged into the input data for multi-bit parallel calculation, and is directly output in parallel during the Qian search. At the same time, the calculation of the error polynomial uses the inverse-free BM algorithm (iBM algorithm), so that the total decoding time in the overall decoding process is compressed to much less than 1 / 2 of the input data time, successfully avoiding blocking and effectively improving the timeliness of the decoding process.

[0182] It is to be understood that the embodiments of the system described above are merely illustrative, and the units described as separate components may or may not be physically separated, and may be located in one place, or may be distributed on different network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art may understand and implement the solution without creative effort.

[0183] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, etc., including a number of instructions to enable a computer device (such as a personal computer, a server, or a network device, etc.) to execute the methods described in the above method embodiments or some parts of the method embodiments.

[0184] In addition, it should be understood by those skilled in the art that, in the application documents of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0185] In the specification of the present invention, a large number of specific details are described. However, it should be understood that embodiments of the present invention can be practiced without these specific details. In some examples, known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this specification. Similarly, it should be understood that in order to simplify the disclosure of the present invention and help understand one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure or description thereof.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DVB-S2 high-speed parallel BCH code decoder, characterized in that: include: N-way parallel syndrome calculation module, error polynomial calculation module, N-way parallel Qian's search module and error correction module; The input end of the N-way parallel syndrome calculation module is connected in parallel with the first input end of the error correction module, and then connected to the input end of the BCH code data to be decoded of DVB-S2, the output end of the N-way parallel syndrome calculation module is connected to the input end of the error polynomial calculation module, the output end of the error polynomial calculation module is connected to the input end of the N-way parallel Qian's search module, the output end of the N-way parallel Qian's search module is connected to the second input end of the error correction module, and the output end of the error correction module is connected to the decoding output end; The N-way parallel syndrome calculation module is used to perform N-way parallel syndrome calculation on the BCH code to be decoded to obtain syndrome results; The error polynomial calculation module is used to determine the error position polynomial output result by performing multiple iterative operations on the syndrome result using the iBM algorithm without inversion; The N-way parallel Qian's search module is used to output the result based on the error position polynomial, use a small lookup table containing an initial value, and iteratively update the judgment by N bits one by one to determine whether an error occurs in the information position of the BCH code to be decoded, and output the judgment result; The error correction module is used to output a high-speed parallel decoding result of the BCH code to be decoded based on the BCH code to be decoded and the judgment result.

2. The DVB-S2 high-speed parallel BCH code decoder according to claim 1, characterized in that: The error polynomial calculation module is specifically used for: Calculate the correction term parameters required for each round of iteration according to the syndrome results corresponding to each round of iteration of the non-inversion iBM algorithm, and determine whether the correction term parameters are 0; If the correction term parameter of any round of iteration is not 0, the coefficients of the current error polynomial are updated, and the updated error polynomial is used as the error pattern; The difference between the updated error polynomial and the current error polynomial is calculated, and the difference is added to the correction term parameter calculation of the next round of iteration until the operation of all the syndrome results is completed, and the error position polynomial output result is output according to the error pattern.

3. The DVB-S2 high-speed parallel BCH code decoder according to claim 2, characterized in that: The algorithm flow of the non-inverse iBM algorithm is as follows: Determine the initial value as μ (0) (x)=1,λ (0) (x)=1,l (0) =0,γ (k) =1(k≤0); According to the following formula, calculate the correction parameter δ (k+1) : In the formula, Represents μ k (x) j The coefficient of the term, s represents the companion matrix in the iterative process, k represents the number of iterations, l represents the intermediate quantity, and the correction term parameter δ k and the intermediate quantity l act as judgment conditions in the iteration process; According to the correction parameter δ (k+1) , the difference is calculated according to the following formula: m (k+1) (x)=γ (k) m (k) (x)-d (k+1) l (k) (x)x; Wherein, μ(x) represents the difference, γ k and λ(x) represent the iterative intermediate variables introduced to replace the inversion process; According to the difference, update the coefficients of the current error polynomial according to the following rules: If δ (k+1) ≠0 and 2l (k) ≤k, then: l (k+1) (x)=μ (k) l (k+1) ＝k+1-l (k) c (k+1) =d (k+1) If δ (k+1) =0 or 2l (k) >k, then: l (k+1) (x)=xλ (k) (x) l (k+1) ＝l (k) c (k+1) =c (k) Repeat the above calculation and update steps for multiple iterations until after 2t iterations, μ(x) = μ (2t) (x); Since the first equation: and k is a non-zero constant, then the error position polynomial output result is obtained by solving the first equation; The error polynomial σ(x) is expressed as: In the formula, σ1, σ2, ..., σ t represents the coefficients of the error polynomial, and the roots of the error polynomial are the inverses of the error positions.

4. The DVB-S2 high-speed parallel BCH code decoder according to claim 1, characterized in that: The N-way parallel Qian's search module is specifically used for: Starting from the highest bit of the error position polynomial output result, the N-bit check code α is converted to i+N-1 , ..., α i+1 , α i ,i=nN,...,2N,0 inverse (α i+N-1 ) -1 =α, ..., (α i+1 ) -1 =α、(α i ) -1 =α, respectively substitute into the error position polynomial output results, and observe whether the error position polynomial output results are 0 in parallel. If the result corresponding to any bit is 0, it is determined that an error occurs in the bit, otherwise there is no error.

5. The DVB-S2 high-speed parallel BCH code decoder according to claim 4, characterized in that: The N-way parallel Qian's search module is also used for: A small lookup table containing initial values ​​is prepared, and based on the small lookup table, in each round of calculation, a check code for the next round of check is obtained through iteration.

6. The DVB-S2 high-speed parallel BCH code decoder according to claim 1, characterized in that: The N-way parallel companion computing module is implemented by pure FPGA, and the N-way parallel companion computing module is specifically used for: While receiving the codeword polynomial of the BCH code to be decoded, iterating through a finite field multiplier to obtain a finite field element at a corresponding position in a BCH code check matrix; Horner's rule is used to decompose and synchronously perform N-bit calculations, and the BCH code check matrix and the corresponding positions of the code word polynomial are multiplied and accumulated to obtain the syndrome result at the next clock after the BCH code to be decoded is input.

7. The DVB-S2 high-speed parallel BCH code decoder according to claim 6, characterized in that: The BCH code check matrix is ​​expressed as: Wherein, H represents the BCH code check matrix, α represents the extended domain element, n represents the code length of the BCH code to be decoded, and t represents the maximum error correction number; The syndrome result is expressed in a matrix as follows: <h2 style=";text-align:left;direction:ltr">S = (s1,s2,s3,…,s)<h2 style=";text-align:left;direction:ltr"> 2t <h2 style=";text-align:left;direction:ltr"> ); Where S represents the result matrix of the syndrome, where S1, S2, ..., S 2t The syndrome results of multiplying the BCH code check matrix and the codeword polynomial are all in the form of extended domain elements; The codeword polynomial of the BCH code to be decoded is expressed as: R(x)=r n-1 x n-1 +r n-2 x n-2 +…+r1x 1 +r0; Wherein, R(x) represents the codeword polynomial, the codeword polynomial is the input signal, r n-1 ,r n-2 ,...,r0 represents the polynomial coefficient, x represents the polynomial variable; The syndrome result can be obtained by solving the following formula: S T =H·R T 。 8. The DVB-S2 high-speed parallel BCH code decoder according to any one of claims 1 to 7, characterized in that: The error correction module is specifically used for: If the judgment result is that an error exists, the N-bit BCH code currently being verified is flipped to achieve error correction, and the corrected data is output as the high-speed parallel decoding result.

9. The DVB-S2 high-speed parallel BCH code decoder according to any one of claims 1 to 7, characterized in that: Also includes parameter configuration modules for: The configuration includes parameters for the order of the predefined polynomial factors in the BCH decoder, the maximum error correction capability code, and the word polynomial length.

10. A DVB-S2 high-speed parallel BCH code decoding method, characterized in that: The method is implemented by the DVB-S2 high-speed parallel BCH code decoder according to any one of claims 1 to 9, comprising: Performing N-way parallel syndrome calculations on the BCH code to be decoded to obtain syndrome results; Using the non-inverse iBM algorithm, by performing multiple iterative operations on the syndrome result, the error position polynomial output result is determined; Based on the error position polynomial output result, using a small lookup table containing an initial value, by iteratively updating the judgment N bits at a time, determine whether an error occurs in the information position of the BCH code to be decoded, and output the judgment result; Based on the BCH code to be decoded and the judgment result, a high-speed parallel decoding result of the BCH code to be decoded is output.

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