DVB-S2 High-Speed ​​Parallel BCH Code Decoder and Decoding Method

Abstract

This invention provides a DVB-S2 high-speed parallel BCH code decoder and its decoding method. The decoder includes an N-way parallel syndrome calculation module, an error polynomial calculation module, an N-way parallel Chan's search module, and an error correction module. These modules perform N-way parallel syndrome calculations on the BCH code to be decoded to obtain the syndrome result; using the iBM algorithm, the error position polynomial is determined by iteratively calculating the syndrome result multiple times; based on the error position polynomial output result, a small lookup table containing initial values ​​is used to determine whether an error has occurred in the information position of the BCH code to be decoded, and the judgment result is output; finally, based on the BCH code to be decoded and the judgment result, the high-speed parallel decoding result is output. This invention uses multi-bit parallel input and output data and utilizes the iBM algorithm to calculate the error polynomial, effectively improving the timeliness of the decoding process.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a DVB-S2 high-speed parallel BCH code decoder and its decoding method. Background Technology

[0002] The BCH code decoding process generally includes several steps: finding the synodus, finding the error polynomial, and Chan's search. All three steps involve the calculation of the Galois field. The commonly used method for this calculation is to create a lookup table for the extended field elements, transforming finite field multiplication into addition and subtraction of its exponents, and writing the extended field elements as fixed constants into the FPGA pre-compiled header file or the soft core. The result is then obtained by looking up the table.

[0003] When using a pure FPGA to compute the Galois field, a finite field multiplier can be used. The commonly used method is to reuse the finite field multiplier through iteration, incorporating the iteration process into the input and output data of the decoding process, and incidentally obtaining the elements of the higher-order Galois field.

[0004] However, in the DVB-S2 protocol, BCH code decoding uses GF(2) 16 ) and GF(2 14 Implementing this on an FPGA requires creating two lookup tables each with sizes of 65535×16 and 16383×14. If static storage is used, multiple lookup tables would need to be repeatedly created to ensure simultaneous read and write operations due to multi-channel parallel decoding, significantly consuming storage resources.

[0005] Furthermore, for the iterative method of finite field multipliers, when performing multi-path parallel decoding, the initiation of the synod process requires some higher-order Galois field elements. If these are obtained through pure iteration, a large number of iterations will be performed, which will also consume a long amount of time and resources.

[0006] If a lookup table method is implemented using a SOC chip and stored in the soft core, it is difficult to meet the real-time requirements of high-speed decoding because it is usually processed serially, requiring multiple machine cycles to complete one instruction cycle, and there is a propagation delay in data interaction between the PS and PL ends. Summary of the Invention

[0007] This invention provides a DVB-S2 high-speed parallel BCH code decoder and its decoding method to overcome the shortcomings of poor decoding timeliness in existing technologies, thereby achieving the goal of effectively shortening decoding time and improving decoding efficiency.

[0008] This invention provides a DVB-S2 high-speed parallel BCH code decoder, comprising: an N-channel parallel syntactic computation module, an error polynomial computation module, an N-channel parallel Chan's search module, and an error correction module;

[0009] The input terminal of the N-way parallel adjoint computation module is connected in parallel with the first input terminal of the error correction module, and then connected to the BCH code data input terminal of the DVB-S2 to be decoded. The output terminal of the N-way parallel adjoint computation module is connected to the input terminal of the error polynomial computation module. The output terminal of the error polynomial computation module is connected to the input terminal of the N-way parallel Chan's search module. The output terminal of the N-way parallel Chan's search module is connected to the second input terminal of the error correction module. The output terminal of the error correction module is connected to the decoding output terminal.

[0010] The N-way parallel syndrome calculation module is used to perform N-way parallel syndrome calculation on the BCH code to be decoded and obtain the syndrome result.

[0011] The error polynomial calculation module is used to determine the error position polynomial output result by performing multiple iterative operations on the adjoint result using the invertless iBM algorithm.

[0012] The N-way parallel Chan's search module is used to determine whether an error has occurred in the information position of the BCH code to be decoded based on the error position polynomial output result, using a small lookup table containing initial values, and updating the judgment bit by bit through N-bit iteration, and output the judgment result.

[0013] The error correction module is used to output a high-speed parallel decoding result for the BCH code to be decoded based on the BCH code to be decoded and the judgment result.

[0014] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, wherein the error polynomial calculation module is specifically used for:

[0015] Based on the adjoint result corresponding to each iteration of the invertible iBM algorithm, calculate the correction term parameter required for each iteration, and determine whether the correction term parameter is 0;

[0016] If the correction term parameter in any iteration is not 0, then update the coefficients of the current erroneous polynomial and use the updated erroneous polynomial as the error pattern.

[0017] Calculate the difference between the updated error polynomial and the current error polynomial, and add the difference to the calculation of the correction term parameter in the next iteration until the operation of all the adjoint results is completed. Then, output the error position polynomial output result according to the error pattern.

[0018] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, and the algorithm flow of the invertible iBM algorithm is as follows:

[0019] The initial value is determined to be μ.(0) (x)=1,λ (0) (x)=1,l (0) =0,γ (k) =1 (k≤0);

[0020] Calculate the correction term parameter δ according to the following formula. (k+1) :

[0021]

[0022] In the formula, μ k (x) in x j The coefficients of the term, s represents the adjoint matrix in the iteration process, k represents the iteration number, l represents intermediate quantities, and the correction term parameter δ k The intermediate quantity l serves as a judgment condition during the iteration process;

[0023] According to the correction term parameter δ (k+1) The difference is calculated using the following formula:

[0024] μ (k+1) (x)=γ (k) μ (k) (x)-δ (k+1) λ (k) (x)x;

[0025] In the formula, μ(x) represents the difference, and γ k λ(x) represents the introduced intermediate variables in the iteration, used to replace the process of finding the inverse;

[0026] Based on the difference, the coefficients of the current erroneous polynomial are updated according to the following rules:

[0027] If δ (k+1) ≠0 and 2l (k) If k ≤ k, then:

[0028] λ (k+1) (x)=μ (k)

[0029] l (k+1) =k+1-l (k)

[0030] γ (k+1) =δ (k+1)

[0031] If δ (k+1) =0 or 2l (k) >k, then:

[0032] λ (k+1) (x)=xλ (k) (x)

[0033] l (k+1) =l (k)

[0034] γ (k+1) =γ (k)

[0035] Repeat the above calculation and update steps, performing multiple iterations until, after 2t iterations, we can obtain μ(x) = μ (2t) (x);

[0036] Because of the first equation:

[0037]

[0038] And since k is a non-zero constant, the error position polynomial output result can be obtained by solving the first equation;

[0039] The error polynomial σ(x) is expressed as:

[0040]

[0041] In the formula, σ1, σ2, ..., σ t The coefficients of the erroneous polynomial are represented by the roots of the erroneous polynomial, which are the reciprocals of the erroneous positions.

[0042] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, wherein the N-channel parallel Chan's search module is specifically used for:

[0043] Starting from the most significant bit of the output result of the polynomial at the error location, increment the check code α bit by bit N. i+N-1 ..., α i+1 α i The inverse of ,i=nN,...,2N,0 (α) i+N-1 ) -1 =α、...、(α i+1 ) -1 =α、(α) i ) -1 =α, respectively, and substitute into the output result of the error position polynomial, and observe in parallel N bits whether the output result of the error position polynomial is 0. If the result corresponding to any bit is 0, it is determined that an error has occurred at that bit; otherwise, there is no error.

[0044] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, wherein the N-channel parallel Chan's search module is further used for:

[0045] A small lookup table containing initial values ​​is created, and based on the small lookup table, the checksum for the next round of verification is obtained through iteration in each round of calculation.

[0046] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, wherein the N-channel parallel syndrome calculation module is implemented using a pure FPGA, and the N-channel parallel syndrome calculation module is specifically used for:

[0047] While receiving the codeword polynomial composed of the BCH code to be decoded, the finite field elements at the corresponding positions in the BCH code parity check matrix are obtained through iteration of the finite field multiplier.

[0048] Horner's rule is used for decomposition, N-bit calculations are performed synchronously, and the corresponding positions of the BCH code parity-check matrix and the codeword polynomial are multiplied and accumulated to obtain the syndrome result in the next clock cycle after the BCH code to be decoded is input.

[0049] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, wherein the BCH code parity check matrix is ​​represented as follows:

[0050]

[0051] In the formula, H represents the BCH code parity check matrix, α represents the extended field element, n represents the code length of the BCH code to be decoded, and t represents the maximum number of error corrections.

[0052] The adjoint result is represented by a matrix as follows:

[0053] S=(s1,s2,s3,…,s 2t );

[0054] In the formula, S represents the adjoint result matrix, where S1, S2, ..., S 2t The result of multiplying the BCH code parity check matrix by the codeword polynomial is in extended field element form.

[0055] The codeword polynomial of the BCH code to be decoded is represented as follows:

[0056] R(x)=r n-1 x n-1 +r n-2 x n-2 +…+r1x 1 +r0;

[0057] In the formula, R(x) represents the codeword polynomial, which is the input signal, r n-1 ,r n-2 r0 represents the polynomial coefficients, and x represents the polynomial variable;

[0058] The result of the adjoint equation can then be obtained by solving the following formula:

[0059] S T =H·R T .

[0060] According to the present invention, a DVB-S2 high-speed parallel BCH code decoder is provided, wherein the error correction module is specifically used for:

[0061] If the judgment result indicates an error, the N-bit BCH code currently being verified is flipped to correct the error, and the corrected data is output as the result of the high-speed parallel decoding.

[0062] A DVB-S2 high-speed parallel BCH code decoder provided by the present invention further includes a parameter configuration module for:

[0063] The configuration includes parameters such as the order of the predefined polynomial factors in the BCH decoder, the maximum error-correcting code, and the word polynomial length.

[0064] This invention also provides a DVB-S2 high-speed parallel BCH code decoding method, implemented using any of the DVB-S2 high-speed parallel BCH code decoders described above, the method comprising:

[0065] Perform N-way parallel syndrome calculation on the BCH code to be decoded to obtain the syndrome result;

[0066] Using the invertless iBM algorithm, the polynomial output result at the error location is determined by performing multiple iterative operations on the adjoint result.

[0067] Based on the error position polynomial output result, using a small lookup table containing initial values, the system iteratively updates the judgment bit by bit to determine whether an error has occurred in the information position of the BCH code to be decoded, and outputs the judgment result.

[0068] Based on the BCH code to be decoded and the judgment result, the high-speed parallel decoding result of the BCH code to be decoded is output.

[0069] The DVB-S2 high-speed parallel BCH code decoder and its decoding method provided by this invention employ multi-bit parallel input and output data. That is, the synod calculation is directly merged into the input data for multi-bit parallel calculation, and the output is directly parallel during the Chan search. At the same time, the error polynomial calculation uses the invertless BM algorithm (iBM algorithm), which compresses the total decoding time in the overall decoding process to much less than 1 / 2 of the input data time, successfully avoiding blocking situations and effectively improving the timeliness of the decoding process. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0071] Figure 1 A schematic diagram of the structure of the DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0072] Figure 2 This is a schematic diagram of the input-output timing of the error polynomial calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention.

[0073] Figure 3 A schematic diagram of the Chan search circuit in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0074] Figure 4 This is a schematic diagram of the input and output timing of the decoder in the DVB-S2 high-speed parallel BCH code decoder provided according to the present invention;

[0075] Figure 5 A schematic diagram of the synergistic calculation circuit in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0076] Figure 6 A schematic diagram of the input-output timing of the synergistic calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention;

[0077] Figure 7 This is a flowchart illustrating the DVB-S2 high-speed parallel BCH code decoding method provided by the present invention. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0079] This invention addresses the poor timeliness of existing BCH code decoding technologies by employing multi-bit parallel input / output data. Specifically, the adjoint equation calculation is directly integrated into the input data for multi-bit parallel computation, and the results are directly output in parallel during the Chancellor search. Simultaneously, the error polynomial calculation utilizes the invertless BM algorithm (iBM algorithm), compressing the total decoding time to far less than half the input data time. This successfully avoids blocking and effectively improves the timeliness of the decoding process. The invention will be further illustrated and described below through several specific embodiments.

[0080] Figure 1 This is a schematic diagram of the structure of the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. This decoder is a high-speed parallel BCH code decoder for DVB-S2 / DVB-S2X systems, implemented using an FPGA. It can be used to achieve high-speed parallel decoding of BCH codes in DVB-S2 / DVB-S2X systems. Figure 1 As shown, the decoder includes an N-channel parallel syndrome calculation module 101, an error polynomial calculation module 102, an N-channel parallel Chan's search module 103, and an error correction module 104. Wherein:

[0081] The input terminal of the N-way parallel adjoint calculation module 101 is connected in parallel with the first input terminal of the error correction module 104, and then connected to the input terminal of the BCH code data to be decoded in the DVB-S2. The output terminal of the N-way parallel adjoint calculation module 101 is connected to the input terminal of the error polynomial calculation module 102. The output terminal of the error polynomial calculation module 102 is connected to the input terminal of the N-way parallel Chan's search module 103. The output terminal of the N-way parallel Chan's search module 103 is connected to the second input terminal of the error correction module 104. The output terminal of the error correction module 104 is connected to the decoding output terminal.

[0082] The N-way parallel syndrome calculation module 101 is used to perform N-way parallel syndrome calculation on the BCH code to be decoded and obtain the syndrome result.

[0083] The error polynomial calculation module 102 is used to determine the error position polynomial output result by performing multiple iterative operations on the adjoint result using the invertless iBM algorithm.

[0084] The N-way parallel Chan's search module 103 is used to determine whether an error has occurred in the information position of the BCH code to be decoded based on the error position polynomial output result, using a small lookup table containing initial values, and updating the judgment bit by bit through N-bit iteration, and output the judgment result.

[0085] The error correction module 104 is used to output the high-speed parallel decoding result of the BCH code to be decoded based on the BCH code to be decoded and the judgment result.

[0086] This can be understood as, for example Figure 1 As shown, the DVB-S2 high-speed parallel BCH code decoder of the present invention should include at least an N-channel parallel syndrome calculation module 101, an error polynomial calculation module 102, an N-channel parallel Chan's search module 103, and an error correction module 104. The connection relationships between these modules are also as follows: Figure 1 As shown, these are used to implement the processing flow of adjoint computation, error polynomial computation, Chan search, and error correction, respectively.

[0087] Specifically, when decoding the BCH code in the DVB-S2 protocol, the input data to be decoded, i.e., the BCH code to be decoded, is first stored in the data storage module of the error correction module 104 for easy retrieval later. At the same time, the BCH code data to be decoded is sent to the N-channel parallel syndrome calculation module 101 for syndrome calculation. When the input BCH code data to be decoded is completed, the syndrome calculation is also completed.

[0088] Next, the adjoint result output by the N-way parallel adjoint calculation module 101 is input to the error position polynomial calculation module, i.e., the error polynomial calculation module 102, to start iterative calculation of the error position polynomial. After 2t iterations, the result is output as the error position polynomial output result.

[0089] Then, the error position polynomial output result, i.e., the error position polynomial, is input into the N-way parallel Chan's search module 103 for Chan's search. Starting from the most significant bit, it searches bit by bit (e.g., bit by bit, 4 bits at a time) to determine whether an error has occurred in the position of the information to be decoded. Combined with the data storage module in the error correction module 104, the decoding result is output in real time. When the Chan's search for the least significant bit is completed, the decoding is finished, and all the decoding result data is output.

[0090] It should be understood that in the DVB-S2 protocol of this invention, the BCH code is the external code and the LDPC code is the internal code. BCH decoding is used to address the problem that a few uncorrectable errors (error planes) exist when LDPC decoding reaches its performance limit. Table 1 shows the error correction coding parameter table specified in the DVB-S2 protocol. The BCH decoding in this invention adopts a hard-decision approach, which can stably correct all decoding errors within the maximum error correction capability range.

[0091] Table 1. BCH Error Correction Code Parameter Table in DVB-S2

[0092]

[0093]

[0094] BCH long code is defined in GF(2). 16 In the domain, the primitive polynomial is 1 + x 2 +x 3+x 5 +x 16 Short codes are defined in GF(2); 14 On the polynomial ), the primitive polynomial is 1 + x + x. 3 +x 5 +x 14 .

[0095] When decoding involves operations in the Galois field, a common method is to create and use an extended field element lookup table. However, considering that the lookup table required for the DVB-S2 protocol is too large, dynamic storage would consume most of the hardware resources, and static storage would result in a significant waste of resources during parallel decoding, this invention uses a Galois field general-purpose multiplier.

[0096] Taking long codes as an example, first in GF(2 16 Any element in the expression can be represented by a polynomial of degree less than 16 (here called the 16-fold representation). When multiplying, polynomial multiplication is performed first in the conventional way to obtain an intermediate variable of degree no greater than 30.

[0097] Secondly, its primitive polynomial is represented as 1 + x 2 +x 3 +x 5 +x 16 Then x 16 =1+x 2 +x 3 +x 5 Based on this, x can be sequentially... 16 To x 30 The result is transformed into a linear combination of natural bases. Substituting the result into the variables of the previous step, after combinational cancellation, a 16-fold representation of the product of field elements can be obtained. The circuit designed based on this logical relationship is a pure combinational logic circuit, which can obtain the output result in only one clock cycle. The actual circuit uses 256 AND gates and 633 XOR gates in one multiplier. The input and output interface of the decoder is described in Table 2.

[0098] Table 2, BCH code decoder interface description table

[0099]

[0100]

[0101] The DVB-S2 high-speed parallel BCH code decoder provided by this invention employs multi-bit parallel input and output data. That is, the synod calculation is directly merged into the input data for multi-bit parallel calculation, and the output is directly parallel during the Chan search. At the same time, the error polynomial calculation uses the invertless BM algorithm (iBM algorithm), which compresses the total decoding time in the overall decoding process to much less than 1 / 2 of the input data time, successfully avoiding blocking situations and effectively improving the timeliness of the decoding process.

[0102] In the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the error polynomial calculation module is specifically used for:

[0103] Based on the adjoint result corresponding to each iteration of the invertible iBM algorithm, calculate the correction term parameter required for each iteration, and determine whether the correction term parameter is 0;

[0104] If the correction term parameter in any iteration is not 0, then update the coefficients of the current erroneous polynomial and use the updated erroneous polynomial as the error pattern.

[0105] Calculate the difference between the updated error polynomial and the current error polynomial, and add the difference to the calculation of the correction term parameter in the next iteration until the operation of all the adjoint results is completed. Then, output the error position polynomial output result according to the error pattern.

[0106] It can be understood that the algorithm used in the circuit of the error polynomial calculation module of the present invention is the invertless BM algorithm, that is, based on the obtained multiple adjoint equation results, the error pattern is obtained by iterative calculation according to the iBM algorithm.

[0107] Specifically, in each iteration, the correction term parameters required for the iteration are calculated based on the adjoint result corresponding to the error position polynomial algorithm iteration. Then, it is determined whether the correction term parameter is zero. If the correction term parameter in any iteration is not zero, it indicates a deviation. The coefficients of each term in the error polynomial are then updated, and the updated error polynomial is used as the error pattern. Simultaneously, the difference between the updated error polynomial and the current error polynomial before the update is calculated, and this difference is added to the calculation of the correction term parameters for the next iteration.

[0108] In each round of iterative computation of the error polynomial calculation module, the above computation steps are repeated to calculate the adjoint result until the computation of all adjoint results is completed. Then, the error position polynomial output result is output according to the determined error pattern.

[0109] Among them, the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments is optional, and the algorithm flow of the invertible iBM algorithm is as follows:

[0110] The initial value is determined to be μ. (0) (x)=1,λ (0) (x)=1,l (0) =0,γ (k) =1 (k≤0);

[0111] Calculate the correction term parameter δ according to the following formula. (k+1) :

[0112]

[0113] In the formula, μ j (k) μ k (x) in x j The coefficients of the term, s represents the adjoint matrix in the iteration process, k represents the iteration number, l represents intermediate quantities, and the correction term parameter δ k The intermediate quantity l serves as a judgment condition during the iteration process;

[0114] According to the correction term parameter δ (k+1) The difference is calculated using the following formula:

[0115] μ (k+1) (x)=γ (k) μ (k) (x)-δ (k+1) λ (k) (x)x;

[0116] In the formula, μ(x) represents the difference, and γ k λ(x) represents the introduced intermediate variables in the iteration, used to replace the process of finding the inverse;

[0117] Based on the difference, the coefficients of the current erroneous polynomial are updated according to the following rules:

[0118] If δ (k+1) ≠0 and 2l (k) If k ≤ k, then:

[0119] λ (k+1) (x)=μ (k)

[0120] l (k+1) =k+1-l (k)

[0121] γ (k+1) =δ (k+1)

[0122] If δ(k+1) =0 or 2l (k) >k, then:

[0123] λ (k+1) (x)=xλ (k) (x)

[0124] l (k+1) =l (k)

[0125] γ (k+1) =γ (k)

[0126] Repeat the above calculation and update steps, performing multiple iterations until, after 2t iterations, we can obtain μ(x) = μ (2t) (x);

[0127] Because of the first equation:

[0128]

[0129] And since k is a non-zero constant, the error position polynomial output result can be obtained by solving the first equation;

[0130] The error polynomial σ(x) is expressed as:

[0131]

[0132] In the formula, σ1, σ2, ..., σ t The coefficients of the erroneous polynomial are represented by the roots of the erroneous polynomial, which are the reciprocals of the erroneous positions.

[0133] This can be understood as follows: to directly obtain the error pattern, it would be difficult to solve 2t equations for 2t unknowns. Therefore, this invention introduces the error polynomial σ(x).

[0134]

[0135] The t roots of the error polynomial are the reciprocals of the error positions. Given the adjoint and the maximum number of errors, the solution can be found. Currently, the commonly used method is the BM iterative decoding algorithm, but this involves inversion operations in finite fields, which is inconvenient for hardware implementation. Therefore, this invention proposes the aforementioned inversion-free BM algorithm, namely the iBM algorithm. The input-output timing diagram of the iBM algorithm module is shown below. Figure 2 The diagram shown is a schematic of the input-output timing of the error polynomial calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. The present invention divides the error polynomial solving process into a state machine for calculating σ(x), μ(x), and updating the information. (2t) (x)=kσ (2t)Since k is a non-zero constant, μ(x) has the same root as the error polynomial and is also the reciprocal of the error position. Furthermore, this invention incorporates γ. (k) This iterative term eliminates the inverse step, making it more convenient for hardware implementation.

[0136] It should be understood that in the DVB-S2 protocol, if the maximum error correction capability required is t, then a maximum of 2t cycles are needed. The total decoding clock cycle is on the order of hundreds of units. At the shortest code length, the error polynomial decoding time is less than half the input data time, which meets the requirements of high-speed decoding.

[0137] This invention's inverse-free BM algorithm adds a new iteration term γ compared to the BM algorithm. (k) This eliminates the need for inversion, making it more convenient for hardware implementation. In this invention, the process of solving the error polynomial is divided into several state machines, namely, calculating σ(x), μ(x), and updating the information. The number of iterations required is twice that of the maximum error correction capability.

[0138] In the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the N-way parallel Chan's search module is specifically used to: starting from the highest bit of the error position polynomial output result, sequentially extract the N-bit check code α bit by bit. i+N-1 ..., α i+1 α i The inverse of ,i=nN,...,2N,0 (α) i+N-1 ) -1 =α、...、(α i+1 ) -1 =α、(α) i ) -1 =α, respectively, and substitute into the output result of the error position polynomial, and observe in parallel N bits whether the output result of the error position polynomial is 0. If the result corresponding to any bit is 0, it is determined that an error has occurred at that bit; otherwise, there is no error.

[0139] This invention addresses the challenge of finding roots in extended fields during engineering projects. The Chien search algorithm, which checks each bit sequentially starting from the highest bit, outputs the results bit by bit. The Chien search algorithm employs a "root verification" method, solving the problem of finding roots for extended field elements in engineering. The root-finding process involves checking each bit sequentially starting from the highest bit, specifically the highest bit r. n-1 If it's wrong, then α n-1 inverse (α) n-1 ) -1 Substitute α into the error polynomial and observe whether the result is 0. If it is 0, it means that an error has occurred at that bit; otherwise, there is no error.

[0140] To examine the highest bit rn-1 If it's incorrect, then put r n-1 Corresponding check code α n-1 inverse (α) n-1 ) -1 Substituting α into the incorrect polynomial will result in σ(x).

[0141] σ(α)=1+σ1α+σ2α 2 +…+σ v α v =0 (v≤t),

[0142] Explanation r n-1 There is an error, otherwise it means r n-1 No mistake.

[0143] The structure of Chien's search circuit is as follows: Figure 3 The diagram shown is a schematic of the Chan's search circuit in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. When using 4-way parallel computing, each clock cycle needs to simultaneously calculate σ(α) i ), σ(α) i+1 ), σ(α) i+2 ) and σ(α) i+3 The Chien search calculates the value of each 4-bit value and then checks if the result is 0. If so, it indicates an error in that bit, and the corresponding position in the data storage module is flipped. After the flip, the 4 bits are output together. Since the extended field element lookup table required for the Galois fields of long and short codes in DVB-S2 is too large, this invention can choose to create a small lookup table containing initial values ​​and obtain the required element for the next step through iteration in each calculation.

[0144] The overall input / output timing of the decoder is as follows: Figure 4 The diagram shown illustrates the input-output timing of the DVB-S2 high-speed parallel BCH code decoder provided by this invention. The decoding result is output starting at the 2t+3rd clock cycle after the end of one frame of input data. Calculated from the completion of the input data, the total decoding time is n / 4 (n is the decoding code length) + 2t iterations (theoretically, the upper limit of the time is less than n / 4) + 1. Within a clock frequency of 196MHz, the total decoding time is less than twice the time of one frame of input data (n / 4), effectively avoiding blocking.

[0145] Optionally, in the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the N-way parallel Chan's search module is further used to: create a small lookup table containing initial values, and based on the small lookup table, obtain the check code for the next round of verification through iteration in each round of calculation.

[0146] This invention can be understood as follows: Initial values ​​are determined by creating a small-scale lookup table, and subsequent calculations are performed iteratively using a Galois multiplier. The multiplier is reused between different steps, effectively reducing hardware resource consumption. The initial values ​​are defined as α to α... 4i After performing the current root verification operation, the used α values ​​are updated for use in the next step. This transforms the creation of the entire extended field element lookup table into the use of multipliers. Since the multiplier requirement is large when performing Chien search, the multipliers used in the previous two steps can be reused, thereby reducing resource consumption.

[0147] In other words, considering the commonalities between the Chien search algorithm and the process of finding the adjoint equation in this invention, the Chien search circuit of this invention also incorporates the finite field multiplier iterative method, which is also integrated into the output data process. Furthermore, while using the finite field multiplier iterative method, a small-scale lookup table is used to determine the initial value, thus eliminating the need to calculate the initial Galois field value through multipliers and directly starting the root verification and output data. Since the extended field elements used in each root verification are more regular than the previous one, and this regularity approximates the adjoint equation process, the Chien search circuit of this invention reuses the multipliers and lookup tables used in the adjoint equation process, reducing resource consumption to a certain extent.

[0148] This invention combines the creation of a small-scale lookup table with iteration, which can directly obtain the corresponding Galois field initial value each time, thus speeding up the decoding speed. For example, in the case of 4-way parallel processing, the decoding time of the shortest code of the DVB-S2 protocol can be reduced by about 1 / 8.

[0149] In the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the N-way parallel adjoint computation module is optionally implemented using a pure FPGA, and the N-way parallel adjoint computation module is specifically used for:

[0150] While receiving the codeword polynomial composed of the BCH code to be decoded, the finite field elements at the corresponding positions in the BCH code parity check matrix are obtained through iteration of the finite field multiplier.

[0151] Horner's rule is used for decomposition, N-bit calculations are performed synchronously, and the corresponding positions of the BCH code parity-check matrix and the codeword polynomial are multiplied and accumulated to obtain the syndrome result in the next clock cycle after the BCH code to be decoded is input.

[0152] This invention's N-way parallel circuit can be explained in detail using a 4-way parallel circuit as an example. The 4-way parallel syndrome calculation circuit is implemented using a pure FPGA and employs a finite field multiplier iterative method to integrate the solution of the syndrome into the input data process. While receiving the BCH code data to be decoded and forming the codeword polynomial, the finite field elements at corresponding positions in the parity check matrix are obtained iteratively. Using Horner's rule decomposition, 4-bit calculations can be performed synchronously. Then, the parity check matrix and the corresponding positions of the codeword polynomial are multiplied and accumulated. The syndrome result can be obtained immediately in the next clock cycle after the input data is completed.

[0153] In this invention, the N-way parallel adjoint calculation module uses a finite field multiplier for iteration and a small-scale lookup table to determine the initial value. Since no index table is created for all the extended field elements needed, no soft core or external storage chip is required. The initial value needed to start the iteration when calculating the adjoint is already stored in the small lookup table. Therefore, it is not necessary to use a multiplier to calculate the initial Galois field value and start the input data and adjoint iteration directly.

[0154] In the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the BCH code parity check matrix is ​​optionally represented as follows:

[0155]

[0156] In the formula, H represents the BCH code parity check matrix, α represents the extended field element, n represents the code length of the BCH code to be decoded, and t represents the maximum number of error corrections.

[0157] The adjoint result is represented by a matrix as follows:

[0158] S=(s1,s2,s3,…,s 2t );

[0159] In the formula, S represents the adjoint result matrix, where S1, S2, ..., S 2t The result of multiplying the BCH code parity check matrix by the codeword polynomial is in extended field element form.

[0160] The codeword polynomial of the BCH code to be decoded is represented as follows:

[0161] R(x)=r n-1 x n-1 +r n-2 x n-2 +…+r1x 1 +r0;

[0162] In the formula, R(x) represents the codeword polynomial, which is the input signal, r n-1 ,rn-2 r0 represents the polynomial coefficients, and x represents the polynomial variable;

[0163] The result of the adjoint equation can then be obtained by solving the following formula:

[0164] S T =H·R T .

[0165] This can be understood as follows: while inputting the BCH code to be decoded, the BCH code to be decoded is used to form the receiving codeword polynomial R(x). Simultaneously, the BCH code parity check matrix H can be predefined as shown above. Then, given both the input and output codes, the code can be decoded based on S... T =H·R T Obtain the adjoint polynomial S. To minimize the time required to calculate the adjoint, iterative calculation of the adjoint begins at each clock cycle of input data, and the iteration is complete when the last N bits of data have been input.

[0166] According to Horner's rule, the calculation of S can be transformed into a nested form. When there are 4 bits of data input in parallel, the calculation of the adjoint also requires 4 bits of parallel calculation, as follows:

[0167] s i =(……(r) n-1 *α 3i +r n-2 *α 2i +r n-3 *α i +r n-4 )

[0168] *α 4i +r n-5 *α 3i ...+r1)*α i +r0

[0169] Therefore, at each clock cycle of the input, the corresponding α is superimposed based on the 4-bit input data. i To α 3i Its circuit structure is as follows Figure 5 The diagram shown is a schematic representation of the synodal computation circuit in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention. In the Galois field, addition is the XOR of the two representations (16-fold), and after superposition, it is multiplied by α. 4i In this way, the syndrome result can be output immediately in the next clock cycle after the input data is completed, where i represents the i-th term in the syndrome. The final input-output timing diagram of the syndrome module is as follows: Figure 6 The diagram shown is a schematic diagram of the input and output timing of the synergistic calculation module in the DVB-S2 high-speed parallel BCH code decoder provided by the present invention.

[0170] In the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments, the error correction module is specifically used to: if the judgment result is that there is an error, flip the currently verified N-bit BCH code to realize error correction, and output the corrected data as the high-speed parallel decoding result.

[0171] It can be understood that the error detection and error correction circuits in this invention are integrated into the output data process. Since an N-bit (e.g., 4-bit) parallel output mechanism is used, after each N-bit simultaneous root check operation, the N bits being checked are flipped according to the detection result and directly output. After the detection of the entire codeword polynomial is completed, all data is also output.

[0172] Furthermore, based on the DVB-S2 high-speed parallel BCH code decoder provided according to the above embodiments, the DVB-S2 high-speed parallel BCH code decoder of the present invention further includes: a parameter configuration module, used to: configure parameters including the order of the predefined polynomial factor in the BCH decoder, the maximum error correction capability code, and the word polynomial length.

[0173] This invention can be understood as follows: the DVB-S2 high-speed parallel BCH code decoder also includes a corresponding parameter configuration module for configuring the parameters of each module of the decoder, and executing the corresponding procedures for finding the synod, solving the error polynomial, performing Chan's search for root verification, and error correction according to the configuration parameters required by the corresponding system. The configured parameters include the order of the predefined polynomial factors in the BCH decoder (corresponding to the short / long code indicator signal), the maximum error correction capability, and the codeword polynomial length (corresponding to the data bit length, i.e., the information bit length plus the generator polynomial length), etc.

[0174] Based on the same inventive concept, this invention also provides a DVB-S2 high-speed parallel BCH code decoding method according to the above embodiments. This method achieves high-speed parallel decoding of BCH codes in DVB-S2 by applying the DVB-S2 high-speed parallel BCH code decoder provided in the above embodiments. Therefore, the descriptions and definitions in the DVB-S2 high-speed parallel BCH code decoders in the above embodiments can be used to understand the relevant processing steps in this invention. For details, please refer to the above embodiments, which will not be repeated here.

[0175] According to an embodiment of the present invention, the processing flow of the DVB-S2 high-speed parallel BCH code decoding method is as follows: Figure 7 The diagram shown is a flowchart of the DVB-S2 high-speed parallel BCH code decoding method provided by the present invention. This method can be implemented by applying the DVB-S2 high-speed parallel BCH code decoder of the above embodiments, and specifically includes the following processing steps:

[0176] S701, Perform N-way parallel syndrome calculation on the BCH code to be decoded to obtain the syndrome result;

[0177] S702, using the invertless iBM algorithm, the polynomial output result at the error location is determined by performing multiple iterative operations on the adjoint result;

[0178] S703, based on the error position polynomial output result, using a small lookup table containing initial values, and through N-bit iterative updates, determine whether an error has occurred in the information position of the BCH code to be decoded, and output the judgment result;

[0179] S704, based on the BCH code to be decoded and the judgment result, output the high-speed parallel decoding result of the BCH code to be decoded.

[0180] Specifically, the BCH code FPGA decoder modules are connected via ports. After entering the decoder, the signals are input to the data storage module of the N-channel parallel syndrome calculation module and the error correction module. The N-channel parallel syndrome calculation module outputs the results of multiple parallel syndromes to the error polynomial calculation module through multiple channels. The error polynomial calculation module inputs the error pattern to the N-channel parallel Chien search module. In addition to its own finite field multiplier, the Chien search module also reuses the finite field multiplier and small-scale lookup table from the syndrome module. It uses the finite field multiplier and small-scale lookup table to determine whether the input codeword polynomial has errors and outputs the result to the error correction module. The error correction module receives the codeword polynomial from the data storage module, performs error correction processing, and outputs the final data as the final high-speed parallel decoding result.

[0181] The DVB-S2 high-speed parallel BCH code decoding method provided by this invention employs multi-bit parallel input and output data. That is, the synod calculation is directly merged into the input data for multi-bit parallel calculation, and the output is directly parallel during the Chan search. At the same time, the error polynomial calculation uses the invertless BM algorithm (iBM algorithm), which compresses the total decoding time in the overall decoding process to much less than 1 / 2 of the input data time, successfully avoiding blocking situations and effectively improving the timeliness of the decoding process.

[0182] It is understood that the embodiments of the system described above are merely illustrative, and the units described as separate components may or may not be physically separated; they may be located in one place or distributed across different network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any inventive effort.

[0183] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a USB flash drive, mobile hard drive, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (such as a personal computer, server, or network device, etc.) to execute the methods described in the above method embodiments or some parts of the method embodiments.

[0184] Furthermore, those skilled in the art should understand that in the application documents of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0185] Numerous specific details are set forth in this specification. However, it should be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification. Similarly, it should be understood that, in order to simplify the disclosure of this invention and aid in the understanding of one or more aspects of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the above description of exemplary embodiments of the invention.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DVB-S2 high-speed parallel BCH code decoder, characterized in that, include: N-way parallel adjoint computation module, error polynomial computation module, N-way parallel Chan search module and error correction module; The input of the N-way parallel adjoint computation module is connected in parallel with the first input of the error correction module, and then connected to the BCH code data input of the DVB-S2 to be decoded. The output of the N-way parallel adjoint computation module is connected to the input of the error polynomial computation module, the output of the error polynomial computation module is connected to the input of the N-way parallel Chan's search module, the output of the N-way parallel Chan's search module is connected to the second input of the error correction module, and the output of the error correction module is connected to the decoding output. The N-way parallel syndrome calculation module is used to perform N-way parallel syndrome calculation on the BCH code to be decoded and obtain the syndrome result. The error polynomial calculation module is used to determine the error position polynomial output result by performing multiple iterative operations on the adjoint result using the invertless iBM algorithm. The N-way parallel Chan's search module is used to determine whether an error has occurred in the information position of the BCH code to be decoded based on the error position polynomial output result, using a small lookup table containing initial values, and updating the judgment bit by bit through N-bit iteration, and output the judgment result. The error correction module is used to output a high-speed parallel decoding result for the BCH code to be decoded based on the BCH code to be decoded and the judgment result; The algorithm flow of the invertless iBM algorithm is as follows: Determine the initial value ; Calculate the correction term parameters using the following formula. : ； In the formula, express middle The coefficient of the term, This represents the adjoint matrix during the iteration process. k Indicates the number of iterations. l Indicates intermediate quantities, correction term parameters and intermediate quantity It serves as a judgment condition during the iteration process; According to the correction parameters Calculate the difference using the following formula: ； In the formula, This represents the difference. and This indicates the introduced intermediate variable in the iteration, used to replace the inverse process; Based on the difference, update the coefficients of the current erroneous polynomial according to the following rules: if and ,but: if or ,but: Repeat the above calculation and update steps, performing multiple iterations, until after 2t iterations, the result can be obtained. ; Because of the first equation: ； and k If it is a non-zero constant, then the error position polynomial output result is obtained by solving the first equation; Among them, the erroneous polynomial Represented as: ； In the formula, σ 1. σ 2、...、 The coefficients of the erroneous polynomial are represented by the roots of the erroneous polynomial, which are the reciprocals of the erroneous positions.

2. The DVB-S2 high-speed parallel BCH code decoder according to claim 1, characterized in that, The error polynomial calculation module is specifically used for: Based on the adjoint result corresponding to each iteration of the invertible iBM algorithm, calculate the correction term parameter required for each iteration, and determine whether the correction term parameter is 0; If the correction term parameter in any iteration is not 0, then update the coefficients of the current erroneous polynomial and use the updated erroneous polynomial as the error pattern. Calculate the difference between the updated error polynomial and the current error polynomial, and add the difference to the calculation of the correction term parameter in the next iteration until the operation of all the adjoint results is completed. Then, output the error position polynomial output result according to the error pattern.

3. The DVB-S2 high-speed parallel BCH code decoder according to claim 1, characterized in that, The N-way parallel Chan's search module is specifically used for: Starting from the most significant bit of the polynomial output at the error location, increment the checksum bit by bit N. α i+N-1 、 ...、 α i+1 、α i , i=nN, ..., 2N, 0 The inverse ( α i+N-1 ) -1 = α、...、 ( α i+1 ) -1 = α、 ( α i ) -1 = α Each bit is substituted into the output result of the error position polynomial, and the output result of the error position polynomial is observed in parallel for N bits. If the result of any bit is 0, it is determined that an error has occurred at that bit; otherwise, there is no error.

4. The DVB-S2 high-speed parallel BCH code decoder according to claim 3, characterized in that, The N-way parallel Chan's search module is also used for: A small lookup table containing initial values ​​is created, and based on the small lookup table, the checksum for the next round of verification is obtained through iteration in each round of calculation.

5. The DVB-S2 high-speed parallel BCH code decoder according to claim 1, characterized in that, The N-way parallel adjoint computing module is implemented using a pure FPGA, and is specifically used for: While receiving the codeword polynomial composed of the BCH code to be decoded, the finite field elements at the corresponding positions in the BCH code parity check matrix are obtained through iteration of the finite field multiplier. Horner's rule is used for decomposition, N-bit calculations are performed synchronously, and the corresponding positions of the BCH code parity-check matrix and the codeword polynomial are multiplied and accumulated to obtain the syndrome result in the next clock cycle after the BCH code to be decoded is input.

6. The DVB-S2 high-speed parallel BCH code decoder according to claim 5, characterized in that, The BCH code parity check matrix is ​​represented as follows: ； In the formula, H This represents the BCH code parity check matrix. α Indicates an extended field element. n This indicates the code length of the BCH code to be decoded. t Indicates the maximum number of errors to correct; The adjoint result is represented by a matrix as follows: ； In the formula, S Denotes the adjoint result matrix, where S 1, S 2, ..., The result of multiplying the BCH code parity check matrix by the codeword polynomial is in extended field element form. The codeword polynomial of the BCH code to be decoded is represented as follows: ； In the formula, This represents the codeword polynomial, where the codeword polynomial is the input signal. , r n-2 , ..., r 0 represents the polynomial coefficient. x Represents a polynomial variable; The result of the adjoint equation can then be obtained by solving the following formula: [wl1]。 7. The DVB-S2 high-speed parallel BCH code decoder according to any one of claims 1-6, characterized in that, The error correction module is specifically used for: If the judgment result indicates an error, the N-bit BCH code currently being verified is flipped to correct the error, and the corrected data is output as the result of the high-speed parallel decoding.

8. The DVB-S2 high-speed parallel BCH code decoder according to any one of claims 1-6, characterized in that, It also includes a parameter configuration module for: The configuration includes parameters such as the order of the predefined polynomial factors in the BCH decoder, the maximum error-correcting code, and the word polynomial length.

9. A DVB-S2 high-speed parallel BCH code decoding method, characterized in that, Implemented using any one of the DVB-S2 high-speed parallel BCH code decoders described in claims 1-8, the method includes: Perform N-way parallel syndrome calculation on the BCH code to be decoded to obtain the syndrome result; Using the invertless iBM algorithm, the polynomial output result at the error location is determined by performing multiple iterative operations on the adjoint result. Based on the error position polynomial output result, using a small lookup table containing initial values, the system iteratively updates the judgment bit by bit to determine whether an error has occurred in the information position of the BCH code to be decoded, and outputs the judgment result. Based on the BCH code to be decoded and the judgment result, the high-speed parallel decoding result of the BCH code to be decoded is output.

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