Printed circuit board

Abstract

The present disclosure provides a printed circuit board, comprising: a substrate having a first through portion; a magnetic layer disposed in at least a portion of the first through portion and having a second through portion; an electronic component having at least a portion provided in the second through portion; a first wiring pattern disposed over the magnetic layer; a second wiring pattern disposed below the magnetic layer; and a first through hole having at least a portion surrounded by the magnetic layer, and including a first via pattern connecting the first wiring pattern and the second wiring pattern to each other.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0138229 filed on October 17, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Recently, in order to reduce the size of semiconductor chips and improve power efficiency, it may be necessary to embed various passive devices (such as capacitors and inductors) in the package substrate. Compared with general chip components, in the case of inductors, it may be necessary to improve inductance by changing materials and structures. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board that can reduce voltage drop and power loss.

[0005] An aspect of the present disclosure is to provide a printed circuit board that can improve inductance.

[0006] An aspect of the present disclosure is to provide a printed circuit board that can achieve size reduction and increase integration.

[0007] One aspect of the present disclosure is to dispose a magnetic layer in a first through-portion of a substrate, form an inductor such as a magnetic composite inductor (MCI) in the magnetic layer, and embed and dispose an electronic component such as a voltage regulator (VR) in a second through-portion of the magnetic layer.

[0008] For example, according to an example embodiment, a printed circuit board includes: a substrate having a first through-portion; a magnetic layer disposed in at least a portion of the first through-portion and having a second through-portion; an electronic component having at least a portion disposed in the second through-portion; a first wiring pattern disposed above the magnetic layer; a second wiring pattern disposed below the magnetic layer; and a first through-hole having at least a portion surrounded by the magnetic layer and including a first via pattern connecting the first wiring pattern and the second wiring pattern to each other.

[0009] For example, according to an example embodiment, a printed circuit board includes: a substrate having a first through-portion; a magnetic layer having at least a portion disposed in the first through-portion, contacting the substrate, and having a second through-portion and a plurality of through-holes; a voltage regulator disposed in at least a portion of the second through-portion; an insulating layer covering at least a portion of each of the substrate, the magnetic layer, and the voltage regulator, and filling a portion of each of the second through-portion and the plurality of through-holes; a first wiring pattern layer disposed on an upper surface of the insulating layer; a second wiring pattern layer disposed on a lower surface of the insulating layer; and a plurality of via patterns passing through each of the insulating layer in the plurality of through-holes.

[0010] According to an example embodiment, a printed circuit board includes: a substrate having a first through-portion passing therethrough; a magnetic layer including a magnetic material disposed in the first through-portion, the magnetic layer having a second through-portion passing therethrough; and an inductor disposed in the magnetic layer and surrounding the second through-portion, the inductor including: a first through-via passing through the magnetic layer in a pattern surrounding the second through-portion; a first wiring pattern disposed above the magnetic layer and contacting top portions of at least some of the first through-vias; and a second wiring pattern disposed below the magnetic layer and contacting bottom portions of at least some of the first through-vias, wherein the first wiring pattern is connected to the second wiring pattern through the first through-via to form the inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram illustrating an example of an electronic device system; Figure 2 is a perspective view showing an example of an electronic device; Figure 3 is a cross-sectional view showing an example of a printed circuit board; Figure 4 is along Figure 3 A cross-sectional view taken along line II' in FIG. Figures 5 to 12 It shows the manufacturing Figure 3 A cross-sectional view of an example of a printed circuit board in FIG. Fig.13 is a cross-sectional view showing another example of a printed circuit board; Fig.14 is a cross-sectional view showing an example of a coil portion; and Fig.15 are plan views showing various examples of the coil portion. DETAILED DESCRIPTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0013] Electronic Devices Figure 1 is a block diagram illustrating an example of an electronic device system.

[0014] Reference Figure 1 , a mainboard 1010 may be accommodated in the electronic device 1000. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the mainboard 1010. These components may be connected to other electronic components described below through various signal lines 1090.

[0015] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0016] The network-related components 1030 may include components that are compatible with or communicate using protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or communicating with various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0017] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the chip-related components 1020 and / or the network-related components 1030 described above.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, the other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0020] Figure 2 is a perspective view illustrating an example of an electronic device.

[0021] Reference Figure 2 , the electronic device may be a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the component 1120 may be a chip-related component, such as, for example, a component package 1121, but example embodiments thereof are not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component including active components and / or passive components is surface mounted. Alternatively, the component package 1121 may be configured in the form of a printed circuit board in which an electronic component including active components and / or passive components is embedded. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0022] Printed Circuit Board Figure 3 is a cross-sectional view showing an example of a printed circuit board.

[0023] Figure 4 is along Figure 3 A cross-sectional view taken along line II' in FIG.

[0024] Reference Figure 3 and Figure 4The printed circuit board 100A according to the example embodiment may include: a substrate 111; a first through-portion H1 passing through a region between an upper surface and a lower surface of the substrate 111; a magnetic layer 150 disposed in the first through-portion H1; a second through-portion H2 passing through a region between an upper surface and a lower surface of the magnetic layer 150; an electronic component 140, at least a portion of which is disposed in the second through-portion H2; a first through hole h1 passing through a region between an upper surface and a lower surface of the magnetic layer 150; a first insulating layer 112 disposed on the substrate 111, covering the magnetic layer 150 and the electronic component 140; The subassembly 140 and fills a portion of each of the second through-portion H2 and the first through-hole h1; the second through-hole h2, passing through the area between the upper surface and the lower surface of the first insulating layer 112 in the first through-hole h1; the first wiring pattern B1, disposed above the magnetic layer 150; the second wiring pattern B2, disposed below the magnetic layer 150; and the first through-hole 131, at least a portion of which is disposed in the second through-hole h2 and surrounded by the magnetic layer 150, and includes a first via pattern M1 connecting the first wiring pattern B1 and the second wiring pattern B2 to each other. The inductor may be disposed on the substrate 111 through the magnetic layer 150 and the first through-hole 131 (including the first via pattern M1 connecting the first wiring pattern B1 and the second wiring pattern B2) to surround at least a portion of the magnetic layer 150. The first insulating layer 112 may be disposed between the lower surface of the first wiring pattern B1 and the magnetic layer 150 and the upper surface of the second wiring pattern B2 and the magnetic layer 150. The first via pattern M1 may be disposed on a wall surface of the second via h2, and the first through via 131 may include a first filler R1 filling at least a portion of a space between the first via patterns M1 in the second via h2. The second via h2 may be filled with the first via pattern M1 without the first filler R1.

[0025] As described above, in the printed circuit board 100A according to the example embodiment, the magnetic layer 150 may be disposed in the first through-portion H1 of the substrate 111 as the core layer, and the first through-via 131 may be formed in the magnetic layer 150, thereby forming an inductor surrounding the magnetic layer 150. In addition, by disposing the electronic component 140 in the second through-portion H2 in the magnetic layer 150, a structure in which the electronic component 140 is embedded together with the inductor may be obtained. In this case, the distance between the electronic component 140 and the inductor may be reduced, and the spatial arrangement in the substrate 111 may be efficient. In addition, the voltage drop and power loss may be reduced, and the inductance may be improved. In addition, the thinness and integration may be increased. A plurality of first through-holes h1 and a plurality of second through-holes h2 may be formed, and therefore, a plurality of first through-holes 131 may be formed. For example, the inductor may include a plurality of first via patterns M1 and a plurality of first wiring patterns B1 and a plurality of second wiring patterns B2. For example, the inductor may include one or more coil portions, wherein a plurality of first wiring patterns B1 and a plurality of second wiring patterns B2 are alternately connected to each other with a plurality of first via patterns M1. In this case, the coil portion may be arranged to surround the electronic component 140 on a plane. Therefore, the above-mentioned effect may be effectively achieved. In addition, the magnetic layer 150 may be arranged in the first through portion H1 of the substrate 111 and may be covered by the first insulating layer 112, so that the metal oxide contained in the magnetic layer 150 may not be exposed to the surface, and the magnetic layer 150 may be prevented from being dissolved in the acid solution.

[0026] The printed circuit board 100A according to the example embodiment may further include: a third through hole h3 passing through an area between the upper and lower surfaces of the substrate 111 and having at least a portion filled by the first insulating layer 112; a fourth through hole h4 passing through an area between the upper and lower surfaces of the first insulating layer 112 in the third through hole h3; a first wiring layer 121 disposed on an upper surface of the first insulating layer 112 and including a first wiring pattern B1; a second wiring layer 122 disposed on a lower surface of the first insulating layer 112 and including a second wiring pattern B2; and a second through via 132 having at least a portion disposed in the fourth through hole h4 and surrounded by the substrate 111, and including a second via pattern M2 connecting the first wiring layer 121 and the second wiring layer 122 to each other. The second via pattern M2 may be disposed on a wall surface of the fourth through hole h4, and the second through via 132 may include a second filler R2 filling at least a portion of a space between the second via patterns M2 in the fourth through hole h4. If necessary, the third through hole h3 may not be provided, and the fourth through hole h4 may directly pass through the substrate 111 without the third through hole h3. If necessary, the fourth through hole h4 may be filled with the second via pattern M2 without the second filler R2. As described above, the first wiring layer 121 and the second wiring layer 122 may be provided on the upper surface and the lower surface of the first insulating layer 112, respectively, so that various wiring designs can be realized. In addition, by forming the second through hole 132 together when forming the first through hole 131, the process can be further simplified and the cost and time can be reduced.

[0027] The printed circuit board 100A according to the example embodiment may include: a first via layer 133 including a first connection via that passes through the upper side of the first insulating layer 112 and connects the first wiring layer 121 to the first connection pad P1 of the electronic component 140; and a second via layer 134 including a second connection via that passes through the lower side of the first insulating layer 112 and connects the second wiring layer 122 to the back surface of the electronic component 140 (for example, the second connection pad P2 provided on the back surface of the electronic component 140). As described above, the electronic component 140 may be electrically connected to the above-mentioned inductor through the first via layer 133 and the first wiring layer 121. In addition, the electronic component 140 may have an excellent heat dissipation effect through the second via layer 134 and the second wiring layer 122.

[0028] A printed circuit board 100A according to an example embodiment may include: a second insulating layer 113 disposed on an upper surface of a first insulating layer 112; a third insulating layer 114 disposed on a lower surface of the first insulating layer 112; a third wiring layer 123 disposed on an upper surface of the second insulating layer 113; a fourth wiring layer 124 disposed on a lower surface of the third insulating layer 114; a third via layer 135 including a third connection via that passes through the second insulating layer 113 and connects the first wiring layer 121 and the third wiring layer 123 to each other; a fourth via layer 136 including a fourth connection via that passes through the third insulating layer 114 and connects the second wiring layer 122 and the fourth wiring layer 124 to each other; a first resist layer 115 disposed on an upper surface of the second insulating layer 113 and including a first opening 115h that exposes at least a portion of the third wiring layer 123; and a second resist layer 116 disposed on a lower surface of the third insulating layer 114 and including a second opening 116h that exposes at least a portion of the fourth wiring layer 124. As described above, a multi-layer package substrate implemented by a build-up process may be obtained.

[0029] Hereinafter, components of a printed circuit board 100A according to example embodiments may be described in more detail with reference to the accompanying drawings.

[0030] The substrate 111 may be configured as a core layer. For example, an organic core layer or an inorganic core layer (e.g., a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer) may be included. The organic core layer may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a material including an inorganic filler, an organic filler, and / or glass fiber (e.g., a glass fabric such as a glass cloth) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto stacked film (ABF), or a prepreg (PPG), but example embodiments thereof are not limited thereto, and other polymer materials may be used. The glass core layer may include glass. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, and the like. However, example embodiments thereof are not limited thereto, and optional glass materials (e.g., fluorine glass, phosphate glass, chalcogen glass, and the like) may also be used as materials for the glass layer. In addition, other additives may be further included to form glass having specific physical properties. The additive may include at least one of magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates and oxides of these elements, for example, calcium carbonate (e.g., lime) or sodium carbonate (e.g., soda). Glass may be distinguished from the above-mentioned glass fiber. The metal core layer may include a metal. The metal may include, for example, copper (Cu), Invar alloy, etc., but example embodiments thereof are not limited thereto. The silicon core layer may include pure silicon (Si). If necessary, the silicon core layer may include an oxide layer formed on the silicon (Si). In addition, a nitride layer formed on the oxide layer may be included. The oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but example embodiments thereof are not limited thereto. The ceramic core layer may include a ceramic material. The ceramic material may include, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si3N4), etc., but example embodiments thereof are not limited thereto.

[0031] The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include an organic insulating material. As described above, the organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including a resin and an inorganic filler, an organic filler, and / or glass fiber (e.g., a glass fabric such as glass cloth). For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto built-up film (ABF), or a prepreg (PPG), but example embodiments thereof are not limited thereto, and other polymer materials may be used. The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include the same or different organic insulating materials. If desired, the first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may be configured as a plurality of layers.

[0032] The first resist layer 115 and the second resist layer 116 may include a liquid solder resist or a film type solder resist, but example embodiments thereof are not limited thereto and may include other organic insulating materials such as ABF. The first resist layer 115 and the second resist layer 116 may have a first opening 115h and a second opening 116h, respectively. A plurality of first openings 115h and a plurality of second openings 116h may be provided. The first opening 115h and the second opening 116h may be formed as a solder mask definition (SMD) and / or a non-solder mask definition (NSMD). The first opening 115h and the second opening 116h may expose the third wiring layer 123 and the fourth wiring layer 124, respectively, and a surface treatment layer may be provided on the surface of the exposed pattern. The surface finishing layer may be formed by electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating / alternative gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), etc., but example embodiments are not limited thereto.

[0033] Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a metal layer. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, the metal layer may include copper (Cu), but the exemplary embodiment thereof is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may perform various functions according to the design. For example, a signal pattern, a power pattern, a ground pattern, etc. may be included. Each of these patterns may have various forms, such as a line, a plane, and a pad, etc. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a seed layer and a metal layer formed on the seed layer. The seed layer may be configured as an electroless plating layer (eg, a chemical copper plating layer) and / or a sputtering layer, and the metal layer may be configured as an electroplating layer (eg, an electroplated copper layer), but example embodiments thereof are not limited thereto.

[0034] The first wiring pattern B1 and the second wiring pattern B2 (included in the first wiring layer 121 and the second wiring layer 122, respectively) and the first via pattern M1 and the second via pattern M2 may include a metal layer. As described above, the metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, etc. Preferably, the metal layer may include copper (Cu), but its exemplary embodiment is not limited thereto. The second via pattern M2 may perform various functions according to the design. For example, a signal via pattern, a power via pattern, and a ground via pattern may be included. The first wiring pattern B1 and the second wiring pattern B2 and the first via pattern M1 and the second via pattern M2 may include a seed layer and a metal layer formed on the seed layer. The seed layer may be an electroless plating layer (e.g., a chemical copper plating layer) and / or a sputtering layer, and the metal layer may be an electroplating layer (e.g., an electroplated copper layer), but its exemplary embodiment is not limited thereto.

[0035] The first filler R1 and the second filler R2 may include a plugging material. The plugging material may include an insulating ink including an insulating resin such as an epoxy resin. However, example embodiments thereof are not limited thereto, and if necessary, the plugging material may include a conductive ink. The first filler R1 and the second filler R2 may be formed by the same process and thus may include the same material, but example embodiments thereof are not limited thereto.

[0036] A plurality of first through holes h1 and a plurality of second through holes h2 may be formed. For example, on a plane, each of the second through holes h2 having a diameter smaller than the diameter of the first through hole h1 may be formed in each first through hole h1. Therefore, a plurality of first through holes 131 may be provided. For example, the inductor may include a plurality of first via patterns M1. A plurality of first wiring patterns B1 and a plurality of second wiring patterns B2 connected to the first via pattern M1 may be provided. A plurality of first wiring patterns B1 and a plurality of second wiring patterns B2 may be included in a first wiring pattern layer and a second wiring pattern layer, respectively. The first wiring pattern layer and the second wiring pattern layer may be included in a first wiring layer 121 and a second wiring layer 122, respectively. A plurality of third through holes h3 and a plurality of fourth through holes h4 may be formed. For example, on a plane, a fourth through hole h4 having a diameter smaller than the diameter of the third through hole h3 may be formed in each third through hole h3. Therefore, a plurality of second through holes 132 may be provided. As required, the third through hole h3 may not be provided, and only the fourth through hole h4 may be formed.

[0037] Each of the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may include a metal layer. As described above, the metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, the metal layer may include copper (Cu), but the exemplary embodiment thereof is not limited thereto. Each of the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may include a filled via that fills the via hole, and may also include a conformal via disposed along the wall surface of the via hole. The first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may perform various functions according to the design. For example, a ground via, a power via, a signal via, etc. may be included. The first via layer 133 and the second via layer 134 may include a first connection via and a second connection via that tapers in opposite directions, respectively. The third via layer 135 and the fourth via layer 136 may include a third connection via and a fourth connection via tapered in opposite directions, respectively. Each of the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electroplating layer (e.g., an electroplated copper layer). A sputtering layer may be included instead of the electroless plating layer (e.g., the chemical copper plating layer), or both the sputtering layer and the electroless plating layer may be included.

[0038] The electronic component 140 may be configured as a chip-type electronic component. For example, the electronic component 140 may be configured as a semiconductor chip, and more specifically, may be an integrated circuit (IC) die in which hundreds to millions of components are integrated into one chip. The integrated circuit die may be formed based on an active wafer, in which case silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material of each body. Various circuits may be formed in the body. The first connection pad P1 may be formed on the front surface of the body to connect to an external circuit such as a signal, power, ground, etc., and the first connection pad P1 may include a conductive material such as aluminum (Al) or copper (Cu). If necessary, a conductive material connected to ground or power may be formed on the back surface of the body to form a second connection pad P2. The electronic component 140 may include a circuit for adjusting voltage. For example, the electronic component 140 may include a voltage regulator. If necessary, a plurality of electronic components 140 may be provided and disposed together in the second through-portion H2, or a plurality of second through-portions H2 may be formed or disposed and the plurality of electronic components 140 may be disposed correspondingly in the plurality of second through-portions H2.

[0039] The magnetic layer 150 may include a magnetic material. The magnetic material may include, for example, a ferrite-based material, a permalloy-based material, and the like. For example, Ni-based ferrite, Ni-Zn-based ferrite, Ni-Zn-Cu-based ferrite, Fe-Si-Al (iron-aluminum-silicon) alloy, Ni-Mo-Fe (MPP: molybdenum permalloy powder core) alloy, Ni-Fe (high magnetic flux core) alloy, and the like may be included, but the exemplary embodiment thereof is not limited thereto, and other commonly used ferrite materials or permalloy-based materials may also be included. In addition, various types of magnetic materials including other magnetic powders may be used. The magnetic material may be used as a paste or a composition to fill the first through portion H1, and the magnetic material may be solidified to form the magnetic layer 150. Therefore, the magnetic layer 150 may be in contact with the wall surface of the first through portion H1. For example, the magnetic layer 150 may be in contact with the substrate 111.

[0040] Figures 5 to 12 It shows the manufacturing Figure 3 A cross-sectional view of an example of a printed circuit board.

[0041] Reference Figure 5 , a first through-hole H1 may be formed in the substrate 111. In addition, a third through-hole h3 may be formed in the substrate 111. The first through-hole H1 and the third through-hole h3 may be formed by various methods (such as laser drilling, mechanical drilling, chemical etching, and sandblasting) according to the material of the substrate 111. In addition, if necessary, the third through-hole h3 may not be provided. For example, the third through-hole h3 may not be formed.

[0042] Reference Figure 6 , the magnetic layer 150 may be formed by filling the first through portion H1 with a magnetic paste or a magnetic composition and curing the paste.

[0043] Reference Figure 7 , a second through portion H2 may be formed in the magnetic layer 150. In addition, a first through hole h1 may be formed in the magnetic layer 150. The second through portion H2 and the first through hole h1 may be formed by mechanical drilling or the like.

[0044] Reference Figure 8 The electronic component 140 may be disposed in the second through portion H2 . The tape 210 may be used to dispose the electronic component 140 .

[0045] Reference Fig. 9 , the first insulating layer 112 may be formed. For example, by laminating the first insulating layer 112 using a lamination process such as PPG or ABF, at least a portion of each of the substrate 111, the magnetic layer 150, and the electronic component 140 may be covered, and at least a portion of each of the second through-hole H2 and the first through-hole h1 and the third through-hole h3 may be filled. Thereafter, as needed, the laminate may be cut into unit sizes by a trimming process. In the process of forming the first insulating layer 112, the tape 210 may be removed.

[0046] Reference Fig.10 , the second through hole h2 and the fourth through hole h4 may be formed in the first through hole h1 and the third through hole h3, respectively. The second through hole h2 and the fourth through hole h4 may be formed by mechanical drilling or the like. In addition, a first via hole 133V for forming the first via layer 133 and a second via hole 134V for forming the second via layer 134 may be formed in the first insulating layer 112 by laser processing or the like. In addition, if necessary, the fourth through hole h4 may be formed without the third through hole h3. For example, the fourth through hole h4 may directly pass through the substrate 111 without the third through hole h3.

[0047] Reference Fig.11 , through the plating process and the plugging process, the first via hole pattern M1 and the second via hole pattern M2, the first filler R1 and the second filler R2, the first wiring layer 121 and the second wiring layer 122 (including the first wiring pattern B1 and the second wiring pattern B2, respectively), and the first via hole layer 133 and the second via hole layer 134 can be formed. For example, a metal layer can be formed on the upper and lower surfaces of the first insulating layer 112 and the wall surfaces of the second through hole h2 and the fourth through hole h4 through the plating process, the space between the metal layers in the second through hole h2 and the fourth through hole h4 can be filled with a plugging material through the plugging process, the metal layer and the plugging material on the upper and lower surfaces of the first insulating layer 112 can be removed through the planarization process, and the metal layer can be formed again on the upper and lower surfaces of the first insulating layer 112 through the plating process, so that the first through-via hole 131 and the second through-via hole 132, the first wiring layer 121 and the second wiring layer 122, and the first via hole layer 133 and the second via hole layer 134 can be formed. In addition, in the plating process, a metal layer patterned according to the design may be formed using a dry film exposure and development process. In addition, through the planarization process, the upper and lower surfaces of each of the first through via 131 and the second through via 132 may be substantially flat, the upper and lower surfaces of the first insulating layer 112 may be coplanar with the upper and lower surfaces of each of the first through via 131 and the second through via 132, respectively, and a boundary may be formed between the metal layers.

[0048] Reference Fig.12, through the stacking process, the required number of second insulating layers 113 and third insulating layers 114, third wiring layers 123 and fourth wiring layers 124, and third via layers 135 and fourth via layers 136 may be formed, and the first resist layer 115 and the second resist layer 116 may be formed. In addition, the first opening 115h and the second opening 116h may be formed in the first resist layer 115 and the second resist layer 116, respectively. The second insulating layer 113 and the third insulating layer 114 may be formed using the above-mentioned stacking process, the third wiring layer 123 and the fourth wiring layer 124, and the third via layer 135 and the fourth via layer 136 may be formed using the above-mentioned plating process, and the first resist layer 115 and the second resist layer 116 may be formed by a stacking process or a liquid material coating process.

[0049] The printed circuit board 100A according to the example embodiment may be manufactured through a series of processes, and the rest of the description may be substantially the same as the above-described example.

[0050] Fig.13 is a cross-sectional view showing another example of a printed circuit board.

[0051] Reference Fig.13 , a printed circuit board 100B according to another example may further include a semiconductor chip 160 disposed on the first resist layer 115 in the printed circuit board 100A according to the above example. In addition, the printed circuit board 100B according to another example may further include a plurality of electrical connection metals 170 disposed on the second resist layer 116. The semiconductor chip 160 may be mounted by a connecting member 165. For example, the semiconductor chip 160 may be connected to the third wiring layer 123 by a connecting member 165. The semiconductor chip 160 may be electrically connected to at least a portion of each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124, the first through-via 131 and the second through-via 132, and the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136. Therefore, the semiconductor chip 160 may be electrically connected to the inductor and the electronic component 140.

[0052] The semiconductor chip 160 may include an integrated circuit (IC) die in which hundreds to millions of elements are integrated into one chip. In this case, the integrated circuit die may be configured as: for example, a processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (e.g., AP); a logic chip, such as a field programmable gate array (FPGA), an analog-to-digital converter, or an application-specific IC (ASIC), but its example embodiments are not limited thereto, and the integrated circuit die may be configured as a memory chip, such as a volatile memory (e.g., DRAM, high bandwidth memory (HBM)), a non-volatile memory (e.g., ROM, flash memory), or the integrated circuit die may be configured as other types of chips (such as a power management IC (PMIC)). The semiconductor chip 160 may be formed based on an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a base material for each body. Various circuits may be formed in the body. A connection pad may be formed on the body, and the connection pad may include a conductive material (such as aluminum (Al) or copper (Cu)). The semiconductor chip 160 may be configured as a bare die, and in this case, the metal bumps may be disposed on the connection pads. The semiconductor chip 160 may be configured as a packaged die, and in this case, an additional redistribution layer may be formed on the connection pads, and the metal bumps may be disposed on the redistribution layer.

[0053] The connection member 165 can mount the semiconductor chip 160 on the package substrate. The connection member 165 can be formed using a low melting point metal (e.g., a solder such as tin (Sn)-aluminum (Al)-copper (Cu)), but its example embodiments are not limited thereto. The connection member 165 can be a ball, a pin, etc. The connection member 165 can be formed in multiple layers or a single layer. When formed in multiple layers, a copper column and a solder can be included, and when formed in a single layer, a tin-silver solder can be included, but its example embodiments are not limited thereto. A plurality of connection members 165 can be provided, and the number of the connection members 165 is not limited to any specific example.

[0054] The electrical connection metal 170 can connect the printed circuit board 100B to the main board or other substrate of the electronic device. The electrical connection metal 170 can be formed using a low melting point metal, such as solder, etc., but its example embodiments are not limited thereto, and the material is not limited thereto. The electrical connection metal 170 can be a ball, a pin, etc. The electrical connection metal 170 can be formed as a multilayer or a single layer. When formed as a multilayer, it can include a copper column and a solder, and when formed as a single layer, it can include a tin-silver solder or copper, but its example embodiments are not limited thereto. A plurality of electrical connection metals 170 can be included, and the number of electrical connection metals 170 is not limited to any specific example.

[0055] The other descriptions may be substantially the same as those described in the printed circuit board 100A according to the above example. In addition, in the process of manufacturing the printed circuit board 100B according to another example, compared with the process of manufacturing the printed circuit board 100A according to the above example, the semiconductor chip 160 may be further mounted on the upper side of the printed circuit board 100A according to the above example using the connecting member 165, and the electrical connection metal 170 may be formed on the lower side of the printed circuit board 100A according to the above example, and a specific description may not be provided.

[0056] Fig.14 is a cross-sectional view showing an example of a coil portion.

[0057] Reference Fig.14 , the inductor included in the above-mentioned printed circuit boards 100A and 100B may include one or more coil parts C, and in the coil part C, a plurality of first wiring patterns B1 and a second wiring pattern B2 formed on the body 180 and a plurality of first via patterns M1 formed in the body 180 may be alternately connected to each other. For example, in the coil part C, in a cross section, a required number of second wiring patterns B2 and first wiring patterns B1 may be connected by the first via pattern M1, so that a coil structure formed vertically alternately may be formed. In addition, the body 180 may include the above-mentioned magnetic layer 150 and the first insulating layer 112. In addition, the first filler R1 may be filled in each through hole in which the first via pattern M1 is formed. As described above, the coil part C may have a structure in which the number of coils around the magnetic layer 150 may be increased, for example, may have a daisy chain shape that may increase inductance. Other descriptions may be substantially the same as the examples described in the above-mentioned printed circuit boards 100A and 100B, and therefore repeated descriptions may not be provided.

[0058] Fig.15 are plan views showing various examples of the coil portion.

[0059] Reference Fig.15, the coil portion C may have various shapes on a plane. For example, as in A, a plurality of coils C1 and C2 may be included that are arranged linearly and in parallel. A plurality of coils C1 and C2 may be spaced apart from each other. Different wiring may be provided between the plurality of coils C1 and C2. Optionally, as in B, coil C3 may be arranged linearly, may be bent downward, and may then be arranged linearly. Optionally, as in C, a coil C4 may be included that is arranged to be repeatedly bent upward and downward. For example, coil C4 may be repeatedly arranged to extend linearly, bend upward, extend linearly, and bend downward. Optionally, as in D, a coil C5 may be included that is repeatedly arranged in an inclined manner in one direction. Optionally, as in E, a coil C6 may be included that is repeatedly arranged to be inclined in one direction, bend downward, and then be repeatedly arranged to be inclined in the opposite direction. Optionally, as in F, a coil C7 may be included that is repeatedly arranged in an X shape. As described above, the coil portion C including various types of coils C1, C2, C3, C4, C5, C6, and C7 may be applied to the above-mentioned printed circuit boards 100A and 100B, and may be repeatedly arranged to surround the electronic component 140. However, the shape of the coil portion is not limited to the above-mentioned example. Other descriptions may be substantially the same as the examples of the description of the above-mentioned printed circuit boards 100A and 100B and the coil portion C, and therefore, repeated descriptions may not be provided.

[0060] In the present disclosure, the term "covering" may include a configuration in which a component is completely covered and a configuration in which a portion of a component is covered, or may include a configuration in which a component is directly covered or indirectly covered. In addition, the term "filling" may include a configuration in which a component is completely filled, and may also include a configuration in which a portion of a component is filled. For example, there may be a gap. In addition, the term "surrounding" may include a configuration in which a component is completely surrounded, and may also include a configuration in which a component is partially surrounded. In addition, the term "exposing" may include a configuration in which a component is completely exposed or a configuration in which a portion of a component is exposed, and "exposing" may refer to exposure from a component. For example, a configuration in which an opening may expose a pad may include exposing the pad from a resist layer, and a surface treatment layer may be further provided on the exposed pad.

[0061] In example embodiments, the configuration in which a component is disposed in a through-portion or a through-hole may include a configuration in which the component is completely disposed in the through-portion or the through-hole in cross section, and may also include a configuration in which the component protrudes outside the through-portion or the through-hole in cross section. For example, in the case in which a component is disposed in a through-portion or a through-hole in a plane, these configurations may be understood in a broader sense.

[0062] According to the above-described example embodiments, a printed circuit board that can reduce voltage drop and power loss can be provided.

[0063] Furthermore, a printed circuit board having improved inductance can be provided.

[0064] Furthermore, a printed circuit board can be provided which can achieve size reduction and can increase the degree of integration.

[0065] In example embodiments, a cross section may refer to a cross-sectional shape when an object is cut vertically, or a cross-sectional shape when an object is viewed from the side. In addition, a plane may refer to a shape when an object is cut horizontally, or a plane shape when an object is viewed from above or below.

[0066] In the present disclosure, example embodiments may include process errors, positional deviations, and measurement errors that occur in the process. For example, a configuration in which components are substantially the same may include examples in which the components are exactly the same, and may also include examples in which there may be slight differences due to process errors. In addition, a configuration in which elements are substantially constant may include examples in which the elements are completely constant, and may also include examples in which slight differences occur due to process errors.

[0067] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" through an adhesive layer or the like. Furthermore, the term "electrical connection" may include a case where an element is "physically connected" and a case where an element is "not physically connected." Furthermore, the terms "first," "second," and the like may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of example embodiments.

[0068] In the example embodiments, the term "example embodiment" may not refer to the same example embodiment, and may be provided to describe and emphasize different unique features of each example embodiment. The above-mentioned suggested example embodiments may be implemented without excluding the possibility of combining with features of other example embodiments. For example, unless otherwise indicated, even if a feature described in an example embodiment is not described in other example embodiments, the description may be understood to be related to other example embodiments.

[0069] Unless it has a clearly different meaning in the context, an expression used in the singular includes the expression in the plural.

[0070] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A substrate having a first through portion; a magnetic layer disposed in at least a portion of the first through-portion and having a second through-portion; an electronic component having at least a portion disposed in the second through portion; A first wiring pattern is arranged above the magnetic layer; a second wiring pattern, disposed below the magnetic layer; as well as The first through via has at least a portion surrounded by the magnetic layer and includes a first via pattern connecting the first wiring pattern and the second wiring pattern to each other.

2. The printed circuit board according to claim 1, wherein: The electronic assembly includes a voltage regulator.

3. The printed circuit board according to claim 1, further comprising: A first insulating layer covers at least a portion of each of the substrate, the magnetic layer, and the electronic component, and fills a portion of the second through portion.

4. The printed circuit board according to claim 3, in, The magnetic layer also has a first through hole, wherein the first insulating layer fills a portion of the first through hole, wherein the first insulating layer has a second through hole located in the first through hole, wherein at least a portion of the first through hole is disposed in the second through hole, and Wherein, the first through hole is separated from the magnetic layer.

5. The printed circuit board according to claim 4, in, The first via pattern is disposed on a wall surface of the second through hole, and The first through via further includes a first filler, and the first filler fills at least a portion of a space between the first via patterns in the second through hole.

6. The printed circuit board according to claim 3, wherein: The first insulating layer is disposed between the first wiring pattern and the upper surface of the magnetic layer and between the second wiring pattern and the lower surface of the magnetic layer, and The first wiring pattern and the second wiring pattern are included in a first wiring layer and a second wiring layer, respectively.

7. The printed circuit board according to claim 6, further comprising: A second through via has at least a portion surrounded by the substrate and includes a second via pattern connecting at least a portion of the first wiring layer and at least a portion of the second wiring layer to each other.

8. The printed circuit board according to claim 7, in, The substrate also has a third through hole, Wherein, the first insulating layer fills a portion of the third through hole, wherein the first insulating layer has a fourth through hole located in the third through hole, wherein at least a portion of the second through hole is disposed in the fourth through hole, and Wherein, the second through hole is spaced apart from the substrate.

9. The printed circuit board according to claim 8, in, The second via pattern is disposed on a wall surface of the fourth through hole, and The second through via further includes a second filler, and the second filler fills at least a portion of a space between the second via patterns in the fourth through hole.

10. The printed circuit board according to claim 6, further comprising: a first via layer passing through an upper side of the first insulating layer and including a first connection via connecting the first wiring layer to the electronic component, The electronic component and the first via pattern are connected to each other through a path passing through the first connection via and the first wiring layer.

11. The printed circuit board according to claim 10, wherein: The printed circuit board also includes: a second via layer passing through a lower side of the first insulating layer and including a second connection via connecting the second wiring layer to the electronic component, wherein the second connecting via is connected to the back surface of the electronic component, and Wherein, the first connecting via and the second connecting via taper in opposite directions.

12. The printed circuit board according to claim 6, further comprising: a second insulating layer, disposed on an upper surface of the first insulating layer; a third insulating layer, disposed on a lower surface of the first insulating layer; a third wiring layer, disposed on an upper surface of the second insulating layer; A fourth wiring layer, disposed on the lower surface of the third insulating layer; a third via layer passing through the second insulating layer and including a third connection via connecting the first wiring layer and the third wiring layer to each other; as well as a fourth via layer passing through the third insulating layer and including a fourth connection via connecting the second wiring layer and the fourth wiring layer to each other, Wherein, the third connecting via and the fourth connecting via taper in opposite directions.

13. The printed circuit board according to claim 12, further comprising: a first resist layer disposed on an upper surface of the second insulating layer and having a first opening exposing at least a portion of the third wiring layer; as well as A second resist layer is provided on a lower surface of the third insulating layer and has a second opening exposing at least a portion of the fourth wiring layer.

14. The printed circuit board according to claim 1, wherein: The magnetic layer is in contact with a wall surface of the first through-portion.

15. The printed circuit board according to claim 1, wherein The substrate includes an organic core layer or an inorganic core layer, and the inorganic core layer includes a glass core layer, a metal core layer, a silicon core layer or a ceramic core layer.

16. The printed circuit board according to claim 1, wherein Each of the first wiring pattern and the second wiring pattern and the first via pattern are connected to each other to form an inductor surrounding at least a portion of the magnetic layer.

17. A printed circuit board comprising: A substrate having a first through portion; a magnetic layer having at least a portion disposed in the first through-portion, contacting the substrate, and having a second through-portion and a plurality of through-holes; a voltage regulator, disposed in at least a portion of the second through portion; an insulating layer covering at least a portion of each of the substrate, the magnetic layer, and the voltage regulator, and filling a portion of each of the second through-portion and the plurality of through-holes; A first wiring pattern layer is disposed on the upper surface of the insulating layer; A second wiring pattern layer is disposed on the lower surface of the insulating layer; as well as A plurality of via patterns passes through each of the insulating layers in the plurality of through holes.

18. The printed circuit board according to claim 17, in, The first wiring pattern layer includes a plurality of first wiring patterns, wherein the second wiring pattern layer includes a plurality of second wiring patterns, and The plurality of first wiring patterns and the plurality of second wiring patterns are alternately connected with the plurality of via patterns to form one or more coil parts.

19. The printed circuit board according to claim 18, wherein The one or more coil portions surround the voltage regulator in a plane.

20. A printed circuit board, comprising: a substrate having a first through portion passing therethrough; a magnetic layer including a magnetic material disposed in the first through-portion, the magnetic layer having a second through-portion passing therethrough; as well as an inductor, disposed in the magnetic layer and surrounding the second through-portion, the inductor comprising: a first through hole passing through the magnetic layer in a pattern surrounding the second through portion; a first wiring pattern disposed over the magnetic layer and contacting top portions of at least some of the first through vias; and a second wiring pattern disposed below the magnetic layer and contacting bottom portions of at least some of the first through vias, The first wiring pattern is connected to the second wiring pattern through the first through via to form the inductor. 21 . The printed circuit board according to claim 20 , further comprising an electronic component disposed in the second through-portion.

22. The printed circuit board according to claim 21, wherein The electronic component is a voltage regulator.

23. The printed circuit board according to claim 21, wherein Each of the first through vias is disposed in a corresponding first through hole passing through the magnetic layer, and a first insulating layer separates the first through via from an inner wall of the corresponding first through hole.

24. The printed circuit board according to claim 23, wherein The first insulating layer covers at least a portion of each of the magnetic layer, the substrate, and the electronic component, and fills at least a portion of the second through portion.

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