Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate; the active layer is arranged on one side of the substrate; the multiple conductive layers are arranged on the side, away from the substrate, of the active layer in a stacked mode, the multiple conductive layers comprise a first conductive layer, the first conductive layer comprises a first grid electrode part, and the first grid electrode part is of an integrated structure; the active layer and the multiple conductive layers form at least one first pixel circuit, and the first pixel circuit comprises a first driving transistor and at least one auxiliary driving transistor; the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the channel region of the first driving transistor on the substrate and the orthographic projection of the at least one auxiliary driving transistor on the substrate. The grid electrodes of the first driving transistor and the auxiliary driving transistors are connected together, so that the channel length of the first driving transistor is prolonged, and the gray scale expansion effect of the array substrate during display is better. The first gate part is of an integrated structure, the distance between metal on the same layer does not need to be considered, and the layout space is saved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more extensive, and correspondingly, the requirements for display panels are becoming higher and higher.

[0003] However, existing high-resolution products cannot provide good display effects at the same time. Summary of the invention

[0004] The present invention provides an array substrate and a display panel to solve the problem that high-resolution products cannot provide good display effects.

[0005] According to one aspect of the present invention, there is provided an array substrate, comprising:

[0006] substrate;

[0007] An active layer, disposed on one side of the substrate;

[0008] A multi-layer conductive layer stacked on a side of the active layer away from the substrate, the multi-layer conductive layer comprising a first conductive layer, the first conductive layer comprising a first gate portion, and the first gate portion is an integrated structure;

[0009] The active layer and the multi-layer conductive layer constitute at least one first pixel circuit, wherein the first pixel circuit includes a first driving transistor and at least one auxiliary driving transistor;

[0010] The channel regions of the first driving transistor and the at least one auxiliary driving transistor are both located in the active layer, and the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the channel region of the first driving transistor on the substrate and the orthographic projection of the at least one auxiliary driving transistor on the substrate.

[0011] Optionally, the first pixel circuit includes two auxiliary driving transistors, namely a first transistor and a second transistor, and a channel region of the first driving transistor, a channel region of the first transistor, and a channel region of the second transistor are connected to each other;

[0012] The first electrode of the first driving transistor, the second electrode of the first transistor, and the second electrode of the second transistor are connected to each other;

[0013] Optionally, the channel region of the first driving transistor extends along a first direction, the channel region of the first transistor and the channel region of the second transistor both extend along a second direction, and the first direction intersects the second direction;

[0014] Optionally, the first electrode, the channel region, and the second electrode of the first transistor are arranged along the second direction, and the second electrode, the channel region, and the first electrode of the second transistor are arranged along the second direction;

[0015] Optionally, the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the second electrode of the second transistor on the substrate.

[0016] Optionally, the first gate portion includes a first sub-portion and a second sub-portion arranged along the first direction, and the first sub-portion and the second sub-portion are connected;

[0017] The orthographic projection of the first sub-portion on the substrate covers the orthographic projections of the channel region of the first driving transistor, the channel region of the first transistor, and the channel region of the second transistor on the substrate, and the orthographic projection of the second sub-portion on the substrate does not overlap with the orthographic projections of the channel region of the first driving transistor, the channel region of the first transistor, and the channel region of the second transistor on the substrate;

[0018] Optionally, a length of an orthographic projection of the second sub-portion on the substrate along the first direction is greater than or equal to 1 micron.

[0019] Optionally, the multi-layer conductive layer further includes a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, the first pixel circuit further includes a storage capacitor, the first gate portion is reused as a first plate of the storage capacitor, and the second plate of the storage capacitor is located in the second conductive layer;

[0020] Optionally, the multi-layer conductive layer further includes a third conductive layer and a fourth conductive layer, the third conductive layer is located on a side of the second conductive layer away from the substrate, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the first pixel circuit further includes a third transistor;

[0021] The array substrate further includes a data line, the data line is located in the fourth conductive layer, the first electrode of the third transistor is connected to the data line through a via hole, and the second electrode of the third transistor is connected to the first electrode of the first transistor;

[0022] The array substrate further includes a first scanning line, the first scanning line is located in the first conductive layer, the first scanning line includes a first scanning sub-portion extending along the first direction, and the orthographic projection of the first scanning sub-portion on the substrate covers the orthographic projection of the channel region of the third transistor on the substrate;

[0023] Optionally, the data line extends along the second direction;

[0024] Optionally, the first pixel circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to a second electrode of the first driving transistor, and a second electrode of the fourth transistor is connected to the first gate portion via a first connecting line located in the third conductive layer;

[0025] The first scanning line further includes a second scanning sub-portion extending along the second direction, the first scanning sub-portion is connected to the second scanning sub-portion, and an orthographic projection of the first scanning sub-portion on the substrate and an orthographic projection of the second scanning sub-portion on the substrate both at least partially overlap with an orthographic projection of the channel region of the fourth transistor on the substrate;

[0026] Optionally, the channel region of the fourth transistor includes a first channel sub-region extending along the second direction and a second channel sub-region extending along the first direction, the first channel sub-region and the second channel sub-region are connected, an orthographic projection of the first scanning sub-portion on the substrate covers an orthographic projection of the first channel sub-region on the substrate, and an orthographic projection of the second scanning sub-portion on the substrate covers an orthographic projection of the second channel sub-region on the substrate;

[0027] Optionally, the first connecting line extends along the second direction.

[0028] Optionally, the array substrate further includes a second scan line and a first initialization signal line, the second scan line is located in the first conductive layer, the first initialization signal line is located in the second conductive layer, and the first pixel circuit further includes a fifth transistor;

[0029] A first electrode of the fifth transistor is connected to the first initialization signal line via a second connection line located in the third conductive layer, a second electrode of the fifth transistor is connected to a second electrode of the fourth transistor, and an orthographic projection of the second scanning line on the substrate covers and overlaps an orthographic projection of a channel region of the fifth transistor on the substrate;

[0030] Optionally, the channel region of the fifth transistor includes a third channel sub-region and a fourth channel sub-region both extending along the second direction, the active layer further includes a second active connection portion, the third channel sub-region is connected to one end of the second active connection portion, the fourth channel sub-region is connected to the other end of the second active connection portion, and the orthographic projection of the second scan line on the substrate covers the orthographic projection of the third channel sub-region on the substrate, and the orthographic projection of the second scan line on the substrate covers the orthographic projection of the fourth channel sub-region on the substrate;

[0031] Optionally, the second scan line and the first initialization signal line both extend along the first direction, the first scan line, the second scan line and the first initialization signal line are arranged along the second direction, and the orthographic projection of the first scan line on the substrate, the orthographic projection of the second scan line on the substrate and the orthographic projection of the first initialization signal line on the substrate are all located on the same side of the first gate portion, the orthographic projection of the second scan line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the first scan line on the substrate, and the orthographic projection of the first initialization signal line on the substrate is located on a side of the orthographic projection of the second scan line on the substrate away from the first gate portion;

[0032] Optionally, the second connecting line extends along the second direction.

[0033] Optionally, the array substrate further includes a light emitting control signal line and a first power line, the light emitting control signal line is located in the first conductive layer, the first power line is located in the fourth conductive layer, and the first pixel circuit further includes a sixth transistor, a seventh transistor and a first light emitting device;

[0034] The first electrode of the sixth transistor is connected to the first power line through a via hole, the second electrode of the sixth transistor is connected to the first electrode of the second transistor, and the orthographic projection of the light emitting control signal line on the substrate covers the orthographic projection of the channel region of the sixth transistor on the substrate;

[0035] The first electrode of the seventh transistor is connected to the second electrode of the first driving transistor, the second electrode of the seventh transistor is connected to the first light-emitting device, and the orthographic projection of the light-emitting control signal line on the substrate covers the orthographic projection of the channel region of the seventh transistor on the substrate;

[0036] Optionally, the light emitting control signal line extends along the first direction, and an orthographic projection of the light emitting control signal line on the substrate is located on a side where an orthographic projection of the first gate portion on the substrate is away from an orthographic projection of the first scanning line on the substrate;

[0037] Optionally, the first power line extends along the second direction.

[0038] Optionally, the array substrate further includes a third scan line, a second initialization signal line and a third initialization signal line, the third scan line is located in the first conductive layer, the second initialization signal line is located in the second conductive layer, the third initialization signal line is located in the third conductive layer, and the first pixel circuit further includes an eighth transistor and a ninth transistor;

[0039] A first electrode of the eighth transistor is connected to the second initialization signal line via a third connection line located in the third conductive layer, a second electrode of the eighth transistor is connected to a second electrode of the seventh transistor, and an orthographic projection of the third scanning line on the substrate covers an orthographic projection of a channel region of the eighth transistor on the substrate;

[0040] A first electrode of the ninth transistor is connected to the third initialization signal line through a via hole, a second electrode of the ninth transistor is connected to the first electrode of the second transistor through a fourth connection line located on the third conductive layer, and an orthographic projection of a channel region of the ninth transistor on the substrate overlaps with an orthographic projection of the third scan line on the substrate;

[0041] Optionally, the third scan line, the second initialization signal line and the third initialization signal line all extend along the first direction, the orthographic projection of the third scan line on the substrate is located on a side where the orthographic projection of the light emitting control signal line on the substrate is away from the orthographic projection of the first gate portion on the substrate, and the projection of the second initialization signal line on the substrate is located on a side where the orthographic projection of the third scan line on the substrate is away from the orthographic projection of the first gate portion on the substrate;

[0042] Optionally, an orthographic projection of the third initialization signal line on the substrate at least partially overlaps with an orthographic projection of the third scan line on the substrate.

[0043] Optionally, the array substrate further includes a third scan line and a second initialization signal line, the third scan line is located in the first conductive layer, the second initialization signal line is located in the third conductive layer, and the first pixel circuit further includes an eighth transistor;

[0044] A first electrode of the eighth transistor is connected to the second initialization signal line through a via hole, a second electrode of the eighth transistor is connected to the second electrode of the seventh transistor, and an orthographic projection of the third scan line on the substrate covers an orthographic projection of a channel region of the eighth transistor on the substrate;

[0045] Optionally, the third scan line and the second initialization signal line both extend along the first direction, and an orthographic projection of the third scan line on the substrate is located on a side of an orthographic projection of the light emitting control signal line on the substrate away from an orthographic projection of the first gate portion on the substrate;

[0046] Optionally, an orthographic projection of the second initialization signal line on the substrate at least partially overlaps with an orthographic projection of the third scan line on the substrate.

[0047] Optionally, the active layer and the multi-layer conductive layer further constitute at least one second pixel circuit;

[0048] The multi-layer conductive layer further includes a fourth conductive layer, the fourth conductive layer is located on a side of the first conductive layer away from the substrate, the array substrate includes a light emitting control signal line and a first power line, the light emitting control signal line is located in the first conductive layer, and the first power line is located in the fourth conductive layer;

[0049] The second pixel circuit includes a second driving transistor, a tenth transistor, an eleventh transistor and a second light-emitting device, the first electrode of the tenth transistor is connected to the first power line through a via hole, the second electrode of the tenth transistor is connected to the first electrode of the second driving transistor, the second electrode of the second driving transistor is connected to the first electrode of the eleventh transistor, the second electrode of the eleventh transistor is connected to the second light-emitting device, the orthographic projection of the light-emitting control signal line on the substrate covers the orthographic projection of the channel region of the tenth transistor on the substrate, and the orthographic projection of the light-emitting control signal line on the substrate covers the orthographic projection of the channel region of the eleventh transistor on the substrate;

[0050] The active layer includes a second gate portion corresponding to each second pixel circuit one by one, a channel region of the second driving transistor is located at an orthographic projection of the second gate portion on the active layer, an orthographic projection of the second gate portion on the substrate does not overlap with an orthographic projection of a first electrode and a second electrode of the second driving transistor on the substrate, and an orthographic projection of the second gate portion on the substrate is smaller than an orthographic projection of the first gate portion on the substrate;

[0051] The array substrate includes multiple pixels, each pixel includes at least two pixel circuits of a first pixel circuit and / or a second pixel circuit, the pixel circuits belonging to the same pixel include light-emitting devices with different luminous colors, each pixel circuit belonging to the same pixel is a first pixel circuit, or at least two pixel circuits belonging to the same pixel include at least one first pixel circuit and at least one second pixel circuit, and the types of pixel circuits connected to light-emitting devices of the same color are the same.

[0052] According to another aspect of the present invention, a display panel is provided, comprising the array substrate described in the above aspect.

[0053] In the technical solution of the embodiment of the present invention, the pixel circuit includes a first driving transistor and at least one auxiliary driving transistor. Since the portion of the first gate portion covering the channel region of the transistor is formed as the gate of the transistor, the orthographic projection of the first gate portion on the substrate is set to cover the orthographic projection of the channel region of the first driving transistor on the substrate and the orthographic projection of at least one auxiliary driving transistor on the substrate, so that the gates of the first driving transistor and each auxiliary driving transistor are connected together, the channel length of the first driving transistor is extended, and the grayscale expansion effect of the array substrate is better during display. At the same time, since the first gate portion is an integrated structure, there is no need to consider the distance limit between the metals in the same layer, which can save the layout space and is conducive to achieving high resolution of the array substrate.

[0054] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 A schematic plan view of a driving transistor and an auxiliary driving transistor in an array substrate provided by an embodiment of the present invention;

[0057] Figure 2 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present invention;

[0058] Figure 3 A schematic structural diagram of a first pixel circuit provided by an embodiment of the present invention;

[0059] Figure 4 A plan view of an active layer in an array substrate provided by an embodiment of the present invention;

[0060] Figure 5 A schematic plan view of an active layer and a first conductive layer in an array substrate provided by an embodiment of the present invention;

[0061] Figure 6 A schematic plan view of an active layer, a first conductive layer, a second conductive layer and a third conductive layer in an array substrate provided by an embodiment of the present invention;

[0062] Figure 7 A schematic plan view of a first pixel circuit in an array substrate provided by an embodiment of the present invention;

[0063] Figure 8 A cross-sectional schematic diagram of another array substrate provided by an embodiment of the present invention;

[0064] Fig. 9 A schematic structural diagram of another first pixel circuit provided by an embodiment of the present invention;

[0065] Fig.10 A schematic plan view of an active layer, a first conductive layer, and a second conductive layer in another array substrate provided by an embodiment of the present invention;

[0066] Fig.11 A schematic plan view of a single pixel in an array substrate provided by an embodiment of the present invention;

[0067] Fig.12 A schematic structural diagram of a second pixel circuit in an array substrate provided by an embodiment of the present invention;

[0068] Fig.13 A schematic plan view of another pixel in an array substrate provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0069] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0070] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] As described in the background art, existing high-resolution products cannot simultaneously achieve good display effects. The inventors have found that the reason is that the longer the channel length of the driving transistor included in the pixel circuit is, the better the grayscale expansion effect is during display. However, within the limited layout space, extending the channel length of the driving transistor will occupy the layout space, which is not conducive to achieving high resolution of the product.

[0072] In view of the above technical problems, an embodiment of the present invention provides a new type of array substrate, which takes into account both high resolution and display effect of the product. Figure 1 A schematic plan view of a driving transistor and an auxiliary driving transistor in an array substrate provided by an embodiment of the present invention, Figure 2 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present invention, wherein Figure 2 For along Figure 1 AA' section view, see Figure 1 and Figure 2 , the array substrate comprises:

[0073] Substrate 10;

[0074] The active layer 11 is disposed on one side of the substrate 10;

[0075] A plurality of conductive layers stacked on a side of the active layer 11 away from the substrate 10, the plurality of conductive layers comprising a first conductive layer 12, the first conductive layer 12 comprising a first gate portion 121, the first gate portion 121 being an integrated structure;

[0076] The active layer 11 and the multi-layer conductive layer constitute at least one first pixel circuit, and the first pixel circuit includes a first driving transistor T0 and at least one auxiliary driving transistor;

[0077] The channel regions of the first driving transistor T0 and at least one auxiliary driving transistor are both located in the active layer 11 , and the orthographic projection of the first gate portion 121 on the substrate 10 covers the orthographic projection of the channel region of the first driving transistor T1 on the substrate 10 and the orthographic projection of at least one auxiliary driving transistor on the substrate 10 .

[0078] Specifically, the substrate 10 is used to provide protection and support for the array substrate, wherein the substrate 10 may be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. The active layer 11 includes polycrystalline silicon so that the turn-on or turn-off speed of the formed transistor is faster. The active layer 11 is provided with a plurality of conductive layers on one side of the substrate 10, and the plurality of conductive layers are isolated from each other by insulating layers.

[0079] In this embodiment, the first pixel circuit includes two auxiliary driving transistors, namely, the first transistor T1 and the second transistor T2. The orthographic projection of the first gate portion 121 on the substrate 10 covers the orthographic projection of the channel region of the first driving transistor T0 on the substrate 10, so that the first gate portion 121 is formed as the gate of the first driving transistor T0, and the orthographic projection of the first gate portion 121 on the substrate 10 covers the orthographic projection of the channel region of each auxiliary driving transistor on the substrate, so that the first gate portion 121 is formed as the gate of each auxiliary driving transistor such as the first transistor T1 and the second transistor T2 in this embodiment. Since the first gate portion 121 is an integrated structure, it is a closed overall structure. Therefore, the connection between the first driving transistor T0 and the gates of each auxiliary transistor is realized through the first gate portion 121. The length of the channel region of the first driving transistor T0 is extended by at least one auxiliary driving transistor, so that the array substrate has a good grayscale expansion effect when displaying, thereby improving the display effect.

[0080] If the gate of the first driving transistor T0 is the first conductive block, and the gates of each auxiliary transistor are auxiliary conductive blocks, the first conductive block and each auxiliary conductive block are both located in the first conductive layer, and the first conductive block and each auxiliary conductive block are independent entities, then the first conductive block and the auxiliary conductive block can also be connected by a cross-line method to achieve the connection between the gates of the first driving transistor and each auxiliary driving transistor. However, in order to ensure that each transistor formed is not affected by process fluctuations, any two of the first conductive block and each auxiliary conductive block need to be separated by a set distance such as 1.5 microns, resulting in a large required layout space, which is not conducive to high resolution. In this embodiment, the first driving transistor T0 and the gates of each auxiliary transistor are connected together through the first gate portion 121 of the integrated structure, without considering the distance limit between the metals on the same layer, which can save layout space.

[0081] In the technical solution of the embodiment of the present invention, the pixel circuit includes a first driving transistor and at least one auxiliary driving transistor. Since the portion of the first gate portion covering the channel region of the transistor is formed as the gate of the transistor, the orthographic projection of the first gate portion on the substrate is set to cover the orthographic projection of the channel region of the first driving transistor on the substrate and the orthographic projection of at least one auxiliary driving transistor on the substrate, so that the gates of the first driving transistor and each auxiliary driving transistor are connected together, the channel length of the first driving transistor is extended, and the grayscale expansion effect of the array substrate is better during display. At the same time, since the first gate portion is an integrated structure, there is no need to consider the distance limit between the metals in the same layer, which can save the layout space and is conducive to achieving high resolution of the array substrate.

[0082] refer to Figure 1Optionally, the first pixel circuit includes two auxiliary driving transistors, namely a first transistor T1 and a second transistor T2, and the channel region of the first driving transistor T0, the channel region of the first transistor T1, and the channel region of the second transistor T2 are connected to each other. When the area of ​​the first gate portion 121 is constant, the channel region of the first driving transistor T0, the channel region of the first transistor T1, and the channel region of the second transistor T2 are connected to each other, which can increase the channel length of the first driving transistor T0;

[0083] The first electrode of the first driving transistor T0 , the second electrode of the first transistor T1 , and the second electrode of the second transistor T2 are connected to each other.

[0084] Exemplarily, the first pixel circuit further includes a data writing transistor and a light emitting control transistor, the data writing transistor is used to write a data voltage to the pixel circuit, and the light emitting control transistor is used to be turned on in the light emitting stage so that the driving current can be transmitted to the light emitting device. The first transistor T1 can be connected between the data writing transistor and the first electrode of the first driving transistor T0, and the second transistor T2 can be connected between the light emitting control transistor and the first driving transistor T0.

[0085] Continue to refer Figure 1 The channel region of the first driving transistor T0 extends along a first direction X, the channel region of the first transistor T1 and the channel region of the second transistor T2 both extend along a second direction Y, and the first direction X intersects with the second direction Y.

[0086] The first electrode, the channel region and the second electrode of the first transistor T1 are arranged along the second direction Y, and the second electrode, the channel region and the first electrode of the second transistor T2 are arranged along the second direction Y.

[0087] The orthographic projection of the first gate portion 121 on the substrate 10 covers the orthographic projection of the second electrode of the first transistor T1 on the substrate 10 and the orthographic projection of the second electrode of the second transistor T2 on the substrate 10 .

[0088] For the first driving transistor T0, the first transistor T1, the second transistor T2, or any transistor described below, the source region and the drain region of the transistor are located at both ends of the channel region, wherein the source region, the drain region and the channel region are all located in the active layer 11. In this embodiment, by performing certain doping in the source region and the drain region, the source region is formed as a source electrode, i.e., a first electrode, and the drain region is formed as a drain electrode, i.e., a second electrode of the first transistor T1, the channel region of the first transistor T1, the second electrode of the second transistor T2, and the channel region of the second transistor T2 are sequentially connected and formed into an integrated whole, which is recorded as a preset active sub-portion, and are all covered by the first gate portion 121.

[0089] Continue to refer Figure 1 and Figure 2 Optionally, the first gate portion 121 includes a first sub-portion A1 and a second sub-portion A2 arranged along the first direction X, and the first sub-portion A1 and the second sub-portion A2 are connected;

[0090] The orthographic projection of the first sub-portion A1 on the substrate 10 covers the orthographic projections of the channel region of the first driving transistor T0, the channel region of the first transistor T1, and the channel region of the second transistor T2 on the substrate 10, and the orthographic projection of the second sub-portion A2 on the substrate 10 has no overlap with the orthographic projections of the channel region of the first driving transistor T0, the channel region of the first transistor T1, and the channel region of the second transistor T2 on the substrate 10.

[0091] The first gate portion 121 includes a first sub-portion A1 and a second sub-portion A2, so that the edge of the first gate portion 121 exceeds the edge of the preset active sub-portion, so as to prevent the first gate portion 121 from shrinking due to other processes and thus affecting the device characteristics of the first transistor T1 and the second transistor T2. Optionally, the length of the orthographic projection of the second sub-portion A2 on the substrate 10 along the first direction X is greater than or equal to 1 micron, that is, along the first direction X, the length of the first gate portion 121 beyond the active layer 11 is greater than or equal to 1 micron, so as to ensure that the formed transistor is not affected by process fluctuations.

[0092] Figure 3 A schematic structural diagram of a first pixel circuit provided by an embodiment of the present invention, Figure 4 A plan view of an active layer in an array substrate provided by an embodiment of the present invention, Figure 5 A schematic plan view of an active layer and a first conductive layer in an array substrate provided by an embodiment of the present invention, Figure 6 A schematic plan view of an active layer, a first conductive layer, a second conductive layer and a third conductive layer in an array substrate provided by an embodiment of the present invention, Figure 7 A schematic plan view of a first pixel circuit in an array substrate provided by an embodiment of the present invention, Figure 8 A cross-sectional schematic diagram of another array substrate provided by an embodiment of the present invention, wherein: Figure 8 For along Figure 7 Cross-section of BB', see Figure 3-Figure 8 Optionally, the multilayer conductive layer further includes a second conductive layer 13, the second conductive layer 13 is located on a side of the first conductive layer 12 away from the substrate 10, the first pixel circuit further includes a storage capacitor Cst, the first gate portion 121 is reused as a first plate of the storage capacitor Cst, that is, a first end of the storage capacitor Cst is connected to the gate of the first driving transistor T0 to store the potential of the gate of the first driving transistor T0, a second plate of the storage capacitor Cst is located in the second conductive layer 13, and a second end of the storage capacitor Cst is used to access a fixed potential, such as Figure 6As shown, the second end of the storage capacitor Cst is connected to the first power line VDD, specifically through a via hole. Figure 6 Not shown in the figure.

[0093] Optionally, the multi-layer conductive layer further includes a third conductive layer 14 and a fourth conductive layer 15, the third conductive layer 14 is located on a side of the second conductive layer 13 away from the substrate 10, and the fourth conductive layer 15 is located on a side of the third conductive layer 14 away from the substrate 10. Among them, a first insulating layer 1 is provided between the active layer 11 and the first conductive layer 12, a second insulating layer 2 is provided between the first conductive layer 12 and the second conductive layer 13, a third insulating layer 3 is provided between the second conductive layer 13 and the third conductive layer 14, and a fourth insulating layer 4 is provided between the third conductive layer 14 and the fourth conductive layer 15. The first pixel circuit further includes a third transistor T3;

[0094] The array substrate further includes a data line Data, which extends along the second direction Y. The data line Data is located in the fourth conductive layer 15. The first electrode of the third transistor T3 is connected to the data line Data through a via hole, and the second electrode of the third transistor T3 is connected to the first electrode of the first transistor T1.

[0095] The array substrate further includes a first scan line S1, which is located in the first conductive layer 12 and includes a first scan sub-portion S11 extending along the first direction X. The orthographic projection of the first scan sub-portion S11 on the substrate 10 covers the orthographic projection of the channel region of the third transistor T3 on the substrate.

[0096] The part where the orthographic projection of the first scanning sub-unit S11 on the substrate 10 overlaps with the orthographic projection of the channel region of the third transistor T3 on the substrate serves as the gate of the third transistor T3. The first electrode of the third transistor T3 can be connected to the data line Data through two vias, namely the first via 5 and the second via 6, wherein the first via 5 is a via extending from the fourth conductive layer 15 to the third conductive layer 14, and the second via 6 is a via extending from the third conductive layer 14 to the active layer 11. The second electrode of the third transistor T3 is directly connected to the first electrode of the first transistor T1 at the active layer. The third transistor T3 is used to provide the data voltage transmitted on the data line Data to the first driving transistor T0 via the first transistor T1.

[0097] Optionally, the first pixel circuit further includes a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the second electrode of the first driving transistor T0, and a second electrode of the fourth transistor T4 is connected to the first gate portion 121 via a first connecting line L1 located in the third conductive layer 14;

[0098] The first scanning line S1 also includes a second scanning sub-section S12 extending along the second direction Y, the first scanning sub-section S11 is connected to the second scanning sub-section S12, and the orthographic projection of the first scanning sub-section S11 on the substrate 10 and the orthographic projection of the second scanning sub-section S12 on the substrate 10 both at least partially overlap with the orthographic projection of the channel region of the fourth transistor T4 on the substrate 10.

[0099] The channel region of the fourth transistor T4 includes a first channel sub-region G41 extending along the second direction Y and a second channel sub-region G42 extending along the first direction X, the first channel sub-region G41 and the second channel sub-region G42 are connected by a first active connecting portion 111 located in the active layer 11, the orthographic projection of the first scanning sub-portion S11 on the substrate 10 covers the orthographic projection of the first channel sub-region G41 on the substrate 10, and the orthographic projection of the second scanning sub-portion S12 on the substrate 10 covers the orthographic projection of the second channel sub-region G42 on the substrate 10.

[0100] The first electrode of the fourth transistor T4 is directly connected to the second electrode of the first driving transistor T0, and the second electrode of the fourth transistor T4 is connected to the gate of the first driving transistor T0. Specifically, the second electrode of the fourth transistor T4 is connected to one end of the first connecting line L1 located in the third conductive layer 14 through a via hole penetrating from the third conductive layer 14 to the active layer 11, and the other end of the first connecting line L1 is connected to the first gate portion 121 through a via hole penetrating from the third conductive layer 14 to the first conductive layer 12, thereby realizing the connection between the second electrode of the fourth transistor T4 and the gate of the first driving transistor T0. Optionally, the first connecting line L1 extends along the second direction Y. Optionally, in order to reduce the size of the leakage current, the fourth transistor T4 is set as a dual-gate transistor, and the fourth transistor T4 includes a first sub-transistor T4_1 and a second sub-transistor T4_2, the first electrode, the channel region and the second electrode of the first sub-transistor T4_1 are arranged along the second direction Y, and the first electrode, the channel region and the second electrode of the second sub-transistor T4_2 are arranged along the first direction X. The first electrode of the first sub-transistor T4_1 serves as the first electrode of the fourth transistor T4, the second electrode of the first sub-transistor T4_1 is connected to the first electrode of the second sub-transistor T4_2, the second electrode of the second sub-transistor T4_2 serves as the second electrode of the fourth transistor T4, the gate of the first sub-transistor T4_1 and the gate of the second sub-transistor T4_2 both serve as the gate of the fourth transistor T4 and are connected to the first scan line S1.

[0101] Continue to refer Figure 3-Figure 8 Optionally, the array substrate further includes a second scan line S2 and a first initialization signal line Vref1, the second scan line S2 is located in the first conductive layer 12, the first initialization signal line Vref1 is located in the second conductive layer 13, and the first pixel circuit further includes a fifth transistor T5;

[0102] The first electrode of the fifth transistor T5 is connected to the first initialization signal line Vref1 through the second connection line L2 located in the third conductive layer 14, the second electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, and the orthographic projection of the second scan line S2 on the substrate 10 covers the orthographic projection of the channel region of the fifth transistor T5 on the substrate 10.

[0103] The first electrode of the fifth transistor T5 is connected to one end of the second connection line L2 through a via hole penetrating from the third conductive layer 14 to the active layer 11, and the other end of the second connection line L2 is connected to the first initialization signal line Vref1 through a via hole penetrating from the third conductive layer 14 to the second conductive layer 13, thereby realizing the connection between the first electrode of the fifth transistor T5 and the first initialization signal line Vref1. The second electrode of the fifth transistor T5 is directly connected to the second electrode of the fourth transistor T4 in the active layer, that is, the second electrode of the fifth transistor T5 is also connected to the gate of the first drive transistor T0 through the first connection line L1, thereby making the second electrode of the fifth transistor T5 also connected to the gate of the first transistor T1 and the gate of the second transistor T2. The fifth transistor T5 is used to transmit the first initialization voltage provided on the first initialization signal line Vref1 to the gate of the first drive transistor T0, the gate of the first transistor T1, and the gate of the second transistor T2 respectively. Optionally, the second connection line L2 extends along the second direction Y.

[0104] Further, the channel region of the fifth transistor T5 includes a third channel sub-region G51 and a fourth channel sub-region G52, both extending along the second direction Y, the active layer 11 also includes a second active connection portion 112, the third channel sub-region G51 is connected to one end of the second active connection portion 112, the fourth channel sub-region G52 is connected to the other end of the second active connection portion 112, and the orthographic projection of the second scan line S2 on the substrate 10 covers the orthographic projection of the third channel sub-region G51 on the substrate 10, and the orthographic projection of the second scan line S2 on the substrate 10 covers the orthographic projection of the fourth channel sub-region G52 on the substrate 10.

[0105] In order to reduce the magnitude of the leakage current, the fifth transistor T5 is set as a dual-gate transistor, including a third sub-transistor T5_1 and a fourth sub-transistor T5_2, the portion of the second scan line S2 whose orthographic projection on the substrate 10 covers the orthographic projection of the third channel sub-region G51 on the substrate 10 serves as the gate of the third sub-transistor T5_1, and the portion of the second scan line S2 whose orthographic projection on the substrate 10 covers the orthographic projection of the fourth channel sub-region G52 on the substrate 10 serves as the gate of the fourth sub-transistor T5_2. The first electrode of the third sub-transistor T5_1 serves as the first electrode of the fifth transistor T5, the second electrode of the third sub-transistor T5_1 is connected to the first electrode of the fourth sub-transistor T5_2, the second electrode of the fourth sub-transistor T5_2 serves as the second electrode of the fifth transistor T5, and the gate of the third sub-transistor T5_1 and the gate of the fourth sub-transistor T5_2 both serve as the gate of the fifth transistor T5, and are connected to the second scan line S2.

[0106] Optionally, the second scan line S2 and the first initialization signal line Vref1 both extend along the first direction X, the first scan line S1, the second scan line S2 and the first initialization signal line Vref1 are arranged along the second direction Y, and the orthographic projection of the first scan line S1 on the substrate 10, the orthographic projection of the second scan line S2 on the substrate 10 and the orthographic projection of the first initialization signal line Vref1 on the substrate 10 are all located on the same side of the first gate portion 121, the orthographic projection of the second scan line S2 on the substrate 10 is located between the orthographic projection of the first initialization signal line Vref1 on the substrate 10 and the orthographic projection of the first scan line S1 on the substrate 10, and the orthographic projection of the first initialization signal line Vref1 on the substrate 10 is located on the side of the orthographic projection of the second scan line S2 on the substrate 10 away from the first gate portion 121.

[0107] Continue to refer Figure 3-Figure 8 Optionally, the array substrate further includes a light emitting control signal line EM and a first power line VDD, the light emitting control signal line EM is located on the first conductive layer 12, the first power line VDD is located on the fourth conductive layer 15, and the first pixel circuit further includes a sixth transistor T6, a seventh transistor T7 and a first light emitting device OLED1;

[0108] The first electrode of the sixth transistor T6 is connected to the first power line VDD through at least one via hole. For example, in an optional embodiment, the first electrode of the sixth transistor T6 is first connected to the connection line located in the third conductive layer 14 through the via hole penetrating from the fourth conductive layer 15 to the third conductive layer 14, and the connection line is further connected to the first electrode of the sixth transistor T6 through the via hole penetrating from the third conductive layer 14 to the active layer 11, thereby realizing the connection between the first electrode of the sixth transistor T6 and the first power line VDD. The second electrode of the sixth transistor T6 is connected to the first electrode of the second transistor T2, the positive projection of the light emitting control signal line EM on the substrate 10 covers the positive projection of the channel region of the sixth transistor T6 on the substrate 10, and the part of the light emitting control signal line EM whose positive projection on the substrate 10 covers the positive projection of the channel region of the sixth transistor T6 on the substrate 10 serves as the gate of the sixth transistor T6.

[0109] The first electrode of the seventh transistor T7 is connected to the second electrode of the first driving transistor T0, the second electrode of the seventh transistor T7 is connected to the first light emitting device OLED1, and the orthographic projection of the light emitting control signal line EM on the substrate 10 covers the orthographic projection of the channel region of the seventh transistor T7 on the substrate 10. The portion of the light emitting control signal line EM whose orthographic projection on the substrate 10 covers the orthographic projection of the channel region of the seventh transistor T7 on the substrate 10 serves as the gate of the seventh transistor T7.

[0110] Optionally, the light control signal line EM extends in the first direction X, and the orthographic projection of the light control signal line EM on the substrate 10 is located on a side away from the orthographic projection of the first gate portion on the substrate 10 and the orthographic projection of the first scan line S1 on the substrate 10. The first power line VDD extends in the second direction Y.

[0111] The sixth transistor T6 and the seventh transistor T7 are used to be turned on in response to the signal on the light emitting control signal line EM during the light emitting phase, so that the driving current generated by the first driving transistor T0 can be transmitted to the first light emitting device OLED1 to drive the first light emitting device OLED1 to emit light.

[0112] Continue to refer Figure 3-Figure 8 Optionally, the array substrate further includes a third scan line S3 and a second initialization signal line Vref2, the third scan line S3 is located in the first conductive layer 12, the second initialization signal line Vref2 is located in the third conductive layer 14, and the first pixel circuit further includes an eighth transistor T8;

[0113] The first electrode of the eighth transistor T8 is connected to the second initialization signal line Vref2 through the fifth connection line L5 located in the third conductive layer 14. Specifically, the first electrode of the eighth transistor T8 is connected to one end of the fifth connection line L5 through the via hole penetrating from the third conductive layer 14 to the active layer 11, and the other end of the fifth connection line L5 is overlapped with the second initialization signal line Vref2, thereby realizing the connection between the first electrode of the eighth transistor T8 and the second initialization signal line Vref2. The second electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, and the positive projection of the third scan line S3 on the substrate 10 covers the positive projection of the channel region of the eighth transistor T8 on the substrate 10, and at least partially overlaps. The part of the positive projection of the third scan line S3 on the substrate 10 that covers the positive projection of the channel region of the eighth transistor T8 on the substrate 10 serves as the gate of the eighth transistor T8. The eighth transistor T8 is used to transmit the second initialization voltage to the first electrode of the first light-emitting device OLED1 in response to the signal on the third scan line S3, so as to initialize the first light-emitting device OLED1. Among them, the second electrode of the first light-emitting device OLED1 is connected to the second power line VSS.

[0114] Optionally, the third scan line S3 and the second initialization signal line Vref2 both extend along the first direction X, and the orthographic projection of the third scan line S3 on the substrate 10 is located on a side of the orthographic projection of the light emitting control signal line EM on the substrate away from the orthographic projection of the first gate portion 121 on the substrate 10 .

[0115] Optionally, the orthographic projection of the second initialization signal line Vref2 on the substrate 10 at least partially overlaps with the orthographic projection of the third scan line S3 on the substrate 10. In an optional embodiment, the orthographic projection of the third scan line S3 on the substrate 10 covers the orthographic projection of the second initialization signal line Vref2 on the substrate 10 to save layout area, which is conducive to the realization of high PPI.

[0116] against Figure 3 The first pixel circuit shown in the figure has a working process including:

[0117] In the first initialization stage, the fifth transistor T5 is turned on in response to the signal on the second scan line S2 to transmit the first initialization voltage to the gate of the first driving transistor T0, the gate of the first transistor T1 and the gate of the second transistor T2 respectively to initialize the above transistors.

[0118] In the data writing and threshold compensation stage, the third transistor T3 and the fourth transistor T4 are both turned on in response to the signal on the first scan line S1 to write the voltage related to the data voltage and the threshold voltage to the gate of the first driving transistor T0, thereby realizing the writing of the data voltage and the compensation of the threshold voltage of the first driving transistor T0.

[0119] In the second initialization stage, the eighth transistor T8 is turned on in response to the third scanning signal S3 to write the second initialization voltage into the first electrode of the first light-emitting device OLED1, thereby initializing the first electrode of the first light-emitting device OLED1 and avoiding the influence of the residual charge of the previous frame on the current frame.

[0120] In the light emitting stage, the sixth transistor T6 and the seventh transistor T7 are turned on in response to the signal on the light emitting control signal line EM, so that the driving current generated by the first driving transistor T0 according to the data voltage is transmitted to the first light emitting device OLED1, driving the first light emitting device OLED1 to emit light.

[0121] In the data writing and threshold compensation stage of the first pixel circuit of the above 9T1C, the data voltage is written into the first driving transistor T0 via the third transistor T3 and the first transistor T1. In the light emitting stage, the driving current is transmitted to the first light emitting device OLED1 via the second transistor T2 and the first driving transistor T0. The channel length of the first driving transistor T0 is extended by the first transistor T1 and the second transistor T2, so that the grayscale expansion effect is good during display.

[0122] Fig. 9 A schematic diagram of the structure of another first pixel circuit provided by an embodiment of the present invention, Fig.10 A schematic plan view of an active layer, a first conductive layer, and a second conductive layer in another array substrate provided in an embodiment of the present invention. Fig. 9 and Fig.10 Optionally, the array substrate further includes a third scan line S3, a second initialization signal line Vref2 and a third initialization signal line Vref3, the third scan line S3 is located in the first conductive layer 12, the second initialization signal line Vref2 is located in the second conductive layer 13, the third initialization signal line Vref3 is located in the third conductive layer 14, and the first pixel circuit further includes an eighth transistor T8 and a ninth transistor T9;

[0123] The first electrode of the eighth transistor T8 is connected to the second initialization signal line Vref2 through the third connection line L3 located in the third conductive layer 14. Specifically, the first electrode of the eighth transistor T8 is connected to one end of the third connection line L3 through a via hole penetrating from the third conductive layer 14 to the active layer 11, and the other end of the third connection line L3 is connected to the second initialization signal line Vref2 through a via hole penetrating from the third conductive layer 14 to the second conductive layer 13, thereby realizing the connection between the first electrode of the eighth transistor T8 and the second initialization signal line Vref2. The second electrode of the eighth transistor T8 is connected to the second electrode of the seventh transistor T7, and the positive projection of the third scan line S3 on the substrate 10 covers the positive projection of the channel region of the eighth transistor T8 on the substrate 10; wherein, the part of the positive projection of the third scan line S3 on the substrate 10 covering the positive projection of the channel region of the eighth transistor T8 on the substrate 10 serves as the gate of the eighth transistor T8.

[0124] The first electrode of the ninth transistor T9 is connected to the third initialization signal line Vref3 through a via hole penetrating from the third conductive layer 14 to the active layer 11, the second electrode of the ninth transistor T9 is connected to the first electrode of the second transistor T2 through the fourth connection line L4 located on the third conductive layer 14, and the positive projection of the third scan line S3 on the substrate 10 covers the positive projection of the channel region of the ninth transistor T9 on the substrate 10; wherein, the portion of the positive projection of the third scan line S3 on the substrate 10 covering the positive projection of the channel region of the ninth transistor T9 on the substrate 10 serves as the gate of the ninth transistor T9. The ninth transistor T9 is used to transmit the third initialization voltage to the first electrode of the second transistor T1 in response to the signal on the third scan line S3, so as to initialize the second transistor T2 and the first driving transistor T0.

[0125] Optionally, the third scan line S3, the second initialization signal line Vref2 and the third initialization signal line Vref3 all extend along the first direction X, the orthographic projection of the third scan line S3 on the substrate 10 is located on a side where the orthographic projection of the light-emitting control signal line EM on the substrate is away from the orthographic projection of the first gate portion 121 on the substrate 10, and the projection of the second initialization signal line Vref2 on the substrate 10 is located on a side where the orthographic projection of the third scan line S3 on the substrate 10 is away from the orthographic projection of the first gate portion 121 on the substrate 10.

[0126] Optionally, the orthographic projection of the third initialization signal line Vref3 on the substrate 10 at least partially overlaps with the orthographic projection of the third scan line S3 on the substrate 10. In an optional embodiment, the orthographic projection of the third scan line S3 on the substrate 10 covers the orthographic projection of the third initialization signal line Vref3 on the substrate 10 to save layout area.

[0127] Whether Fig.10 The plan view shown is Figure 6 As shown in the plan schematic diagram, the channel region of the first transistor T1, the channel region of the second transistor T2, the channel region of the third transistor T3, the channel region of the first sub-transistor T4_1, the channel region of the fifth transistor T5, the channel region of the sixth transistor T6, the channel region of the seventh transistor T7 and the channel region of the eighth transistor T8 all extend along the second direction Y, and the channel region of the first driving transistor T0 and the channel region of the second sub-transistor T4_2 all extend along the first direction X. Fig.10 The channel region of the ninth transistor T9 also extends along the second direction Y.

[0128] Fig.11 A schematic plan view of a single pixel in an array substrate provided by an embodiment of the present invention, Fig.12 A schematic diagram of the structure of a second pixel circuit in an array substrate provided by an embodiment of the present invention is provided. Based on the above embodiment, Fig.11 and Fig.12 Optionally, the active layer and the multi-layer conductive layer further constitute at least one second pixel circuit 8;

[0129] The multi-layer conductive layer further includes a fourth conductive layer 15, which is located on a side of the first conductive layer 12 away from the substrate 10, and the array substrate includes a light emitting control signal line EM and a first power line VDD, the light emitting control signal line EM is located on the first conductive layer 12, and the first power line VDD is located on the fourth conductive layer 15;

[0130] The second pixel circuit 8 includes a second driving transistor T01, a tenth transistor T10, an eleventh transistor T11 and a second light emitting device OLED2, a first electrode of the tenth transistor T10 is connected to the first power line VDD through a via hole, a second electrode of the tenth transistor T10 is connected to the first electrode of the second driving transistor T01, a second electrode of the second driving transistor T01 is connected to the first electrode of the eleventh transistor T11, a second electrode of the eleventh transistor T11 is connected to the second light emitting device OLED2, an orthographic projection of the light emitting control signal line EM on the substrate covers an orthographic projection of the channel region of the tenth transistor T10 on the substrate, and an orthographic projection of the light emitting control signal line EM on the substrate covers an orthographic projection of the channel region of the eleventh transistor T11 on the substrate;

[0131] The active layer includes a second gate portion 122 corresponding one-to-one to the second pixel circuit 8, and the channel region of the second driving transistor T01 is located at the orthographic projection of the second gate portion 122 on the active layer. The orthographic projection of the second gate portion 122 on the substrate has no overlap with the orthographic projection of the first electrode and the second electrode of the second driving transistor T01 on the substrate, and the area of ​​the orthographic projection of the second gate portion 122 on the substrate is smaller than the area of ​​the orthographic projection of the first gate portion 121 on the substrate.

[0132] The difference between the second pixel circuit 8 and the first pixel circuit 7 is that the second pixel circuit does not include the first transistor and the second transistor for extending the channel length of the driving transistor, and the second pixel circuit is a 7T1C pixel circuit or an 8T1C pixel circuit. The second pixel circuit 8 also includes a twelfth transistor T12 connected between the data line Data and the first electrode of the second driving transistor T01, a thirteenth transistor T13 connected between the second electrode and the gate of the second driving transistor T01, a fourteenth transistor T14 connected between the first initialization signal line Vref1 and the gate of the second driving transistor T01, a fifteenth transistor T15 connected between the second initialization signal line Vref2 and the second light-emitting device OLED2, and a sixteenth transistor T16 connected between the third initialization signal line Vref3 and the first electrode of the second driving transistor T01. Except for the second driving transistor T01, the structures of the remaining transistors in the second pixel circuit 8 are the same as those of the transistors at the corresponding positions in the first pixel circuit 7, and are not repeated here.

[0133] The array substrate includes a plurality of pixels, each pixel includes at least two pixel circuits of a first pixel circuit and / or a second pixel circuit, at least two pixel circuits belonging to the same pixel include at least one first pixel circuit and at least one second pixel circuit, the pixel circuits belonging to the same pixel include light-emitting devices of different light-emitting colors, the types of pixel circuits connected to light-emitting devices of the same color are the same, the types and quantities of pixel circuits connected to light-emitting devices of the same color are the same, such as the pixel circuits connected to red light-emitting devices are all 10T1C circuits in the first pixel circuit, the pixel circuits connected to green light-emitting devices are all 8T1C circuits in the second pixel circuit, and the pixel circuits connected to blue light-emitting devices are all 10T1C circuits in the first pixel circuit. In an optional embodiment, the array substrate includes light-emitting devices of three light-emitting colors, namely, red light-emitting devices, green light-emitting devices, and blue light-emitting devices, wherein the pixel circuit where the red light-emitting device is located and the pixel circuit where the green light-emitting device is located constitute a pixel, which is recorded as a first type pixel, the pixel circuit where the green light-emitting device is located and the pixel circuit where the blue light-emitting device is located constitute a pixel, which is recorded as a second type pixel, and a plurality of first type pixels and a plurality of second type pixels are arranged in an array. In this embodiment, a pixel includes a first pixel circuit 7 and a second pixel circuit 8, wherein the first pixel circuit 7 can be Fig.11 The 10T1C pixel circuit shown in FIG. 8 is a second pixel circuit 8. Fig.11 The 8T1C pixel circuit shown in the figure, or in other embodiments, the first pixel circuit 7 may also be Figure 5 The 9T1C pixel circuit shown in the figure, the second pixel circuit 8 can also be a 7T1C pixel circuit, that is, Fig.12 The circuit is based on removing the fifteenth transistor T15. Fig.13 A schematic plan view of another pixel in an array substrate provided by an embodiment of the present invention, in another optional implementation manner, each pixel circuit belonging to the same pixel is a first pixel circuit 7. The first pixel circuit 7 may be Fig.13 The 10T1C pixel circuit shown can also be Figure 6 The 9T1C pixel circuit shown. Different colors of light emitting devices have different luminous materials, and the ratio of the three colors when forming white light is also different. Therefore, it is possible to choose whether to use 10T1C or 9T1C for the pixel circuit according to needs, or to choose a first pixel circuit of 10T1C or 9T1C and a second pixel circuit of 8T1C or 7T1C.

[0134] An embodiment of the present invention further provides a display panel, comprising the array substrate in any of the above embodiments, and the beneficial effects of the display panel are the same as those of the array substrate, which will not be described in detail herein.

[0135] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0136] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer, disposed on one side of the substrate; A multi-layer conductive layer stacked on a side of the active layer away from the substrate, the multi-layer conductive layer comprising a first conductive layer, the first conductive layer comprising a first gate portion, and the first gate portion is an integrated structure; The active layer and the multi-layer conductive layer constitute at least one first pixel circuit, wherein the first pixel circuit includes a first driving transistor and at least one auxiliary driving transistor; The channel regions of the first driving transistor and the at least one auxiliary driving transistor are both located in the active layer, and the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the channel region of the first driving transistor on the substrate and the orthographic projection of the at least one auxiliary driving transistor on the substrate.

2. The array substrate according to claim 1, characterized in that: The first pixel circuit includes two auxiliary driving transistors, namely a first transistor and a second transistor, and a channel region of the first driving transistor, a channel region of the first transistor, and a channel region of the second transistor are connected to each other; The first electrode of the first driving transistor, the second electrode of the first transistor, and the second electrode of the second transistor are connected to each other; Preferably, the channel region of the first driving transistor extends along a first direction, the channel region of the first transistor and the channel region of the second transistor both extend along a second direction, and the first direction intersects with the second direction; Preferably, the first electrode, the channel region, and the second electrode of the first transistor are arranged along the second direction, and the second electrode, the channel region, and the first electrode of the second transistor are arranged along the second direction; Preferably, the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the second electrode of the second transistor on the substrate.

3. The array substrate according to claim 2, characterized in that: The first gate portion includes a first sub-portion and a second sub-portion arranged along the first direction, and the first sub-portion and the second sub-portion are connected; The orthographic projection of the first sub-portion on the substrate covers the orthographic projections of the channel region of the first driving transistor, the channel region of the first transistor, and the channel region of the second transistor on the substrate, and the orthographic projection of the second sub-portion on the substrate does not overlap with the orthographic projections of the channel region of the first driving transistor, the channel region of the first transistor, and the channel region of the second transistor on the substrate; Preferably, the length of the orthographic projection of the second sub-portion on the substrate along the first direction is greater than or equal to 1 micron.

4. The array substrate according to claim 2, characterized in that: The multi-layer conductive layer further includes a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, the first pixel circuit further includes a storage capacitor, the first gate portion is reused as a first plate of the storage capacitor, and the second plate of the storage capacitor is located on the second conductive layer; Preferably, the multi-layer conductive layer further includes a third conductive layer and a fourth conductive layer, the third conductive layer is located on a side of the second conductive layer away from the substrate, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the first pixel circuit further includes a third transistor; The array substrate further includes a data line, the data line is located in the fourth conductive layer, the first electrode of the third transistor is connected to the data line through a via hole, and the second electrode of the third transistor is connected to the first electrode of the first transistor; The array substrate further includes a first scanning line, the first scanning line is located in the first conductive layer, the first scanning line includes a first scanning sub-portion extending along the first direction, and the orthographic projection of the first scanning sub-portion on the substrate covers the orthographic projection of the channel region of the third transistor on the substrate; Preferably, the data line extends along the second direction; Preferably, the first pixel circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to a second electrode of the first driving transistor, and a second electrode of the fourth transistor is connected to the first gate portion via a first connecting line located in the third conductive layer; The first scanning line further includes a second scanning sub-portion extending along the second direction, the first scanning sub-portion is connected to the second scanning sub-portion, and an orthographic projection of the first scanning sub-portion on the substrate and an orthographic projection of the second scanning sub-portion on the substrate both at least partially overlap with an orthographic projection of the channel region of the fourth transistor on the substrate; Preferably, the channel region of the fourth transistor includes a first channel sub-region extending along the second direction and a second channel sub-region extending along the first direction, the first channel sub-region and the second channel sub-region are connected, an orthographic projection of the first scanning sub-portion on the substrate covers an orthographic projection of the first channel sub-region on the substrate, and an orthographic projection of the second scanning sub-portion on the substrate covers an orthographic projection of the second channel sub-region on the substrate; Preferably, the first connecting line extends along the second direction.

5. The array substrate according to claim 4, characterized in that: The array substrate further includes a second scan line and a first initialization signal line, the second scan line is located in the first conductive layer, the first initialization signal line is located in the second conductive layer, and the first pixel circuit further includes a fifth transistor; A first electrode of the fifth transistor is connected to the first initialization signal line via a second connection line located in the third conductive layer, a second electrode of the fifth transistor is connected to a second electrode of the fourth transistor, and an orthographic projection of the second scanning line on the substrate covers and overlaps an orthographic projection of a channel region of the fifth transistor on the substrate; Preferably, the channel region of the fifth transistor includes a third channel sub-region and a fourth channel sub-region both extending along the second direction, the active layer further includes a second active connection portion, the third channel sub-region is connected to one end of the second active connection portion, the fourth channel sub-region is connected to the other end of the second active connection portion, and the orthographic projection of the second scan line on the substrate covers the orthographic projection of the third channel sub-region on the substrate, and the orthographic projection of the second scan line on the substrate covers the orthographic projection of the fourth channel sub-region on the substrate; Preferably, the second scan line and the first initialization signal line both extend along the first direction, the first scan line, the second scan line and the first initialization signal line are arranged along the second direction, and the orthographic projection of the first scan line on the substrate, the orthographic projection of the second scan line on the substrate and the orthographic projection of the first initialization signal line on the substrate are all located on the same side of the first gate portion, the orthographic projection of the second scan line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the first scan line on the substrate, and the orthographic projection of the first initialization signal line on the substrate is located on a side of the orthographic projection of the second scan line on the substrate away from the first gate portion; Preferably, the second connecting line extends along the second direction.

6. The array substrate according to claim 4, characterized in that: The array substrate further includes a light emitting control signal line and a first power line, the light emitting control signal line is located in the first conductive layer, the first power line is located in the fourth conductive layer, and the first pixel circuit further includes a sixth transistor, a seventh transistor and a first light emitting device; The first electrode of the sixth transistor is connected to the first power line through a via hole, the second electrode of the sixth transistor is connected to the first electrode of the second transistor, and the orthographic projection of the light emitting control signal line on the substrate covers the orthographic projection of the channel region of the sixth transistor on the substrate; The first electrode of the seventh transistor is connected to the second electrode of the first driving transistor, the second electrode of the seventh transistor is connected to the first light-emitting device, and the orthographic projection of the light-emitting control signal line on the substrate covers the orthographic projection of the channel region of the seventh transistor on the substrate; Preferably, the light emitting control signal line extends along the first direction, and an orthographic projection of the light emitting control signal line on the substrate is located on a side where an orthographic projection of the first gate portion on the substrate is away from an orthographic projection of the first scanning line on the substrate; Preferably, the first power line extends along the second direction.

7. The array substrate according to claim 6, characterized in that: The array substrate further includes a third scan line, a second initialization signal line and a third initialization signal line, the third scan line is located in the first conductive layer, the second initialization signal line is located in the second conductive layer, the third initialization signal line is located in the third conductive layer, and the first pixel circuit further includes an eighth transistor and a ninth transistor; A first electrode of the eighth transistor is connected to the second initialization signal line via a third connection line located in the third conductive layer, a second electrode of the eighth transistor is connected to a second electrode of the seventh transistor, and an orthographic projection of the third scanning line on the substrate covers an orthographic projection of a channel region of the eighth transistor on the substrate; A first electrode of the ninth transistor is connected to the third initialization signal line through a via hole, a second electrode of the ninth transistor is connected to the first electrode of the second transistor through a fourth connection line located on the third conductive layer, and an orthographic projection of a channel region of the ninth transistor on the substrate overlaps with an orthographic projection of the third scan line on the substrate; Preferably, the third scan line, the second initialization signal line and the third initialization signal line all extend along the first direction, the orthographic projection of the third scan line on the substrate is located on a side where the orthographic projection of the light emitting control signal line on the substrate is away from the orthographic projection of the first gate portion on the substrate, and the projection of the second initialization signal line on the substrate is located on a side where the orthographic projection of the third scan line on the substrate is away from the orthographic projection of the first gate portion on the substrate; Preferably, an orthographic projection of the third initialization signal line on the substrate at least partially overlaps with an orthographic projection of the third scanning line on the substrate.

8. The array substrate according to claim 6, characterized in that: The array substrate further includes a third scan line and a second initialization signal line, the third scan line is located in the first conductive layer, the second initialization signal line is located in the third conductive layer, and the first pixel circuit further includes an eighth transistor; A first electrode of the eighth transistor is connected to the second initialization signal line through a via hole, a second electrode of the eighth transistor is connected to the second electrode of the seventh transistor, and an orthographic projection of the third scan line on the substrate covers an orthographic projection of a channel region of the eighth transistor on the substrate; Preferably, the third scan line and the second initialization signal line both extend along the first direction, and the orthographic projection of the third scan line on the substrate is located on a side where the orthographic projection of the light emitting control signal line on the substrate is away from the orthographic projection of the first gate portion on the substrate; Preferably, an orthographic projection of the second initialization signal line on the substrate at least partially overlaps with an orthographic projection of the third scanning line on the substrate.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The active layer and the multi-layer conductive layer also form at least one second pixel circuit; The multi-layer conductive layer further includes a fourth conductive layer, the fourth conductive layer is located on a side of the first conductive layer away from the substrate, the array substrate includes a light emitting control signal line and a first power line, the light emitting control signal line is located in the first conductive layer, and the first power line is located in the fourth conductive layer; The second pixel circuit includes a second driving transistor, a tenth transistor, an eleventh transistor and a second light-emitting device, the first electrode of the tenth transistor is connected to the first power line through a via hole, the second electrode of the tenth transistor is connected to the first electrode of the second driving transistor, the second electrode of the second driving transistor is connected to the first electrode of the eleventh transistor, the second electrode of the eleventh transistor is connected to the second light-emitting device, the orthographic projection of the light-emitting control signal line on the substrate covers the orthographic projection of the channel region of the tenth transistor on the substrate, and the orthographic projection of the light-emitting control signal line on the substrate covers the orthographic projection of the channel region of the eleventh transistor on the substrate; The active layer includes a second gate portion corresponding to each second pixel circuit one by one, a channel region of the second driving transistor is located at an orthographic projection of the second gate portion on the active layer, an orthographic projection of the second gate portion on the substrate does not overlap with an orthographic projection of a first electrode and a second electrode of the second driving transistor on the substrate, and an orthographic projection of the second gate portion on the substrate is smaller than an orthographic projection of the first gate portion on the substrate; The array substrate includes multiple pixels, each pixel includes at least two pixel circuits of a first pixel circuit and / or a second pixel circuit, the pixel circuits belonging to the same pixel include light-emitting devices with different luminous colors, each pixel circuit belonging to the same pixel is a first pixel circuit, or at least two pixel circuits belonging to the same pixel include at least one first pixel circuit and at least one second pixel circuit, and the types of pixel circuits connected to light-emitting devices of the same color are the same.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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