Display substrate, preparation method thereof and display panel

Abstract

The invention provides a display substrate, belongs to the technical field of display, and can solve the problem that the light utilization rate of the display substrate is low. The display substrate comprises a substrate body and a plurality of pixel units arranged on the substrate body. Each pixel unit comprises a pixel driving circuit and a light-emitting device connected with the pixel driving circuit; wherein a planarization layer is arranged on the side, away from the substrate, of the pixel driving circuit, the planarization layer is provided with a plurality of first grooves, and the first electrode of one light-emitting device covers the first grooves; a pixel limiting layer is arranged on one side, deviating from the substrate, of the layer where the first electrode of each light-emitting device is located; the pixel defining layer is provided with a plurality of pixel openings; the orthographic projection of one pixel opening on the substrate is located in the limited range of the orthographic projection of one first groove on the substrate.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a preparation method thereof, and a display panel. Background Art

[0002] Organic Light-Emitting Display (OLED) has the advantages of self-luminescence, fast response, wide viewing angle, high brightness, bright colors, and thinness compared to liquid crystal display devices, and is considered to be the next generation of display technology. The self-luminous element, namely the OLED device, is mainly composed of an anode layer, an organic material functional layer (usually including an electron transport layer, a light-emitting layer, and a hole transport layer) and a cathode layer, which are arranged away from the substrate in sequence. However, existing OLED devices have the problem of low light utilization. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, comprising a base substrate, and a plurality of pixel units arranged on the base substrate; the pixel unit comprises a pixel driving circuit and a light emitting device connected to the pixel driving circuit; wherein,

[0004] A planarization layer is provided on a side of the pixel driving circuit away from the base substrate, and the planarization layer has a plurality of first grooves, and a first electrode of the light-emitting device covers the first groove; the first electrode of the light-emitting device is provided on a side of the planarization layer away from the base substrate, and a first electrode of the light-emitting device covers the bottom and sidewall of the first groove;

[0005] A pixel defining layer is arranged on the side of the layer where the first electrode of each light-emitting device is located away from the base substrate; the pixel defining layer has a plurality of pixel openings; the orthographic projection of one of the pixel openings on the base substrate is located within the limited range of the orthographic projection of one of the first grooves on the base substrate.

[0006] In some embodiments, the light-emitting layer of the light-emitting device is arranged on the side of the first electrode away from the base substrate, and the light-emitting layer is located at the pixel opening; the shape of the orthographic projection of the light-emitting layer and the pixel opening on the base substrate is different.

[0007] In some embodiments, the distances between the light emitting layer and the sidewalls of the first groove are different at least at some positions.

[0008] In some embodiments, the pixel defining layer includes a pixel blocking wall defining the plurality of pixel openings; the first electrode includes a first sub-electrode and a second sub-electrode electrically connected; the first sub-electrode covers the bottom of the first groove, and the second sub-electrode at least covers the sidewall of the first groove;

[0009] The orthographic projection of the pixel blocking wall on the base substrate covers the orthographic projection of the second sub-electrode on the base substrate, and at least partially overlaps with the orthographic projection of the first sub-electrode on the base substrate.

[0010] In some embodiments, the planarization layer includes a first sub-planarization layer and a second sub-planarization layer stacked in a direction away from the substrate;

[0011] The surface of the first sub-planarization layer facing away from the base substrate is a first surface; the second sub-planarization layer includes a plurality of flat portions; and the side walls of four adjacent flat portions and the first surface together define the first groove.

[0012] In some embodiments, a dihedral angle formed by a sidewall of the flat portion and the first surface is θ, and 20°≤θ≤80°.

[0013] In some embodiments, the pixel defining layer contacts at least a portion of the first electrode; a maximum distance between an orthographic projection of the pixel defining layer on the first surface and an orthographic projection of the flat portion on the first surface is w, 0um<w≤3um.

[0014] In some embodiments, the display substrate further includes an interlayer insulating layer disposed between the layer where the pixel driving circuit is located and the first sub-planarization layer, and a first conductive layer disposed between the interlayer insulating layer and the first sub-planarization layer;

[0015] The first conductive layer includes a first transfer electrode; the pixel driving circuit includes at least a driving thin film transistor; the first transfer electrode is connected to the drain of the driving thin film transistor through a first via hole penetrating the interlayer insulating layer; the first electrode is connected to the first transfer electrode through a second via hole penetrating the flat portion and the first sub-planarization layer in sequence.

[0016] In some embodiments, the first conductive layer further includes an auxiliary electrode; the orthographic projection of the auxiliary electrode on the base substrate is located within a limited range of the orthographic projection of the light emitting layer on the base substrate.

[0017] In some embodiments, it also includes a supporting layer arranged on the side of the pixel defining layer away from the base substrate; the orthographic projection of the supporting layer on the base substrate is located within the limited range of the orthographic projection of the pixel defining layer on the base substrate.

[0018] In some embodiments, the plurality of pixel units include a first color pixel unit, a second color pixel unit, and a third color pixel unit having different luminous colors;

[0019] The plurality of pixel units are divided into a first pixel group and a second pixel group arranged alternately along a first direction, and two adjacent second pixel groups are staggered; the plurality of pixel units are divided into a third pixel group and a fourth pixel group arranged alternately along a second direction, and two adjacent fourth pixel groups are staggered; the first direction intersects with the second direction;

[0020] The first pixel group includes a plurality of first color pixel units arranged at intervals along the second direction; the second pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the second direction; the third pixel group includes a plurality of first color pixel units arranged at intervals along the first direction; the fourth pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the first direction.

[0021] In some embodiments, a spacing between two adjacent first color pixel units in the first pixel group, a spacing between adjacent second color pixel units and the third color pixel unit in the second pixel group, a spacing between two adjacent first color pixel units in the third pixel group, and a spacing between adjacent second color pixel units and the third color pixel unit in the fourth pixel group are all equal.

[0022] In some embodiments, the sizes of the first color pixel unit, the second color pixel unit, and the third color pixel unit are all 2um to 60nm;

[0023] The distance between the first color pixel unit and the first color pixel unit closest to it is 5um~30nm; the distance between the first color pixel unit and the third color pixel unit closest to it is 5um~30nm; the distance between the second color pixel unit and the third color pixel unit closest to it is 5um~30nm.

[0024] In some embodiments, the orthographic projection of the first groove on the base substrate includes any one of a square, a rectangle, a circle, a triangle, and an irregular shape; the orthographic projection of the light-emitting layer on the base substrate includes any one of a square, a rectangle, a circle, a triangle, and an irregular shape.

[0025] The present disclosure also provides a method for preparing the above-mentioned display substrate, comprising:

[0026] Providing a base substrate, on which a plurality of pixel driving circuits are formed;

[0027] Forming a planarization layer on a side of the layer where the pixel driving circuit is located away from the base substrate, and forming a plurality of first grooves on the planarization layer;

[0028] A plurality of first electrodes of light-emitting devices are formed on a side of the planarization layer away from the base substrate; the first electrode of one of the light-emitting devices covers the bottom and sidewall of the first groove;

[0029] A pixel defining layer is formed on the side of the layer where the first electrode of each light-emitting device is located away from the base substrate; the pixel defining layer has a plurality of pixel openings; the orthographic projection of one of the pixel openings on the base substrate is located within the limited range of the orthographic projection of one of the first grooves on the base substrate.

[0030] The present disclosure also provides a display panel, comprising the display substrate in the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of the structure of an existing display substrate;

[0032] Figure 2 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0033] Figure 3 A schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure;

[0034] Figure 4 A schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure;

[0035] Figure 5 A graph showing the relationship between the dihedral angle θ and the light intensity on the light-emitting side of the display substrate provided in an embodiment of the present disclosure;

[0036] Figure 6 A schematic diagram of a partial structure of an actual display substrate provided in an embodiment of the present disclosure;

[0037] Figure 7A schematic diagram of a partial structure of another actual display substrate provided in an embodiment of the present disclosure;

[0038] Figure 8 A top view of a first groove and a light-emitting layer provided in an embodiment of the present disclosure;

[0039] Fig. 9 A schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure;

[0040] Fig.10 A schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure;

[0041] Fig.11 A schematic diagram of an arrangement of pixel units in a display substrate provided by the present disclosure;

[0042] Fig.12a A schematic diagram of the structure of an intermediate product in step S1 in the process of preparing a display substrate provided in an embodiment of the present disclosure;

[0043] Figure 12b A schematic diagram of the structure of an intermediate product in step S2 in the process of preparing a display substrate provided in an embodiment of the present disclosure;

[0044] Fig.12c A schematic diagram of the structure of an intermediate product in step S3 in the process of preparing a display substrate provided in an embodiment of the present disclosure;

[0045] Fig.12d A schematic diagram of the structure of an intermediate product in step S4 in the process of preparing a display substrate provided in an embodiment of the present disclosure;

[0046] Fig.12e A schematic diagram of the structure of an intermediate product in step S5 in the process of preparing a display substrate provided by an embodiment of the present disclosure;

[0047] Fig.12f A schematic diagram of the structure of an intermediate product in step S6 in the process of preparing a display substrate provided in an embodiment of the present disclosure;

[0048] Figure 12g A schematic diagram of the structure of an intermediate product in step S7 in the process of preparing a display substrate provided by an embodiment of the present disclosure;

[0049] Figure 12h A schematic diagram of the structure of an intermediate product in step S8 in the process of preparing a display substrate provided by an embodiment of the present disclosure;

[0050] Fig.12i This is a schematic diagram of the structure of an intermediate product in step S9 in the process of preparing a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0052] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0053] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0054] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate. Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0055] In the related art, refer to Figure 1 In order to achieve surface flattening of the device, the planarization layer PLN of the display substrate completely covers the driving circuit layer DL below including multiple driving circuits PC, and the thickness of the planarization layer PLN at each position is equal. The anode Anode of the light-emitting device is arranged above the planarization layer PLN, the pixel defining layer PDL is arranged above the layer where the anode Anode is located, and the pixel opening in the pixel defining layer PDL enables at least part of the anode Anode to contact the light-emitting layer EL of the light-emitting device to drive the light-emitting device to emit light. However, the light emitted by the light-emitting device is directed in all directions, among which the light emitted to the left and right sides will be transmitted laterally along the light-emitting layer EL, and cannot be reflected to the light-emitting side of the display substrate to be effectively utilized, resulting in a reduction in the utilization rate of the light.

[0056] Based on the above problems, the present disclosure provides a display substrate, referring to Figure 2 , which includes a substrate SUB, and a plurality of pixel units arranged on the substrate SUB, each pixel unit includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. Among them, the light-emitting device includes but is not limited to an organic light-emitting diode OLED (Organic Light-Emitting Diode). The organic light-emitting diode includes a first electrode, a light-emitting layer EL and a second electrode stacked in sequence in a direction away from the substrate SUB, the first electrode can be an anode Anode, and the second electrode can be a cathode Cathode. The pixel driving circuit at least includes a driving thin film transistor TFT Td, and the drain D of the thin film transistor TFT Td is electrically connected to the anode Anode of the light-emitting device. After applying a driving voltage to the anode Anode through the pixel driving circuit, the light-emitting layer EL can emit light. The pixel driving circuit can adopt a pixel driving circuit such as 2T1C, 7T1C, etc.

[0057] Specifically, refer to Figure 2-Figure 4The display substrate includes a base substrate SUB, and a driving circuit layer DL (specifically including Figure 2 The planarization layer includes a driving thin film transistor TFTTd, a storage capacitor Cst, a first gate insulating layer G11 and a second gate insulating layer G12), a planarization layer, a first electrode layer and a pixel defining layer PDL. Among them, the driving circuit layer DL includes a pixel driving circuit of each pixel unit. The planarization layer has a plurality of first grooves GRV, and each first groove GRV is arranged corresponding to a pixel unit. The first electrode layer includes an anode Anode of a light-emitting device in each pixel unit, and the anode Anode covers the first groove GRV. It should be noted that the first groove GRV includes a side wall and a bottom, and the anode Anode includes an electrically connected first sub-electrode 31 and a second sub-electrode 32, wherein the first sub-electrode 31 covers the bottom of the first groove GRV, and the second sub-electrode 32 at least covers the side wall of the first groove GRV. The pixel defining layer PDL has a plurality of pixel openings OP, and a pixel barrier DQ that defines a plurality of pixel openings OP. Among them, the pixel opening OP is used to set the light-emitting layer EL of the light-emitting device. In some embodiments, the orthographic projection of the pixel retaining wall DQ on the substrate SUB covers the orthographic projection of the second sub-electrode 32 on the substrate SUB, and the orthographic projection of the pixel retaining wall DQ on the substrate SUB at least partially overlaps with the orthographic projection of the first sub-electrode 31 on the substrate SUB. At this time, the orthographic projection of a pixel opening OP on the substrate SUB is located within the limited range of the orthographic projection of a first groove GRV on the substrate SUB. In this case, the light-emitting layer EL located in the pixel opening OP is also located in the first groove GRV, and the anode Anode on the side wall of the first groove GRV can be used as a reflector to reflect the light emitted from the light-emitting layer EL to the left and right sides, and finally make most of the light emitted by the light-emitting layer EL emerge from the light-emitting side of the display substrate, effectively improving the light utilization rate.

[0058] Further, see Figure 2 and Figure 3, the first planarization layer includes a stacked first sub-planarization layer PLN1 and a second sub-planarization layer PLN2, and the first sub-planarization layer PLN1 is closer to the base substrate SUB than the second sub-planarization layer PLN2. Among them, the thickness of the first sub-planarization layer PLN1 is equal everywhere, and the second sub-planarization layer PLN2 includes a plurality of flat portions PLN2-1 that are disconnected. In some examples, the thickness h of the flat portion PLN2-1 ranges from 1um<h≤3um. From the light-emitting side of the display substrate, the extension direction of part of the flat portion PLN2-1 is the row direction, and the extension direction of part of the flat portion PLN2-1 is the column direction. The cross-arranged plurality of flat portions PLN2-1 form a second sub-planarization layer PLN2 with a grid-like structure. The side of the first sub-planarization layer PLN1 that is away from the base substrate SUB is the first surface O1, and the first surface O1 and the side walls of the four adjacent flat portions PLN2-1 together form the first groove GRV. Viewed from the light-emitting side of the display substrate, the four adjacent flat portions PLN2-1 form a "mouth"-shaped structure, which is one of the grids in the grid structure. The area in the middle of the grid is the first groove GRV, which is used to set the light-emitting device.

[0059] In some examples, continue to refer to Figure 2-Figure 4 The dihedral angle formed by the side wall of the flat portion PLN2-1 and the first surface O1 is θ, and the value range of θ is 20°≤θ≤80°. Preferably, θ is 40°~60°, and more preferably, θ is 50°. Figure 5 The relationship between the value of θ and the light intensity on the light-emitting side of the display panel is shown in Figure 1. Figure 5 , under the same power, the light intensity of the traditional display substrate is set to 100% (at this time θ is 0°), when θ is 40°, the light intensity is 104.2%, that is, the light intensity is 1.042 times that of the traditional display substrate; when θ is 50°, the light intensity is 111.1%, that is, the light intensity is 1.111 times that of the traditional display substrate; when θ is 60°, the light intensity is 105.1%, that is, the light intensity is 1.051 times that of the traditional display substrate. Therefore, the display substrate of the present application can make the light emitted by the light-emitting layer EL to the left and right sides be reflected by the anode Anode covered on the side wall of the flat portion PLN2-1 to the light-emitting side of the display panel, effectively improving the light utilization rate.

[0060] The size of the dihedral angle θ depends on the shape of the mask plate used when forming the first groove GRV. It can be understood that in the process of forming the first groove GRV, the mask plate is used to block part of the photoresist so that the blocked part of the photoresist is not exposed to chemical reaction, so that the blocked part of the photoresist is washed away in the subsequent process to form the shape of the first groove GRV. Therefore, the shape of the light shield is the same as the shape of the orthographic projection of the first groove GRV on the substrate SUB. Among them, the shape of the orthographic projection of the first groove GRV on the substrate SUB can include any one of a square, a rectangle, a circle, a triangle, a regular polygon or an irregular figure. Figure 6 and Figure 7 Two partial cross-sectional views of the actual display substrate are provided as examples. Figure 6 When the orthographic projection of the first groove GRV on the substrate SUB is a square, the dihedral angle θ formed is 51.5°. Figure 7 When the orthographic projection of the first groove GRV on the substrate SUB is a circle, the dihedral angle θ formed is 60.4°. Using masks of different shapes can form flat portions PLN2-1 of different morphologies and dihedral angles θ of different angle values.

[0061] In some examples, the shape of the first groove GRV is different from the shape of the orthographic projection of the light emitting layer EL on the substrate SUB. The shape of the orthographic projection of the light emitting layer EL on the substrate SUB may also include any one of a square, a rectangle, a circle, a triangle, a regular polygon or an irregular shape. For example, the shape of the orthographic projection of the first groove GRV on the substrate SUB is a square, and the shape of the orthographic projection of the light emitting layer EL on the substrate SUB is a triangle, such as Figure 8 As shown. For another example, the orthographic projection of the first groove GRV on the substrate SUB is a semicircular shape, and the orthographic projection of the light emitting layer EL on the substrate SUB is a rectangular shape. In this case, the distances between the sidewalls of the first groove GRV and the light emitting layer EL at least in some positions are not equal. For example, when the orthographic projection of the first groove GRV on the substrate SUB is a square shape, and the orthographic projection of the light emitting layer EL on the substrate SUB is a circle, refer to Figure 8 , the distance between the side wall of the first groove GRV and the light-emitting layer EL first decreases monotonically and then increases monotonically along the column direction. This arrangement is to ensure that light from different emission positions of the light-emitting layer EL can be reflected to the light-emitting side by the anode Anode on the side wall, and that the distance between the side wall of the first groove GRV and the light-emitting layer EL at at least some positions is different to avoid excessive local light intensity, thereby improving light uniformity.

[0062] In some examples, the pixel defining layer PDL not only covers the orthographic projection of the second sub-electrode 32 on the base substrate SUB, but also at least partially overlaps with the orthographic projection of the first sub-electrode 31 on the base substrate SUB. Figure 2 and Figure 3 , at this time, there is a certain preset distance between the light emitting layer EL disposed in the pixel opening OP and the first groove GRV. The preset distance can ensure that the light emitted from the left and right sides of the light emitting layer EL has enough space for reflection, further improving the light utilization rate. Exemplarily, the maximum distance between the orthographic projection of the flat portion PLN2-1 on the first surface O1 and the orthographic projection of the pixel defining layer PDL on the first surface O1 is set to w, and the value range of w is 0um<w≤3um.

[0063] In some examples, the display substrate further includes a support layer disposed on a side of the pixel defining layer PDL away from the base substrate SUB. The support layer includes a plurality of support blocks PS disposed at intervals, and the orthographic projection of the support blocks PS on the base substrate SUB is located within the defined range of the orthographic projection of the flat portion PLN2-1 on the base substrate SUB. The support layer may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx) and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0064] In some examples, the display substrate further includes an encapsulation layer disposed on a side of the support layer away from the base substrate SUB. The encapsulation layer EPL covers the organic light emitting diode and the pixel definition pattern to seal the organic light emitting diode, thereby reducing or preventing degradation of the organic light emitting diode caused by moisture and / or oxygen included in the environment. The encapsulation layer EPL may be a single-layer structure or a multi-layer structure including a stacked structure of an inorganic layer and an organic layer. For example, the encapsulation layer EPL may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer disposed in sequence.

[0065] Next, the specific structure of each film layer between the first sub-planarization layer PLN1 and the base substrate SUB is introduced.

[0066] Take the 2T1C circuit as an example, refer to Fig. 9, the pixel driving circuit PC in the driving circuit layer DL includes a driving thin film transistor (TFT) Td, a switching thin film transistor TFT Ts and a storage capacitor Cst. The switching thin film transistor TFT Ts is connected to the gate line GL and the data line DL, and is configured to transmit a data signal received through the data line DL to the driving thin film transistor TFT Td according to a scan signal received through the gate line GL. The storage capacitor Cst is connected to the switching thin film transistor TFT Ts and the driving voltage line PL, and is configured to store a voltage corresponding to the difference between a voltage received from the switching thin film transistor TFT Ts and a driving voltage ELVDD supplied to the driving voltage line PL. The driving thin film transistor TFT Td is connected to the driving voltage line PL and the storage capacitor Cst, and can be used to control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a desired brightness by the driving current. The organic light emitting diode OLED can emit, for example, red light, green light, blue light or white light. The drain electrode of the driving thin film transistor TFT Td is connected to the anode Anode (ie, the first electrode) of the organic light emitting diode OLED.

[0067] In some examples, reference Fig.10 The driving circuit layer DL may include a semiconductor layer 10, a first gate insulating layer G11, a gate electrode layer G1, a second gate insulating layer G12 and a source-drain conductive layer SD1 which are sequentially arranged in a direction away from the substrate SUB.

[0068] The semiconductor layer 10 includes an active layer of a driving thin film transistor TFT Td and a switching thin film transistor TFT Ts. The active layer may include, for example, an inorganic semiconductor material (eg, polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material.

[0069] The first gate insulating layer GI1 may cover the active layer. For example, the first gate insulating layer GI1 may fully cover the thickness of the active layer. The first gate insulating layer GI1 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The first gate insulating layer GI1 may be formed as a single layer or a multilayer.

[0070] The gate electrode layer G1 includes the gates of the driving thin film transistor TFT Td and the switching thin film transistor TFT Ts, and the first electrode plate of the storage capacitor Cst. The gate electrode layer may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the gate electrode layer may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode may have a single layer or a multilayer.

[0071] The second gate insulating layer GI2 may cover the gate electrode and the first electrode plate of the storage capacitor Cst. The second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second gate insulating layer GI2 may be formed as a single layer or a multilayer.

[0072] The source-drain conductive layer SD1 may include the source and drain electrodes of the driving thin film transistor TFT Td and the switching thin film transistor TFT Ts, and the first electrode plate of the storage capacitor Cst. The source-drain conductive layer SD1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the source-drain conductive layer SD1 may be a single layer or multiple layers composed of metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0073] In some embodiments, continue to refer to Fig.10The display substrate further includes an interlayer insulating layer ILD disposed between the source-drain conductive layer SD1 and the first sub-planarization layer PLN1, and a first conductive layer 20 disposed between the interlayer insulating layers ILD. The first conductive layer 20 includes a first transfer electrode RX, which is connected to the drain of the driving thin film transistor TFT Ts through a first via hole VIA1 penetrating the interlayer insulating layer ILD, and a second sub-electrode 32 is connected to the first transfer electrode RX through a second via hole VIA2 penetrating the flat portion PLN2-1 and the first sub-planarization layer PLN1 in sequence. In this way, the driving thin film transistor TFT Ts and the anode Anode are electrically connected through the first transfer electrode RX.

[0074] In some embodiments, continue to refer to Fig.10 The first conductive layer 20 further includes an auxiliary electrode FX, whose orthographic projection on the base substrate SUB is located within the limited range of the orthographic projection of the light emitting layer EL on the base substrate SUB. The auxiliary electrode FX may be a signal line connected to the source of the driving thin film transistor TFT Ts, such as a driving voltage line PL. The auxiliary electrode FX may also be a signal line connected to the source of the switching thin film transistor TFT Ts, such as a data line DL.

[0075] In some examples, the display substrate further includes a buffer layer BFL (Buffer Layer) disposed between the semiconductor layer and the base substrate SUB. The buffer layer BFL may prevent or reduce diffusion of metal atoms and / or impurities from the base substrate SUB into the semiconductor layer. For example, the buffer layer BFL may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx) and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0076] Fig.11 A top view of a display substrate provided by the present disclosure. The display substrate includes a plurality of pixel units, and the plurality of pixel units include a first color pixel unit, a second color pixel unit, and a third color pixel unit with different luminous colors. Exemplarily, the pixel arrangement of the display substrate of the present disclosure is described below by taking the first color pixel unit as a green pixel unit G, the second color pixel unit as a red pixel unit R, and the third color pixel unit as a blue pixel unit B as an example.

[0077] Reference Fig.11, a first pixel group PG1 and a second pixel group PG2 in which a plurality of pixel units are alternately arranged along a first direction. The first pixel group PG1 includes a plurality of green pixel units G spaced apart along a second direction, the second pixel group PG2 includes a plurality of red pixel units R and blue pixel units B alternately arranged along a second direction, and two adjacent second pixel groups PG2 are staggered. That is to say, the arrangement of the pixel units of the first second pixel group PG2 is blue→red→blue→red→…, the arrangement of the pixel units of the second second pixel group PG2 is red→blue→red→blue…, and so on. This arrangement is to ensure that the blue pixel units B and the red pixel units R are evenly distributed, thereby improving the uniformity of light.

[0078] Continue to refer to Fig.11 , a third pixel group PG3 and a fourth pixel group PG4 in which a plurality of pixel units are alternately arranged along the second direction. The third pixel group PG3 includes a plurality of green pixel units G arranged at intervals in the first direction, the fourth pixel group PG4 includes a plurality of red pixel units R and blue pixel units B arranged alternately along the first direction, and the two adjacent fourth pixel groups PG4 are staggered. That is to say, the arrangement of the pixel units of the first fourth pixel group PG4 is blue→red→blue→red→…, the arrangement of the pixel units of the second fourth pixel group PG4 is red→blue→red→blue…, and so on. Here, the first direction may be a row direction, and the second direction may be a column direction.

[0079] In some examples, the distance between any two adjacent pixel units in the above pixel unit array is equal. That is, the distance between two adjacent green pixel units G in the first pixel group PG1, the distance between two adjacent green pixel units G in the third pixel group PG3, the distance between two adjacent blue pixel units B and red pixel units R in the second pixel group PG2, and the distance between two adjacent blue pixel units B and red pixel units R in the fourth pixel group PG4 are all equal. In this way, the layout of the display substrate can be ensured to be beautiful and neat, and it is conducive to achieving uniform display of the picture. Of course, the distance between the pixel units can be designed differently according to the actual display effect and different display requirements. Among them, the distance between the green pixel unit G and the red pixel unit R closest to it can be 5um~30nm, the distance between the green pixel unit G and the blue pixel unit B closest to it can be 5um~30nm, and the distance between the red pixel unit R and the blue pixel unit B closest to it can be 5um~30nm.

[0080] In some examples, the size of the green pixel unit G, the red pixel unit R, and the blue pixel unit B can all be 2um to 60nm. When the shape of the orthographic projection of the pixel unit on the substrate SUB is a square, the size refers to the side length of the square pixel unit. When the shape of the orthographic projection of the pixel unit on the substrate SUB is a circle, the size refers to the diameter of the circular pixel unit.

[0081] Based on the specific structure of the above display substrate, the present disclosure also provides a method for preparing a display substrate, which includes steps S1 to S9. Figure 12a-12i , the preparation method comprises:

[0082] S1. Provide a substrate SUB, such as Fig.12a shown.

[0083] In some examples, step S1 may specifically include: cleaning the substrate SUB by a standard cleaning process. The cleaning method of the substrate SUB may include: alkaline cleaning, soaking the substrate SUB in a solution containing sodium hydroxide or ammonium hydroxide, the common solution concentration is 5% to 10%, which can clean the organic matter and metal ions on the surface of the substrate SUB; acid cleaning, soaking the substrate SUB in a solution containing hydrofluoric acid or hydrochloric acid, the common solution concentration is 10% to 30%, which can clean the oxide and silica impurities on the surface of the substrate SUB; oxidation cleaning, soaking the substrate SUB in a solution containing potassium hydroxide or hydrogen peroxide, the common solution concentration is 5% to 10%, which can clean the carbon and metal elements on the surface of the substrate SUB; ultrapure water cleaning, soaking or spraying the substrate SUB in ultrapure water, which can clean the tiny particles on the surface of the substrate SUB.

[0084] S2, forming a driving circuit layer DL on the substrate SUB1, the driving circuit layer DL may include a semiconductor layer, a first gate insulating layer G11, a gate electrode layer G1, a second gate insulating layer G12 and a source-drain conductive layer SD1 arranged in sequence in a direction away from the substrate SUB, such as Figure 12b shown.

[0085] The semiconductor layer includes an active layer of a driving thin film transistor TFT Td and a switching thin film transistor TFT Ts. The first gate insulating layer GI1 covers the active layer. The gate electrode layer G1 includes the gates of the driving thin film transistor TFT Td and the switching thin film transistor TFT Ts, and a first electrode plate of the storage capacitor Cst. The second gate insulating layer GI2 covers the gate electrode and the first electrode plate of the storage capacitor Cst. The source-drain conductive layer SD1 may include a source and a drain of the driving thin film transistor TFT Td and the switching thin film transistor TFTTs, and a second electrode plate of the storage capacitor Cst.

[0086] S3, forming an interlayer insulating layer ILD on the side of the source-drain conductive layer SD1 away from the substrate SUB, and forming a first via hole VIA1 penetrating through the interlayer insulating layer ILD, such as Fig.12c shown.

[0087] Specifically, an interlayer insulating layer ILD and a metal layer can be deposited in sequence by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECRCVD), and then the metal layer is patterned to form a pattern including a first transfer electrode RX and an auxiliary electrode FX.

[0088] The step of patterning may include: forming a pattern including a first transfer electrode RX and an auxiliary electrode FX on the metal layer through an etching process. The etching process may be dry etching or wet etching. Dry etching is to expose the surface of the metal layer to the plasma generated in the gaseous state, and the plasma reacts physically or chemically with the metal layer through the window opened in the photoresist, thereby removing the exposed surface material. Dry etching may specifically include: ion milling etching, plasma etching and reactive ion etching. Wet etching is to immerse the metal layer in a certain chemical reagent or reagent solution so that the part of the film surface that is not masked by the resist reacts chemically with the reagent and is removed. Compared with dry etching, wet etching is simple to operate, has low equipment requirements, and is easy to achieve mass production. However, dry etching greatly improves the anisotropic properties of etching and can ensure the accuracy of the pattern.

[0089] S4, forming a planarization layer on the side of the layer where the first transfer electrode RX and the auxiliary electrode FX are located away from the base substrate SUB, such as Fig.12d shown.

[0090] In some examples, the planarization layer includes a stacked first sub-planarization layer PLN1 and a second sub-planarization layer PLN2, the second sub-planarization layer PLN2 includes a plurality of planar portions PLN2-1, and the side walls of the planar portions PLN2-1 form a first groove GRV with the surface of the first sub-planarization layer PLN1 facing away from the substrate SUB.

[0091] In some examples, the first sub-planarization layer PLN1 and the second sub-planarization layer PLN2 can be sequentially deposited by the above-mentioned deposition process, and then the second sub-planarization layer PLN2 can be processed by a photolithography process (photo process) to form a plurality of flat portions PLN2-1. Alternatively, a thicker planarization layer can be deposited by the above-mentioned deposition process, and then a first groove GRV that at least partially penetrates can be formed by a photolithography process (photo process). In other examples, the first sub-planarization layer PLN1 and the second sub-planarization layer PLN2 can be directly formed by a 3D printing process.

[0092] Taking the example of depositing two planarization layers in sequence and then forming a flat portion PLN2-1 through a photolithography process, step S4 may include: forming a first planarization film and a second planarization film in sequence through a deposition process on the side of the layer where the first transfer electrode RX and the auxiliary electrode FX are located away from the substrate SUB, and then coating a layer of photoresist on the second planarization film, exposing it after being shielded by a mask plate to cause a chemical reaction in the unshielded photoresist, and then washing away the unexposed photoresist with a chemical reagent so that the photoresist has a pattern of a first groove GRV, and then etching the second planarization film through the above-mentioned etching process to form a second sub-planarization layer PLN2 having a first groove portion.

[0093] S5, forming a second via hole VIA2 penetrating the flat portion PLN2-1 and the first sub-planarization layer PLN1, so that the drain electrode of the driving thin film transistor TFT Ts is exposed, and forming an anode Anode in the first groove GRV, the anode Anode extending to the second via hole VIA2 and electrically connected to the first transfer electrode RX through the second via hole VIA2, as shown in FIG. Fig.12e shown.

[0094] S6, forming a pixel defining layer PDL on the side of the layer where the first electrode is located away from the substrate SUB. The pixel defining layer PDL has a plurality of pixel openings OP, and the pixel openings OP expose at least a portion of the first electrode located in the first groove GRV. Fig.12f shown.

[0095] In some examples, the pixel definition layer PDL may include an organic material or an inorganic material, specifically, an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride.

[0096] S7, forming an organic functional layer on the side of the first electrode away from the substrate SUB, the organic functional layer may include a light emitting layer EL, such as Figure 12g shown.

[0097] In some examples, the light-emitting layer EL may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent luminescent material or a phosphorescent luminescent material, may emit red light, green light, blue light, or may emit white light. Further, as required, the organic functional layer may also include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, etc.

[0098] S8, forming a support layer on the side of the flat portion PLN2-1 away from the substrate SUB, the support layer comprising a plurality of support blocks PS, such as Figure 12h As shown, the orthographic projection of the support block PS on the substrate SUB is located within the limited range of the orthographic projection of the flat portion PLN2-1 on the substrate SUB.

[0099] In some examples, the material of the support layer may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON), and may be formed as a multi-layer or a single-layer.

[0100] S9, forming an encapsulation layer EPL on the side of the support layer away from the substrate SUB, such as Fig.12i shown.

[0101] In some examples, the material of the encapsulation layer EPL may include insulating materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), and polymer resins. Inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx) have high density and can prevent the intrusion of water, oxygen, and the like; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and to relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior.

[0102] The present disclosure also provides a display panel, which includes the display substrate in the above embodiment. The display panel can be used in a display device, which can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or a combination of any electronic device and hardware, which is not limited by the embodiments of the present disclosure.

[0103] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a base substrate, and a plurality of pixel units arranged on the base substrate; the pixel units comprise a pixel driving circuit and a light emitting device connected to the pixel driving circuit; wherein: A planarization layer is provided on a side of the pixel driving circuit away from the base substrate, and the planarization layer has a plurality of first grooves; a first electrode of the light-emitting device is provided on a side of the planarization layer away from the base substrate, and a first electrode of the light-emitting device covers a bottom and a side wall of the first groove; A pixel defining layer is arranged on a side of the layer where the first electrode of each light-emitting device is located away from the base substrate; The pixel defining layer has a plurality of pixel openings; An orthographic projection of the pixel opening on the base substrate is located within a limited range of an orthographic projection of the first groove on the base substrate.

2. The display substrate according to claim 1, wherein: The light-emitting layer of the light-emitting device is arranged on a side of the first electrode away from the base substrate, and the light-emitting layer is located at the pixel opening; the light-emitting layer and the first groove have different shapes of orthographic projection on the base substrate.

3. The display substrate according to claim 2, wherein: The distances between the light emitting layer and the sidewall of the first groove are different at least in some positions.

4. The display substrate according to claim 1, wherein: The pixel defining layer includes a pixel blocking wall defining the plurality of pixel openings; the first electrode includes a first sub-electrode and a second sub-electrode electrically connected; the first sub-electrode covers the bottom of the first groove, and the second sub-electrode at least covers the sidewall of the first groove; The orthographic projection of the pixel blocking wall on the base substrate covers the orthographic projection of the second sub-electrode on the base substrate, and at least partially overlaps with the orthographic projection of the first sub-electrode on the base substrate.

5. The display substrate according to claim 1, wherein: The planarization layer comprises a first sub-planarization layer and a second sub-planarization layer stacked in a direction away from the substrate; The surface of the first sub-planarization layer facing away from the base substrate is a first surface; the second sub-planarization layer includes a plurality of flat portions; and the side walls of four adjacent flat portions and the first surface together define the first groove.

6. The display substrate according to claim 5, wherein: A dihedral angle formed by the side wall of the flat portion and the first surface is θ, and 20°≤θ≤80°.

7. The display substrate according to claim 5, wherein: The pixel defining layer contacts at least a portion of the first electrode; a maximum distance between an orthographic projection of the pixel defining layer on the first surface and an orthographic projection of the flat portion on the first surface is w, 0um<w≤3um.

8. The display substrate according to claim 5, wherein: The display substrate further includes an interlayer insulating layer disposed between the layer where the pixel driving circuit is located and the first sub-planarization layer, and a first conductive layer disposed between the interlayer insulating layer and the first sub-planarization layer; The first conductive layer includes a first switching electrode; The pixel driving circuit includes at least a driving thin film transistor; the first switching electrode is connected to the drain of the driving thin film transistor through a first via hole penetrating the interlayer insulating layer; the first electrode is connected to the first switching electrode through a second via hole penetrating the flat portion and the first sub-planarization layer in sequence.

9. The display substrate according to claim 8, wherein: The first conductive layer further includes an auxiliary electrode; the orthographic projection of the auxiliary electrode on the base substrate is located within a limited range of the orthographic projection of the light emitting layer on the base substrate.

10. The display substrate according to claim 1, wherein: It also includes a supporting layer arranged on the side of the pixel defining layer away from the base substrate; the orthographic projection of the supporting layer on the base substrate is located within a limited range of the orthographic projection of the pixel defining layer on the base substrate.

11. The display substrate according to claim 1, wherein: The plurality of pixel units include a first color pixel unit, a second color pixel unit and a third color pixel unit with different luminous colors; The plurality of pixel units are divided into a first pixel group and a second pixel group arranged alternately along a first direction, and two adjacent second pixel groups are staggered; the plurality of pixel units are divided into a third pixel group and a fourth pixel group arranged alternately along a second direction, and two adjacent fourth pixel groups are staggered; the first direction intersects with the second direction; The first pixel group includes a plurality of first color pixel units arranged at intervals along the second direction; the second pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the second direction; the third pixel group includes a plurality of first color pixel units arranged at intervals along the first direction; the fourth pixel group includes a plurality of second color pixel units and the third color pixel units arranged alternately along the first direction.

12. The display panel according to claim 11, wherein: The spacing between two adjacent first color pixel units in the first pixel group, the spacing between the second color pixel unit and the third color pixel unit adjacent to each other in the second pixel group, the spacing between two adjacent first color pixel units in the third pixel group, and the spacing between the second color pixel unit and the third color pixel unit adjacent to each other in the fourth pixel group are all equal.

13. The display panel according to claim 11, wherein: The sizes of the first color pixel unit, the second color pixel unit, and the third color pixel unit are all 2um to 60nm; The distance between the first color pixel unit and the first color pixel unit closest to it is 5um~30nm; the distance between the first color pixel unit and the third color pixel unit closest to it is 5um~30nm; the distance between the second color pixel unit and the third color pixel unit closest to it is 5um~30nm.

14. The display substrate according to claim 2, wherein: The orthographic projection of the first groove on the base substrate includes any one of a square, a rectangle, a circle, a triangle, and an irregular shape; the orthographic projection of the light-emitting layer on the base substrate includes any one of a square, a rectangle, a circle, a triangle, and an irregular shape.

15. A method for preparing a display substrate according to any one of claims 1 to 14, comprising: Providing a base substrate, on which a plurality of pixel driving circuits are formed; Forming a planarization layer on a side of the layer where the pixel driving circuit is located away from the base substrate, and forming a plurality of first grooves on the planarization layer; forming a first electrode of a plurality of light-emitting devices on a side of the planarization layer away from the base substrate; A first electrode of the light emitting device covers the bottom and sidewalls of the first groove; Forming a pixel defining layer on a side of the layer where the first electrode of each light-emitting device is located away from the base substrate; The pixel defining layer has a plurality of pixel openings; An orthographic projection of the pixel opening on the base substrate is located within a limited range of an orthographic projection of the first groove on the base substrate.

16. A display panel comprising the display substrate according to any one of claims 1 to 14.

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