Clock BUS line and quiescent current BUS line area evaluation method

Abstract

The invention discloses a clock BUS line and quiescent current BUS line area evaluation method, and relates to the technical field of image processing. By accurately analyzing a quiescent current line and a clock line in chip design and optimizing wiring resource allocation by utilizing a graph theory algorithm, the chip utilization rate is improved, the problem of line layout in a compact space is solved, lines are effectively grouped through a hierarchical clustering algorithm, crosstalk is reduced, signal integrity is enhanced, and accuracy of data transmission is ensured; a wiring topological structure is optimized by combining a genetic algorithm with a simulated annealing algorithm, and by calculating wiring delay and signal arrival time, time sequence performance is improved, congestion is reduced, wiring efficiency and circuit reliability are improved, and strict time sequence requirements are met. Through comprehensive application of the technologies, the overall performance and reliability of chip design are remarkably improved.

Description

Technical Field

[0001] The invention relates to the technical field of data processing, and in particular to a method for evaluating the areas of a clock BUS line and a static current BUS line. Background Art

[0002] In the design of high-speed chips, the layout optimization of static current BUS lines and clock BUS lines faces many technical challenges. First, with the continuous improvement of chip integration, the number of static current lines and clock lines has increased dramatically, and the wiring resources and chip area they occupy have also increased. How to achieve efficient layout of massive BUS lines within a limited chip area has become an urgent problem to be solved; secondly, when high-frequency signals are transmitted in BUS lines, they are easily interfered by crosstalk from adjacent lines, resulting in reduced signal integrity. This requires that when laying out BUS lines, multiple factors such as line distance, line width, and interlayer isolation must be considered comprehensively to minimize the crosstalk effect. Furthermore, there is an essential difference between the layout of static current lines and clock lines. The former is responsible for providing stable bias for the amplifier and is insensitive to wiring delay, while the latter requires strict control of signal arrival time. The two have different requirements in terms of wiring topology and line length matching, and need to be treated differently during layout optimization. Finally, the increasing number of functional modules inside the chip has also led to an increasingly complex wiring topology for BUS lines. When different BUS lines are cross-wired, it is easy to form wiring congestion, affecting wiring efficiency and reliability. Summary of the invention

[0003] The purpose of the present invention is to provide a method for evaluating the area of ​​clock BUS lines and static current BUS lines, and to find the optimal BUS line layout scheme in the wiring topology by adopting reasonable wiring strategies and algorithms to achieve the goal of minimizing wiring congestion.

[0004] The purpose of the present invention can be achieved through the following technical solutions: The present application provides a method for evaluating the area of ​​a clock BUS line and a static current BUS line, comprising the following steps: Obtain the number and distribution information of static current lines and clock lines in chip design, and generate an initial wiring resource allocation diagram; According to the initial wiring resource allocation diagram, the line width and line distance of each line are calculated to generate a line width matching matrix and a line distance matrix; These include: Obtain an initial wiring resource allocation diagram, extract the position coordinate information of each line in the wiring diagram, calculate the distance between adjacent lines based on the line position coordinates, and obtain line distance data; According to the wiring resource allocation diagram, the line width parameter information of each line is extracted, and the line distance data is constructed into a line distance matrix, in which each element in the matrix represents the distance value between two corresponding lines; The line width parameters are constructed into a line width matching matrix, where each element in the matrix represents the line width value of the corresponding line. Cluster analysis is performed on the line distance matrix, and lines with similar distances are grouped to obtain the line clustering results. According to the line clustering results and line width matching matrix, the wiring resources are optimized and the line layout is adjusted to make the distance between lines uniform and reasonable and the line width matching optimal; Obtain the line width matching matrix and line distance matrix of the lines, integrate them by weighted average to get the comprehensive similarity matrix. The elements in the matrix represent the similarity between the lines. Then, based on the similarity matrix, use the hierarchical clustering algorithm to group the lines. According to the line grouping results, the interlayer isolation requirements of each group of lines are calculated to generate an interlayer isolation requirement matrix. Then, a genetic algorithm is used to optimize the line grouping and interlayer isolation requirement matrix to generate an optimized wiring topology structure. According to the optimized wiring topology, the wiring delay and signal arrival time of each line are calculated, and the wiring delay matrix and signal arrival matrix are generated.

[0005] Furthermore, the number and distribution information of static current lines and clock lines in the chip design are obtained to generate an initial wiring resource allocation diagram, which specifically includes: According to the chip design netlist file, extract the connection information of static current lines and clock lines, count the number of interconnection lines of each type, analyze the physical distribution characteristics of static current lines and clock lines in the chip layout, and obtain the key parameters of interconnection lines; Based on the topological structure and physical parameters of the interconnection lines, a wiring resource allocation model is established using a graph theory algorithm. By solving the wiring resource allocation model, the initial wiring scheme for the static current line and the clock line is obtained, and the wiring layer and wiring width of each line are determined; When the wiring resource allocation result does not meet the timing constraints or the wiring congestion exceeds the threshold, the weight parameters in the mathematical model are adjusted, the resource allocation plan is re-solved, and the wiring topology of the static current line and the clock line is generated.

[0006] Furthermore, the line width matching matrix and the line distance matrix of the lines are obtained, and the comprehensive similarity matrix is ​​obtained by integrating them in a weighted average manner. The elements in the matrix represent the similarity between the lines. Then, according to the similarity matrix, the lines are grouped using a hierarchical clustering algorithm, including: calculating the distances between all lines in the comprehensive similarity matrix, selecting the two lines with the closest distance to merge into one cluster, and updating the similarity matrix until all lines are assigned to the cluster to form a hierarchical clustering structure. In forming the hierarchical clustering structure, the granularity of the clustering is controlled by setting a threshold. When the threshold is larger, The fewer the number of clusters formed, the greater the difference in line attributes within the cluster; the smaller the threshold, the more clusters formed, and the smaller the difference in line attributes within the cluster; for each generated cluster, calculate the average value of the line width and line distance of all lines within the cluster as the representative attribute of the cluster; compare the differences in representative attributes between different clusters, and when the difference is greater than the preset threshold, maintain the independence of the clusters; when the difference is less than the preset threshold, merge similar clusters, and then group the lines from top to bottom according to the hierarchy and representative attributes of the clusters, and divide the lines with similar attributes into the same group.

[0007] Furthermore, when the comprehensive similarity matrix is ​​obtained by integration in a weighted average manner, the routing space of the clock signal line is also calculated. The total width of the clock line is calculated by determining the line width of the clock line and the space on both sides of the line and the overall space. The total width of the clock line is composed of its own line width plus twice the space on both sides and the additional overall space. The specific total width of the clock line is expressed as: CLK_total = 5*W+1, where W represents the line width of the clock line and 1 represents the overall space.

[0008] Furthermore, a genetic algorithm is used to optimize the line grouping and inter-layer isolation requirement matrix to generate an optimized wiring topology structure, including: According to the line attributes and routing constraints, the clustering algorithm is used to group the lines to obtain the initial line grouping results, and the inter-layer isolation requirements of each group of lines are analyzed, the inter-layer isolation distance matrix is ​​calculated, and the initial inter-layer isolation requirement matrix is ​​formed; The line grouping results and the inter-layer isolation requirement matrix are used as the initial population of the genetic algorithm. Each individual represents a line grouping and isolation scheme. The fitness function of the genetic algorithm is defined to evaluate the individuals in the population. Through genetic operations such as selection, crossover and mutation, the line grouping and inter-layer isolation matrix are continuously optimized to continuously improve the fitness function value. When the number of iterations or the fitness threshold is reached, the best individual is selected from the population to obtain the optimized line grouping result and inter-layer isolation requirement matrix. Based on the optimized line grouping and inter-layer isolation matrix, the final wiring topology is generated to guide the actual wiring operations and wiring hierarchy arrangements.

[0009] Further, according to the optimized wiring topology, the wiring delay and signal arrival time of each line are calculated, and a wiring delay matrix and a signal arrival matrix are generated, including: according to the optimized wiring topology, the physical parameters of each line are obtained, and the theoretical wiring delay time of each line is calculated in combination with the signal transmission speed; According to the wiring topology, determine the lines and nodes that the signal needs to pass through from the source to the destination, accumulate the actual wiring delay time of each line, and obtain the total delay time of the signal from the source to the destination, that is, the time it takes for the signal to reach the destination. Then traverse all source-to-destination line combinations in the wiring topology, calculate the total signal delay time of each line combination, and generate a wiring delay matrix containing all source-to-destination line delays; When routing the delay matrix, the actual arrival time of the signal received at each destination is calculated based on the signal transmission time, and a signal arrival matrix containing the arrival times of all destination signals is generated. A timing analysis tool is used to analyze the timing performance based on the routing delay matrix and the signal arrival matrix to determine whether the design requirements are met, and to optimize the timing violation paths. Based on the timing analysis results, the routing topology is optimized, and the routing delay matrix and the signal arrival matrix are regenerated until the system timing requirements are met.

[0010] Furthermore, after generating the wiring delay matrix and the signal arrival matrix, a simulated annealing algorithm is used to adjust the wire length matching and wiring congestion in the wiring topology structure to generate a final wiring plan; Furthermore, a simulated annealing algorithm is used to adjust the wire length matching and wiring congestion in the wiring topology structure to generate a final wiring plan, including: according to the generated wiring delay matrix and signal arrival matrix, a simulated annealing algorithm is used to adjust the wiring topology structure; during the adjustment process, the topology structure adjustment cost is calculated according to the wire length matching degree, and the wiring congestion degree is calculated at the same time as the constraint condition for the topology structure adjustment; if the current topology structure adjustment cost is less than the historical optimal cost, the current topology structure is updated to the optimal topology structure; if the current topology structure adjustment cost is greater than the historical optimal cost, the current topology structure is accepted, and the final wiring plan is determined; according to the determined final wiring plan, the final wiring delay matrix and signal arrival matrix are obtained; a genetic algorithm is used to optimize the wire length matching and wiring congestion to obtain an optimized wiring plan; according to the optimized wiring plan, an optimized wiring delay matrix and signal arrival matrix are calculated; when the optimized wiring delay matrix and signal arrival matrix meet the preset performance indicators, the optimized wiring plan is output; when the optimized wiring delay matrix and signal arrival matrix do not meet the preset performance indicators, a particle swarm algorithm is used to optimize the wire length matching and wiring congestion to obtain the final wiring plan.

[0011] The beneficial effects of the present invention are: By accurately analyzing the connection information of static current lines and clock lines in chip design and their physical distribution characteristics, and using graph theory algorithms to optimize wiring resource allocation, a large number of BUS lines can be efficiently laid out within a limited chip area, thereby improving chip utilization. This method solves the problem of how to reasonably arrange line layout in a compact space to maximize chip performance. A hierarchical clustering algorithm is used to group the lines to ensure that lines with similar line width and line distance are effectively grouped, which helps to reduce crosstalk between adjacent lines during wiring and enhance signal integrity. In this way, the problem of signal integrity degradation caused by crosstalk during high-speed signal transmission is solved, ensuring the accuracy and reliability of data transmission; Genetic algorithms are used to optimize line grouping and inter-layer isolation requirements to generate optimized wiring topology. At the same time, the timing performance of the system is analyzed and optimized by calculating the wiring delay matrix and signal arrival matrix. In addition, simulated annealing algorithms are used to adjust the wiring topology to reduce line length matching and wiring congestion. These methods work together to solve the timing violations and congestion problems in the wiring process, improve wiring efficiency and circuit reliability, and ensure that the chip design meets strict timing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0013] Figure 1A flowchart of a method for evaluating the area of ​​a clock BUS line and a static current BUS line provided in the present application; Figure 2 A schematic diagram of a process for generating an initial wiring resource allocation diagram for a method for evaluating the area of ​​a clock BUS line and a static current BUS line provided in the present application; Figure 3 A schematic flow chart of a method for evaluating the area of ​​a clock BUS line and a static current BUS line provided in the present application for generating a line width matching matrix and an inter-line distance matrix. DETAILED DESCRIPTION

[0014] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0015] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0016] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0017] See also Figure 1-Figure 3 This embodiment provides a method for evaluating the area of ​​a clock BUS line and a static current BUS line, comprising the following steps: S1. Obtain the number and distribution information of static current lines and clock lines in the chip design, and generate an initial wiring resource allocation diagram; Furthermore, the number and distribution information of static current lines and clock lines in the chip design are obtained to generate an initial wiring resource allocation diagram, which specifically includes: S11. Extract the connection information of static current lines and clock lines according to the netlist file of chip design, count the number of interconnection lines of various types, analyze the physical distribution characteristics of static current lines and clock lines in chip layout, and obtain key parameters such as interconnection line length and congestion; S12. Based on the topological structure and physical parameters of the interconnection lines, a wiring resource allocation model is established using a graph theory algorithm. By solving the wiring resource allocation model, an initial wiring scheme for the static current line and the clock line is obtained, and the wiring layer and wiring width of each line are determined; S13. When the wiring resource allocation result does not meet the timing constraint or the wiring congestion exceeds the threshold, the weight parameters in the mathematical model are adjusted, the resource allocation plan is re-solved, and the wiring topology structure of the static current line and the clock line is generated.

[0018] Specifically, by accurately analyzing and extracting the connection information of static current lines and clock lines in chip design, as well as the physical distribution characteristics in the chip layout, this method can generate a detailed initial wiring resource allocation diagram, providing a structured wiring starting point for chip design, ensuring that the wiring scheme is optimized in terms of meeting timing constraints and minimizing congestion, thereby laying a solid foundation for subsequent wiring optimization and performance improvement, and significantly improving the efficiency of chip design and the performance of the final product.

[0019] S2. Calculate the line width and line distance of each line according to the initial wiring resource allocation diagram, and generate a line width matching matrix and a line distance matrix; Furthermore, according to the initial wiring resource allocation diagram, the line width and line distance of each line are calculated to generate a line width matching matrix and a line distance matrix, which specifically includes: S21, obtaining an initial wiring resource allocation diagram, extracting the position coordinate information of each line in the wiring diagram, calculating the distance between adjacent lines according to the line position coordinates, and obtaining line distance data; S22, extracting the line width parameter information of each line according to the wiring resource allocation diagram, and constructing the line distance data into a line distance matrix, where each element in the matrix represents the distance value between two corresponding lines; S23, constructing a line width matching matrix with line width parameters, where each element in the matrix represents the line width value of the corresponding line, performing cluster analysis on the line distance matrix, grouping lines with similar distances, and obtaining a line clustering result; S24. According to the line clustering results and the line width matching matrix, the wiring resources are optimized and the line layout is adjusted to make the distance between lines uniform and reasonable and the line width matching optimal.

[0020] Specifically, by accurately calculating the line width and line distance of each line in the chip design, and constructing a line width matching matrix and a line distance matrix, the effect of this method is to significantly improve the optimization level of the wiring scheme, ensure that the distance between lines is uniform and reasonable, the line width configuration is optimal, effectively reduce wiring congestion, and improve signal integrity, thereby enhancing the performance and reliability of the chip while meeting the design rules and optimizing the wiring layout.

[0021] Among them, calculating the line width and line spacing of each line includes calculating the static wire routing space, determining the current capacity and signal type (such as clock, data, power, etc.) of each line according to the requirements of circuit design, and for static wires (such as power lines and ground lines), calculating the required line width to meet the requirements of current transmission, considering current density, voltage drop limit and process rules; Use Ohm's law and parasitic resistance model to calculate line width; V(drop) = I(line current) * R (parasitic resistance), where the parasitic resistance in the integrated circuit comes from the line length L and width W. The foundry provides the line square resistance, which is defined as a square (W=L) resistor, called Square_RES, where R (parasitic resistance) = L / W *Square_RES.

[0022] According to the performance requirements of the circuit, a safe value of the maximum allowable voltage drop is set as V(drop).

[0023] V(drop)>I(trace current) * R(parasitic resistance); V(drop)> I * L / W * Square_RES; V(drop) / (I * L * Square_RES )>1 / W; (I * L * Square_RES ) / V(drop)>W; Based on the voltage drop requirement and parasitic resistance, the required line width can be calculated, expressed as W= (I×L×Square_RES) / V(drop); According to the design rule check, there is space between different traces, and there is a safe production distance between different traces, which is called DRC_space. The spacing of the current line (current_pitch) includes the line width and the safe production distance (W). current_pitch = DRC_space + W; When this line has N current lines, total = N * current_pitch; Total = N * [(I * L * Square_RES ) / V(drop) + DRC_space]; To improve signal integrity, shielding wires are arranged around the current lines, taking into account the width and space of the shielding wires. For example, if the shielding wire width is 0.2um and the space is 0.3um, then the shielding wires on both sides require a total of (0.2+0.3)*2=1um of space.

[0024] Add the space of the shielding line to the total width, and set it to total + 1 = N * [(I * L * Square_RES ) / V(drop) + DRC_space] + 1(um), where +1um represents the total width of the shielding lines on both sides.

[0025] S3. Obtain the line width matching matrix and line distance matrix of the line, integrate them by weighted average to obtain a comprehensive similarity matrix. The elements in the matrix represent the similarity between the lines. Then, based on the similarity matrix, a hierarchical clustering algorithm is used to group the lines. The results of the hierarchical clustering can be fed back into the wiring resource allocation to adjust the calculation of the line width and the distance between the lines to achieve a better wiring layout.

[0026] Furthermore, the line width matching matrix and the line distance matrix of the lines are obtained, and the comprehensive similarity matrix is ​​obtained by integrating them in a weighted average manner. The elements in the matrix represent the similarity between the lines. Then, according to the similarity matrix, the lines are grouped using a hierarchical clustering algorithm, which specifically includes: calculating the distance between all lines in the comprehensive similarity matrix, selecting the two lines with the closest distance to merge into one cluster, and updating the similarity matrix until all lines are assigned to the cluster to form a hierarchical clustering structure. In forming the hierarchical clustering structure, the granularity of the clustering is controlled by setting a threshold. When the threshold is larger, the smaller the clustering is, the smaller the clustering is. The smaller the threshold, the more clusters are formed, and the smaller the difference in line attributes within the cluster. For each generated cluster, the average value of the line width and line distance of all lines within the cluster is calculated as the representative attribute of the cluster. The differences in representative attributes between different clusters are compared. When the difference is greater than the preset threshold, the independence of the clusters is maintained. When the difference is less than the preset threshold, similar clusters are merged, and then the lines are grouped from top to bottom according to the hierarchical structure and representative attributes of the clusters, and the lines with similar attributes are divided into the same group.

[0027] During the grouping process, priority is given to ensuring the consistency of line attributes within the group, while taking into account the differences between groups to achieve a reasonable division of lines. The grouping results are evaluated and optimized, and the standard deviation of the line attributes within each group is calculated. If the standard deviation exceeds the preset threshold, the group is considered to be further split into multiple subgroups to improve the similarity of the lines within the group; if the difference in attributes between groups is too small, consider merging similar groups to reduce the number of groups.

[0028] Specifically, by integrating the line width matching matrix and the line distance matrix, using weighted average to integrate into a comprehensive similarity matrix, and applying a hierarchical clustering algorithm to group the lines, the effect of this method is to significantly improve the efficiency and quality of integrated circuit wiring. By quantifying the similarity between lines, the reasonable grouping of lines is achieved, the allocation of wiring resources is optimized, and the consistency of line attributes within the group is ensured. At the same time, the granularity of clustering is controlled by adjusting the threshold, making the wiring layout more uniform and reasonable. In addition, by evaluating and optimizing the grouping results, such as calculating the standard deviation and further splitting or merging groups as needed, the similarity of the lines within the group and the rationality of the overall wiring are further improved, which helps to reduce wiring congestion and improve signal integrity.

[0029] Furthermore, when the comprehensive similarity matrix is ​​obtained by integration in a weighted average manner, the routing space of the clock signal line is also calculated. The total width of the clock line is calculated by determining the line width of the clock line and the space on both sides of the line and the overall space. The total width of the clock line is composed of its own line width plus twice the space on both sides and the additional overall space. The specific total width of the clock line is expressed as: CLK_total = 5*W+1, where W represents the line width of the clock line and 1 represents the overall space.

[0030] Specifically, when integrating the similarity matrix, the similarity between each line (including clock lines and ordinary signal lines) is calculated based on their line width and line distance. For clock lines, their larger line width and special shielding requirements will occupy a significant weight in the similarity calculation to ensure that lines with similar line width and line distance (especially clock lines) can be effectively grouped during the clustering process. Such grouping helps to perform special treatment on clock lines in subsequent routing optimization, such as giving priority to their requirements for signal integrity and timing during routing, and isolating them from other signal lines when possible to reduce crosstalk and improve the overall performance of the circuit.

[0031] Furthermore, the total width of the clock line and the current line is compared to determine whether it needs to be adjusted to save area. By placing the CLK line on the current line to make two layers of layer routing shielding lines, the overall width is compared. In order to save area, the overall routing width needs to be compared. By inputting the CLK width and the current BUS width, when it is determined that the CLK width and the current BUS width are greater than 3um, each corresponding width is reduced and a layer is superimposed.

[0032] S4. According to the line grouping results, the interlayer isolation requirements of each group of lines are calculated to generate an interlayer isolation requirement matrix. Then, a genetic algorithm is used to optimize the line grouping and the interlayer isolation requirement matrix to generate an optimized wiring topology.

[0033] Furthermore, a genetic algorithm is used to optimize the line grouping and inter-layer isolation requirement matrix to generate an optimized wiring topology, including: According to the line attributes and routing constraints, the clustering algorithm is used to group the lines to obtain the initial line grouping results, and the inter-layer isolation requirements of each group of lines are analyzed, the inter-layer isolation distance matrix is ​​calculated, and the initial inter-layer isolation requirement matrix is ​​formed; The line grouping results and the inter-layer isolation requirement matrix are used as the initial population of the genetic algorithm. Each individual represents a line grouping and isolation scheme. The fitness function of the genetic algorithm is defined to evaluate the individuals in the population. Through genetic operations such as selection, crossover and mutation, the line grouping and inter-layer isolation matrix are continuously optimized to continuously improve the fitness function value. When the number of iterations or the fitness threshold is reached, the best individual is selected from the population to obtain the optimized line grouping result and inter-layer isolation requirement matrix. Based on the optimized line grouping and inter-layer isolation matrix, the final wiring topology is generated to guide the actual wiring operations and wiring hierarchy arrangements.

[0034] Specifically, the quality of the integrated circuit wiring topology is significantly improved by optimizing the line grouping and interlayer isolation requirement matrix using a genetic algorithm. First, the initial line grouping is obtained through a clustering algorithm, and then the interlayer isolation requirements of each group of lines are analyzed to form an interlayer isolation requirement matrix; these data are then used as the initial population of the genetic algorithm, and different line grouping and isolation schemes are evaluated by defining a fitness function. The selection, crossover, and mutation operations of the genetic algorithm allow the individuals in the population to evolve continuously, thereby finding the optimal line grouping and isolation scheme. Ultimately, these optimized grouping and isolation matrices are used to generate the final wiring topology, which not only improves the efficiency and reliability of wiring, but also helps reduce wiring congestion and improve signal integrity, providing optimized wiring guidance for achieving high-performance chip design.

[0035] S5. According to the optimized wiring topology, the wiring delay and signal arrival time of each line are calculated to generate a wiring delay matrix and a signal arrival matrix.

[0036] Furthermore, according to the optimized wiring topology, the wiring delay and signal arrival time of each line are calculated, and a wiring delay matrix and a signal arrival matrix are generated, which specifically includes: according to the optimized wiring topology, the physical parameters of each line are obtained, including line length, line material, line cross-sectional area, etc., and the theoretical wiring delay time of each line is calculated in combination with the signal transmission speed; According to the wiring topology, determine the lines and nodes that the signal needs to pass through from the source to the destination, accumulate the actual wiring delay time of each line, and obtain the total delay time of the signal from the source to the destination, that is, the time it takes for the signal to reach the destination. Then traverse all source-to-destination line combinations in the wiring topology, calculate the total signal delay time of each line combination, and generate a wiring delay matrix containing all source-to-destination line delays; When routing the delay matrix, the actual arrival time of the signal received at each destination is calculated based on the signal transmission time, and a signal arrival matrix containing the arrival times of all destination signals is generated. A timing analysis tool is used to analyze the timing performance of the system based on the routing delay matrix and the signal arrival matrix to determine whether the design requirements are met and to optimize the timing violation paths. Based on the timing analysis results, the routing topology is further optimized, such as adjusting the routing strategy of the critical path, adding delay balancing measures, etc., and the routing delay matrix and the signal arrival matrix are regenerated until the system timing requirements are met.

[0037] Specifically, by accurately calculating the wiring delay and signal arrival time, this method optimizes the chip timing performance and solves the timing violation problem in high-speed signal transmission. By generating the wiring delay matrix and signal arrival matrix, it provides accurate data for timing analysis, allowing designers to effectively identify and optimize critical paths, reduce signal delays, and improve chip synchronization performance. This process ensures that the chip design meets strict timing requirements, thereby improving product reliability and performance and meeting the market demand for high-performance chips.

[0038] Furthermore, after generating the wiring delay matrix and the signal arrival matrix, a simulated annealing algorithm is used to adjust the wire length matching and wiring congestion in the wiring topology structure to generate a final wiring plan; Furthermore, a simulated annealing algorithm is used to adjust the wire length matching and wiring congestion in the wiring topology structure to generate a final wiring plan, which specifically includes: according to the generated wiring delay matrix and signal arrival matrix, a simulated annealing algorithm is used to adjust the wiring topology structure; during the adjustment process, the topology structure adjustment cost is calculated according to the wire length matching degree, and the wiring congestion degree is calculated at the same time as the constraint condition for the topology structure adjustment; if the current topology structure adjustment cost is less than the historical optimal cost, the current topology structure is updated to the optimal topology structure; if the current topology structure adjustment cost is greater than the historical optimal cost, the current topology structure is accepted, and the final wiring plan is determined; according to the determined final wiring plan, the final wiring delay matrix and signal arrival matrix are obtained; a genetic algorithm is used to optimize the wire length matching and wiring congestion to obtain an optimized wiring plan; according to the optimized wiring plan, an optimized wiring delay matrix and signal arrival matrix are calculated; when the optimized wiring delay matrix and signal arrival matrix meet the preset performance indicators, the optimized wiring plan is output; when the optimized wiring delay matrix and signal arrival matrix do not meet the preset performance indicators, a particle swarm algorithm is used to optimize the wire length matching and wiring congestion to obtain the final wiring plan.

[0039] Specifically, by adopting simulated annealing algorithm and genetic algorithm, this method realizes fine adjustment of wiring topology and solves wiring congestion and line length matching problems. The simulated annealing algorithm simulates the physical annealing process and allows a certain degree of random perturbation in the process of searching for the optimal solution, which helps to find the global optimal wiring scheme, reduce wiring congestion and optimize line length matching. The genetic algorithm further optimizes line length matching and wiring congestion, and iteratively improves the wiring scheme by simulating natural selection and genetic mechanisms. The application of these algorithms ensures that the final wiring scheme improves the timing performance and overall reliability of the chip while meeting the preset performance indicators, thereby solving the key wiring challenges in integrated circuit design. If the results of these algorithm optimizations still do not meet the performance indicators, the particle swarm algorithm will be used for further optimization to ensure a high-quality final wiring scheme.

[0040] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for evaluating the area of ​​a clock BUS line and a static current BUS line, characterized in that: Includes steps: Obtain the number and distribution information of static current lines and clock lines in the chip design, and generate an initial wiring resource allocation diagram; According to the initial wiring resource allocation diagram, the line width and line distance of each line are calculated to generate a line width matching matrix and a line distance matrix; The generating of the initial wiring resource allocation diagram comprises: Based on the topological structure and physical parameters of the interconnection lines, a wiring resource allocation model is established using a graph theory algorithm. By solving the wiring resource allocation model, the initial wiring scheme for the static current line and the clock line is obtained, and the wiring layer and wiring width of each line are determined; The generating of the line width matching matrix and the line distance matrix comprises: Extract the position coordinates of each line in the wiring diagram, calculate the line distance data between adjacent lines and construct a line distance matrix. Each element in the matrix represents the distance value between two corresponding lines. Perform cluster analysis on the line distance matrix, group lines with similar distances, and obtain the clustering results of the lines. The line width parameters of each line are extracted to construct a line width matching matrix. Each element in the matrix represents the line width value of the corresponding line. According to the line clustering results and the line width matching matrix, the wiring resources are optimized. According to the line width matching matrix and the line distance matrix, the comprehensive similarity matrix is ​​obtained by weighted average and the hierarchical clustering algorithm is used to optimize the line grouping. According to the line grouping results, the interlayer isolation requirements of each group of lines are calculated to generate an interlayer isolation requirement matrix. Then, a genetic algorithm is used to optimize the line grouping and interlayer isolation requirement matrix to generate an optimized wiring topology structure. According to the optimized wiring topology, the wiring delay and signal arrival time of each line are calculated, and the wiring delay matrix and signal arrival matrix are generated.

2. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 1, characterized in that: The generating of the initial wiring resource allocation diagram further includes: According to the chip design netlist file, extract the connection information of static current lines and clock lines, count the number of interconnection lines of each type, analyze the physical distribution characteristics of static current lines and clock lines in the chip layout, and obtain the length and congestion of interconnection lines; When the wiring resource allocation result does not meet the timing constraints or the wiring congestion exceeds the threshold, the weight parameters in the mathematical model are adjusted, the resource allocation plan is re-solved, and the wiring topology of the static current line and the clock line is generated.

3. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 1, characterized in that: According to the line width matching matrix and the line distance matrix, a comprehensive similarity matrix is ​​obtained by weighted average and the lines are optimized and grouped using a hierarchical clustering algorithm, including: calculating the distances between all lines in the comprehensive similarity matrix, selecting the two lines with the closest distance to merge into one cluster, and updating the similarity matrix until all lines are assigned to the cluster to form a hierarchical clustering structure.

4. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 3, characterized in that: In forming a hierarchical clustering structure, the granularity of clustering is controlled by setting a threshold. When the threshold is larger, the number of clusters formed is smaller, and the difference in line attributes within the cluster is larger; when the threshold is smaller, the number of clusters formed is larger, and the difference in line attributes within the cluster is smaller; for each generated cluster, the average value of the line width and line distance of all lines within the cluster is calculated as the representative attribute of the cluster; the difference in representative attributes between different clusters is compared, and when the difference is greater than the preset threshold, the independence of the cluster is maintained; When the difference is less than the preset threshold, similar clusters are merged, and then the lines are grouped from top to bottom according to the hierarchy and representative attributes of the clusters, and the lines with similar attributes are divided into the same group.

5. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 3, characterized in that: The comprehensive similarity matrix is ​​obtained by weighted averaging, and the routing space of the clock signal line is calculated. The total width of the clock line is calculated by determining the line width of the clock line and the space on both sides of the line and the overall space. The total width of the clock line is composed of its own line width plus twice the space on both sides and the additional overall space. The total width of the specific clock line is expressed as: CLK_total = 5*W+1, where W represents the line width of the clock line and 1 represents the overall space.

6. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 1, characterized in that: Genetic algorithms are used to optimize line grouping and inter-layer isolation requirement matrices to generate optimized wiring topology structures, including: According to the line attributes and routing constraints, the clustering algorithm is used to group the lines to obtain the initial line grouping results, and the inter-layer isolation requirements of each group of lines are analyzed, the inter-layer isolation distance matrix is ​​calculated, and the initial inter-layer isolation requirement matrix is ​​formed; The line grouping results and the inter-layer isolation requirement matrix are used as the initial population of the genetic algorithm. Each individual represents a line grouping and isolation scheme. The fitness function of the genetic algorithm is defined to evaluate the individuals in the population. Through selection, crossover and mutation, the line grouping and inter-layer isolation matrix are continuously optimized to continuously improve the fitness function value. When the number of iterations or the fitness threshold is reached, the best individual is selected from the population to obtain the optimized line grouping result and inter-layer isolation requirement matrix. Based on the optimized line grouping and inter-layer isolation matrix, the final wiring topology is generated to guide the actual wiring operations and wiring hierarchy arrangements.

7. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 1, characterized in that: According to the optimized wiring topology, the wiring delay and signal arrival time of each line are calculated, and a wiring delay matrix and a signal arrival matrix are generated, including: according to the optimized wiring topology, the physical parameters of each line are obtained, and the theoretical wiring delay time of each line is calculated in combination with the signal transmission speed; According to the wiring topology, determine the lines and nodes that the signal needs to pass through from the source to the destination, accumulate the actual wiring delay time of each line, and get the total delay time of the signal from the source to the destination. Then traverse all source-to-destination line combinations in the wiring topology, calculate the total signal delay time of each line combination, and generate a wiring delay matrix containing all source-to-destination line delays.

8. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 7, characterized in that: When routing the delay matrix, the actual arrival time of the signal received at each destination is calculated based on the signal transmission time, and a signal arrival matrix containing the arrival times of all destination signals is generated. A timing analysis tool is used to analyze the timing performance based on the routing delay matrix and the signal arrival matrix to determine whether the design requirements are met, and to optimize the timing violation paths. Based on the timing analysis results, the routing topology is optimized, and the routing delay matrix and the signal arrival matrix are regenerated until the requirements are met.

9. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 1, characterized in that: After generating the routing delay matrix and signal arrival matrix, the simulated annealing algorithm is used to adjust the wire length matching and routing congestion in the routing topology to generate the final routing solution.

10. The method for evaluating the area of ​​a clock BUS line and a static current BUS line according to claim 9, characterized in that: The simulated annealing algorithm is used to adjust the wire length matching and routing congestion in the routing topology to generate the final routing solution, including: According to the generated wiring delay matrix and signal arrival matrix, the simulated annealing algorithm is used to adjust the wiring topology. During the adjustment process, the topology adjustment cost is calculated according to the line length matching degree, and the wiring congestion degree is calculated as the constraint condition of the topology adjustment. If the current topology adjustment cost is less than the historical optimal cost, the current topology is updated to the optimal topology. If the current topology adjustment cost is greater than the historical optimal cost, the current topology is accepted and the final wiring plan is determined; According to the final routing scheme determined, the final routing delay matrix and signal arrival matrix are obtained, and the genetic algorithm is used to optimize the line length matching and routing congestion to obtain the optimized routing scheme; According to the optimized wiring scheme, the optimized wiring delay matrix and signal arrival matrix are calculated. When the optimized wiring delay matrix and signal arrival matrix meet the preset performance indicators, the optimized wiring scheme is output. When the optimized wiring delay matrix and signal arrival matrix do not meet the preset performance indicators, the particle swarm algorithm is used to optimize the line length matching and wiring congestion to obtain the final wiring scheme.

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