A method for evaluating the area of a clock BUS line and a static current BUS line

Abstract

The present invention discloses a method for evaluating the area of a clock BUS line and a static current BUS line, which relates to the technical field of image processing. By precisely analyzing the static current lines and clock lines in chip design, the present invention utilizes graph theory algorithms to optimize the allocation of routing resources, improves chip utilization rate, solves the problem of line layout in a compact space, effectively groups lines through hierarchical clustering algorithms, reduces crosstalk, enhances signal integrity, ensures the accuracy of data transmission, and then optimizes the routing topology structure through a genetic algorithm combined with a simulated annealing algorithm. By calculating the routing delay and signal arrival time, the timing performance is improved, congestion is reduced, the routing efficiency and circuit reliability are increased, and strict timing requirements are met. The comprehensive application of these technologies significantly improves the overall performance and reliability of chip design.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and specifically to a method for evaluating the area of a clock BUS line and a static current BUS line. Background Art

[0002] In the design of high-speed chips, there are many technical challenges in optimizing the layout of static current BUS lines and clock BUS lines. First of all, with the continuous improvement of chip integration, the number of static current lines and clock lines has increased sharply, and the routing resources and chip area they occupy have also increased accordingly. How to achieve efficient layout of a large number of BUS lines within a limited chip area has become an urgent problem to be solved. Secondly, when high-frequency signals are transmitted in BUS lines, they are easily affected by crosstalk interference from adjacent lines, resulting in a decline in signal integrity. This requires that when laying out BUS lines, multiple factors such as line spacing, line width, and interlayer isolation must be comprehensively considered to minimize the crosstalk effect. Moreover, there are essential differences in the layout of static current lines and clock lines. The former is responsible for providing stable bias for amplifiers and is insensitive to routing delay, while the latter requires strict control of the signal arrival time. The two have different requirements in terms of routing topology and line length matching, and need to be distinguished and processed during layout optimization. Finally, the continuous increase in the number of internal functional modules of the chip has also led to the increasing complexity of the BUS line routing topology. When different BUS lines cross-wire, it is easy to form routing congestion, affecting routing efficiency and reliability. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for evaluating the area of a clock BUS line and a static current BUS line, which adopts a reasonable routing strategy and algorithm to find the optimal BUS line layout scheme in the routing topology to achieve the goal of minimizing routing congestion.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] The present application provides a method for evaluating the area of a clock BUS line and a static current BUS line, including the following steps:

[0006] Obtain the quantity and distribution information of static current lines and clock lines in the chip design, and generate an initial routing resource allocation diagram;

[0007] According to the initial routing resource allocation diagram, calculate the line width and line spacing of each line, and generate a line width matching matrix and a line spacing matrix;

[0008] Including:

[0009] Obtain the initial routing resource allocation diagram, extract the position coordinate information of each line in the routing diagram, and calculate the distance between adjacent lines according to the line position coordinates to obtain the line spacing data;

[0010] According to the wiring resource allocation diagram, extract the line width parameter information of each line, construct the line - to - line distance data into a line - to - line distance matrix, and each element in the matrix represents the distance value between the corresponding two lines;

[0011] Construct the line width parameter into a line width matching matrix, where each element in the matrix represents the line width value of the corresponding line. Conduct a clustering analysis on the line - to - line distance matrix, group the lines with similar distances, and obtain the clustering result of the lines;

[0012] According to the line clustering result and the line width matching matrix, optimize the wiring resources, adjust the line layout to make the line - to - line distance uniform and reasonable, and achieve the optimal line width matching;

[0013] Obtain the line width matching matrix and the line - to - line distance matrix of the lines, integrate them through weighted averaging to obtain a comprehensive similarity matrix, where the elements in the matrix represent the similarity degree between the lines. Then, according to the similarity matrix, use the hierarchical clustering algorithm to group the lines;

[0014] According to the line grouping result, calculate the inter - layer isolation requirements of each group of lines, generate an inter - layer isolation requirements matrix, and then use the genetic algorithm to optimize the line grouping and the inter - layer isolation requirements matrix to generate an optimized wiring topology structure;

[0015] According to the optimized wiring topology structure, calculate the wiring delay and signal arrival time of each line, and generate a wiring delay matrix and a signal arrival matrix.

[0016] Furthermore, obtain the quantity and distribution information of the static current lines and clock lines in the chip design, and generate an initial wiring resource allocation diagram, specifically including:

[0017] According to the netlist file of the chip design, extract the connection information of the static current lines and clock lines, count the quantity of each type of interconnected lines, analyze their physical distribution characteristics in the chip layout based on the static current lines and clock lines, and obtain the key parameters of the interconnected lines;

[0018] Based on the topological structure and physical parameters of the interconnected lines, establish a wiring resource allocation model using graph theory algorithms. By solving the wiring resource allocation model, obtain the initial wiring scheme of the static current lines and clock lines, and determine the wiring layer and wiring width of each line;

[0019] When the wiring resource allocation result does not meet the timing constraints or the wiring congestion degree exceeds the threshold, adjust the weight parameters in the mathematical model, re - solve the resource allocation scheme, and generate the wiring topology structure of the static current lines and clock lines.

[0020] Furthermore, obtain the line width matching matrix and the line - to - line distance matrix of the circuit lines, and integrate them through weighted average to obtain the comprehensive similarity matrix. The elements in the matrix represent the similarity degree between circuit lines. Then, according to the similarity matrix, use the hierarchical clustering algorithm to group the circuit lines, including: calculating the distances between all circuit lines in the comprehensive similarity matrix, selecting the two circuit lines with the closest distance to merge into a cluster, and updating the similarity matrix until all circuit lines are assigned to clusters, forming a hierarchical clustering structure. In the process of forming the hierarchical clustering structure, control the granularity of clustering by setting a threshold. When the threshold is larger, the number of formed clusters is smaller, and the difference in the circuit line attributes within the cluster is larger; when the threshold is smaller, the number of formed clusters is larger, and the difference in the circuit line attributes within the cluster is smaller. For each generated cluster, calculate the average value of the line width and the line - to - line distance of all circuit lines within the cluster as the representative attribute of the cluster. Compare the differences in the representative attributes between different clusters. When the difference is greater than the preset threshold, maintain the independence of the cluster; when the difference is less than the preset threshold, merge the similar clusters. Then, according to the hierarchical structure and representative attributes of the clusters, group the circuit lines from top to bottom, and divide the circuit lines with similar attributes into the same group.

[0021] Furthermore, when integrating through weighted average to obtain the comprehensive similarity matrix, it also includes calculating the routing space of the clock signal line. By determining the line width of the clock line and the space on both sides of the line and the overall space, calculate the total width of the clock line. Among them, the total width of the clock line consists of its own line width plus twice the space on each side and an additional overall space. Specifically, the total width of the clock line is expressed as: CLK_total = 5*W + 1, where W represents the line width of the clock line and 1 represents the overall space.

[0022] Furthermore, adopt the genetic algorithm to optimize the circuit line grouping and the inter - layer isolation requirement matrix, and generate an optimized wiring topology structure, including:

[0023] According to the circuit line attributes and wiring constraint conditions, use the clustering algorithm to group the circuit lines to obtain the initial circuit line grouping result, analyze the inter - layer isolation requirements of each group of circuit lines, calculate the inter - layer isolation distance matrix, and form the initial inter - layer isolation requirement matrix;

[0024] Take the circuit line grouping result and the inter - layer isolation requirement matrix as the initial population of the genetic algorithm. Each individual represents a circuit line grouping and isolation scheme. By defining the fitness function of the genetic algorithm, evaluate the individuals in the population;

[0025] Through genetic operations such as selection, crossover, and mutation, continuously optimize the circuit grouping and inter-layer isolation matrix to continuously improve the fitness function value. When the iteration number or fitness threshold is reached, select the optimal individual from the population to obtain the optimized circuit grouping result and the inter-layer isolation requirement matrix;

[0026] Generate the final routing topology according to the optimized circuit grouping and inter-layer isolation matrix to guide the actual routing operation and routing layer arrangement.

[0027] Furthermore, according to the optimized routing topology, calculate the routing delay and signal arrival time of each circuit, and generate a routing delay matrix and a signal arrival matrix, including: according to the optimized routing topology, obtain the physical parameters of each circuit, and combine the signal transmission speed to calculate the theoretical routing delay time of each circuit;

[0028] According to the routing topology, determine the circuits and nodes that the signal needs to pass through from the source end to the destination end, accumulate the actual routing delay time of each circuit, and obtain the total delay time of the signal from the source end to the destination end, that is, the time when the signal arrives at the destination end. Then, traverse all the circuit combinations from the source end to the destination end in the routing topology, calculate the total signal delay time of each circuit combination, and generate a routing delay matrix containing all the circuit delays from the source end to the destination end;

[0029] When generating the routing delay matrix, calculate the actual arrival time of the signal received by each destination end according to the signal transmission time, generate a signal arrival matrix containing the signal arrival times of all destination ends, use a timing analysis tool, according to the routing delay matrix and the signal arrival matrix, analyze the timing performance, judge whether it meets the design requirements, and optimize the timing violation paths. According to the timing analysis results, optimize the routing topology and regenerate the routing delay matrix and the signal arrival matrix until the system timing requirements are met.

[0030] Furthermore, after generating the routing delay matrix and the signal arrival matrix, use the simulated annealing algorithm to adjust the wire length matching and routing congestion in the routing topology to generate the final routing scheme;

[0031] Furthermore, the simulated annealing algorithm is adopted to adjust the wire length matching and routing congestion in the routing topology structure to generate the final routing scheme, including: according to the generated routing delay matrix and signal arrival matrix, the simulated annealing algorithm is used to adjust the routing topology structure. During the adjustment process, the topology structure adjustment cost is calculated according to the wire length matching degree, and at the same time, the routing congestion degree is calculated as the constraint condition for the topology structure adjustment. If the current topology structure adjustment cost is less than the historical optimal cost, the current topology structure is updated as the optimal topology structure. If the current topology structure adjustment cost is greater than the historical optimal cost, the current topology structure is accepted, and the final routing scheme is determined. According to the determined final routing scheme, the final routing delay matrix and signal arrival matrix are obtained, and the genetic algorithm is used to optimize the wire length matching and routing congestion to obtain the optimized routing scheme. According to the optimized routing scheme, the optimized routing delay matrix and signal arrival matrix are calculated. When the optimized routing delay matrix and signal arrival matrix meet the preset performance indicators, the optimized routing scheme is output. When the optimized routing delay matrix and signal arrival matrix do not meet the preset performance indicators, the particle swarm algorithm is used to optimize the wire length matching and routing congestion to obtain the final routing scheme.

[0032] The beneficial effects of the present invention are as follows:

[0033] By accurately analyzing the connection information of the static current lines and clock lines in the chip design and their physical distribution characteristics, and using graph theory algorithms to optimize the routing resource allocation, it is ensured that a large number of BUS lines can be efficiently laid out within a limited chip area, thereby improving the utilization rate of the chip. This method solves the problem of how to reasonably arrange the line layout in a compact space to maximize the chip performance;

[0034] The hierarchical clustering algorithm is used to group the lines to ensure that the lines with similar line widths and inter-line distances are effectively grouped, which helps to reduce the crosstalk between adjacent lines during routing and enhance the signal integrity. In this way, the problem of signal integrity degradation caused by crosstalk during high-speed signal transmission is solved, ensuring the accuracy and reliability of data transmission;

[0035] The genetic algorithm is used to optimize the line grouping and inter-layer isolation requirements to generate an optimized routing topology structure. At the same time, by calculating the routing delay matrix and signal arrival matrix, the timing performance of the system is analyzed and optimized. In addition, the simulated annealing algorithm is used to adjust the routing topology structure to reduce the wire length matching and routing congestion. These means work together to solve the timing violation and congestion problems during the routing process, improve the routing efficiency and the reliability of the circuit, and ensure that the chip design meets strict timing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] For better understanding and implementation, the technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 It is a schematic flow chart of a method for evaluating the area of a clock BUS line and a static current BUS line provided by this application;

[0038] Figure 2 It is a schematic flow chart for generating an initial wiring resource allocation diagram of a method for evaluating the area of a clock BUS line and a static current BUS line provided by this application;

[0039] Figure 3 It is a schematic flow chart for generating a line width matching matrix and a line spacing matrix of a method for evaluating the area of a clock BUS line and a static current BUS line provided by this application. Detailed implementation manners

[0040] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the exemplary embodiments will be described in detail herein, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are only examples of methods and systems consistent with some aspects of this application as detailed in the appended claims.

[0041] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0042] The following will elaborate in detail on the specific implementation manners, features, and effects of the present invention in combination with the drawings and preferred embodiments.

[0043] Please refer to Figures 1-3 , this embodiment provides a method for evaluating the area of a clock BUS line and a static current BUS line, including the following steps:

[0044] S1. Obtain the quantity and distribution information of the static current lines and clock lines in the chip design, and generate an initial wiring resource allocation diagram;

[0045] Further, obtaining the quantity and distribution information of the static current lines and clock lines in the chip design and generating an initial wiring resource allocation diagram specifically includes:

[0046] S11. Extract the connection information of the static current lines and clock lines from the netlist file of the chip design, count the number of each type of interconnection line, analyze their physical distribution characteristics in the chip layout based on the static current lines and clock lines, and obtain key parameters such as the length and congestion degree of the interconnection lines.

[0047] S12. Based on the topological structure and physical parameters of the interconnection lines, establish a wiring resource allocation model using graph theory algorithms. By solving the wiring resource allocation model, obtain the initial wiring scheme for the static current lines and clock lines, and determine the wiring layer and wiring width of each line.

[0048] S13. When the wiring resource allocation result does not meet the timing constraints or the wiring congestion degree exceeds the threshold, adjust the weight parameters in the mathematical model, re-solve the resource allocation scheme, and generate the wiring topological structure of the static current lines and clock lines.

[0049] Specifically, by accurately analyzing and extracting the connection information of the static current lines and clock lines in the chip design and their physical distribution characteristics in the chip layout, this method can generate a detailed initial wiring resource allocation diagram, providing a structured wiring starting point for chip design, ensuring that the wiring scheme is optimized in terms of meeting timing constraints and minimizing congestion degree, thus laying a solid foundation for subsequent wiring optimization and performance improvement, and significantly improving the efficiency of chip design and the performance of the final product.

[0050] S2. According to the initial wiring resource allocation diagram, calculate the line width and the distance between lines of each line, and generate a line width matching matrix and a distance between lines matrix.

[0051] Furthermore, according to the initial wiring resource allocation diagram, calculate the line width and the distance between lines of each line, and generate a line width matching matrix and a distance between lines matrix, specifically including:

[0052] S21. Obtain the initial wiring resource allocation diagram, extract the position coordinate information of each line in the wiring diagram, and calculate the distance between adjacent lines according to the line position coordinates to obtain the distance data between lines.

[0053] S22. According to the wiring resource allocation diagram, extract the line width parameter information of each line, construct the distance data between lines into a distance between lines matrix, and each element in the matrix represents the distance value between the corresponding two lines.

[0054] S23. Construct the line width parameters into a line width matching matrix, where each element in the matrix represents the line width value of the corresponding line. Perform clustering analysis on the distance between lines matrix, group the lines with close distances, and obtain the clustering result of the lines.

[0055] S24. Optimize the routing resources according to the line clustering results and the line width matching matrix, adjust the line layout, so that the distance between lines is uniform and reasonable, and the line width matching is optimal.

[0056] Specifically, by accurately calculating the line width and the distance between lines in the chip design, and constructing a line width matching matrix and a distance between lines matrix, the effect of this method is to significantly improve the optimization level of the routing scheme, ensure that the distance between lines is uniform and reasonable, the line width configuration is optimal, effectively reduce routing congestion, improve signal integrity, so as to enhance the performance and reliability of the chip while meeting the design rules, and optimize the routing layout.

[0057] Among them, calculating the line width and the distance between lines for each line includes calculating the static wire routing space. According to the requirements of the circuit design, determine the current capacity and signal type (such as clock, data, power supply, etc.) of each line. For static wires (such as power supply lines and ground lines), calculate the required line width to meet the requirements of current transmission, considering current density, voltage drop limit and process rules;

[0058] Use Ohm's law and the parasitic resistance model to calculate the line width; V(drop) = I(routing current) * R (parasitic resistance), where the parasitic resistance in the integrated circuit comes from the routing length L, width W, and the foundry provides the sheet resistance of the routing. The definition of the sheet resistance is the resistance of a square (W = L), which is called Square_RES, where R (parasitic resistance) = L / W * Square_RES.

[0059] Set a safety value of the maximum allowable voltage drop as V(drop) according to the performance requirements of the circuit.

[0060] V(drop)>I(routing current) * R (parasitic resistance);

[0061] V(drop)> I * L / W * Square_RES;

[0062] V(drop) / (I * L * Square_RES )>1 / W;

[0063] (I * L * Square_RES ) / V(drop)>W;

[0064] According to the voltage drop requirement and the parasitic resistance, the required line width can be calculated, expressed as W=

[0065] (I×L×Square_RES) / V(drop);

[0066] According to the design rule check, there is space between different traces, and there will be a safety production distance between different lanes, which is called DRC_space. The pitch of current-carrying lines (current_pitch) includes the line width and the safety production distance (W).

[0067] current_pitch = DRC_space + W;

[0068] When there are N current-carrying lines in this line, total = N * current_pitch;

[0069] Total = N *

(I * L * Square_RES ) / V(drop) + DRC_space

[0070] To improve signal integrity, shielded lines are arranged around the current-carrying lines. Considering the width and space of the shielded lines, for example, if the width of the shielded line is 0.2um and the space is 0.3um, then the total space required for the shielded lines on both sides is (0.2 + 0.3) * 2 = 1um.

[0071] Adding the space of the shielded lines to the total width, it is set as total + 1 = N *

(I * L * Square_RES ) / V(drop) + DRC_space

[0072] S3. Obtain the line width matching matrix and the line spacing matrix of the circuit. Integrate them through weighted average to obtain the comprehensive similarity matrix. The elements in the matrix represent the similarity degree between circuits. Then, according to the similarity matrix, use the hierarchical clustering algorithm to group the circuits; the result of hierarchical clustering can be fed back to the routing resource allocation to adjust the calculation of line width and line spacing to achieve a better routing layout.

[0073] Further, obtain the line width matching matrix and the inter-line distance matrix of the circuit lines, and integrate them by weighted average to obtain the comprehensive similarity matrix. The elements in the matrix represent the similarity degree between circuit lines. Then, according to the similarity matrix, use the hierarchical clustering algorithm to group the circuit lines. Specifically, calculate the distances between all circuit lines in the comprehensive similarity matrix, select the two circuit lines with the closest distance and merge them into a cluster, and update the similarity matrix until all circuit lines are assigned to clusters, forming a hierarchical clustering structure. In the process of forming the hierarchical clustering structure, control the granularity of clustering by setting a threshold. When the threshold is larger, the number of formed clusters is smaller, and the difference in line attributes within the clusters is larger; when the threshold is smaller, the number of formed clusters is larger, and the difference in line attributes within the clusters is smaller. For each generated cluster, calculate the average values of the line widths and inter-line distances of all circuit lines within the cluster as the representative attributes of the cluster. Compare the differences in representative attributes between different clusters. When the difference is greater than the preset threshold, maintain the independence of the clusters; when the difference is less than the preset threshold, merge the similar clusters. Then, according to the hierarchical structure and representative attributes of the clusters, group the circuit lines from top to bottom, and divide the circuit lines with similar attributes into the same group.

[0074] During the grouping process, prioritize ensuring the consistency of line attributes within the group while taking into account the differences between groups to achieve a reasonable division of the circuit lines. Evaluate and optimize the grouping results. Calculate the standard deviation of the line attributes within each group. If the standard deviation exceeds the preset threshold, consider further splitting the group into multiple subgroups to increase the similarity of the circuit lines within the group; if the difference in attributes between groups is too small, consider merging similar groups to reduce the number of groups.

[0075] Specifically, by integrating the line width matching matrix and the inter-line distance matrix, using weighted average to form the comprehensive similarity matrix, and applying the hierarchical clustering algorithm to group the circuit lines, the effect of this method is to significantly improve the efficiency and quality of integrated circuit wiring. By quantifying the similarity between circuit lines, it realizes a reasonable grouping of circuit lines, optimizes the allocation of wiring resources, ensures the consistency of line attributes within the group, and at the same time controls the granularity of clustering by adjusting the threshold, making the wiring layout more uniform and reasonable. In addition, by evaluating and optimizing the grouping results, such as calculating the standard deviation and further splitting or merging groups as needed, it further improves the similarity of the circuit lines within the group and the rationality of the overall wiring, which helps to reduce wiring congestion and improve signal integrity.

[0076] Further, when integrating to obtain the comprehensive similarity matrix through weighted average, it also includes calculating the routing space of the clock signal line. By determining the line width of the clock line, the space on both sides of the line, and the overall space, the total width of the clock line is calculated. Among them, the total width of the clock line consists of its own line width plus twice the space on each side and an additional overall space. Specifically, the total width of the clock line is expressed as: CLK_total = 5*W + 1, where W represents the line width of the clock line and 1 represents the overall space.

[0077] Specifically, when integrating the similarity matrix, the similarity between each line (including the clock line and the ordinary signal line) is calculated based on its line width and the distance between lines. For the clock line, its larger line width and special shielding requirements will occupy a significant weight in the similarity calculation to ensure that during the clustering process, lines with similar line widths and distances between lines (especially clock lines) can be effectively grouped. Such grouping helps to specifically process the clock line in subsequent routing optimization, such as giving priority to its requirements for signal integrity and timing during routing, and isolating it from other signal lines as much as possible to reduce crosstalk and improve the overall performance of the circuit.

[0078] Further, compare the total widths of the clock line and the current line to determine whether adjustment is needed to save area. By placing the CLK line above the current line to make two-layer layer routing shielding lines and comparing the overall widths, in order to save area, it is necessary to compare the overall routing widths. By inputting the CLK width and the current BUS width, when it is determined that both the CLK width and the current BUS width are greater than 3 um, each corresponding width is reduced and one more layer is added.

[0079] S4. According to the line grouping result, calculate the interlayer isolation requirements for each group of lines to generate an interlayer isolation requirement matrix, and then use the genetic algorithm to optimize the line grouping and the interlayer isolation requirement matrix to generate an optimized routing topology structure.

[0080] Further, use the genetic algorithm to optimize the line grouping and the interlayer isolation requirement matrix to generate an optimized routing topology structure, specifically including:

[0081] According to the line attributes and routing constraint conditions, use the clustering algorithm to group the lines to obtain the initial line grouping result, analyze the interlayer isolation requirements for each group of lines, calculate the interlayer isolation distance matrix, and form the initial interlayer isolation requirement matrix;

[0082] Take the line grouping result and the interlayer isolation requirement matrix as the initial population of the genetic algorithm. Each individual represents a line grouping and isolation scheme, and by defining the fitness function of the genetic algorithm, the individuals in the population are evaluated;

[0083] Through genetic operations such as selection, crossover, and mutation, continuously optimize the circuit grouping and interlayer isolation matrix to continuously improve the fitness function value. When the iteration number or fitness threshold is reached, select the optimal individual from the population to obtain the optimized circuit grouping result and the interlayer isolation requirement matrix;

[0084] Generate the final wiring topology structure according to the optimized circuit grouping and interlayer isolation matrix to guide the actual wiring operation and wiring layer arrangement.

[0085] Specifically, by using the genetic algorithm to optimize the circuit grouping and interlayer isolation requirement matrix, the quality of the integrated circuit wiring topology structure is significantly improved. First, obtain the initial circuit grouping through the clustering algorithm, and then analyze the interlayer isolation requirements of each group of circuits to form the interlayer isolation requirement matrix; then use these data as the initial population of the genetic algorithm, and evaluate different circuit grouping and isolation schemes by defining the fitness function. The selection, crossover, and mutation operations of the genetic algorithm enable the individuals in the population to continuously evolve, so as to find the optimal circuit grouping and isolation scheme. Finally, these optimized grouping and isolation matrices are used to generate the final wiring topology structure, which not only improves the efficiency and reliability of wiring, but also helps to reduce wiring congestion and improve signal integrity, providing optimized wiring guidance for the realization of high-performance chip design.

[0086] S5. Calculate the wiring delay and signal arrival time of each circuit according to the optimized wiring topology structure, and generate the wiring delay matrix and signal arrival matrix.

[0087] Furthermore, calculate the wiring delay and signal arrival time of each circuit according to the optimized wiring topology structure, and generate the wiring delay matrix and signal arrival matrix, specifically including: according to the optimized wiring topology structure, obtain the physical parameters of each circuit, including the circuit length, circuit material, circuit cross-sectional area, etc., and combine the signal transmission speed to calculate the theoretical wiring delay time of each circuit;

[0088] According to the wiring topology structure, determine the circuits and nodes that the signal needs to pass through from the source end to the destination end, accumulate the actual wiring delay time of each circuit, and obtain the total delay time of the signal from the source end to the destination end, that is, the time when the signal arrives at the destination end. Then traverse all the circuit combinations from the source end to the destination end in the wiring topology structure, calculate the total signal delay time of each circuit combination, and generate a wiring delay matrix containing all the line delays from the source end to the destination end;

[0089] When wiring the delay matrix, according to the signal transmission time, calculate the actual arrival time of the signal received by each destination, generate a signal arrival matrix containing the signal arrival times of all destinations, use a timing analysis tool, according to the wiring delay matrix and the signal arrival matrix, analyze the timing performance of the system, judge whether it meets the design requirements, and optimize the timing violation paths. According to the timing analysis results, further optimize the wiring topology structure, such as adjusting the wiring strategy of the critical path, adding delay equalization measures, etc., and regenerate the wiring delay matrix and the signal arrival matrix until the system timing requirements are met.

[0090] Specifically, by accurately calculating the wiring delay and the signal arrival time, this method realizes the optimization of the chip timing performance, solves the timing violation problem in high-speed signal transmission. By generating the wiring delay matrix and the signal arrival matrix, it provides accurate data for timing analysis, enabling designers to effectively identify and optimize the critical path, reduce signal delay, and improve the synchronization performance of the chip. This process ensures that the chip design meets strict timing requirements, thereby enhancing the reliability and performance of the product and meeting the market demand for high-performance chips.

[0091] Furthermore, after generating the wiring delay matrix and the signal arrival matrix, use the simulated annealing algorithm to adjust the wire length matching and wiring congestion in the wiring topology structure to generate the final wiring scheme;

[0092] Furthermore, use the simulated annealing algorithm to adjust the wire length matching and wiring congestion in the wiring topology structure to generate the final wiring scheme, which specifically includes: according to the generated wiring delay matrix and the signal arrival matrix, use the simulated annealing algorithm to adjust the wiring topology structure. During the adjustment process, calculate the topology structure adjustment cost according to the wire length matching degree, and at the same time calculate the wiring congestion degree as the constraint condition for the topology structure adjustment. If the current topology structure adjustment cost is less than the historical optimal cost, update the current topology structure as the optimal topology structure. If the current topology structure adjustment cost is greater than the historical optimal cost, accept the current topology structure to determine the final wiring scheme. According to the determined final wiring scheme, obtain the final wiring delay matrix and the signal arrival matrix, use the genetic algorithm to optimize the wire length matching and wiring congestion to obtain the optimized wiring scheme. According to the optimized wiring scheme, calculate the optimized wiring delay matrix and the signal arrival matrix. When the optimized wiring delay matrix and the signal arrival matrix meet the preset performance indicators, output the optimized wiring scheme. When the optimized wiring delay matrix and the signal arrival matrix do not meet the preset performance indicators, use the particle swarm algorithm to optimize the wire length matching and wiring congestion to obtain the final wiring scheme.

[0093] Specifically, by adopting the simulated annealing algorithm and the genetic algorithm, this method realizes the fine adjustment of the wiring topology structure, solves the problems of wiring congestion and wire length matching. The simulated annealing algorithm simulates the physical annealing process, allows a certain degree of random perturbation during the search for the optimal solution, helps to find the globally optimal wiring scheme, reduces wiring congestion and optimizes wire length matching. The genetic algorithm further optimizes wire length matching and wiring congestion, and iteratively improves the wiring scheme by simulating natural selection and genetic mechanisms. The application of these algorithms ensures that the final wiring scheme meets the preset performance indicators while improving the timing performance and overall reliability of the chip, thus solving the key wiring challenges in integrated circuit design. If the results after optimizing these algorithms still do not meet the performance indicators, the particle swarm algorithm will be used for further optimization to ensure a high-quality final wiring scheme.

[0094] As described above, it is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any brief modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for evaluating the area of a clock BUS line and a static current BUS line, characterized in that: Including the steps: Obtain the quantity and distribution information of static current lines and clock lines in the chip design, and generate an initial wiring resource allocation diagram; According to the initial wiring resource allocation diagram, calculate the line width and the distance between lines of each line, and generate a line width matching matrix and a line distance matrix; The generation of the initial wiring resource allocation diagram includes: Based on the topological structure and physical parameters of the interconnecting lines, establish a wiring resource allocation model using graph theory algorithms. By solving the wiring resource allocation model, obtain the initial wiring scheme of the static current lines and clock lines, and determine the wiring layer and wiring width of each line; The generation of the line width matching matrix and the line distance matrix includes: Extract the position coordinates of each line in the wiring diagram, calculate the line distance data between adjacent lines to construct a line distance matrix, and each element in the matrix represents the distance value between the corresponding two lines; perform clustering analysis on the line distance matrix, group the lines with similar distances, and obtain the clustering result of the lines; Extract the line width parameters of each line to construct a line width matching matrix, and each element in the matrix represents the line width value of the corresponding line. According to the line clustering result and the line width matching matrix, optimize the wiring resources; According to the line width matching matrix and the line distance matrix, obtain a comprehensive similarity matrix by weighted average and use the hierarchical clustering algorithm to optimize the grouping of lines, including: calculate the distances between all lines in the comprehensive similarity matrix, select the two lines with the closest distance to merge into a cluster, and update the similarity matrix until all lines are assigned to clusters, forming a hierarchical clustering structure; According to the line grouping result, calculate the interlayer isolation requirements of each group of lines, generate an interlayer isolation requirements matrix, and then use the genetic algorithm to optimize the line grouping and the interlayer isolation requirements matrix to generate an optimized wiring topology structure; According to the optimized wiring topology structure, calculate the wiring delay and signal arrival time of each line, and generate a wiring delay matrix and a signal arrival matrix.

2. The method for evaluating the area of a clock BUS line and a static current BUS line according to claim 1, wherein: The generation of the initial wiring resource allocation diagram further includes: According to the netlist file of the chip design, extract the connection information of the static current lines and clock lines, count the quantity of each type of interconnecting line, analyze the physical distribution characteristics of the static current lines and clock lines in the chip layout, and obtain the interconnecting line length and congestion degree; When the wiring resource allocation result does not meet the timing constraint or the wiring congestion degree exceeds the threshold, adjust the weight parameter in the mathematical model, re-solve the resource allocation scheme, and generate the wiring topology structure of the static current lines and clock lines.

3. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 1, characterized in that: In the formation of the hierarchical clustering structure, control the clustering granularity by setting a threshold. When the threshold is larger, the number of formed clusters is smaller, and the difference in line attributes within the clusters is larger; when the threshold is smaller, the number of formed clusters is larger, and the difference in line attributes within the clusters is smaller; for each generated cluster, calculate the average value of the line width and the distance between lines within the cluster as the representative attribute of the cluster; compare the differences in representative attributes between different clusters, and when the difference is greater than the preset threshold, maintain the independence of the clusters; When the difference is less than the preset threshold, merge the similar clusters, and then group the lines from top to bottom according to the hierarchical structure and representative attributes of the clusters, and divide the lines with similar attributes into the same group.

4. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 1, characterized in that: The method of obtaining the comprehensive similarity matrix by weighted average further includes calculating the routing space of the clock signal line. By determining the line width of the clock line, the space on both sides of the line, and the overall space, the total width of the clock line is calculated. The total width of the clock line consists of its own line width plus twice the space on each side and an additional overall space. Specifically, the total width of the clock line is expressed as: CLK_total = 5*W + 1, where W represents the line width of the clock line and 1 represents the overall space.

5. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 1, characterized in that: Adopt the genetic algorithm to optimize the line grouping and the interlayer isolation requirement matrix, and generate an optimized routing topology structure, including: According to the line attributes and routing constraint conditions, use the clustering algorithm to group the lines to obtain the initial line grouping result, analyze the interlayer isolation requirements of each group of lines, calculate the interlayer isolation distance matrix, and form the initial interlayer isolation requirement matrix; Use the line grouping result and the interlayer isolation requirement matrix as the initial population of the genetic algorithm. Each individual represents a line grouping and isolation scheme. By defining the fitness function of the genetic algorithm, evaluate the individuals in the population; Through selection, crossover, and mutation, continuously optimize the line grouping and the interlayer isolation matrix to continuously improve the fitness function value. When the iteration number or the fitness threshold is reached, select the optimal individual from the population to obtain the optimized line grouping result and the interlayer isolation requirement matrix; According to the optimized line grouping and the interlayer isolation matrix, generate the final routing topology structure to guide the actual routing operation and the routing layer arrangement.

6. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 1, characterized in that: According to the optimized routing topology structure, calculate the routing delay and the signal arrival time of each line, and generate the routing delay matrix and the signal arrival matrix, including: according to the optimized routing topology structure, obtain the physical parameters of each line, and combine with the signal transmission speed to calculate the theoretical routing delay time of each line; According to the routing topology structure, determine the lines and nodes that the signal needs to pass through from the source end to the destination end, accumulate the actual routing delay time of each line, and obtain the total delay time of the signal from the source end to the destination end. Then traverse all the line combinations from the source end to the destination end in the routing topology structure, calculate the total signal delay time of each line combination, and generate the routing delay matrix including all the line delays from the source end to the destination end.

7. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 6, characterized in that: When generating the routing delay matrix, calculate the actual arrival time of the signal received by each destination end according to the signal sending time, generate the signal arrival matrix including the signal arrival time of all destination ends. Use the timing analysis tool to analyze the timing performance according to the routing delay matrix and the signal arrival matrix, judge whether it meets the design requirements, and optimize the timing violation paths. According to the timing analysis results, optimize the routing topology structure and regenerate the routing delay matrix and the signal arrival matrix until the requirements are met.

8. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 1, characterized in that: After generating the routing delay matrix and the signal arrival matrix, the simulated annealing algorithm is used to adjust the wire length matching and routing congestion in the routing topology to generate the final routing scheme.

9. A method for evaluating the area of a clock BUS line and a static current BUS line according to claim 8, characterized in that: Using the simulated annealing algorithm to adjust the wire length matching and routing congestion in the routing topology to generate the final routing scheme, including: According to the generated routing delay matrix and signal arrival matrix, the simulated annealing algorithm is used to adjust the routing topology. During the adjustment process, the topology adjustment cost is calculated according to the wire length matching degree, and the routing congestion degree is calculated at the same time as the constraint condition for topology adjustment. If the current topology adjustment cost is less than the historical optimal cost, the current topology is updated as the optimal topology; If the current topology adjustment cost is greater than the historical optimal cost, the current topology is accepted to determine the final routing scheme; According to the determined final routing scheme, the final routing delay matrix and signal arrival matrix are obtained, and the genetic algorithm is used to optimize the wire length matching and routing congestion to obtain the optimized routing scheme; According to the optimized routing scheme, the optimized routing delay matrix and signal arrival matrix are calculated. When the optimized routing delay matrix and signal arrival matrix meet the preset performance indicators, the optimized routing scheme is output. When the optimized routing delay matrix and signal arrival matrix do not meet the preset performance indicators, the particle swarm algorithm is used to optimize the wire length matching and routing congestion to obtain the final routing scheme.

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