A configurable MOCB hardware abstraction layer packaging design method

Abstract

The present application belongs to the technical field of software radio system, and particularly relates to a configurable MOCB hardware abstraction layer packaging design method. The MOCB hardware includes three categories, which are: general processor GPP, digital signal processor DSP and programmable logic gate array FPGA; each hardware can generate events to other hardware; each hardware accesses the FPGA by generating address access signals, the address access signals are signals for describing operations on the memory content pointed by the address, and the signals contain specified memory addresses and access modes; each hardware can access the shared memory of the DSP and the GPP; each hardware has a MOCB layer and a bus adaptation layer; the MOCB layer is used for logical mapping management and interactive timing control; the bus adaptation layer is used for realizing the read-write interface of the memory and the sending-receiving of the events, and providing the local operable address for the bus with local mapping requirements.

Description

Technical Field

[0001] This invention belongs to the field of software radio system technology, and specifically relates to a configurable MOCB hardware abstraction layer encapsulation design method. Background Technology

[0002] In software-defined radio systems, a Modem Hardware Abstraction Layer (MHAL) and an MHAL on Chip Bus (MOCB) are used to provide a communication interface between heterogeneous computing units. The MOCB implements the hardware abstraction layer based on shared memory, mapping target memory through logic ports. Users operate on the target memory through these logic ports. The MOCB supports communication between General Purpose Processors (GPPs), Digital Signal Processors (DSPs), and Field Programmable Gate Arrays (FPGAs), providing a consistent interface for cross-platform waveforms.

[0003] The use of standard MOCBs requires user-controlled timing and self-negotiation to achieve reliable communication, offering flexibility but placing higher demands on users. Using MOCBs requires intrusive modifications to the program design based on the bus, imposing a burden on MOCB designers to maintain program stability and reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a configurable MOCB hardware abstraction layer encapsulation design method to reduce the difficulty for users to use MOCB and reduce the maintenance burden for MOCB designers.

[0005] The technical solution of the present invention:

[0006] A configurable MOCB hardware abstraction layer packaging design method is proposed. The MOCB hardware includes three types: general-purpose processor (GPP), digital signal processor (DSP), and programmable gate array (FPGA).

[0007] Each piece of hardware can generate events to other hardware;

[0008] Each piece of hardware accesses the FPGA by generating address access signals. Address access signals are signals that contain a specified memory address and access method and are used to describe the operation on the memory content pointed to by the address.

[0009] Each piece of hardware can access the shared memory of the DSP and GPP;

[0010] Each piece of hardware has an MOCB layer and a bus adaptation layer;

[0011] The MOCB layer is used for logic mapping management and interaction timing control.

[0012] The bus adaptation layer is used to implement memory read and write interfaces and event sending and receiving, and provides access to locally operable addresses for buses with local mapping requirements.

[0013] Furthermore, the bus adaptation layer includes the following operations:

[0014] Write to memory: Writes data of a specified length to a specified address of a specified bus node; MOCB obtains the address to be written to the bus node by calculating the base address and offset address, and performs the write through this interface;

[0015] Read memory: Reads data of a specified length from a specified address of a specified bus node;

[0016] Event notification: Notifies the specified event number to the specified bus node; through the event number notification, the MOCB of the target node knows the logical port where the data was written and retrieves the data from that logical port;

[0017] Registered event receive callback: When this bus node receives an event, the registered callback should be called; it is used to notify the MOCB that the logical port has been written to in order to acquire data.

[0018] Address mapping: Maps an address to a locally operable address.

[0019] Furthermore, logical mapping management includes:

[0020] i. Logical port mapping: Query the physical port, event number, offset address, number of blocks, and block size through the logical port;

[0021] ii. Mapping of physical ports: query the bus number, bus node, base address, and characteristics of the corresponding bus through the physical port;

[0022] iii. The bus number is associated with the bus adapter layer. The bus adapter layer is obtained through the bus number to perform operations on a specific bus.

[0023] Furthermore, logical mapping management uses the following data format: length 16*N+20 bytes;

[0024] The first 15 bits of the first two bytes are the logical port, and the last bit is the release flag.

[0025] The 3rd and 4th bytes represent the logical mapping table control type;

[0026] Bytes 5-8 represent the data packet length;

[0027] Bytes 9-16 are reserved bytes;

[0028] Bytes 17 and 18 are the mapping table update method flags;

[0029] 19 and 20 represent the number N of logical port mappings in the mapping table;

[0030] The following 16 bytes form a group, for a total of N groups, and each group represents a mapping relationship.

[0031] Furthermore, when registering a bus number, the event reception callback should be registered through the bus adaptation layer. The registered event reception callback looks up the associated semaphore based on the event number and triggers that semaphore.

[0032] Furthermore, the interactive timing control adopts the following data format: length 16 + load length bytes;

[0033] The first 15 bits of the first two bytes are the logical port, and the last bit is the release flag.

[0034] Bytes 3 and 4 are reserved bytes;

[0035] Bytes 5-8 represent the data packet length;

[0036] Bytes 9-16 are reserved bytes;

[0037] The following is the load, which is the data that needs to be written or read.

[0038] Furthermore, in interactive timing control, data transmission includes the following processes:

[0039] Step a: Obtain the target base address, bus node, bus adapter layer, offset address, event number, number of blocks N, block size, and characteristics based on the logical port;

[0040] Step b: If the feature is 0, it means that the logic port is located on the GPP / DSP, proceed to step c; if the feature is 1, it means that the logic port is located on the FPGA, proceed to step f.

[0041] Step c: If the hardware itself is GPP / DSP, proceed to step d; otherwise, proceed to step e.

[0042] Step d: Calculate the address of the current target transmission block number by combining the target base address; write the payload to the target address + 16 of the bus node through the bus adaptation layer; write the data header to the target address + 0 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target transmission block number to the next target transmission block number; if the number of blocks N is reached, return to the target transmission block number 0.

[0043] Step e: Calculate the address of the current target transmission block number by combining the target base address; write the payload to the target address + 16 of the bus node through the bus adapter layer. According to the characteristics of the FPGA, the user writes the payload data to the MOCB layer in the form of streaming data. The MOCB layer passes the data to the bus adapter layer for writing; write the data header to the target address + 0 of the bus node through the bus adapter layer; send the target event number to the bus node through the bus adapter layer; set the target transmission block number to the next target transmission block number. If the number of blocks N is reached, return to the target transmission block number 0.

[0044] Step f: Calculate the address of the current target transmission block number by combining the target base address; write the data header to the target address + 0 of the bus node through the bus adaptation layer; write the payload to the target address + 16 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target transmission block number to the next target transmission block number; if the number of blocks N is reached, return to the target transmission block number 0.

[0045] Furthermore, in interactive timing control, data reception includes the following processes:

[0046] If the hardware is an FPGA, streaming data reception is used. Data is distributed based on the logic port of the data header and the input receiving logic port. If they match, the data is passed to the matching module; otherwise, the data is discarded. Data is read according to the following steps: obtain the length of data to be read based on the data header; receive data streamingly from the bus adapter layer, calculate the length of data already read, and pass or discard the data to the designated module; when the length of data already read is greater than or equal to the length of data to be read, it means that all data has been read.

[0047] If the hardware is GPP / DSP, obtain the local operable address corresponding to the base address through the bus adaptation layer; calculate the address of the current target receive block number; check the data block to be released field. If it is to be released, return the address and data length; otherwise, increment the target receive block number by 1. If the number of blocks N is reached, return to the target receive block number 0. If not all target block numbers have been checked, recalculate the address of the current target receive block number and recheck the data block to be released field. If all target block numbers have been checked and none are to be released, then this reception is invalid.

[0048] The beneficial effects of this invention are:

[0049] 1) Encapsulate the mapping and management of logical ports, physical ports, and shared memory; determine the interaction sequence, encapsulate the communication process, and implement a message-like interface to reduce the difficulty of use for users and improve user development efficiency;

[0050] 2) Design a MOCB bus adapter layer to decouple the bus design from the MOCB design, forming a unidirectional dependency, reducing maintenance burden, and improving the stability of the MOCB design. Attached Figure Description

[0051] Figure 1 This invention addresses the system architecture and describes the interaction capabilities between various devices.

[0052] Figure 2 This describes the overall design concept of the present invention and the functional position of each component of the present invention.

[0053] Figure 3 It is the overall design of logical mapping management, describing the content of logical mapping management.

[0054] Figure 4 It is a data block design that describes the format of interactive data blocks.

[0055] Figure 5 It is the logic mapping table control format, which describes the control data format used to modify the logic mapping table.

[0056] Figure 6 This describes the logical port query process, outlining how to query the required target information through a logical port. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0058] A configurable MOCB hardware abstraction layer encapsulation design method is proposed to reduce the difficulty of using MOCB for users and reduce the maintenance burden of MOCB designers.

[0059] This invention mainly includes: interactive timing control, logic mapping management, bus adaptation layer design, etc.

[0060] 1. The typical system architecture targeted by this solution is as follows: Figure 1 As shown:

[0061] Events can be generated between 1.1GPP, DSP, and FPGA to any device;

[0062] 1.2 GPP, DSP, and FPGA can access the shared memory of DSP and GPP;

[0063] 1.3 The FPGA is accessed by generating address access signals. Address access signals are signals that contain a specified memory address, access mode (read, write), etc., to describe the operation on the memory content pointed to by the address.

[0064] 1.4GPP, DSP, and FPGA all have an MOCB layer and a bus adaptation layer;

[0065] The 1.5 MOCB layer is used for logic mapping management and interaction timing control.

[0066] 2. The overall design of this plan is as follows: Figure 2 As shown:

[0067] 2.1 In the sending process:

[0068] 2.1.1 The logical mapping management is responsible for converting the logical ports input by the user into information such as bus adapter layer, bus node address, base address, ring buffer, event, and offset address;

[0069] 2.1.2 The bus adaptation layer is responsible for abstracting the bus write memory interface and event notification interface;

[0070] 2.1.3 Interactive timing control follows a defined process, calls the bus adapter layer interface based on the information obtained from the logical mapping management, writes data to shared memory, and sends event notifications.

[0071] 2.2 In the receiving process:

[0072] 2.2.1 Interactive timing control determined the design of using event numbers to reflect data writing and write location information;

[0073] 2.2.2 The bus adaptation layer provides the ability to map addresses to locally operable addresses;

[0074] 2.2.3 Logical mapping management provides the ability to obtain information such as bus adapter layer, base address, offset address, and ring buffer by event number.

[0075] 2.3 In addition, logical mapping management is also responsible for providing the ability to modify mapping information.

[0076] 3. Logical mapping management

[0077] 3.1 The overall design of logical mapping management is shown in [reference]. Figure 3 .

[0078] 3.2 Logical mapping consists of three parts.

[0079] 3.3.1 Logical port mapping: The physical port, event number, offset address, number of blocks, and block size can be queried through the logical port.

[0080] 3.3.2 Physical port mapping: The physical port is used to query its corresponding bus number, bus node, base address, and characteristics.

[0081] 3.3.3 The bus number is associated with the bus adapter layer. The bus adapter layer is obtained through the bus number to realize the operation of a specific bus.

[0082] 3.3.4 All mappings are stored in a dynamically ordered array and mapped using indices and logical ports.

[0083] 3.2 Mapping Control

[0084] 3.2.1 Logical mapping control uses the same format as general data blocks, such as... Figure 4 The 0 field will be reserved as the control type field of the logical mapping table;

[0085] 3.2.2 When the control type field of the logical mapping table is 0, it indicates logical port mapping table control, which is the default control type. Other values ​​can be expanded.

[0086] 3.2.3 The logic port mapping table control format is as follows: Figure 5 When the feature field is 0, the logical port mapping table is completely replaced with the mapping table in the data; when it is 1, the logical port mappings related to the mapping table in the data are replaced. If the physical port value is 0, it means that the logical port mapping needs to be deleted.

[0087] 3.2.4 When applying MOCB to a practical system, plan and determine the logical port for each MOCB node to receive logical mapping control.

[0088] 3.2.5 When the logical port mapping table is modified, create a semaphore and associate it with the event number.

[0089] 3.2.6 When the logical port mapping table modification is complete, update the index mapping of all logical ports.

[0090] 3.3: When registering a bus number, the event reception callback operation should be performed through the bus adapter layer. The registered callback looks up the associated semaphore based on the event number and triggers that semaphore.

[0091] 1) The MOCB management layer performs a three-layer logical mapping, which distinguishes logical ports, physical ports, and bus numbers. A logical port expresses the data transmission needs of that port; a physical port can be represented as multiple logical ports through address partitioning. A physical port expresses the bus information of that port; a bus node can be represented as multiple physical ports through base address partitioning. The bus number expresses the bus driver used by that port, enabling multi-bus adaptation.

[0092] 2) Logical Mapping Table Control: Through the logical mapping table control interface, MOCB can remotely configure the logical port mapping table to meet the needs of system software node refactoring.

[0093] 4. Bus adapter layer design

[0094] 4.1 The bus adaptation layer is required to implement memory read and write interfaces and event sending and receiving capabilities, and provide the ability to obtain locally operable addresses for buses with local mapping requirements;

[0095] 4.2 Write to memory: Writes data of a specified length to a specified address on a specified bus node. MOCB calculates the base address and offset address to obtain the address to write to the bus node, and performs the write operation through this interface;

[0096] 4.3 Read Memory: Reads data of a specified length from a specified address of a specified bus node;

[0097] 4.4 Event Notification: Notify the specified event number to the specified bus node; the event number notification enables the MOCB layer of the target node to know the logical port from which data has been written, and to retrieve the data from that logical port;

[0098] 4.5 Register Event Receive Callback: When this bus node receives an event, the registered callback should be called; it is used to notify the MOCB that the logical port has been written to in order to acquire data.

[0099] 4.6 Mapping Address Acquisition: Maps the address to a locally operable address.

[0100] 1) The MOCB is adapted to multiple bus types by providing memory and event interfaces through the bus adaptation layer.

[0101] 5. Interactive timing control

[0102] 5.1 Interactive timing encapsulation determines the data block format and interaction protocol.

[0103] 5.2 Data block format as follows Figure 4 As shown.

[0104] 5.3 Pass Figure 6 This method queries the target information corresponding to a logical port. It also records the target transmit block number and receive block number for that logical port.

[0105] 5.4 The data interaction sequence is described as follows:

[0106] 5.4.1 Obtain the target base address, bus node, bus adapter layer, offset address, event number, number of blocks N, block size, and characteristics from the logical mapping management based on the logical port;

[0107] 5.4.2 If the feature is 0, it means that the logic port is located on the GPP / DSP, and the transmission timing to the GPP / DSP is referenced; if the feature is 1, it means that the logic port is located on the FPGA, and the transmission timing to the FPGA is referenced.

[0108] 5.4.3 GPP / DSP to GPP / DSP transmission timing

[0109] 5.4.3.1 Calculate the address of the current target transmission block number by combining the target base address;

[0110] 5.4.3.2 Write the payload to the target address +16 of the bus node through the bus adapter layer;

[0111] 5.4.3.3 Write the data header to the target address +0 of the bus node through the bus adapter layer;

[0112] 5.4.3.4 Send the target event number to the bus node through the bus adaptation layer;

[0113] 5.4.3.5 Set the target transmission block number to the next target transmission block number. If the number of blocks N is reached, return to the target transmission block number 0.

[0114] 5.4.4 GPP / DSP to FPGA Transmission Timing

[0115] 5.4.4.1 Calculate the address of the current target transmission block number by combining the target base address;

[0116] 5.4.4.2 Write the data header to the target address +0 of the bus node through the bus adapter layer;

[0117] 5.4.4.3 Write the payload to the target address +16 of the bus node through the bus adapter layer;

[0118] 5.4.4.4 Send the target event number to the bus node through the bus adaptation layer;

[0119] 5.4.4.5 Set the target transmission block number to the next target transmission block number. If the number of blocks N is reached, return to the target transmission block number 0.

[0120] 5.4.5GPP / DSP Receive Timing

[0121] 5.4.5.1 Waiting for the semaphore associated with the logical port mapping event number;

[0122] 5.4.5.2 Obtain the locally operable address corresponding to the base address through the bus adaptation layer;

[0123] 5.4.5.3 Calculate the address of the current target receive block number;

[0124] 5.4.5.4 Check the data block to be released field. If it is to be released, return the address and data length; otherwise, increment the target receive block number by 1. If the number of blocks N is reached, return to the target send block number 0. If not all target block numbers have been checked, return 3. If all target block numbers have been checked and none are to be released, then this reception is invalid.

[0125] 5.4.6 FPGA sends timing information to GPP / DSP

[0126] 5.4.6.1 Calculate the address of the current target transmission block number by combining the target base address;

[0127] 5.4.6.2 Write the load to the target address +16 of the bus node through the bus adapter layer. According to the characteristics of the FPGA, the user writes the load data to the MOCB layer in the form of streaming data. The MOCB layer passes the data to the bus adapter layer for writing.

[0128] 5.4.6.3 Write the data header to the target address +0 of the bus node through the bus adapter layer;

[0129] 5.4.6.4 Send the target event number to the bus node through the bus adaptation layer;

[0130] 5.4.6.5 Set the target sending block number to the next target sending block number. If the number of blocks N is reached, return to the target sending block number 0.

[0131] 5.4.7 FPGA receiving timing, using streaming data reception

[0132] 5.4.7.2 Data is distributed based on the logical port of the data header and the input receiving logical port. If they match, the data is passed to the matching module; otherwise, the data is discarded. Data is read according to the following steps.

[0133] 5.4.7.3 Obtain the length of data to be read based on the data header.

[0134] 5.4.7.4 Stream data is received from the bus adapter layer, the length of the read data is calculated, and the data is passed to or discarded by the designated module.

[0135] 5.4.7.5 When the length of the data already read is greater than or equal to the length of the data to be read, it means that all the data has been read.

[0136] 1) Data block protocol design: The data block contains logical ports and control types used for mapping control, which is the basic protocol for this interaction timing design;

[0137] 2) Interactive timing design: By transmitting the payload and data header separately, incorrect payload data is read based on the data header when the data portion is sent; by using streaming data on the FPGA, the processing efficiency of the FPGA for MOCB data is improved.

[0138] Example

[0139] The following examples describe the implementation process on GPP / DSP:

[0140] A. System Initialization

[0141] A.1 Initialize the bus according to the system bus usage, create a bus adapter layer, and assign a unique bus number to the bus adapter layer;

[0142] A.2 Initialize the mapping control management resources, create an array structure to store the three-layer logic mapping: logic port mapping array, physical port mapping array, and bus number registration array, create an event number array to store the association between event numbers and semaphores, and determine the physical ports of this hardware.

[0143] A.3 Register the bus number by sorting "bus number and bus adapter layer" in ascending order of bus number and placing them in the bus number registration array, and then calling the event receiver callback registration operation of the bus adapter layer.

[0144] A.3.1 Event Reception Callback: When the callback is invoked, the event number array is queried based on the input event number to obtain the semaphore, and the semaphore is triggered;

[0145] A.4 Allocate physical ports according to the system design, perform physical port mapping, and sort the "physical port, bus number, bus target node, base address, and characteristics" in ascending order of physical port and put them into the physical port mapping array;

[0146] A.5 Initialize the logical port mapping by sorting "logical port, physical port, offset address, event number, number of blocks, and block size" in ascending order of logical port and placing them into the logical port mapping array; if the physical port is located in this hardware, create a semaphore based on the event number and sort "event number and semaphore" in ascending order of event number and place them into the event number array.

[0147] A.5 Create a mapping control task to receive and process the "Logical Mapping Table Control" message.

[0148] B. Data Manipulation

[0149] B.1 The user obtains handle information for operating the logical port by inputting the logical port. The logical mapping management system, based on the logical port, queries the logical port mapping array to obtain the index, event number, and physical port of the logical port; queries the physical port mapping array to obtain the index and bus number of the physical port; queries the bus number registration array to obtain the index of the bus number; and queries the event number array to obtain the semaphore corresponding to the event number. The system returns the three retrieved indices, the semaphore, and the target transmit block number and target receive block number as handle information, where the target transmit block number and target receive block number are initially set to 0. The user then performs read and write operations on the logical port using this handle information.

[0150] B.2 Data Read Operation: Users complete data read operations using handle information to obtain the local memory address and length of the data; after processing the data, users need to set the fields to be released to 0.

[0151] B.2.1 After waiting for the semaphore in the handle information to be triggered, proceed to B.2.2;

[0152] B.2.2 Obtain the following mapping information through handle information: "offset address, number of blocks, block size", "base address", "bus adaptation layer" and target receive block number;

[0153] B.2.3 The base address is converted into a locally operable address through the mapping address acquisition operation of the bus adapter layer;

[0154] B.2.4 The address is calculated as "local operable address + offset address + target receive block number × block size" using the target receive block number and block size. Figure 4 Query the field to be released. If it is 1, return the address and length of the payload, and assign the result of incrementing the target receive block number by one and taking the remainder of the block count to the target receive block number. This read operation ends. Otherwise, proceed to B.2.5.

[0155] B.2.5 Increment the target receive block number by one and assign the result of taking the remainder of the block count to the target receive block number. If the number of entries in B.2.4 is not less than the block count, then the process ends; otherwise, proceed to B.2.4.

[0156] B.3 Data write operation: The user completes the data write operation by using handle information and inputting the memory address and length of the data to be written.

[0157] B.3.1 Creation Figure 4 The data header should be filled in with the logical port and length;

[0158] B.3.2 Obtain the following mapping information through handle information: "Offset address, event number, number of blocks, block size", "bus target node, base address, characteristics", "bus adaptation layer" and target transmission block number;

[0159] B.3.3 The data header write address is calculated as "base address + offset address + target sending block number × block size", and the payload write address is calculated as "base address + offset address + target sending block number × block size + 16".

[0160] B.3.4 If the feature is 0, the user writes the data to be written to the load of the bus target node through the bus adaptation layer, and then writes the data header to the data header through the address; if the feature is 1, the user writes the data header to the data header of the bus target node through the bus adaptation layer, and then writes the data to be written to the load through the address.

[0161] B.3.5 Based on the event number, send event notifications to the bus target node through the bus adaptation layer;

[0162] B.3.6 Increment the target send block number by one and then assign the result of taking the remainder of the block number to the target send block number.

[0163] C. Mapping control task: This task starts a loop to perform data read operations. After reading the data, it performs the following operations:

[0164] C.1 Parse the logical mapping table control type in the data header. If it is not 0, proceed to the next loop.

[0165] C.2 At this point, the load data is in the logical port mapping table control format. Parse the characteristic value. If it is 0, proceed to C.3; if it is 1, proceed to C.5; otherwise, proceed to the next loop.

[0166] C.3 Clear the logical port mapping array, the event number array, and destroy the semaphores within them;

[0167] C.4 Obtain all logical port mapping groups based on the number N of logical port mappings, and perform logical port mapping for each group in accordance with the method in A.5; proceed to C.6;

[0168] C.5 Obtain all logical port mapping groups based on the number N of logical port mappings. Check the logical port of each group. If it exists in the logical port mapping array, delete the corresponding event number and destroy the corresponding semaphore in the event number array. Then update the information of the item according to the obtained logical port mapping group's "physical port, offset address, event number, number of blocks, and block size". If the physical port is located in this hardware, create a semaphore according to the event number and insert "event number and semaphore" into the event number array according to the event number size.

[0169] C.6 Check all logical ports in the logical port mapping array. If the user has already obtained the handle information of the logical port, query the logical port mapping array to get the index, event number and physical port of the logical port, query the physical port mapping array to get the index and bus number of the physical port, query the bus number registration array to get the index of the bus number, query the event number array to get the semaphore corresponding to the event number, update the index and semaphore information in the handle information; enter the next loop.

[0170] D. Bus Adapter Layer

[0171] Taking the Serial Rapid IO (SRIO) bus as an example, the bus node is designed as the SRIO node ID, and the event number is designed as Doorbell information;

[0172] D.1 Write to memory: Use SRIO's NWrite transaction to write data to the bus node;

[0173] D.2 Read Memory: Use SRIO's NRead transaction to read data from the bus node;

[0174] D.3 Event Notification: Use SRIO Doorbell transactions to send Doorbell information to bus nodes;

[0175] D.4 Register event receiving callback: When a Doorbell is received, trigger an interrupt and obtain the Doorbell information as an event number for processing;

[0176] 4.6 Mapping Address Acquisition: Convert the SRIO address to a local address.

[0177] The above description is merely a specific embodiment of the present invention, providing a detailed description of the invention. Parts not covered herein are conventional techniques. However, the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A configurable MOCB hardware abstraction layer encapsulation design method, characterized in that: MOCB hardware includes three categories: general-purpose processors (GPP), digital signal processors (DSP), and programmable gate arrays (FPGA). Each piece of hardware can generate events to other hardware; Each piece of hardware accesses the FPGA by generating address access signals. Address access signals are signals that contain a specified memory address and access method and are used to describe the operation on the memory content pointed to by the address. Each piece of hardware can access the shared memory of the DSP and GPP; Each piece of hardware has an MOCB layer and a bus adaptation layer; The MOCB layer is used for logic mapping management and interaction timing control. Logical mapping management includes: i. Mapping of logical ports, which involves querying the physical port, event number, offset address, number of blocks, and block size through the logical port; where, when the physical port is located in the local hardware, a semaphore is created and associated with the event number; ii. Mapping of physical ports, which involves querying the bus number, bus node, base address, and characteristics of the corresponding bus through the physical port; iii. Associating the bus number with the bus adaptation layer, which involves obtaining the bus adaptation layer through the bus number to perform operations on a specific bus. The interactive timing control uses the following data format: length is 16 + payload length bytes; the first 15 bits of the first two bytes are logical ports, and the last bit is a release flag; bytes 3 and 4 are reserved bytes; bytes 5-8 are the data packet length; bytes 9-16 are reserved bytes; the following bytes are the payload, which is the data to be written or read. The bus adaptation layer implements memory read / write interfaces and event transmission / reception, and provides access to locally operable addresses for buses with local mapping requirements. The bus adaptation layer includes the following operations: Write Memory: Writes data of a specified length to a specified address on a specified bus node; the MOCB calculates the base address and offset address to obtain the address to be written to the bus node, and performs the write operation through that address; Read Memory: Reads data of a specified length from a specified address on a specified bus node; Event Notification: Notifies a specified bus node of a specified event number; the event number notification informs the target node's MOCB of the logical port from which data was written, and allows it to retrieve the data from that logical port; Register Event Reception Callback: When this bus node receives an event, the registered callback should be called; used to notify the MOCB that a logical port has been written to for data retrieval; Mapped Address Acquisition: Maps the address to a locally operable address.

2. The method according to claim 1, characterized in that: Logical mapping management uses the following data format: length 16*N+20 bytes; The first 15 bits of the first two bytes are the logical port, and the last bit is the release flag. The 3rd and 4th bytes represent the logical mapping table control type; Bytes 5-8 represent the data packet length; Bytes 9-16 are reserved bytes; Bytes 17 and 18 are the mapping table update method flags; 19 and 20 represent the number N of logical port mappings in the mapping table; The following 16 bytes form a group, for a total of N groups, and each group represents a mapping relationship.

3. The method according to claim 2, characterized in that: When registering a bus number, the event receiving callback is registered through the bus adaptation layer; the registered event receiving callback finds the associated semaphore based on the event number and triggers that semaphore.

4. The method according to claim 3, characterized in that: In interactive timing control, data transmission includes the following processes: Step a: Obtain the target base address, bus node, bus adapter layer, offset address, event number, number of blocks N, block size, and characteristics based on the logical port; Step b: If the feature is 0, it means that the logic port is located on the GPP or DSP, proceed to step c; If the feature is 1, it means that the logic port is located on the FPGA, proceed to step f; Step c: If the hardware itself is GPP or DSP, proceed to step d; otherwise, proceed to step e. Step d: Calculate the address of the current target transmission block number by combining the target base address; write the payload to the target address + 16 of the bus node through the bus adaptation layer; write the data header to the target address + 0 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target transmission block number to the next target transmission block number; if the number of blocks N is reached, return to the target transmission block number 0. Step e: Calculate the address of the current target transmission block number by combining the target base address; write the payload to the target address + 16 of the bus node through the bus adapter layer. According to the characteristics of the FPGA, the user writes the payload data to the MOCB layer in the form of streaming data. The MOCB layer passes the data to the bus adapter layer for writing; write the data header to the target address + 0 of the bus node through the bus adapter layer; send the target event number to the bus node through the bus adapter layer; set the target transmission block number to the next target transmission block number. If the number of blocks N is reached, return to the target transmission block number 0. Step f: Calculate the address of the current target transmission block number by combining the target base address; write the data header to the target address + 0 of the bus node through the bus adaptation layer; write the payload to the target address + 16 of the bus node through the bus adaptation layer; send the target event number to the bus node through the bus adaptation layer; set the target transmission block number to the next target transmission block number; if the number of blocks N is reached, return to the target transmission block number 0.

5. The method according to claim 4, characterized in that: In interactive timing control, data reception includes the following processes: If the hardware is an FPGA, streaming data reception is used. Data is distributed according to the logic port of the data header and the input receiving logic port. If they match, the data is passed to the matching module; otherwise, the data is discarded. The data is read according to the following steps: obtain the length of the data to be read according to the data header; receive data streamingly from the bus adapter layer, calculate the length of the data already read, and pass the data to the designated module or discard it; when the length of the data already read is greater than or equal to the length of the data to be read, it means that all the data has been read. If the hardware is a GPP or DSP, the local operable address corresponding to the base address is obtained through the bus adaptation layer. Calculate the address of the current target receive block number; check the data block to be released field, and if it is to be released, return the address and data length; Otherwise, increment the target receive block number by 1. If the number of blocks N is reached, return to the target receive block number 0. If not all target block numbers have been checked, recalculate the address of the current target receive block number and recheck the data block to be released field. If all target block numbers have been checked and none are to be released, then this reception is invalid.

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