Microcontrol circuit, control method and operating system

Abstract

A micro control circuit, a control method and an operating system, wherein the micro control circuit comprises a memory, an image processing circuit, a first temporary register, a second temporary register, a control circuit and a display circuit. The memory comprises a first storage space and a second storage space. The image processing circuit writes a first image data into the first storage space and a second image data into the second storage space. The first temporary register stores a start address of one of the first storage space and the second storage space. The second temporary register stores another start address of the first storage space and the second storage space. The control circuit exchanges the values of the first temporary register and the second temporary register according to a vertical synchronization signal. The display circuit reads the image data of the first storage space or the second storage space according to the value of the first temporary register.

Description

Technical Field

[0001] This invention relates to a microcontroller circuit, and more particularly to a microcontroller circuit that can provide image signals. Background Technology

[0002] With the advancement of technology, electronic devices are becoming increasingly diverse in type and function. Liquid crystal displays (LCDs) are one such new type of display device. Due to their advantages of being thin, lightweight, and emitting low radiation, LCDs have become increasingly widely used in recent years. Summary of the Invention

[0003] This invention provides a microcontroller circuit, including a memory, an image processing circuit, a first register, a second register, a control circuit, and a display circuit. The memory includes a first storage space and a second storage space. The image processing circuit writes first image data into the first storage space and second image data into the second storage space. The first register stores the starting address of one of the first and second storage spaces. The second register stores the other starting address of the first and second storage spaces. The control circuit swaps the values ​​of the first and second registers according to a vertical synchronization signal. The display circuit reads image data from either the first or second storage space based on the value of the first register.

[0004] The present invention also provides an operating system, including a display device and a microcontroller circuit. The display device presents an image based on an image signal. The microcontroller circuit provides the image signal and includes a memory, an image processing circuit, a first register, a second register, a control circuit, and a display circuit. The memory includes a first storage space and a second storage space. The image processing circuit writes first image data into the first storage space and writes second image data into the second storage space. The first register stores the starting address of one of the first and second storage spaces. The second register stores the other starting address of the first and second storage spaces. When a vertical synchronization signal is enabled and the value of a third register is a preset value, the control circuit swaps the values ​​of the first and second registers. When the value of the first register corresponds to the first storage space, the display circuit generates an image signal based on the first image data. When the value of the first register corresponds to the second storage space, the display circuit generates an image signal based on the second image data.

[0005] The present invention further provides a control method applicable to a microcontroller circuit. The microcontroller circuit includes a memory, a first register, and a second register. The memory has a first storage space and a second storage space. The control method of the present invention includes: receiving a vertical synchronization signal; exchanging the values ​​of the first register and the second register according to the vertical synchronization signal; when the value of the first register corresponds to the first storage space, generating an image signal according to the first image data in the first storage space; and when the value of the first register corresponds to the second storage space, generating an image signal according to the second image data in the second storage space.

[0006] The control method of the present invention can be implemented via the microcontroller circuit of the present invention, which is hardware or firmware capable of performing specific functions, or it can be implemented by recording program code in a recording medium and combined with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes the microcontroller circuit for implementing the present invention. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the operating system of the present invention.

[0008] Figure 2 for Figure 1 A schematic diagram of the operating system.

[0009] Figure 3 This is another schematic diagram of the operating system of the present invention.

[0010] Figure 4 This is a flowchart illustrating the control method of the present invention.

[0011] Figure 5 This is another schematic diagram of the control method of the present invention.

[0012] Icon labels:

[0013] 100, 300: Operating system

[0014] 110, 310: Microcontroller circuits

[0015] 120, 320: Display devices

[0016] 111, 311: Image processing circuits

[0017] 112, 312: Memory

[0018] 113, 313: Display circuit

[0019] 114, 314: Control circuit

[0020] Reg_OnLine, Reg_OffLine, Reg_BufReady, Reg_BufWidth: scratchpad

[0021] SIG: Image signal

[0022] SA1, SA2: Storage space

[0023] VSYNC: Vertical Synchronization Signal

[0024] S411~S415, S511~S519: Steps Detailed Implementation

[0025] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0026] Figure 1 This is a schematic diagram of the operating system of the present invention. As shown, the operating system 100 includes a microcontroller circuit 110 and a display device 120. The display device 120 displays an image based on an image signal SIG. The present invention does not limit the type of display device 120. In one possible embodiment, the display device 120 is a liquid crystal display (LCD).

[0027] The microcontroller circuit 110 provides the image signal SIG and includes an image processing circuit 111, a memory 112, a display circuit 113, a control circuit 114, a register Reg_OnLine, and a register Reg_OffLine. This invention does not limit the type of microcontroller circuit 110. In one possible embodiment, the microcontroller circuit 110 is a microcontroller unit (MCU).

[0028] The memory 112 includes storage spaces SA1 and SA2. The present invention does not limit the number of storage spaces. In one possible embodiment, the memory 112 has more storage space. In this embodiment, storage spaces SA1 and SA2 are non-contiguous storage spaces. The present invention does not limit the type of memory 112. In one possible embodiment, the memory 112 is a volatile memory, such as DRAM.

[0029] Image processing circuit 111 is used to write image data to storage spaces SA1 and SA2. In one possible embodiment, image processing circuit 111 writes a first image data to storage space SA1 and a second image data to storage space SA2. In this embodiment, image processing circuit 111 updates the image data in storage spaces SA1 and SA2 according to the value of the register Ref_OffLine.

[0030] For example, when the value of the register Ref_OffLine points to storage space SA1, the image processing circuit 111 writes a third image data into storage space SA1 to replace the first image data. In this example, the amount of the third image data is the same as the amount of the first image data. In another possible embodiment, the amount of the third image data is less than the amount of the first image data. In this example, the image processing circuit 111 uses the third image data to update a portion of the image data in storage space SA1. When the value of the register Ref_OffLine points to storage space SA2, the image processing circuit 111 writes a third image data into storage space SA2 to replace the second image data. In this example, the amount of the third image data is the same as the amount of the second image data. In another possible embodiment, the amount of the third image data is less than the amount of the second image data. In this example, the image processing circuit 111 uses the third image data to update a portion of the image data in storage space SA2. In other embodiments, the image processing circuit 111 uses a direct memory access (DMA) technique to access memory 112.

[0031] The register Ref_OnLine stores a first access address. The register Ref_OffLine stores a second access address. In one possible embodiment, the first access address is the starting address of one of the storage spaces SA1 and SA2, and the second access address is the starting address of the other storage space SA1 and SA2. For example, the access address recorded in register Ref_OnLine is the same as the starting address of storage space SA1, and the access address recorded in register Ref_OffLine is the same as the starting address of storage space SA2.

[0032] In one possible embodiment, the register Ref_OffLine is integrated into the image processing circuitry 111 or the memory 112. In another possible embodiment, the register Ref_OffLine is separate from both the image processing circuitry 111 and the memory 112. In still other embodiments, the register Ref_OnLine is integrated into the display circuitry 113 or the memory 112. In yet another possible embodiment, the register Ref_OnLine is separate from both the display circuitry 113 and the memory 112.

[0033] Control circuit 114 receives a vertical synchronization signal VSYNC and, based on VSYNC, exchanges the values ​​stored in registers Ref_OnLine and Ref_OffLine. For example, when the vertical synchronization signal VSYNC is enabled, control circuit 114 copies the value stored in register Ref_OnLine (e.g., 0x10000) to register Ref_OffLine, and copies the value originally stored in register Ref_OffLine (e.g., 0x20000) to register Ref_OnLine.

[0034] The display circuit 113 reads either storage space SA1 or SA2 based on the value of the register Ref_OnLine. For example, when the value of the register Ref_OnLine points to storage space SA1, the display circuit 113 generates an image signal SIG based on the image data in storage space SA1. When the value of the register Ref_OnLine points to storage space SA2, the display circuit 113 generates an image signal SIG based on the image data in storage space SA2. In one possible embodiment, the display circuit 113 utilizes DMA technology to access memory 112.

[0035] Figure 2 for Figure 1 The diagram illustrates the operation of the operating system. At time T1, the vertical synchronization signal VSYNC is enabled. Therefore, the control circuit 114 swaps the values ​​of the registers Ref_OnLine and Ref_OffLine. For example, after the swap, the value of register Ref_OnLine corresponds to the starting address 0x10000 of storage space SA1, and the value of register Ref_OffLine corresponds to the starting address 0x20000 of storage space SA2. Therefore, the display circuit 113 reads the image data stored in storage space SA1, starting from the starting address 0x10000. The image displayed by the display device 120 corresponds to the image data in storage space SA1.

[0036] In some embodiments, when the display circuit 113 reads the image data stored in the storage space SA1 according to the register Ref_OnLine, the image processing circuit 111 writes new image data starting from the starting address 0x20000 of the storage space SA2 according to the value stored in the register Ref_OffLine (such as 0x20000).

[0037] At time T2, the vertical synchronization signal VSYNC is enabled again. Therefore, control circuit 114 swaps the values ​​of registers Ref_OnLine and Ref_OffLine. For example, after the swap, the value of register Ref_OnLine corresponds to the starting address 0x20000 of storage space SA2, and the value of register Ref_OffLine corresponds to the starting address 0x10000 of storage space SA1. Therefore, display circuit 113 reads the image data stored in storage space SA2, starting from the starting address 0x20000. At this time, the image displayed by display device 120 corresponds to the image data in storage space SA2.

[0038] In some embodiments, when the display circuit 113 reads the image data stored in the storage space SA2 according to the register Ref_OnLine, the image processing circuit 111 writes new image data starting from the starting address 0x10000 of the storage space SA1 according to the value stored in the register Ref_OffLine (such as 0x10000).

[0039] Before the vertical sync signal VSYNC is enabled, the image processing circuit 111 updates the image data in the corresponding storage space. Therefore, when the vertical sync signal VSYNC is enabled, the image processing circuit 111 can generate the image signal SIG based on the updated image data. As a result, the display device 120 presents the correct image without image tearing.

[0040] Figure 3 This is another schematic diagram of the operating system of the present invention. As shown, the operating system 300 includes a microcontroller circuit 310 and a display device 320. The display device 320 displays an image based on the image signal SIG. Since the characteristics of the display device 320 are the same as... Figure 1 The characteristics of the display device 120 are not described in detail here.

[0041] The microcontroller circuit 310 includes an image processing circuit 311, a memory 312, a display circuit 313, a control circuit 314, and temporary registers Reg_OnLine, Reg_OffLine, and Reg_BufReady. Since the image processing circuit 311, memory 312, display circuit 313, control circuit 314, and temporary registers Reg_OnLine and Reg_OffLine have the same characteristics... Figure 1 The image processing circuit 111, memory 112, display circuit 113, control circuit 114, temporary register Reg_OnLine and Reg_OffLine are included, so they will not be described in detail here.

[0042] When the value of the register Reg_BufReady equals a preset value, it indicates that the image processing circuit 311 has updated the corresponding storage space according to the register Reg_OffLine. Therefore, when the vertical synchronization signal VSYNC is enabled, the control circuit 314 swaps the values ​​of the registers Ref_OnLine and Ref_OffLine. In one possible embodiment, after the control circuit 314 has swapped the values ​​of the registers Ref_OnLine and Ref_OffLine, the control circuit 314 sets the value of the register Reg_BufReady to be different from the preset value. At this time, the value of the register Reg_BufReady may be 0.

[0043] When the value of the register Reg_BufReady is not equal to the preset value and the vertical synchronization signal VSYNC is not enabled, the image processing circuit 311 performs an update operation on the storage space SA1 or SA2 according to the value of the register Ref_OffLine. After the update operation is completed, the image processing circuit 311 may set the value of the register Reg_BufReady to equal the preset value, such as the value 1.

[0044] In some embodiments, when the value of the temporary register Reg_BufReady is not equal to a preset value, the image processing circuit 311 updates the image data in the memory 312 according to the value of the temporary register Ref_OffLine. For example, when the value of the temporary register Ref_OffLine points to storage space SA1, the image processing circuit 311 writes new image data (or third image data) to storage space SA1. When the value of the temporary register Ref_OffLine points to storage space SA2, the image processing circuit 311 writes third image data to storage space SA2.

[0045] This invention does not limit the amount of third image data. In one possible embodiment, the amount of third image data is the same as the amount of image data in storage spaces SA1 and SA2. For example, storage spaces SA1 and SA2 each store 320*240*4 data. In this example, the amount of third image data is equal to 320*240*4. In another possible embodiment, the amount of third image data is less than the amount of data in storage spaces SA1 and SA2. In this example, the image processing circuit 311 uses the third image signal to update a portion of the image data in storage spaces SA1 and SA2.

[0046] In some embodiments, when the value of the register Reg_BufReady is not equal to a preset value, it indicates that the image processing circuit 311 has not yet completed the update operation. At this time, if the vertical sync signal VSYNC is enabled, the display circuit 313 reads the image data from the corresponding storage space according to the value of the register Reg_OnLine. For example, suppose the value of the register Reg_OnLine corresponds to storage space SA1, and storage space SA1 stores the first image data. During a first period, when the value of the register Reg_BufReady is not equal to the preset value and the vertical sync signal VSYNC is enabled, the display circuit 313 generates an image signal SIG based on the first image data in storage space SA1. At this time, the display device 320 displays a specific image. Then, during a second period, when the value of the register Reg_BufReady is still not equal to the preset value and the vertical sync signal VSYNC is enabled again, the display circuit 313 generates an image signal SIG based on the first image data in storage space SA1. At this time, the display device 320 displays the same specific image. Because the display device 320 displays a large number of images per second (possibly 120 images per second), even if the same image is displayed, it is not easily noticed by the user.

[0047] Furthermore, after the image processing circuit 311 completes the update operation, the control circuit 314 swaps the values ​​of the temporary registers Reg_OnLine and Reg_OffLine, thus ensuring that the storage space read by the display circuit 313 contains complete image data. Therefore, the image displayed by the display device 320 will not exhibit tearing.

[0048] In some embodiments, the microcontroller circuit 310 further includes a register Reg_BufWidth. The value of the register Reg_BufWidth is related to the resolution and image format of the display device 320. For example, suppose the resolution of the display device 320 is 320*240 and the image format is RGB888. In this example, the register Reg_BufWidth stores a value of 320*240*4.

[0049] When the value of the temporary register Reg_BufReady is not equal to the preset value, the image processing circuit 311 writes new image data to the corresponding storage space according to the value of the temporary register Ref_OffLine. In one possible embodiment, the image processing circuit 311 may use DMA technology to access the memory 312. After the write operation is completed, the value of the temporary register Reg_BufReady is set to the preset value.

[0050] This invention does not limit how to determine whether a write operation has been completed. In one possible embodiment, the write operation is considered complete when image data is written to the storage cell corresponding to a specific address in memory 312. For example, suppose the value of the register Ref_OffLine is 0x10000 and the value of the register Reg_BufWidth is 0x05000. In this example, the image processing circuit 311 starts writing new image data from address 0x10000 of storage space SA1. When the storage cell corresponding to address 0x14FFF (i.e., address 0x15000-1) of storage space SA1 has been updated with stored data, it indicates that all image data has been written to storage space SA1. Therefore, the image processing circuit 311 may set the value of register Reg_BufReady to a preset value, such as the value 1.

[0051] Figure 4 This is a flowchart illustrating the control method of the present invention. The control method of the present invention can exist through program code. When the program code is loaded and executed by a machine, the machine becomes a microcontroller circuit for implementing the present invention. In one possible embodiment, the microcontroller circuit includes a memory, a first temporary register, and a second temporary register. The memory has a first storage space and a second storage space. In some embodiments, the first and second storage spaces store image data.

[0052] First, a vertical synchronization signal is received (step S411), and it is determined whether the vertical synchronization signal is enabled (step S412). In one possible embodiment, when the vertical synchronization signal is enabled, the vertical synchronization signal is a low level. When the vertical synchronization signal is disabled (not enabled), the vertical synchronization signal is a high level. In another possible embodiment, when the vertical synchronization signal is enabled, the vertical synchronization signal is a high level. When the vertical synchronization signal is disabled, the vertical synchronization signal is a low level.

[0053] When the vertical synchronization signal is enabled, the values ​​of the first and second registers are swapped (step S413). In one possible embodiment, the first register stores a first access address, and the second register stores a second access address. In this example, one of the first and second access addresses points to the first storage space, and the other of the first and second access addresses points to the second storage space. For example, the first access address is the starting address of the first storage space, such as 0x10000, and the second access address is the starting address of the second storage space, such as 0x20000. In this example, after step S413, the first access address of the first register is the starting address of the second storage space, i.e., 0x20000, and the second access address of the second register is the starting address of the first storage space, such as 0x10000.

[0054] When the vertical synchronization signal is not enabled, the values ​​of the first and second registers are maintained (step S414). Assume that the first access address of the first register is equal to the starting address of the first storage space, such as 0x10000, and the second access address of the second register is equal to the starting address of the second storage space, such as 0x20000. After step S414, the first access address of the first register still equals the starting address of the first storage space, such as 0x10000, and the second access address of the second register still corresponds to the starting address of the second storage space, such as 0x20000.

[0055] Based on the value of the first register, an image signal is generated (step S415). In one possible embodiment, when the first access address of the first register points to the first storage space, step S415 reads the image data of the first storage space and generates an image signal based on the image data. In another possible embodiment, when the first access address of the first register points to the second storage space, step S415 reads the image data of the second storage space and generates an image signal based on the image data.

[0056] Figure 5 This is another schematic diagram of the control method of the present invention. First, the values ​​of the first and second registers are set (step S511). In one possible embodiment, the first access address of the first register points to the first storage space, and the second access address of the second register points to the second storage space. In some embodiments, the first access address of the first register is equal to the starting address of the first storage space, and the second access address of the second register is equal to the starting address of the second storage space.

[0057] In another possible instance, step S511 further sets a value for a format register. In this example, the value of the format register is related to the resolution of a display device and the color format displayed by the display device. For example, suppose the resolution of the display device is 320*240 and the color format displayed by the display device is RGB888. In this example, the value of the format register is 320*240*4.

[0058] Next, it is determined whether a vertical synchronization signal is enabled (step S512). In one possible embodiment, when the vertical synchronization signal is at a low level, it indicates that the vertical synchronization signal is enabled. When the vertical synchronization signal is enabled, it is determined whether the value of a third register is a first value (step S513). In one possible embodiment, the first value (or a preset value) is the value 1.

[0059] When the value of the third register is not the first value, image data from the corresponding storage space (e.g., the first storage space) is read according to the value of the first register (e.g., 0x10000) to generate an image signal (step S516). In one possible embodiment, the values ​​of the first and second registers remain unchanged. Then, the process returns to step S512, waiting for the vertical synchronization signal to be enabled again.

[0060] When the value of the third register is the first value, it indicates that the image data in the second storage space is ready. Therefore, the values ​​of the first and second registers are swapped (step S514). In one possible embodiment, before step S514, the value of the first register is 0x10000, and the value of the second register is 0x20000. After step S514, the value of the first register is 0x20000, and the value of the second register is 0x10000.

[0061] Next, the value of the third register is set to the second value (step S515). In one possible embodiment, the second value is 0. Then, based on the value of the first register (e.g., 0x20000), image data from the corresponding storage space (e.g., the second storage space) is read to generate an image signal. Then, the process returns to step S512, waiting for the vertical synchronization signal to be enabled again.

[0062] When the vertical synchronization signal is not enabled, it is determined whether the value of the third register is the second value (step S517). When the value of the third register is not the second value, the image data of the corresponding storage space (such as the second storage space) is read according to the value of the first register (such as 0x20000) to generate an image signal (step S516).

[0063] When the value of the third register is the second value, an update operation (step S518) is performed based on the value of the second register (e.g., 0x10000). In one possible embodiment, the update operation updates the image data in the storage space corresponding to the second register. For example, when the value of the second register points to the first storage space, step S518 updates the complete image data or part of the image data in the first storage space. When the value of the second register points to the second storage space, step S518 updates the complete image data or part of the image data in the second storage space.

[0064] Then, the value of the third register is set to the first value (step S519). At this time, the value of the third register may change from 0 (second value) to 1 (first value). Then, based on the value of the first register (e.g., 0x20000), the image data of the corresponding storage space (e.g., the second storage space) is read to generate an image signal (step S516). Next, return to step S512 to determine whether the vertical synchronization signal is enabled.

[0065] In this embodiment, when the value of the third register is a preset value (e.g., value 1) and the vertical synchronization signal is enabled, the values ​​of the first and second registers are swapped. Then, the corresponding image data is read according to the swapped value of the first register. In this example, when the value of the third register is not a preset value or the vertical synchronization signal is not enabled, the swapping of the values ​​of the first and second registers is paused. In a possible embodiment, after swapping the values ​​of the first and second registers, the value of the third register is set to be different from the preset value. At this time, the value of the third register may change from value 1 to value 0.

[0066] In other embodiments, when the vertical synchronization signal is not enabled, if the value of the third register is not a preset value (e.g., value 1), the image data in the first or second storage space is updated according to the value of the second register. For example, if the value of the second register is equal to the starting address of the first storage space, the new image data (or third image data) replaces the original complete image data (or first image data) stored in the first storage space, or replaces a portion of the image data in the first storage space. However, if the value of the second register is equal to the starting address of the second storage space, the new image data (or third image data) replaces the original complete image data (or second image data) stored in the second storage space, or replaces a portion of the image data in the second storage space. In this example, after writing new image data to the storage space specified by the second register, the value of the third register is set to the preset value.

[0067] In one possible embodiment, the amount of new image data is the same as the amount of first image data in the first storage space and also the same as the amount of second image data in the second storage space. For example, the amount of first to third image data is 320*240*4. In another possible embodiment, the amount of new image data is less than the amount of first image data in the first storage space and also less than the amount of second image data in the second storage space. In this example, the amount of first image data in the first storage space is the same as the amount of second image data in the second storage space.

[0068] It is important to understand that when a component or layer is mentioned as being "coupled" to another component or layer, it can be directly coupled or connected to the other component or layer, or have other components or layers interposed therein. Conversely, if a component or layer is "connected" to another component or layer, there will be no other component or layer interposed therein. Furthermore, "enable" should mean changing the state of a Boolean signal. A Boolean signal can be enabled to be high or have a higher voltage, and a Boolean signal can be enabled to be low or have a lower voltage at the discretion of the circuit designer. Similarly, "disable" should indicate changing the state of a Boolean signal to a voltage level opposite to its enabled state.

[0069] The control method, or a specific form or part thereof, of the present invention may exist in the form of program code. The program code may be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or may be a computer program product, not limited to an external form. When the program code is loaded and executed by a machine, such as a computer, that machine becomes a component of the microcontroller circuitry of the present invention. The program code may also be transmitted via transmission media, such as wires or cables, optical fibers, or any other transmission method. When the program code is received, loaded, and executed by a machine, such as a computer, that machine becomes a component of the microcontroller circuitry of the present invention. When implemented in a general-purpose processing unit, the program code, in conjunction with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0070] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their relevant technical field, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0071] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A microcontroller circuit, characterized in that, include: A memory, comprising a first storage space and a second storage space; An image processing circuit writes a first image data into the first storage space and a second image data into the second storage space. A first temporary register stores the starting address of the first storage space and one of the second storage spaces; A second temporary register stores the first storage space and another starting address of the second storage space; A control circuit, based on a vertical synchronization signal, exchanges the values ​​of the first and second temporary registers; and A display circuit reads image data from the first storage space or the second storage space based on the value of the first register. in: The image processing circuit updates the image data in the first storage space or the second storage space based on the value of the second register. When the value of the second register points to the first storage space, the image processing circuit writes third image data into the first storage space to replace and update the first storage space. When the value of the second register points to the second storage space, the image processing circuit writes the third image data into the second storage space to replace and update the second storage space.

2. The microcontroller circuit as described in claim 1, characterized in that, Including: A third temporary register, When the value of the third register is equal to a preset value and the vertical synchronization signal is enabled, the control circuit exchanges the values ​​of the first register and the second register.

3. The microcontroller circuit as described in claim 2, characterized in that, When the value of the third register is not equal to the preset value and the vertical synchronization signal is not enabled, the image processing circuit performs an update operation on the first image data or the second image data according to the value of the second register.

4. The microcontroller circuit as described in claim 3, characterized in that, When the value of the third register is not equal to the preset value and the value of the second register is the same as the starting address of the first storage space, the image processing circuit writes third image data to the first storage space. When the value of the third register is not equal to the preset value and the value of the second register is the same as the starting address of the second storage space, the image processing circuit writes the third image data to the second storage space.

5. The microcontroller circuit as described in claim 4, characterized in that, The first image data, the second image data, and the third image data all have the same data volume.

6. The microcontroller circuit as described in claim 1, characterized in that, When the value of the first register corresponds to the starting address of the first storage space, the display circuit reads the first image data; when the value of the first register corresponds to the starting address of the second storage space, the display circuit reads the second image data.

7. A control method, characterized in that, Applicable to a microcontroller circuit, the microcontroller circuit including a memory, a first temporary register and a second temporary register, the memory having a first storage space and a second storage space, the control method including: Receive a vertical synchronization signal; Based on the vertical synchronization signal, the values ​​of the first register and the second register are exchanged; When the value of the first register corresponds to the first storage space, an image signal is generated based on a first image data in the first storage space. When the value of the first register corresponds to the second storage space, the image signal is generated based on a second image data in the second storage space; Update the image data of the first storage space or the second storage space according to the value of the second register; When the value of the second register points to the first storage space, third image data is written to the first storage space to replace and update the first storage space; and When the value of the second register points to the second storage space, the image processing circuit writes the third image data into the second storage space to replace and update the second storage space.

8. The control method as described in claim 7, characterized in that, Including: Check the value of the third temporary register; When the value of the third register is a preset value and the vertical synchronization signal is enabled, the values ​​of the first register and the second register are swapped.

9. The control method as described in claim 8, characterized in that, Including: After the values ​​of the first and second temporary registers are exchanged, the value of the third temporary register is set to be different from the preset value.

10. An operating system, characterized in that, include: A display device that displays an image based on an image signal; as well as A microcontroller circuit, comprising: A memory, comprising a first storage space and a second storage space; An image processing circuit writes a first image data into the first storage space and a second image data into the second storage space. A first temporary register stores the starting address of one of the first and second storage spaces; A second temporary register stores another starting address of the first and second storage spaces; A control circuit, when a vertical synchronization signal is enabled and the value of a third register is a preset value, swaps the values ​​of the first and second registers; and A display circuit generates an image signal based on the first image data when the value of the first register corresponds to the first storage space, and generates an image signal based on the second image data when the value of the first register corresponds to the second storage space. in: The image processing circuit updates the image data in the first storage space or the second storage space based on the value of the second register. When the value of the second register points to the first storage space, the image processing circuit writes third image data into the first storage space to replace and update the first storage space. When the value of the second register points to the second storage space, the image processing circuit writes the third image data into the second storage space to replace and update the second storage space.

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