Sampling circuit in metastable state environment

Abstract

The invention relates to a sampling circuit in a metastable state environment. The sampling circuit comprises a first high-speed switch, a tracking memory circuit, a storage circuit and an output unit which are connected in sequence, the first high-speed switch receives to-be-sampled input data and a clock signal; the first high-speed switch is turned on under the low-level control of a clock signal, and at the moment, the tracking memory circuit is used for tracking the high-low level change of to-be-sampled input data in real time to generate tracking data; the first high-speed switch is switched off under the high-level control of a clock signal, and at the moment, the tracking memory circuit memorizes a level value of to-be-sampled input data before the first high-speed switch is switched off to generate memory data; the tracking memory circuit outputs tracking data and memory data to the storage unit; the storage circuit receives a clock signal, collects, stores and tracks an output signal of the memory circuit under the control of the clock signal and outputs the output signal to the output unit; and the output unit is used for increasing the driving capability of the output signal of the storage circuit and realizing the acquisition of the to-be-sampled input data.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a sampling circuit in a metastable environment. Background Art

[0002] In current sampling circuits, a large number of D flip-flops are used as sampling storage units. The input signals of the D flip-flops include the clock input signal CLK and the input data. During the rising edge of CLK, the D flip-flop samples the input data and outputs the sampled data to the output pin Q after a specific delay. Due to the structural characteristics of the existing D flip-flops, in order to ensure the correctness of the sampled data, CLK and D are required to meet the timing relationship of setup time and hold time.

[0003] The setup time and hold time requirements of the D flip-flop determine that reliable sampling cannot be performed in a metastable environment. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a sampling circuit in a metastable environment, so as to solve the problem that the existing integrated circuit cannot perform reliable sampling in a metastable environment.

[0005] An embodiment of the present invention provides a sampling circuit in a metastable environment, the sampling circuit comprising a first high-speed switch, a tracking memory circuit, a storage circuit, and an output unit connected in sequence;

[0006] The first high-speed switch receives input data to be sampled and a clock signal; the first high-speed switch is turned on under the control of a low level of the clock signal, and at this time, the tracking memory circuit is used to track the high and low level changes of the input data to be sampled in real time to generate tracking data; the first high-speed switch is turned off under the control of a high level of the clock signal, and at this time, the tracking memory circuit memorizes the level value of the input data to be sampled before the first high-speed switch is turned off to generate memory data; the tracking memory circuit outputs the tracking data and the memory data to the storage unit;

[0007] The storage circuit receives the clock signal, and under the control of the clock signal, the storage circuit collects and stores the output signal of the tracking memory circuit and outputs it to the output unit;

[0008] The output unit is used to increase the driving capability of the storage circuit output signal and realize the collection of the input data to be sampled.

[0009] Furthermore, the storage circuit includes a first delay circuit, a first pulse generator, a second high-speed switch, and a storage unit connected in sequence; the input end of the second high-speed switch receives the output data of the tracking memory circuit; the first delay circuit is used to receive a clock signal and generate a first delay signal; the first pulse generator generates a first pulse signal under the control of the first delay signal, and the first pulse signal realizes the control of the on and off of the second high-speed switch, and the output end of the second high-speed switch is connected to the storage unit; the storage unit is used to realize the storage function of the output data of the second high-speed switch.

[0010] Furthermore, the tracking memory circuit is a low-power tracking memory circuit; the low-power tracking memory circuit includes a control unit, a transmission branch, and a feedback branch; the transmission branch includes a first NOT gate and a first switch circuit connected in sequence; the feedback branch includes a second NOT gate and a second switch circuit connected in sequence; the second NOT gate output end is connected to the second switch circuit input end, and the first NOT gate input end of the transmission branch is connected to the second switch circuit output end of the feedback branch; the first switch circuit output end of the transmission branch is connected to the second NOT gate input end of the feedback branch, and the first NOT gate output end is connected to the first switch circuit input end; the control unit is used to control the on and off of the first switch circuit and the second switch circuit; when the first switch circuit and the second switch circuit are connected, the low-power tracking memory circuit is used to generate memory data; when the first switch circuit and the second switch circuit are disconnected, the low-power tracking memory circuit is used to generate tracking data.

[0011] Furthermore, the control unit includes a second delay circuit and a logic circuit; the logic circuit includes a third NOT gate; the third NOT gate receives a clock signal and generates an inverted phase signal of the clock signal; the second delay circuit is used to delay the input clock signal and the inverted phase signal of the clock signal for a preset time, and output a control signal for the first switch circuit and the second switch circuit.

[0012] Furthermore, starting from the falling edge of the clock signal, the control unit disconnects the first switch circuit and the second switch circuit; before the rising edge of the clock signal arrives, the control unit controls the first switch circuit and the second switch circuit to close, and the second preset time is greater than the maximum value of the delay time of the first NOT gate and the second NOT gate.

[0013] Furthermore, the storage unit includes a fourth NOT gate and a fifth NOT gate; the input end of the fourth NOT gate is connected to the output end of the second high-speed switch; the output end of the fourth NOT gate is connected to the input end of the fifth NOT gate; the output end of the fifth NOT gate is connected to the output end of the second high-speed switch; the pulse width of the first pulse signal is not less than the delay time of the fourth NOT gate and not greater than T / 2-Δt1-Δt2, where T is the period of the clock signal, Δt1 is the delay of the storage circuit, and Δt2 is the delay of the output unit.

[0014] Furthermore, the sampling circuit also includes a third high-speed switch; the first high-speed switch input end is used to receive a positive end of a pair of differential input data to be sampled and a clock signal; the third high-speed switch input end is used to receive a negative end of a pair of differential input data to be sampled and a clock signal; the third high-speed switch output end is connected to the input end of the second NOT gate in the feedback branch of the low-power tracking memory circuit, and the first high-speed switch output end is connected to the input end of the first NOT gate in the transmission branch of the low-power tracking memory circuit.

[0015] Furthermore, the storage circuit also includes a third delay circuit, a second pulse generator, and a fourth high-speed switch connected in sequence; the third delay circuit is the same as the first delay circuit, the second pulse generator is the same as the first pulse generator, and the fourth high-speed switch is the same as the second high-speed switch; the input end of the third delay circuit is connected to the negative end of the clock differential signal to generate a third delay signal; the input end of the fourth high-speed switch is connected to the input end of the second NOT gate in the feedback branch of the low-power tracking memory circuit; the output end of the fourth high-speed switch is connected to the input end of the fifth NOT gate of the storage unit; the second pulse generator generates a second pulse signal under the control of the third delay signal, and the second pulse signal realizes the control of the on and off of the fourth high-speed switch.

[0016] Furthermore, the first to fourth high-speed switches, the first switch circuit, and the second switch circuit each include an NMOS field effect transistor and a PMOS field effect transistor.

[0017] Furthermore, the gate of the first high-speed switch NMOS field effect tube is connected to the signal of the clock signal after being inverted by the NOT gate; and the gate of the PMOS field effect tube is connected to the clock signal.

[0018] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0019] 1. A sampling circuit in a metastable environment of the present invention adopts a first high-speed switch, a tracking memory circuit, a storage circuit, and an output unit. It can reliably sample input data to be sampled in a metastable environment, and does not require the input data to be sampled to meet the timing relationship of setup time and hold time with the input clock, thereby solving the problem of reliable sampling in a metastable environment.

[0020] 2. A low-power tracking memory circuit of a sampling circuit in a metastable environment of the present invention includes a control unit, a transmission branch, and a feedback branch; the transmission branch includes a first NOT gate and a first switch circuit connected in sequence; the feedback branch includes a second NOT gate and a second switch circuit connected in sequence; the control unit includes a second delay circuit and a logic circuit; the control unit inputs a clock signal and outputs a control signal for the first and second switch circuits. Starting from the falling edge of the input clock signal, the control unit turns off the first and second switch circuits, at which time the low-power tracking memory unit can only realize the tracking function of the input signal and does not have a memory function; before the rising edge of the input clock signal arrives, the control unit controls the first and second switch circuits to open, at which time the low-power tracking memory unit has a memory function, and realizes the level memory of the input data to be sampled before the first high-speed switch unit is disconnected. At the same time, since the low-power tracking memory unit does not have a memory function when the input clock signal is at a low level, the power consumption of this part of the circuit is reduced. The low-power tracking memory circuit realizes a low-power and reliable metastable sampling circuit.

[0021] 3. The storage circuit of a sampling circuit in a metastable environment of the present invention comprises a delay circuit, a pulse generator, a high-speed switch, and a storage unit connected in sequence; wherein the delay circuit is used to realize a predetermined delay to ensure that the output signal of the low-power tracking memory circuit is stable at the moment when the high-speed switch is turned on; the pulse generator is used to generate a pulse signal, and the pulse signal controls the on and off of the high-speed switch to realize the sampling of the output signal of the low-power tracking memory circuit; the storage unit is used to realize the storage function of the sampled signal. The storage circuit realizes the stable sampling and storage of the output data of the low-power tracking memory unit.

[0022] 4. A sampling circuit in a metastable environment of the present invention can be used to receive a single-ended signal of input data to be sampled or a differential signal of input data to be sampled; when receiving a differential signal of input data to be sampled, a third high-speed switch needs to be added on the basis of the circuit for receiving the single-ended signal, and the third high-speed switch is used to receive the negative end and the clock signal of the differential signal of the input data to be sampled, and send the output negative end signal to the input end of the second NOT gate of the feedback branch of the low-power tracking memory circuit; a pair of differential signals output by the feedback branch of the low-power tracking memory circuit are sent to the storage circuit, and the storage circuit adds a third delay circuit, a second pulse generator, and a fourth high-speed switch. This design accelerates the speed of sampling and storing data in a metastable environment.

[0023] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0025] Figure 1 A diagram showing the structure of a sampling circuit in a metastable environment;

[0026] Figure 2 It is a timing diagram of the sampling circuit in a metastable environment;

[0027] Figure 3 A diagram of first to fourth high-speed switches, a first switch circuit and a second switch circuit of a sampling circuit in a metastable environment;

[0028] Figure 4 A circuit diagram for tracking memory of a sampling circuit in a metastable environment;

[0029] Figure 5 A low power tracking memory circuit diagram for a sampling circuit in a metastable environment;

[0030] Figure 6 A schematic diagram of the connection of a sampling circuit storage circuit in a metastable environment. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0032] A specific embodiment of the present invention discloses a sampling circuit in a metastable environment, such as Figure 1 As shown, the sampling circuit includes a first high-speed switch, a tracking memory circuit, a storage circuit, and an output unit connected in sequence;

[0033] The first high-speed switch receives input data to be sampled and a clock signal; the first high-speed switch is turned on under the control of a low level of the clock signal, and at this time, the tracking memory circuit is used to track the high and low level changes of the input data to be sampled in real time to generate tracking data; the first high-speed switch is turned off under the control of a high level of the clock signal, and at this time, the tracking memory circuit memorizes the level value of the input data to be sampled before the first high-speed switch is turned off to generate memory data; the tracking memory circuit outputs the tracking data and the memory data to the storage unit;

[0034] The storage circuit receives the clock signal, and under the control of the clock signal, the storage circuit collects and stores the output signal of the tracking memory circuit and outputs it to the output unit;

[0035] The output unit is used to increase the driving capability of the storage circuit output signal and realize the collection of the input data to be sampled.

[0036] Specifically, the input data to be sampled can be a single-ended signal or a differential signal. In the case of using a differential signal, faster and more accurate signal sampling can be achieved. When receiving the differential signal of the input data to be sampled, it is necessary to add a third high-speed switch on the basis of the circuit receiving the single-ended signal. The third high-speed switch is used to receive the negative end signal and the clock signal of the differential signal of the input data to be sampled, and output it to the input end of the second NOT gate of the feedback branch of the low-power tracking memory circuit. The positive and negative signals of a pair of differential signals output by the low-power tracking memory circuit are respectively sent to Figure 6 The second high-speed switch and the fourth high-speed switch input terminals of the storage circuit shown in the figure. This design for differential signals speeds up the speed of sampling and storing data in a metastable environment.

[0037] The sampling circuit also includes a third high-speed switch; the first high-speed switch input end is used to receive a positive end of a pair of differential input data to be sampled and a clock signal; the third high-speed switch input end is used to receive a negative end of a pair of differential input data to be sampled and a clock signal; the third high-speed switch output end is connected to the input end of the second NOT gate in the feedback branch of the low-power tracking memory circuit, and the first high-speed switch output end is connected to the input end of the first NOT gate in the transmission branch of the low-power tracking memory circuit.

[0038] like Figure 3 As shown, the first high-speed switch includes an NMOS field effect transistor and a PMOS field effect transistor.

[0039] Specifically, the substrate of the NMOS field effect tube is grounded, and the substrate of the PMOS field effect tube is connected to the power supply. The input ends of the NMOS field effect tube and the PMOS field effect tube are connected (in this design, either the source or the drain can be used as the input end), and the output ends are connected; the gate ON of the NMOS field effect tube receives the anti-phase signal of the clock signal; the gate of the PMOS field effect tube receives the clock signal. When the ON receiving signal is high and the ON# receiving signal is low, IN and OUT are connected; when ON is low and ON# is high, IN and OUT are disconnected. In order to ensure the consistency of the opening of PMOS and NMOS, the size of PMOS and NMOS needs to be adjusted to ensure that the on-resistance of PMOS and NMOS is consistent when the input data to be sampled is at an intermediate level; at the same time, in order to ensure the accuracy of the sampling time, the phase difference of the ON and ON# receiving signals is required to be 180°; since the tube with a short channel length has a fast conduction speed, the embodiment of the present invention adopts the tube with the shortest channel length in the relevant process to achieve the high speed of the first high-speed switch.

[0040] The gate of the first high-speed switch NMOS field effect tube is connected to the signal after the clock signal is inverted by the NOT gate; the gate of the PMOS field effect tube is connected to the clock signal.

[0041] The first to fourth high-speed switches, the first switch circuit and the second switch circuit each include an NMOS field effect transistor and a PMOS field effect transistor.

[0042] Specifically, the first to fourth high-speed switches, the first switch circuit, and the second switch circuit may all adopt the same structure as the first high-speed switch.

[0043] The tracking memory circuit is a low-power tracking memory circuit; the low-power tracking memory circuit includes a control unit, a transmission branch, and a feedback branch; the transmission branch includes a first NOT gate and a first switch circuit connected in sequence; the feedback branch includes a second NOT gate and a second switch circuit connected in sequence; the second NOT gate output end is connected to the second switch circuit input end, and the first NOT gate input end of the transmission branch is connected to the second switch circuit output end of the feedback branch; the first switch circuit output end of the transmission branch is connected to the second NOT gate input end of the feedback branch, and the first NOT gate output end is connected to the first switch circuit input end; the control unit is used to control the first switch circuit and the second switch circuit to be turned on and off; when the first switch circuit and the second switch circuit are connected, the low-power tracking memory circuit is used to generate memory data; when the first switch circuit and the second switch circuit are disconnected, the low-power tracking memory circuit is used to generate tracking data.

[0044] Specifically, the tracking memory circuit can be used as follows Figure 4 The circuit shown in the figure is realized by two NOT gates connected end to end, or it can be realized by Figure 5 The low-power tracking memory circuit implementation shown.

[0045] The two NOT gates are connected end to end to form positive feedback to realize the memory function. In order to realize the tracking function, the driving capability of the two NOT gates is required to be much weaker than the driving capability of the input data Din to be sampled, so that the target of Din can be tracked by the tracking memory circuit.

[0046] When the input data Din to be sampled is a single-ended signal, only use Figure 4 and Figure 5 In the figure, DP serves as the input and output ends of the input data to be sampled; when the input data Din to be sampled is a differential signal, DP and DN both serve as the input and output ends of a pair of differential signals of the input data Din to be sampled, DP is the input and output end of the differential positive signal, and DN is the input and output end of the differential negative signal (the input and output ends are multiplexed).

[0047] When the first high-speed switch and the third high-speed switch are closed, the tracking memory circuit tracks the output signals of the first high-speed switch and the third high-speed switch. Since the output signal generated by the tracking memory circuit under the non-gate drive is much weaker than the output signals of the first high-speed switch and the third high-speed switch, the signal levels of DP and DN are respectively determined by the output signals of the first high-speed switch and the third high-speed switch; when the input data to be sampled is cut off by the first high-speed switch and the third high-speed switch, due to the existence of positive feedback, the tracking memory circuit will restore the level of the tracking signal before the cut-off and maintain the level value at that moment.

[0048] In the tracking memory circuit, the input signal and output signal of the tracking memory circuit are connected together, which increases the power consumption. In order to reduce the power consumption, the Figure 5 The low-power tracking memory circuit optimizes power consumption. Accurate control of the tracking memory circuit is achieved by adding a control unit, a first switch circuit, and a second switch circuit. The control unit receives the input clock signal Clk and outputs a control signal for the NMOS field effect transistors in the first switch circuit and the second switch circuit through the second delay circuit in the control unit. The third NOT gate of the control unit generates an inverted phase signal of the clock signal. The inverted phase signal of the clock signal controls the PMOS field effect transistors in the first switch circuit and the second switch circuit after passing through the second delay circuit. Starting from the falling edge of the clock signal Clk, the control unit turns off the first switch circuit and the second switch circuit. At this time, the tracking memory circuit can only realize the tracking function of the input signal and does not have a memory function; before the rising edge of Clk arrives, the control unit controls the first switch circuit and the second switch circuit to open. At this time, the tracking memory unit has a memory function, which can realize the level memory of the input signal at the moment before the first high-speed switch and the third high-speed switch are disconnected. At the same time, since the tracking memory circuit does not have a memory function when Clk is at a low level, the power consumption of this part of the circuit is reduced.

[0049] The first switch circuit and the second switch circuit can use a general transmission gate (such as Figure 3 The control unit can be implemented using a second delay circuit and a logic circuit. In the embodiment of the present invention, the opening and closing signals of the first switch circuit and the second switch circuit use a synchronous control signal.

[0050] The control unit includes a second delay circuit and a logic circuit; the logic circuit includes a third NOT gate; the third NOT gate receives a clock signal and generates an inverted phase signal of the clock signal; the second delay circuit is used to delay the input clock signal and the inverted phase signal of the clock signal for a preset time, and output a control signal for the first switch circuit and the second switch circuit.

[0051] Starting from the falling edge of the clock signal, the control unit disconnects the first switch circuit and the second switch circuit; before the rising edge of the clock signal arrives, the control unit controls the first switch circuit and the second switch circuit to close at a second preset time, and the second preset time is greater than the maximum value of the delay time of the first NOT gate and the second NOT gate.

[0052] Specifically, the tracking memory circuit should enter the memory state before the next closing of the first and third high-speed switch units and transfer the memory data to the memory unit in the memory circuit before the next Clk low level comes.

[0053] The storage circuit includes a first delay circuit, a first pulse generator, a second high-speed switch, and a storage unit connected in sequence; the input end of the second high-speed switch receives the output data of the tracking memory circuit; the first delay circuit is used to receive a clock signal and generate a first delay signal; the first pulse generator generates a first pulse signal under the control of the first delay signal, and the first pulse signal realizes the control of the on and off of the second high-speed switch, and the output end of the second high-speed switch is connected to the storage unit; the storage unit is used to realize the storage function of the output data of the second high-speed switch.

[0054] Specifically, the storage circuit is used to implement the storage function of the output data of the tracking memory circuit. The storage is completed Δt1 after the Clk rising edge, and released at the next Clk rising edge. There are many ways to implement the storage circuit. For some applications where the sampling clock Clk frequency is not too high, but the frequency of the sampled data Din is extremely high, the storage circuit can be implemented using a general D flip-flop. However, for the use of extremely high sampling clock Clk, a high-speed storage circuit is required.

[0055] A high-speed storage circuit implementation method based on a differential input signal to be sampled is as follows Figure 6 shown.

[0056] The storage circuit also includes a third delay circuit, a second pulse generator, and a fourth high-speed switch connected in sequence; the third delay circuit is the same as the first delay circuit, the second pulse generator is the same as the first pulse generator, and the fourth high-speed switch is the same as the second high-speed switch; the input end of the third delay circuit is connected to the negative end of the clock differential signal to generate a third delay signal; the input end of the fourth high-speed switch is connected to the input end of the second NOT gate in the feedback branch of the low-power tracking memory circuit; the output end of the fourth high-speed switch is connected to the input end of the fifth NOT gate of the storage unit; the second pulse generator generates a second pulse signal under the control of the third delay signal, and the second pulse signal realizes the control of the on and off of the fourth high-speed switch.

[0057] Specifically, the high-speed storage circuit includes a first and a third delay circuit, a first and a second pulse generator, a second and a fourth high-speed switch, and a storage unit, wherein the first and the third delay circuits are used to realize a Δt1-t3 delay, t3 is the sum of the delay of the first (or second) pulse generator and the delay of the second (or fourth) high-speed switch, to ensure that the input signals Din_P and Din_N are stable at the moment the second and fourth high-speed switches are turned on; the first and the second pulse generators are both used to generate a pulse signal, and the two pulse signals control the second and the fourth high-speed switches to realize the sampling of the input signals Din_P and Dout_N, requiring that the pulse width is not less than the delay time of a non-gate in the storage unit, and not greater than T / 2-Δt1-Δt2 time, wherein T is the period of the clock signal, Δt1 is the delay of the storage circuit, and Δt2 is the delay of the output unit; the storage unit is used to realize the storage function of the sampled signal.

[0058] The storage unit includes a fourth NOT gate and a fifth NOT gate; the input end of the fourth NOT gate is connected to the output end of the second high-speed switch; the output end of the fourth NOT gate is connected to the input end of the fifth NOT gate; the output end of the fifth NOT gate is connected to the output end of the second high-speed switch; the pulse width of the first pulse signal is not less than the delay time of the fourth NOT gate and not greater than T / 2-Δt1-Δt2, where T is the period of the clock signal, Δt1 is the delay of the storage circuit, and Δt2 is the delay of the output unit.

[0059] Specifically, the output unit is used to increase the driving capability of the storage circuit to achieve normal driving of the subsequent circuit of the sampling circuit. The output unit can be formed by cascading NOT gates with increasing W / L.

[0060] The second and fourth high-speed switches adopt Figure 3 Circuit implementation, Figure 5 Medium DP connection Figure 6 Medium DIN_P, Figure 5 Medium DN connection Figure 6 Medium DIN_N.

[0061] The sampling circuit timing diagram is as follows: Figure 2 As shown. When the clock signal Clk is at a low level, the first high-speed switch unit collects the input data Din to be sampled and outputs D1 to the tracking memory unit, and the tracking memory unit tracks the change of the D1 signal; when Clk is at a high level, the first high-speed switch unit is turned off and does not collect the input data Din to be sampled. The tracking memory unit memorizes and maintains the level of D1 before the first high-speed switch is turned off, and outputs it to the storage circuit; the storage circuit outputs D3 after a delay of Δt1 at the rising edge of Clk, and D3 is then output to Dout after a delay of Δt2 by the output unit, and finally the sampling process is completed.

[0062] Compared with the prior art, the sampling circuit in a metastable environment provided by the present embodiment adopts the architecture of the first high-speed switch, the tracking memory circuit, the storage circuit, and the output unit, which can reliably sample the input data to be sampled in the metastable environment, and does not require the timing relationship between the input data to be sampled and the input clock to meet the setup time and the hold time, thereby solving the problem of reliable sampling in the metastable environment. The low-power tracking memory circuit of the sampling circuit in a metastable environment provided by the present embodiment includes a control unit, a transmission branch, and a feedback branch; the transmission branch includes a first NOT gate and a first switch circuit connected in sequence; the feedback branch includes a second NOT gate and a second switch circuit connected in sequence; the control unit includes a second delay circuit and a logic circuit; the control unit inputs a clock signal and outputs a control signal for the first and second switch circuits. Starting from the falling edge of the input clock signal, the control unit turns off the first and second switch circuits, at which time the low-power tracking memory unit can only realize the tracking function of the input signal and does not have a memory function; before the rising edge of the input clock signal arrives, the control unit controls the first and second switch circuits to be opened, at which time the low-power tracking memory unit has a memory function, realizing the level memory of the input data to be sampled before the moment when the first high-speed switch unit is disconnected. At the same time, since the low-power tracking memory unit does not have a memory function when the input clock signal is at a low level, the power consumption of this part of the circuit is reduced. A low-power, reliable metastable sampling circuit is realized. The storage circuit of a sampling circuit in a metastable environment provided in this embodiment includes a delay circuit, a pulse generator, a high-speed switch, and a storage unit connected in sequence; wherein the delay circuit is used to realize a predetermined delay to ensure that the output signal of the low-power tracking memory circuit is stable at the moment the high-speed switch is turned on; the pulse generator is used to generate a pulse signal, and the pulse signal controls the on and off of the high-speed switch to realize the sampling of the output signal of the low-power tracking memory circuit; the storage unit is used to realize the storage function of the sampled signal. The storage circuit realizes stable sampling and storage of the output data of the low-power tracking memory unit. The sampling circuit in a metastable environment provided by the present embodiment can be used to receive a single-ended signal of input data to be sampled or a differential signal of input data to be sampled; when receiving a differential signal of input data to be sampled, a third high-speed switch needs to be added on the basis of the circuit receiving the single-ended signal, and the third high-speed switch is used to receive the negative end and the clock signal of the differential signal of the input data to be sampled, and send the output negative end signal to the input end of the second NOT gate of the feedback branch of the low-power tracking memory circuit; a pair of differential signals output by the feedback branch of the low-power tracking memory circuit are sent to the storage circuit, and the storage circuit is added with a third delay circuit, a second pulse generator, and a fourth high-speed switch. This design accelerates the speed of sampling and storing data in a metastable environment.

[0063] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0064] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A sampling circuit in a metastable environment, characterized in that: The sampling circuit includes a first high-speed switch, a tracking memory circuit, a storage circuit, and an output unit connected in sequence; The first high-speed switch receives input data to be sampled and a clock signal; the first high-speed switch is opened under the control of a low level of the clock signal, and at this time, the tracking memory circuit is used to track the high and low level changes of the input data to be sampled in real time to generate tracking data; the first high-speed switch is disconnected under the control of a high level of the clock signal, and at this time, the tracking memory circuit memorizes the level value of the input data to be sampled before the first high-speed switch is disconnected to generate memory data; The tracking memory circuit outputs the tracking data and the memory data to the storage unit; The storage circuit receives the clock signal, and under the control of the clock signal, the storage circuit collects and stores the output signal of the tracking memory circuit and outputs it to the output unit; The output unit is used to increase the driving capability of the storage circuit output signal and realize the collection of the input data to be sampled.

2. The sampling circuit according to claim 1, characterized in that: The storage circuit includes a first delay circuit, a first pulse generator, a second high-speed switch, and a storage unit connected in sequence; the input end of the second high-speed switch receives the output data of the tracking memory circuit; the first delay circuit is used to receive a clock signal and generate a first delay signal; The first pulse generator generates a first pulse signal under the control of the first delay signal, and the first pulse signal realizes the control of the on and off of the second high-speed switch. The output end of the second high-speed switch is connected to the storage unit; the storage unit is used to realize the storage function of the output data of the second high-speed switch.

3. The sampling circuit according to claim 2, characterized in that: The tracking memory circuit is a low-power tracking memory circuit; the low-power tracking memory circuit includes a control unit, a transmission branch, and a feedback branch; the transmission branch includes a first NOT gate and a first switch circuit connected in sequence; the feedback branch includes a second NOT gate and a second switch circuit connected in sequence; The second NOT gate output end is connected to the second switch circuit input end, the first NOT gate input end of the transmission branch is connected to the second switch circuit output end of the feedback branch; the first switch circuit output end of the transmission branch is connected to the second NOT gate input end of the feedback branch, and the first NOT gate output end is connected to the first switch circuit input end; the control unit is used to control the first switch circuit and the second switch circuit to be turned on and off; when the first switch circuit and the second switch circuit are connected, the low-power tracking memory circuit is used to generate memory data; When the first switch circuit and the second switch circuit are disconnected, the low power consumption trace memory circuit is used to generate trace data.

4. The sampling circuit according to claim 3, characterized in that: The control unit includes a second delay circuit and a logic circuit; the logic circuit includes a third NOT gate; the third NOT gate receives a clock signal and generates an inverted phase signal of the clock signal; the second delay circuit is used to delay the input clock signal and the inverted phase signal of the clock signal for a preset time, and output a control signal for the first switch circuit and the second switch circuit.

5. The sampling circuit according to claim 4, characterized in that: Starting from the falling edge of the clock signal, the control unit disconnects the first switch circuit and the second switch circuit; before the rising edge of the clock signal arrives, the control unit controls the first switch circuit and the second switch circuit to close at a second preset time, and the second preset time is greater than the maximum value of the delay time of the first NOT gate and the second NOT gate.

6. The sampling circuit according to claim 3, characterized in that: The storage unit includes a fourth NOT gate and a fifth NOT gate; the input end of the fourth NOT gate is connected to the output end of the second high-speed switch; the output end of the fourth NOT gate is connected to the input end of the fifth NOT gate; the output end of the fifth NOT gate is connected to the output end of the second high-speed switch; the pulse width of the first pulse signal is not less than the delay time of the fourth NOT gate and not greater than T / 2-Δt1-Δt2, where T is the period of the clock signal, Δt1 is the delay of the storage circuit, and Δt2 is the delay of the output unit.

7. The sampling circuit according to claim 6, characterized in that: The sampling circuit also includes a third high-speed switch; the first high-speed switch input end is used to receive a positive end of a pair of differential input data to be sampled and a clock signal; the third high-speed switch input end is used to receive a negative end of a pair of differential input data to be sampled and a clock signal; the third high-speed switch output end is connected to the input end of the second NOT gate in the feedback branch of the low-power tracking memory circuit, and the first high-speed switch output end is connected to the input end of the first NOT gate in the transmission branch of the low-power tracking memory circuit.

8. The sampling circuit according to claim 7, characterized in that: The storage circuit also includes a third delay circuit, a second pulse generator, and a fourth high-speed switch connected in sequence; the third delay circuit is the same as the first delay circuit, the second pulse generator is the same as the first pulse generator, and the fourth high-speed switch is the same as the second high-speed switch; the input end of the third delay circuit is connected to the negative end of the clock differential signal to generate a third delay signal; the input end of the fourth high-speed switch is connected to the input end of the second NOT gate in the feedback branch of the low-power tracking memory circuit; the output end of the fourth high-speed switch is connected to the input end of the fifth NOT gate of the storage unit; the second pulse generator generates a second pulse signal under the control of the third delay signal, and the second pulse signal realizes the control of the on and off of the fourth high-speed switch.

9. The sampling circuit according to claims 1 to 8, characterized in that: The first to fourth high-speed switches, the first switch circuit and the second switch circuit each include an NMOS field effect transistor and a PMOS field effect transistor.

10. The sampling circuit according to claim 9, characterized in that: The gate of the first high-speed switch NMOS field effect tube is connected to the signal after the clock signal is inverted by the NOT gate; the gate of the PMOS field effect tube is connected to the clock signal.

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