Flash type quantizer for Delta-Sigma modulator and control method of Flash type quantizer

Abstract

The invention provides a Flash type quantizer for a Delta-Sigma modulator and a control method thereof, and the quantizer comprises a reference voltage scrambling module which is used for sequentially scrambling a plurality of pairs of differential reference voltage output obtained through voltage division of a resistor array and then outputting a target reference voltage pair; a plurality of comparators, each comparator receiving a differential input voltage and the target reference voltage pair to obtain a comparison result, and controlling a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, the differential input voltage being an output voltage of the loop filter, and the target reference voltage pair being an output voltage of the Delta-Sigma modulator. The logarithm of the differential reference voltage corresponds to the number of the comparators; the plurality of chopping modules are used for exchanging input end signals of the comparators and then inputting the signals into the corresponding comparators so as to eliminate offset voltages of the comparators, and the chopping modules and the comparators are arranged in a one-to-one correspondence mode. The power consumption can be effectively reduced, and the overall performance of the circuit is improved.

Description

Technical Field

[0001] The invention relates to the field of digital-analog hybrid integrated circuit design, and in particular to a Flash type quantizer for a Delta-Sigma modulator and a control method thereof. Background Art

[0002] Delta-Sigma analog-to-digital converter structures are widely used in high-precision applications. In the design of Delta-Sigma analog-to-digital converter circuits, quantizers are a key link. The speed and accuracy of quantizers determine the effective bandwidth and effective conversion bit number of the analog-to-digital converter. Flash quantizers are high-speed quantization circuits based on comparators, and the key lies in the design of comparators. However, existing quantizers generally use process adjustment or calibration circuits to improve DAC mismatch, which has the problems of complex circuits and high power consumption. Summary of the invention

[0003] In view of the above problems existing in the prior art, the present invention proposes a Flash type quantizer for Delta-Sigma modulator and a control method thereof, which mainly solves the problem that the existing quantizer DAC mismatch improvement method relies on complex circuit structure, has high power consumption and affects the overall performance of the circuit.

[0004] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0005] The present application provides a Flash type quantizer for a Delta-Sigma modulator, comprising: a reference voltage scrambling module, which is used to sequentially scramble multiple pairs of differential reference voltage outputs obtained by resistor array voltage division and then output a target reference voltage pair; a plurality of comparators, each of which receives a differential input voltage and the target reference voltage pair to obtain a comparison result, and controls a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the logarithm of the differential reference voltage corresponds to the number of the comparators; and a plurality of chopping modules, which are used to exchange the input terminal signals of the comparators and then input them into the corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopping modules are arranged in a one-to-one correspondence with the comparators.

[0006] In one embodiment of the present application, the reference voltage scrambling module includes: a plurality of delay elimination units, which receive a multi-bit input control signal and generate a corresponding output control signal pair, wherein the delay elimination unit eliminates the delay between the output control signal pairs through a cross-coupling structure; wherein the number of bits of the input control signal corresponds to the number of the output control signal pairs and the comparators; a switch array, which receives the output control signal pair to control the transmission relationship between the plurality of pairs of differential reference voltages obtained by voltage division of the resistor array and the target reference voltage pair, and polls the multi-bit input control signal in an interval polling manner to adjust the output order of the target reference voltage pairs.

[0007] In one embodiment of the present application, the delay elimination unit includes: a delay device, a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, the input end of the delay device is connected to the gate of the second NMOS tube as the input end of the delay elimination unit, and is connected to the input control signal; the output end of the delay device is connected to the gate of the first NMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are grounded; the drain of the first NMOS tube is connected to the source of the first PMOS tube as the first output end of the delay elimination unit; the drain of the second NMOS tube is connected to the source of the first PMOS tube as the second output end of the delay elimination unit; the gate of the first PMOS tube is connected to the source of the second PMOS tube, and the gate of the second PMOS tube is connected to the source of the first PMOS tube to form the cross-coupling structure; the drain of the first PMOS tube and the drain of the second PMOS tube are respectively connected to the power supply voltage; wherein the output control signal of the second output end is the inverted signal of the output control signal of the first output end.

[0008] In one embodiment of the present application, the switch array includes a plurality of switch units, wherein the number of the switch units is the square of the number of the delay elimination units; each of the switch units includes a third NMOS tube, a fourth NMOS tube, a third PMOS tube and a fourth PMOS tube, the source of the third NMOS tube is connected to the source of the third PMOS tube as the first input end of the switch unit, and the drain of the third NMOS tube is connected to the drain of the third PMOS tube as the first output end of the switch unit; the source of the fourth NMOS tube is connected to the source of the fourth PMOS tube as the second input end of the switch unit, and the drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube as the second output end of the switch unit; the gate of the third NMOS tube is connected to the first output end of the delay elimination unit as the first control end of the switch unit; the gate of the fourth NMOS tube is connected to the first output end of the delay elimination unit as the second control end of the switch unit; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube as the fifth control end of the switch unit connected to the second output end of the delay elimination unit.

[0009] In one embodiment of the present application, the chopping module includes a first chopping unit, a second chopping unit, a third chopping unit, a fourth chopping unit and a fifth chopping unit; the first input terminal of the first chopping unit is connected to a first input voltage, the second input terminal is connected to a first reference voltage, the first output terminal is connected to the first input terminal of the second chopping unit, and the second output terminal is connected to the first input terminal of the fourth chopping unit; the first input terminal of the third chopping unit is connected to a second reference voltage, the second input terminal is connected to a second input voltage, the first output terminal is connected to the second input terminal of the second chopping unit, and the second output terminal is connected to the second input terminal of the fourth chopping unit; the second chopping unit The two output ends of the first chopping unit and the two output ends of the fourth chopping unit are respectively connected to the corresponding input ends of the comparator; the first input end and the second input end of the fifth chopping unit are connected to the corresponding output ends of the comparator, and the two output ends of the fifth chopping unit output the comparison result, wherein the first chopping unit and the third chopping unit are controlled by a first clock signal, and the second chopping unit, the fourth chopping unit and the fifth chopping unit are all controlled by a second clock signal; the first input voltage and the second input voltage form a pair of differential input voltages, and the first reference voltage and the second reference voltage form a pair of target reference voltages.

[0010] In one embodiment of the present application, the circuit structures of the first chopping unit, the second chopping unit, the third chopping unit, the fourth chopping unit and the fifth chopping unit are the same, and the first chopping unit includes: a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube as the first input end of the first chopping unit, the drain is connected to the drain of the seventh NMOS tube as the first output end of the first chopping unit, and the gate is connected to the first clock signal; the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube as the first input end of the first chopping unit, the source is connected to the source of the sixth NMOS tube as the second output end of the first chopping unit, and the gate is connected to the first clock signal.

[0011] In an embodiment of the present application, the comparator includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; a source of the first transistor, a source of the third transistor, a drain of the fifth transistor, a drain of the seventh transistor, a gate of the sixth transistor, a source of the ninth transistor and a gate of the eleventh transistor The gates of the first transistor, the drain of the third transistor, the drain of the second transistor, the drain of the fourth transistor and the source of the tenth transistor are connected, the gate of the first transistor and the gate of the second transistor are connected to the differential input voltage pair, the gate of the third transistor and the gate of the fourth transistor are connected to the target reference voltage pair, the source of the second transistor, the source of the fourth transistor, the drain of the sixth transistor, the drain of the eighth transistor, the gate of the fifth transistor, the drain of the ninth transistor and the gate of the twelfth transistor are connected; the gate of the tenth transistor , the gate of the seventh transistor, the gate of the eighth transistor and the gate of the ninth transistor are connected to the clock signal; the drain of the tenth transistor is connected to the power supply voltage; the source of the eleventh transistor and the twelfth transistor is grounded; the drain of the eleventh transistor, the source of the thirteenth transistor, and the source of the nineteenth transistor are connected, and the drain of the twelfth transistor, the source of the fourteenth transistor and the source of the twentieth transistor are connected; the drain of the thirteenth transistor is connected to the source of the fifteenth transistor, the source of the seventeenth transistor, the gate of the sixteenth transistor and the gate of the fourteenth transistor, as the ratio The first output terminal of the comparator; the drain of the fourteenth transistor is connected to the source of the sixteenth transistor, the source of the eighteenth transistor, the gate of the fifteenth transistor and the gate of the thirteenth transistor, as the second output terminal of the comparator; the drain of the fifteenth transistor, the drain of the sixteenth transistor, the drain of the seventeenth transistor, the drain of the eighteenth transistor, the drain of the nineteenth transistor and the drain of the twentieth transistor are connected to the power supply voltage; the gate of the seventeenth transistor, the gate of the eighteenth transistor, the gate of the nineteenth transistor and the gate of the twentieth transistor are connected to the inverted signal of the clock signal.

[0012] The present application also provides a control method for a Flash-type quantizer of a Delta-Sigma modulator, comprising: sequentially scrambling multiple pairs of differential reference voltage outputs obtained by resistor array voltage division and then outputting a target reference voltage pair through a reference voltage scrambling module; receiving a differential input voltage and the target reference voltage pair through each of a plurality of comparators to obtain a comparison result, and controlling the connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the logarithm of the differential reference voltage corresponds to the number of the comparators; exchanging the input terminal signals of the comparators through a plurality of chopping modules and then inputting them into the corresponding comparators to eliminate the offset voltage of the comparator, wherein the chopping modules are arranged in a one-to-one correspondence with the comparators.

[0013] As described above, the Flash type quantizer for Delta-Sigma modulator and the control method thereof of the present invention have the following beneficial effects.

[0014] The present application can eliminate the offset voltage by introducing a chopper circuit in the quantizer; adding a reference voltage scrambling module in the quantizer can reduce circuit overhead, effectively reduce power consumption, and improve the overall performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the overall architecture of a Flash quantizer used in a Delta-Sigma modulator in one embodiment of the present application.

[0016] Figure 2 This is a chopping circuit diagram of a four-input dynamic comparator in an embodiment of the present application.

[0017] Figure 3 Schematic diagram of the circuit structure of a four-input dynamic comparator in one embodiment of the present application.

[0018] Figure 4 Schematic diagram of the circuit structure of a chopper module in one embodiment of the present application.

[0019] Figure 5 Schematic diagram of the circuit structure of a delay elimination unit in one embodiment of the present application.

[0020] Figure 6 Schematic diagram of the circuit structure of a switch array in one embodiment of the present application.

[0021] Figure 7 Schematic diagram of the scrambling method in one embodiment of the present application.

[0022] Figure 8A flowchart of a control method for a Flash quantizer of a Delta-Sigma modulator in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0025] See also Figure 1 , Figure 1 The overall structure diagram of the Flash type quantizer for Delta-Sigma modulator in one embodiment of the present application. The Flash type quantizer for Delta-Sigma modulator provided in the embodiment of the present application includes: a reference voltage scrambling module, which is used to sequentially scramble the outputs of multiple pairs of differential reference voltages obtained by resistor array voltage division and then output a target reference voltage pair; a plurality of comparators, each of which receives a differential input voltage and the target reference voltage pair to obtain a comparison result, and controls the connected DAC circuit to output to the loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the logarithm of the differential reference voltage corresponds to the number of the comparators; a plurality of chopping modules, which are used to exchange the input terminal signals of the comparator and input them into the corresponding comparator to eliminate the offset voltage of the comparator, wherein the chopping module is set one-to-one with the comparator. The number of specific comparators and chopping modules can be set and adjusted according to actual application requirements, and is not limited here.

[0026] Specifically, see Figure 2 , Figure 2This is a chopping circuit diagram of a four-input dynamic comparator in an embodiment of the present application. The comparators in the embodiments of the present application all adopt a four-input dynamic comparator, and the comparator includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20; the source of the first transistor M1, the third transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20; The source of the first transistor M1, the drain of the third transistor M3, the drain of the second transistor M2, the drain of the fourth transistor M4 and the source of the tenth transistor M10 are connected, the gate of the first transistor M1 and the gate of the second transistor M2 are connected to the differential input voltage pair, the gate of the third transistor M3 and the gate of the fourth transistor M4 are connected to the target reference voltage pair, the source of the second transistor M2, the drain of the third transistor M3, the drain of the second transistor M2, the drain of the fourth transistor M4 and the source of the tenth transistor M10 are connected, the gate of the first transistor M1 and the gate of the second transistor M2 are connected to the differential input voltage pair, the gate of the third transistor M3 and the gate of the fourth transistor M4 are connected to the target reference voltage pair, the source of the second transistor M2, the drain of the third transistor M3, the drain of the second transistor M2, the drain of the fourth transistor M4 and the source of the tenth transistor M10 are connected, The source of the fourth transistor M4, the drain of the sixth transistor M6, the drain of the eighth transistor M8, the gate of the fifth transistor M5, the drain of the ninth transistor M9 and the gate of the twelfth transistor M12 are connected; the gate of the tenth transistor M10, the gate of the seventh transistor M7, the gate of the eighth transistor M8 and the gate of the ninth transistor M9 are connected to the clock signal; the drain of the tenth transistor M10 is connected to the power supply voltage; the source of the eleventh transistor M11 and the twelfth transistor M12 are grounded; the drain of the eleventh transistor M11, the source of the thirteenth transistor M13, the gate of the nineteenth transistor M19 are connected to the ground; The sources of the twelfth transistor M12, the source of the fourteenth transistor M14 and the source of the twentieth transistor M20 are connected; the drain of the thirteenth transistor M13 is connected to the source of the fifteenth transistor M15, the source of the seventeenth transistor M17, the gate of the sixteenth transistor M16 and the gate of the fourteenth transistor M14, as the first output end of the comparator; the drain of the fourteenth transistor M14 is connected to the source of the sixteenth transistor M16, the source of the eighteenth transistor M18, the gate of the fifteenth transistor M15 and the gate of the thirteenth transistor M13, as the second output end of the comparator;The drain of the fifteenth transistor M15, the drain of the sixteenth transistor M16, the drain of the seventeenth transistor M17, the drain of the eighteenth transistor M18, the drain of the nineteenth transistor M19 and the drain of the twentieth transistor M20 are connected to the power supply voltage; the gate of the seventeenth transistor M17, the gate of the eighteenth transistor M18, the gate of the nineteenth transistor M19 and the gate of the twentieth transistor M20 are connected to the inverted signal of the clock signal. ;

[0027] In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19 and the twentieth transistor M20 may all be PMOS transistors. The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 may all be NMOS transistors.

[0028] In one embodiment, the specific design of the four-input dynamic comparator is as follows: Figure 3 As shown, it includes a preamplifier and a latch. The preamplifier realizes the function of inputting VREFN-VIN and VIP-VREFP through a differential pair of tubes, and amplifies and adds the two signals respectively. The preamplifier ensures common-mode stability, high gain and high bandwidth through a cross-coupling structure. The output result of the preamplifier is connected to the latch for further comparison. The working principle of the highly dynamic comparator is: when CLK is high, the comparator is in the reset stage, M7, M8, and M9 are turned on, and M10 is disconnected. There is no static power consumption in the circuit. At the same time, the output of the preamplifier is pulled down to GND, M17, M18, M19, and M20 are turned on and the output voltages VOUTP and VOUTN are increased to VDD, and the drain voltages of M19 and M20 are increased to VDD to prevent mismatch caused by incomplete discharge in the comparison stage, resulting in erroneous comparator results; when CLK is low, the comparator is in the comparison stage, M10 is turned on, and M7, M8, and M9 are turned off. Assuming VIN-VREFN>VIP-VREFP, the current flowing through M4 is greater than the current flowing through M3, the gate voltage of M11 rises slower than the gate voltage of M12, M6 is turned on, and the gate voltage of M12 is quickly pulled down to GND, M5 is turned off, and M14 is turned on. When the gate voltage of M11 reaches the threshold voltage of M11, M11 is turned on before M12, and the speed at which VOP discharges through M13 and M11 is faster than the speed at which VON discharges, causing M16 to be turned on before M15, and the output voltage VON is pulled up to VDD. M15 is always turned off, and the output VOP is discharged to GND, and the comparison result is obtained.

[0029] In one embodiment, each comparator is provided with five chopping units, and the five chopping units together constitute a chopping module. The chopping module includes a first chopping unit, a second chopping unit, a third chopping unit, a fourth chopping unit and a fifth chopping unit; the first input terminal of the first chopping unit is connected to a first input voltage VIP, the second input terminal is connected to a first reference voltage VREFN, the first output terminal is connected to a first input terminal of the second chopping unit, and the second output terminal is connected to a first input terminal of the fourth chopping unit; the first input terminal of the third chopping unit is connected to a second reference voltage VREFP, the second input terminal is connected to a second input voltage VIN, the first output terminal is connected to a second input terminal of the second chopping unit, and the second output terminal is connected to a second input terminal of the fourth chopping unit; the two output terminals of the second chopping unit are connected to the first input terminal of the second chopping unit. The two output ends of the fourth chopping unit are respectively connected to the corresponding input ends of the comparator; the first input end and the second input end of the fifth chopping unit are connected to the corresponding output ends of the comparator, and the two output ends of the fifth chopping unit output the comparison result, wherein the first chopping unit and the third chopping unit are controlled by the first clock signal CLK1, and the second chopping unit, the fourth chopping unit and the fifth chopping unit are all controlled by the second clock signal CLK2; the first input voltage VIP and the second input voltage VIN form a pair of differential input voltages, and the first reference voltage VREFN and the second reference voltage VREFP form a pair of target reference voltages.

[0030] See also Figure 4 , Figure 4The circuit structure diagram of the chopping module in one embodiment of the present application is shown in FIG. The circuit structures of the first chopping unit, the second chopping unit, the third chopping unit, the fourth chopping unit and the fifth chopping unit are the same, and the first chopping unit includes: a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7 and an eighth NMOS tube N8; the source of the fifth NMOS tube N5 is connected to the drain of the sixth NMOS tube N6 as the first input of the first chopping unit, the drain is connected to the drain of the seventh NMOS tube N7 as the first output of the first chopping unit, and the gate is connected to the first clock signal; the drain of the eighth NMOS tube N8 is connected to the source of the seventh NMOS tube N7 as the first input of the first chopping unit, the source is connected to the source of the sixth NMOS tube N6 as the second output of the first chopping unit, and the gate is connected to the first clock signal. Specifically, the chopping module is controlled by CLK1 and CLK2 signals, and each chopping unit is composed of four NMOS tubes, which realizes the function of exchanging input signals under clock drive. The input signals are VIN and VIP, and the reference voltages are VREFN and VREFP. CLK2 mainly controls the exchange of VREFN / VIN and the exchange of VREFP / VIP, and eliminates the offset voltages of the comparator input ports VIP and VREFP, VIN and VREFN. At the same time, since the output of the differential comparator changes with the exchange of input signals, the chopping module at the output end is controlled by CLK2 to ensure that the output result does not change with the chopping operation. CLK1 mainly controls the exchange of VIP / VREFN and VIN / VREFP, and eliminates the offset voltage of the differential input pair tubes in the four-input comparator, and the exchange process controlled by CLK1 does not affect the output result, so the output end does not need to add a chopping module controlled by CLK1.

[0031] In one embodiment, the reference voltage scrambling module includes: a plurality of delay elimination units, which receive a multi-bit input control signal and generate a corresponding output control signal pair, wherein the delay elimination unit eliminates the delay between the output control signal pairs through a cross-coupling structure; wherein the number of bits of the input control signal corresponds to the number of the output control signal pairs and the comparators; a switch array, which receives the output control signal pair to control the transmission relationship between the plurality of pairs of differential reference voltages obtained by voltage division of the resistor array and the target reference voltage pair, and polls the multi-bit input control signal in an interval polling manner to adjust the output order of the target reference voltage pairs.

[0032] See also Figure 5 , Figure 5The circuit structure diagram of the delay elimination unit in one embodiment of the present application. The delay elimination unit includes: a delay device INV1, a first NMOS tube N1, a second NMOS tube N2, a first PMOS tube P1 and a second PMOS tube P2. The input end of the delay device INV1 is connected to the gate of the second NMOS tube N2 as the input end of the delay elimination unit and is connected to the input control signal; the output end of the delay device INV1 is connected to the gate of the first NMOS tube N1, the source of the first NMOS tube N1 and the source of the second NMOS tube N2 are grounded; the drain of the first NMOS tube N1 is connected to the source of the first PMOS tube P1 as the input end of the delay elimination unit. The first output end of the delay elimination unit; the drain of the second NMOS tube N2 is connected to the source of the first PMOS tube P1 as the second output end of the delay elimination unit; the gate of the first PMOS tube is connected to the source of the second PMOS tube P2, and the gate of the second PMOS tube P2 is connected to the source of the first PMOS tube P1 to form the cross-coupling structure; the drain of the first PMOS tube P1 and the drain of the second PMOS tube P2 are respectively connected to the power supply voltage; wherein the output control signal of the second output end is the inverted signal of the output control signal of the first output end.

[0033] See also Figure 6 , Figure 6 The schematic diagram of the circuit structure of the switch array in one embodiment of the present application. The switch array includes a plurality of switch units, wherein the number of the switch units is the square of the delay elimination unit; each of the switch units includes a third NMOS tube N3, a fourth NMOS tube N4, a third PMOS tube P3 and a fourth PMOS tube P4, the source of the third NMOS tube N3 is connected to the source of the third PMOS tube P3 as the first input end of the switch unit, the drain of the third NMOS tube N3 is connected to the drain of the third PMOS tube P3 as the first output end of the switch unit; the source of the fourth NMOS tube N4 is connected to the source of the fourth PMOS tube P4 The gate of the fourth NMOS tube N4 is connected to the first output end of the delay elimination unit as the second input end of the switch unit; the gate of the third NMOS tube N3 is connected to the first output end of the delay elimination unit as the first control end of the switch unit; the gate of the fourth NMOS tube N4 is connected to the first output end of the delay elimination unit as the second control end of the switch unit; the gate of the third PMOS tube P3 is connected to the gate of the fourth PMOS tube P4 as the fifth control end of the switch unit connected to the second output end of the delay elimination unit.

[0034] See also Figure 7 , Figure 7The following is a schematic diagram of the scrambling method in an embodiment of the present application. Taking eight reference voltages and one differential input voltage as an example, the quantizer input signal is the differential output signal of the loop filter in the Delta-Sigma modulator, the reference voltage is the different voltages obtained by the reference voltage under the resistor voltage division, there are a total of 8 reference voltages and one differential input signal, the reference voltage is defined as REF[7:0], the quantizer is mainly composed of 8 comparators and a reference voltage scrambling module, the comparator is a four-input comparator, in which VIP and VIN are connected to the differential input signal, the VREFN and VREFP of the 8 comparators can be written as VREFN[7:0] and VREFP[7:0], and the VREFN[n] and VREFP[n] inputs are the reference voltages after scrambling by the reference voltage scrambling module. The control signal IN is an 8-bit selection signal, with a total of 8 groups. The OUT signal is the same as the IN signal, and OUTN is the inverted signal of the OUT signal. In the first clock cycle, the reference voltage scrambling module is equivalent to IN input IN1 = 00000001, IN2 = 00000010, IN3 = 00000100 until IN8 = 10000000. Here, the IN input is represented as IN1 = 1, IN2 = 2 until IN8 = 8. This group of signals makes REF[n] = VREFP[n], REF[7-n] = VREFN[n], and the reference voltage is connected to the comparator in order of size; when the scrambling process starts, according to Figure 4 As shown in the figure, after the second clock cycle arrives, IN1=2, IN2=4, IN3=1, IN4=6, IN5=3, IN6=8, IN7=5, IN8=7, which makes REF[1]=VREFP[0], REF[3]=VREFP[1], REF[0]=VREFP[2], REF[5]=VREFP[3], REF[2]=VREFP[4], REF[7]=VREFP[5], REF[4]=VREFP[6], REF[6]=VREFP[7], thus realizing the first scrambling of the reference voltage. After the subsequent clock cycle arrives, the eight groups of input signals IN are scrambled according to Figure 4 The scrambling strategy shown continues to change, so that the connection sequence of the reference voltages and the comparators is regularly scrambled over time.

[0035] After the four input signals, power supply voltage and control clock signal are connected, the comparator starts to work. When the control clock is high, the comparator is reset and the comparator output is high. When the control clock is low, the comparator compares the size of the VIN-VREFN and VIP-VREFP signals and outputs the result. Since the output of the 8 comparators is an 8-bit thermometer code, the order of the thermometer code does not affect its size, so it does not affect the quantized output result. Only the thermometer code is scrambled, but different thermometer codes representing the same result control different equal-weight DACs. Therefore, the scrambled thermometer code controls different DACs when representing the same digital quantity, which makes the subsequent DACs scrambled following the scrambling method of the thermometer code, reducing the nonlinear distortion of the DAC.

[0036] Based on the technical solutions of the above embodiments of the present application, the offset voltage of the comparator is reduced by chopping technology, thereby improving the accuracy of the quantizer; the speed and accuracy of the traditional comparator are improved by an improved four-input comparator, while the threshold voltage loss is reduced, which is easier to implement under advanced processes with low power supply voltage; the input reference voltages of each comparator are scrambled by a reference voltage scrambling module, so that the output 8-bit thermometer code has a scrambling effect, and controlling the operation of subsequent DAC circuits with equal weights can effectively reduce the nonlinear distortion problem of the DAC.

[0037] See also Figure 8 , Figure 8 A flow chart of a control method for a Flash quantizer of a Delta-Sigma modulator in an embodiment of the present application. The method comprises:

[0038] Step S800, using a reference voltage scrambling module to sequentially scramble multiple pairs of differential reference voltage outputs obtained by resistor array voltage division and then output a target reference voltage pair;

[0039] Step S810, receiving a differential input voltage and the target reference voltage pair through each of the plurality of comparators to obtain a comparison result, and controlling the connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is an output voltage of the loop filter, and the logarithm of the differential reference voltage corresponds to the number of the comparators;

[0040] Step S820, exchanging the input terminal signals of the comparators through a plurality of chopping modules and inputting the signals into corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopping modules are arranged in a one-to-one correspondence with the comparators.

[0041] The specific execution process has been described in detail in the aforementioned circuit embodiment and will not be repeated here.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A Flash quantizer for a Delta-Sigma modulator, characterized in that: include: A reference voltage scrambling module, which is used to sequentially scramble the outputs of multiple pairs of differential reference voltages obtained by voltage division of the resistor array and then output a target reference voltage pair; A plurality of comparators, each of which receives a differential input voltage and the target reference voltage pair to obtain a comparison result, and controls a connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is an output voltage of the loop filter, and the logarithm of the differential reference voltage corresponds to the number of the comparators; A plurality of chopping modules are used for exchanging the input terminal signals of the comparators and inputting the signals into the corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopping modules are arranged in a one-to-one correspondence with the comparators.

2. The Flash type quantizer for Delta-Sigma modulator according to claim 1, characterized in that: The reference voltage scrambling module comprises: A plurality of delay elimination units are connected to a multi-bit input control signal and generate a corresponding output control signal pair, wherein the delay elimination unit eliminates the delay between the output control signal pairs through a cross-coupling structure; The number of bits of the input control signal corresponds to the number of the output control signal pairs and the comparators; A switch array is connected to the output control signal pair to control the transmission relationship between the multiple pairs of differential reference voltages obtained by the resistor array voltage division and the target reference voltage pair, and polls the multi-bit input control signal in an interval polling manner to adjust the output order of the target reference voltage pair.

3. The Flash type quantizer for Delta-Sigma modulator according to claim 2, characterized in that: The delay elimination unit includes: a delay device, a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube, the input end of the delay device is connected to the gate of the second NMOS tube as the input end of the delay elimination unit, and is connected to the input control signal; the output end of the delay device is connected to the gate of the first NMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are grounded; the drain of the first NMOS tube is connected to the source of the first PMOS tube as the first output end of the delay elimination unit; the drain of the second NMOS tube is connected to the source of the first PMOS tube as the second output end of the delay elimination unit; the gate of the first PMOS tube is connected to the source of the second PMOS tube, and the gate of the second PMOS tube is connected to the source of the first PMOS tube to form the cross-coupling structure; the drain of the first PMOS tube and the drain of the second PMOS tube are respectively connected to the power supply voltage; wherein the output control signal of the second output end is the inverted signal of the output control signal of the first output end.

4. The Flash type quantizer for Delta-Sigma modulator according to claim 3, characterized in that: The switch array includes a plurality of switch units, wherein the number of the switch units is the square of the number of the delay elimination units; each of the switch units includes a third NMOS tube, a fourth NMOS tube, a third PMOS tube and a fourth PMOS tube, the source of the third NMOS tube is connected to the source of the third PMOS tube as the first input end of the switch unit, and the drain of the third NMOS tube is connected to the drain of the third PMOS tube as the first output end of the switch unit; the source of the fourth NMOS tube is connected to the source of the fourth PMOS tube as the second input end of the switch unit, and the drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube as the second output end of the switch unit; the gate of the third NMOS tube is connected to the first output end of the delay elimination unit as the first control end of the switch unit; the gate of the fourth NMOS tube is connected to the first output end of the delay elimination unit as the second control end of the switch unit; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube as the fifth control end of the switch unit connected to the second output end of the delay elimination unit.

5. The Flash type quantizer for Delta-Sigma modulator according to claim 1, characterized in that: The chopping module comprises a first chopping unit, a second chopping unit, a third chopping unit, a fourth chopping unit and a fifth chopping unit; the first input terminal of the first chopping unit is connected to a first input voltage, the second input terminal is connected to a first reference voltage, the first output terminal is connected to a first input terminal of the second chopping unit, and the second output terminal is connected to a first input terminal of the fourth chopping unit; the first input terminal of the third chopping unit is connected to a second reference voltage, the second input terminal is connected to a second input voltage, the first output terminal is connected to a second input terminal of the second chopping unit, and the second output terminal is connected to a second input terminal of the fourth chopping unit; two output terminals of the second chopping unit and two output terminals of the fourth chopping unit are respectively connected to corresponding input terminals of the comparator; the first input terminal and the second input terminal of the fifth chopping unit are connected to corresponding output terminals of the comparator, and two output terminals of the fifth chopping unit output comparison results, wherein the first chopping unit and the third chopping unit are controlled by a first clock signal, and the second chopping unit, the fourth chopping unit and the fifth chopping unit are all controlled by a second clock signal; the first input voltage and the second input voltage form a pair of differential input voltages, and the first reference voltage and the second reference voltage form a pair of target reference voltage pairs.

6. The Flash type quantizer for Delta-Sigma modulator according to claim 5, characterized in that: The circuit structures of the first chopping unit, the second chopping unit, the third chopping unit, the fourth chopping unit and the fifth chopping unit are the same. The first chopping unit includes: a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and an eighth NMOS tube; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube as the first input end of the first chopping unit, the drain is connected to the drain of the seventh NMOS tube as the first output end of the first chopping unit, and the gate is connected to the first clock signal; the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube as the first input end of the first chopping unit, the source is connected to the source of the sixth NMOS tube as the second output end of the first chopping unit, and the gate is connected to the first clock signal.

7. The Flash type quantizer for Delta-Sigma modulator according to claim 4, characterized in that: The comparator includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor; The source of the first transistor, the source of the third transistor, the drain of the fifth transistor, the drain of the seventh transistor, the gate of the sixth transistor, the source of the ninth transistor and the gate of the eleventh transistor are connected, the drain of the first transistor, the drain of the third transistor, the drain of the second transistor, the drain of the fourth transistor and the source of the tenth transistor are connected, the gate of the first transistor and the gate of the second transistor are connected to the differential input voltage pair, the gate of the third transistor and the gate of the fourth transistor are connected to the target reference voltage pair, the source of the second transistor, the source of the fourth transistor, the drain of the sixth transistor, the drain of the eighth transistor, the gate of the fifth transistor, the drain of the ninth transistor and the gate of the twelfth transistor are connected; the gate of the tenth transistor, the gate of the seventh transistor, the gate of the eighth transistor and the gate of the ninth transistor are connected; the gate of the tenth transistor, the gate of the seventh transistor, the gate of the eighth transistor and the gate of the ninth transistor are connected to the clock signal; the drain of the tenth transistor is connected to the power supply voltage; the gate of the eleventh transistor and the twelfth transistor are connected to the gate of the twelfth transistor. The source is grounded; the drain of the eleventh transistor, the source of the thirteenth transistor, and the source of the nineteenth transistor are connected, and the drain of the twelfth transistor, the source of the fourteenth transistor, and the source of the twentieth transistor are connected; the drain of the thirteenth transistor is connected to the source of the fifteenth transistor, the source of the seventeenth transistor, the gate of the sixteenth transistor, and the gate of the fourteenth transistor, as the first output end of the comparator; the drain of the fourteenth transistor is connected to the source of the sixteenth transistor, the source of the eighteenth transistor, the gate of the fifteenth transistor, and the gate of the thirteenth transistor, as the second output end of the comparator; the drain of the fifteenth transistor, the drain of the sixteenth transistor, the drain of the seventeenth transistor, the drain of the eighteenth transistor, the drain of the nineteenth transistor, and the drain of the twentieth transistor are connected to the power supply voltage; the gate of the seventeenth transistor, the gate of the eighteenth transistor, the gate of the nineteenth transistor, and the gate of the twentieth transistor are connected to the inverted signal of the clock signal.

8. A control method for a flash quantizer of a Delta-Sigma modulator, characterized in that: include: The reference voltage scrambling module sequentially scrambles the multiple pairs of differential reference voltage outputs obtained by the resistor array voltage division and then outputs the target reference voltage pair; Each of the plurality of comparators receives a differential input voltage and the target reference voltage pair to obtain a comparison result, and controls the connected DAC circuit to output to a loop filter in the Delta-Sigma modulator according to the comparison result, wherein the differential input voltage is the output voltage of the loop filter, and the logarithm of the differential reference voltage corresponds to the number of the comparators; The input terminal signals of the comparators are exchanged through a plurality of chopping modules and then input into corresponding comparators to eliminate the offset voltage of the comparators, wherein the chopping modules are arranged in a one-to-one correspondence with the comparators.

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