A three-dimensional SiC superjunction diode and its fabrication method

Abstract

This invention provides a three-dimensional SiC superjunction diode and its fabrication method. The diode comprises a p+ type SiC epitaxial layer arranged in multiple spaced hemispheres, with an n+ type SiC epitaxial layer deposited on top. An n+ type electron transport layer is positioned between two hemispheres on the left side of the diode and located inside the n+ type SiC epitaxial layer. A field oxide passivation layer is deposited on the right side of the n+ type SiC epitaxial layer. A groove is located at the center of each hemisphere, directly opposite the anode PAD. This invention utilizes an annealing and reflow process with an alkaline earth-doped silicon oxide mask to achieve the three-dimensional structure etching mask, solving the problem of realizing a three-dimensional superjunction structure. This results in a three-dimensional superjunction structure with multiple hemispheres formed by the p+ type SiC epitaxial layer. The superjunction diode fabricated based on this structure exhibits superior voltage-resistance balance and can achieve lower resistance under the same voltage level.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically relating to a three-dimensional SiC superjunction diode and its fabrication method. Background Technology

[0002] Silicon carbide superjunction (SJ) devices are a novel type of power semiconductor device that combines the excellent properties of silicon carbide material with the advantages of a superjunction structure. They show promising applications in electric vehicles, renewable energy, industrial power supplies, and consumer electronics. Research and development of SJ devices is progressing rapidly and is expected to bring significant technological innovations to the field of high-efficiency power electronics.

[0003] Existing technologies often use 2D silicon carbide superjunction structures to fabricate super devices. The electric field of 2D silicon carbide superjunction structures spreads rapidly, which is not conducive to balancing the blocking voltage and on-resistance of the devices. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a three-dimensional SiC superjunction diode and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides a three-dimensional SiC superjunction diode comprising: an n+ type SiC substrate, a p+ type SiC epitaxial layer, an n+ type SiC epitaxial layer, an n+ type electron transport layer, a field oxide passivation layer, an ohmic contact, an anode PAD, a passivation protection layer, and a cathode PAD;

[0006] The p+ type SiC epitaxial layer is in the form of multiple hemispheres, spaced apart on the n+ type SiC substrate. The n+ type SiC epitaxial layer is deposited on top of the p+ type SiC epitaxial layer. The n+ type electron transport layer is disposed between two hemispheres on the left side and is located inside the n+ type SiC epitaxial layer. The field oxide passivation layer is deposited on the right side of the n+ type SiC epitaxial layer. The anode PAD is deposited on the left side of the n+ type SiC epitaxial layer and has a groove at the center of each hemisphere. The passivation protection layer is deposited on top of the field oxide passivation layer. The ohmic contact is disposed on the back side of the n+ type SiC substrate, and the cathode PAD is deposited on the ohmic contact.

[0007] Secondly, the present invention provides a method for fabricating a three-dimensional SiC superjunction diode, comprising:

[0008] S100, select an n+ type SiC substrate and grow a p+ type SiC epitaxial layer on it;

[0009] S200, using a hemispherical mask to etch the p+ type SiC epitaxial layer to make it present a multi-hemispherical structure;

[0010] S300, an n+ type SiC epitaxial layer is epitaxially grown on multiple hemispherical structures, and an n+ type electron transport layer is formed by ion implantation and activation after implantation in the spacer region of the hemispherical structure on the left side of the n+ type SiC epitaxial layer.

[0011] S400, at the top of the hemispherical structure on the left side of the n+ type SiC epitaxial layer, a groove is formed by dry etching from top to bottom, and then sacrificial oxidation is performed.

[0012] S500, a field oxide passivation layer is grown on the right side portion of the n+ type SiC epitaxial layer using a PECVD process;

[0013] S600, Ni metal is deposited on the back side of the n+ type SiC substrate to form an ohmic contact;

[0014] S700, Schottky metal is deposited on the left side portion of the p+ type SiC epitaxial layer to form an anode PAD;

[0015] S800 uses photolithography to form a passivation protective layer on the field oxide passivation layer and deposits Ti / Ni / Ag metal on the back side of the ohmic contact to form a cathode PAD.

[0016] Beneficial effects:

[0017] This invention provides a three-dimensional SiC superjunction diode and its fabrication method. The fabricated diode has multiple hemispherical p+ type SiC epitaxial layers spaced apart on an n+ type SiC substrate. The n+ type SiC epitaxial layers are deposited on top of the p+ type SiC epitaxial layers. The n+ type electron transport layer is disposed between two hemispheres on the left side of the n+ type SiC epitaxial layer and located inside the n+ type SiC epitaxial layer. A field oxide passivation layer is deposited on the right side of the n+ type SiC epitaxial layer, and an anode PAD is deposited on the left side of the n+ type SiC epitaxial layer, with a groove at the center of each hemisphere. A passivation protection layer is deposited on the field oxide passivation layer. This invention uses an annealing and reflow process with an alkaline earth-doped silicon oxide mask to achieve the three-dimensional structure etching mask, solving the problem of realizing a three-dimensional superjunction structure, resulting in a three-dimensional superjunction structure with multiple hemispheres on the p+ type SiC epitaxial layer. The superjunction diode fabricated based on this structure has better voltage-resistance balance capabilities and can achieve lower resistance under the same voltage level.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a three-dimensional SiC superjunction diode provided by the present invention;

[0020] Figures 2-14 This is a schematic diagram illustrating the process of fabricating a three-dimensional SiC superjunction diode provided by the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] like Figure 1 As shown, the present invention provides a three-dimensional SiC superjunction diode comprising: an n+ type SiC substrate 1, a p+ type SiC epitaxial layer 2, an n+ type SiC epitaxial layer 3, an n+ type electron transport layer 4, a field oxide passivation layer 5, an ohmic contact 6, an anode PAD 7, a passivation protection layer 8, and a cathode PAD 9.

[0023] The p+ type SiC epitaxial layer 2 is in the form of multiple hemispheres, spaced apart on the n+ type SiC substrate 1; the n+ type SiC epitaxial layer 3 is deposited on the p+ type SiC epitaxial layer 2; the n+ type electron transport layer 4 is disposed between the two hemispheres on the left side and is located inside the n+ type SiC epitaxial layer 3; the field oxide passivation layer 5 is deposited on the right side of the n+ type SiC epitaxial layer 3; the anode PAD 7 is deposited on the left side of the n+ type SiC epitaxial layer 3, and a groove is present at the center of each hemisphere; the passivation protection layer 8 is deposited on the field oxide passivation layer 5; the ohmic contact 6 is disposed on the back side of the n+ type SiC substrate 1; and the cathode PAD 9 is deposited on the ohmic contact 6.

[0024] like Figure 1 As shown, the present invention has 5 hemispheres, with the hemisphere with the largest diameter located at the center, and two hemispheres on the left and two on the right. The two hemispheres on the same side have the same diameter, and the diameters of the two hemispheres on the right side are larger than the diameters of the two hemispheres on the left side.

[0025] Secondly, the present invention provides a method for fabricating a three-dimensional SiC superjunction diode, comprising:

[0026] S100, select an n+ type SiC substrate 1, and grow a p+ type SiC epitaxial layer 2 on it;

[0027] This step involves growing a p+ type SiC epitaxial layer 2 on an n+ type SiC substrate 1. The substrate thickness is 350 μm, and the carrier concentration is 5e18, which translates to 5 × 10⁻⁶. 18 cm -3All other concentrations can be converted using conversion methods; the p+ type epitaxial layer thickness is 6–20 μm, and the carrier concentration is 2e¹⁶–6e¹⁶, such as... Figure 2 As shown.

[0028] S200, using a hemispherical mask to etch the p+ type SiC epitaxial layer 2, so that it presents a multi-hemispherical structure;

[0029] In one specific embodiment of the present invention, S200 includes:

[0030] S210, an alkaline earth-doped silicon oxide layer is grown on the p+ type SiC epitaxial layer 2; wherein, the thickness of the alkaline earth-doped silicon oxide layer is 6–20 μm, such as Figure 3 As shown.

[0031] S220 uses photolithography and etching processes to form an etching mask by creating square windows in an alkaline earth-doped silicon oxide layer. There is a certain gap between adjacent windows of the etching mask.

[0032] This step uses photolithography and etching processes to create square windows in the alkaline earth-doped silicon oxide layer, with window side lengths ranging from 6 to 20 μm. Figure 4 As shown.

[0033] S230 uses a rapid thermal annealing process to reflow the etched mask to form a hemispherical mask;

[0034] This step uses a rapid thermal annealing process to reflow the alkaline earth-doped silicon oxide etching mask to form a hemispherical mask. The annealing temperature is 900–1000 degrees Celsius, and the time is 120–180 seconds. Figure 5 As shown.

[0035] S240, a hemispherical mask is placed on the p+ type SiC epitaxial layer 2 and etched using a dry etching process to make it present a multi-hemispherical structure;

[0036] A dry etching process was used to etch the p+ type SiC epitaxial layer 2 to form a hemispherical structure. The etching selectivity was maintained at 1 or higher. Figure 6 As shown.

[0037] This invention uses an annealing and reflow process for alkaline earth-doped silicon oxide masks to achieve three-dimensional structure etching masks, thereby realizing three-dimensional superjunction structures.

[0038] S300, n+ type SiC epitaxial layers are epitaxially grown on multiple hemispherical structures, such as Figure 7 As shown, in the spacer region of the hemispherical structure on the left side of the n+ type SiC epitaxial layer 3, ion implantation is used and activated after implantation to form an n+ type electron transport layer 4, as shown. Figure 8 As shown.

[0039] The n+ type SiC epitaxial layer 3 has a thickness of 4–28 μm and a carrier concentration of 2e16–6e16. At this concentration, the n+ type SiC epitaxial layer 3 and the p+ type SiC epitaxial layer 2 achieve charge balance. The implanted ions used to form the n+ type electron transport layer 4 are nitrogen, with a total concentration of 1e18–5e18.

[0040] S400, at the top of the hemispherical structure on the left side of the n+ type SiC epitaxial layer 3, a groove is formed by dry etching from top to bottom, and then sacrificial oxidation is performed.

[0041] S500, on the right side of the n+ type SiC epitaxial layer 3, a field oxide passivation layer 5 is grown using PECVD process;

[0042] This invention uses a dry etching process to first create windows in the source electrode region. Then, sacrificial oxidation is performed, and a front-side field oxide passivation layer 5 is grown using a PECVD process, as shown below. Figure 10 As shown.

[0043] S600, depositing Ti or Ni metal on the back side of n+ type SiC substrate 1 to form ohmic contact 6;

[0044] This step uses electron beam evaporation to deposit Ti or Ni metal on the back side of the n+ type SiC substrate 1, followed by rapid thermal annealing to form ohmic contacts 6; the thickness of the Ti or Ni metal is 75–100 nm; the annealing temperature is 950–1050 °C, and the annealing time is 120–300 s. Figure 11 As shown.

[0045] S700, Schottky metal is deposited on the left side of the p+ type SiC epitaxial layer 2 to form the anode PAD7;

[0046] In one specific embodiment of the present invention, S700 includes:

[0047] S710, Schottky metal Ti or Ni is deposited on the left side of the p+ type SiC epitaxial layer 2 using electron beam evaporation or magnetron sputtering process;

[0048] S720 uses photolithography and wet etching processes to open windows and form Schottky contact patterns, and then uses rapid thermal annealing to form Schottky contact patterns. The annealing temperature is 400-600℃ and the annealing time is 5-10 minutes.

[0049] In S730, Al metal is deposited on the left side of the p+ type SiC epitaxial layer 2 using electron beam evaporation or magnetron sputtering. Then, photolithography and wet etching are used to create a windowed PAD pattern, forming the anode PAD7. Figure 12 As shown.

[0050] S800 uses photolithography to form a passivation protection layer 8 on the field oxide passivation layer 5 and deposits Ti / Ni / Ag metal on the back of the ohmic contact 6 to form a cathode PAD9.

[0051] In one specific embodiment of the present invention, S800 includes:

[0052] S810, a passivation protection layer 8 is formed on the field oxide passivation layer 5 using a photolithography process, such as Figure 13 As shown; the passivation protective layer 8 has a thickness of 6 μm;

[0053] S820 uses electron beam evaporation to form a Ti / Ni / Ag cathode PAD9 on the back side of the p+ type SiC epitaxial layer 2, such as... Figure 14 As shown; wherein the thickness of the cathode PAD9 is 200nm, 200nm or 1000nm.

[0054] It is worth noting that the overall resistance of a superjunction device is related to the carrier concentration in the drift region. Based on charge balance theory, superjunction devices can be fabricated using drift regions with high carrier concentrations. Therefore, the diode in this application has a lower resistance compared to traditional structures. Avalanche breakdown occurs because the internal peak electric field reaches the critical breakdown field strength. The electric field vector in a traditional 2D silicon carbide superjunction structure can be decomposed into the superposition of electric field vectors in the transverse and longitudinal directions. Excessive electric field extension in either direction leads to avalanche breakdown. The 3D SiC superjunction diode in this application exhibits a slower electric field extension capability compared to the 2D structure, thus achieving superior superjunction device performance.

[0055] This invention provides a three-dimensional SiC superjunction diode and its fabrication method. The fabricated diode has multiple hemispherical p+ type SiC epitaxial layers spaced apart on an n+ type SiC substrate. An n+ type SiC epitaxial layer is deposited on top of the p+ type SiC epitaxial layer. An n+ type electron transport layer is disposed between two hemispheres on the left side and located inside the n+ type SiC epitaxial layer. A field oxide passivation layer is deposited on the right side of the n+ type SiC epitaxial layer, and an anode PAD is deposited on the left side of the n+ type SiC epitaxial layer, with a groove at the center of each hemisphere. A passivation protection layer is deposited on top of the field oxide passivation layer. This invention uses an annealing and reflow process with an alkaline earth-doped silicon oxide mask to achieve a three-dimensional structure etching mask, solving the problem of realizing a three-dimensional superjunction structure. This results in a three-dimensional superjunction structure with multiple hemispherical p+ type SiC epitaxial layers. The superjunction diode fabricated based on this structure has better voltage-resistance balance capabilities and can achieve lower resistance under the same voltage level.

[0056] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0057] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A three-dimensional SiC superjunction diode, characterized in that, include: n+ type SiC substrate (1) p+ type SiC epitaxial layer (2), n+ type SiC epitaxial layer (3), n+ type electron transport layer (4), field oxygen passivation layer (5), ohmic contact (6), anode PAD (7), passivation protection layer (8) and cathode PAD (9); Among them, the p+ type SiC epitaxial layer (2) is in the form of multiple hemispheres, which are spaced apart on the n+ type SiC substrate (1); the n+ type SiC epitaxial layer (3) is deposited on the p+ type SiC epitaxial layer (2); the n+ type electron transport layer (4) is disposed between the two hemispheres on the left side and is located inside the n+ type SiC epitaxial layer (3); the field oxide passivation layer (5) is deposited on the right side of the n+ type SiC epitaxial layer (3); the anode PAD (7) is deposited on the left side of the n+ type SiC epitaxial layer (3) and has a groove at the center of each hemisphere; the passivation protection layer (8) is deposited on the field oxide passivation layer (5); the ohmic contact (6) is disposed on the back side of the n+ type SiC substrate (1); and the cathode PAD (9) is deposited on the ohmic contact (6).

2. The three-dimensional SiC superjunction diode according to claim 1, characterized in that, The number of hemispheres is 5, with the hemisphere with the largest diameter placed in the center, and two hemispheres placed on the left and two on the right. The two hemispheres on the same side have the same diameter, and the diameters of the two hemispheres on the right are larger than the diameters of the two hemispheres on the left.

3. A method for fabricating a three-dimensional SiC superjunction diode, characterized in that, include: S100, select an n+ type SiC substrate (1) and grow a p+ type SiC epitaxial layer on it (2). S200, the p+ type SiC epitaxial layer (2) is etched using a hemispherical mask to make it present a multi-hemispherical structure; S300, an n+ type SiC epitaxial layer (3) is epitaxially grown on multiple hemispherical structures, and an n+ type electron transport layer (4) is formed by ion implantation and activation after implantation in the spacer region of the hemispherical structure on the left side of the n+ type SiC epitaxial layer (3). S400, at the top of the hemispherical structure on the left side of the n+ type SiC epitaxial layer (3), a groove is formed by dry etching from top to bottom, and then sacrificial oxidation is performed. S500, a field oxide passivation layer (5) is grown on the right side of the n+ type SiC epitaxial layer (3) using a PECVD process. S600, Ni metal is deposited on the back side of the n+ type SiC substrate (1) to form an ohmic contact (6). S700, Schottky metal is deposited on the left side portion of the p+ type SiC epitaxial layer (2) to form an anode PAD (7). S800, a passivation protection layer (8) is formed on the field oxygen passivation layer (5) using a photolithography process, and Ti / Ni / Ag metal is deposited on the back side of the ohmic contact (6) to form a cathode PAD (9).

4. The method for fabricating a three-dimensional SiC superjunction diode according to claim 3, characterized in that, S200 includes: S210, an alkaline earth-doped silicon oxide layer is grown on the p+ type SiC epitaxial layer (2); S220 uses photolithography and etching processes to form an etching mask by creating square windows in an alkaline earth-doped silicon oxide layer. There is a certain gap between adjacent windows of the etching mask. S230, using a rapid thermal annealing process, the etched mask is reflowed to form a hemispherical mask; S240, the hemispherical mask is placed on the p+ type SiC epitaxial layer (2) and etched using a dry etching process to make it present a multi-hemispherical structure.

5. The method for fabricating a three-dimensional SiC superjunction diode according to claim 4, characterized in that, The n+ type SiC substrate (1) has a thickness of 350 μm and a carrier concentration of 5e18 cm⁻¹. -3 The thickness of the p+ type SiC epitaxial layer (2) is 6~20 μm, and the carrier concentration is 2e16~6e16 cm. -3 .

6. The method for fabricating a three-dimensional SiC superjunction diode according to claim 3, characterized in that, The thickness of the n+ type SiC epitaxial layer (3) is 4~28 μm, and the carrier concentration is 2e16~6e16 cm. -3 At this concentration, the n+ type SiC epitaxial layer (3) and the p+ type SiC epitaxial layer (2) reach charge balance.

7. The method for fabricating a three-dimensional SiC superjunction diode according to claim 4, characterized in that, In S300, nitrogen is used as the implanted ion to form an n+ type electron transport layer (4) by ion implantation, with a total concentration of 1e18-5e18 cm⁻¹. -3 .

8. The method for fabricating a three-dimensional SiC superjunction diode according to claim 4, characterized in that, The S600 includes: Ti or Ni metal is deposited on the back side of the n+ type SiC substrate (1) using an electron beam evaporation process, and then an ohmic contact (6) is formed using a rapid thermal annealing process; wherein the thickness of the Ti or Ni metal is 75~100nm; the annealing temperature is 950~1050℃, and the annealing time is 120s~300s.

9. The method for fabricating a three-dimensional SiC superjunction diode according to claim 3, characterized in that, The S700 includes: S710, Schottky metal Ti or Ni is deposited on the left side portion of the p+ type SiC epitaxial layer (2) using electron beam evaporation or magnetron sputtering process; S720 uses photolithography and wet etching processes to form Schottky contact patterns, followed by rapid thermal annealing to form Schottky contact patterns; the annealing temperature is 400~600℃, and the annealing time is 5min~10min. S730 uses electron beam evaporation or magnetron sputtering to deposit Al metal on the left side of the p+ type SiC epitaxial layer (2), and then uses photolithography and wet etching to open the window to form a PAD pattern, forming an anode PAD (7).

10. The method for fabricating a three-dimensional SiC superjunction diode according to claim 3, characterized in that, The S800 includes: S810, a passivation protection layer (8) is formed on the field oxide passivation layer (5) using photolithography; the passivation protection layer (8) has a thickness of 6 μm; S820, using electron beam evaporation process to form a Ti / Ni / Ag cathode PAD (9) on the back side of the p+ type SiC epitaxial layer (2); wherein the cathode PAD (9) has a thickness of 200 nm or 1000 nm.

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