ESD protection device, ESD protection circuit and chip

Abstract

The invention relates to an ESD protection device, an ESD protection circuit and a chip. The ESD protection device comprises a substrate; the N well is located in the substrate; the P well is located in the substrate; the first P-type region is positioned in the N well; the N-type region is positioned in the P well; the second P-type region is separated from the first P-type region by the N well; the grid electrode is positioned on the N well between the second P-type region and the first P-type region; wherein the first P-type region, the N well and the grid electrode are used for being connected with an anode, and the N-type region and the P well are used for being connected with a cathode. The trigger voltage of the whole ESD protection device is reduced through avalanche breakdown of the parasitic diode, the SCR and the GDPMOS are ingeniously combined, more discharge current channels are formed, the problem that a traditional GGNMOS multi-finger structure is burnt in advance due to uneven conduction is solved, the discharge current capacity of the device per unit area can be greatly improved, and robustness is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an ESD protection device, an ESD protection circuit, and a chip. Background Art

[0002] Most of the failures in integrated circuits are caused by electrostatic discharge. ESD (Electro-Static Discharge) protection is an important part of IC (Integrated Circuit) design. The reliability of the chip depends to a large extent on the electrostatic protection device of the I / O PAD. Figure 1 , ESD protection devices are used between the anode (also known as the positive electrode) and the cathode (also known as the negative electrode). As the requirements for chip reliability continue to increase, obtaining strong anti-static protection capabilities under the limited chip area has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] Based on this, it is necessary to provide an ESD protection device with strong electrostatic protection capability.

[0004] An ESD protection device comprises: a substrate; an N-well located in the substrate; a P-well located in the substrate; a first P-type region located in the N-well; an N-type region located in the P-well; a second P-type region separated from the first P-type region by the N-well; and a gate located on the N-well between the second P-type region and the first P-type region; wherein the first P-type region, the N-well and the gate are used to connect to an anode, and the N-type region and the P-well are used to connect to a cathode.

[0005] The ESD protection device, the first P-type region, the second P-type region, the N-well and the gate constitute a GDPMOS (the gate is connected to V DDThe first P-type region, N-well, P-well, and N-type region constitute an SCR (Silicon Controlled Rectifier, thyristor) structure, and the second P-type region and N-well constitute a parasitic diode. When the anode is subjected to ESD stress, the parasitic diode is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The electrons drift toward the anode with high voltage, and the generated electronic current produces a voltage drop on the parasitic resistance formed by the N-well, causing the PNP transistor in the SCR to turn on. In addition, the GDPMOS will turn on and form a current discharge path. The hole current generated by the avalanche breakdown of the parasitic diode produces a voltage drop on the parasitic resistance formed by the P-well, causing the NPN transistor in the SCR to turn on, and the SCR turns on, forming another current discharge path. This application utilizes the avalanche breakdown of the parasitic diode to reduce the trigger voltage of the entire ESD protection device, and cleverly combines the SCR with the GDPMOS to form more discharge current channels, avoiding the premature burning problem caused by the uneven conduction of the traditional GGNMOS multi-finger structure, which can greatly improve the device's discharge current capacity per unit area and has strong robustness.

[0006] In one embodiment, the first P-type region serves as the source of the PMOS, the second P-type region serves as the drain of the PMOS, and the gate serves as the gate of the PMOS; the first P-type region also serves as the emitter of the PNP transistor in the thyristor, the N-well serves as the base of the PNP transistor and the collector of the NPN transistor in the thyristor, the P-well serves as the collector of the PNP transistor and the base of the NPN transistor, and the N-type region serves as the emitter of the NPN transistor; the second P-type region also serves as the anode of the diode, and the N-well also serves as the cathode of the diode.

[0007] In one embodiment, each of the P-wells is surrounded by the N-well, and the second P-type region is located between adjacent P-wells.

[0008] In one embodiment, the ESD protection device further includes: an N-well lead-out region located in the N-well, the doping concentration of the N-well lead-out region is greater than the doping concentration of the N-well, and the N-well is connected to the anode through the N-well lead-out region.

[0009] In one of the embodiments, the ESD protection device further includes: a P-well lead-out region located in the P-well, the doping concentration of the P-well lead-out region is greater than the doping concentration of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

[0010] In one of the embodiments, the N-well lead-out region is surrounded by the first P-type region in a cross section.

[0011] In one embodiment, the P-well lead-out region is surrounded by the N-type region in a cross section.

[0012] In one of the embodiments, the cross-section of the N-well lead-out region and the cross-section of the P-well lead-out region are octagonal.

[0013] In one embodiment, an outer contour of a cross section of the first P-type region and an outer contour of a cross section of the N-type region are octagonal.

[0014] In one of the embodiments, the layouts of the N-well and the P-well are octagonal, and the layout of the second P-type region is quadrilateral and is located in a region enclosed by the layouts of the two N-wells and the layouts of the two P-wells.

[0015] In one embodiment, the ESD protection device further includes a floating gate structure, the floating gate structure is located above the P-well and the N-well between the first P-type region and the N-type region, and the floating gate structure includes a dielectric layer and a gate layer on the dielectric layer.

[0016] In one of the embodiments, a floating gate structure is also provided on the P-well between the N-type region and the second P-type region.

[0017] In one of the embodiments, the substrate is a P-type substrate.

[0018] In one embodiment, the doping concentration of the second P-type region is greater than the doping concentration of the P-well.

[0019] It is also necessary to provide an ESD protection circuit.

[0020] An ESD protection circuit comprises: a thyristor, comprising a PNP transistor and an NPN transistor, wherein the base of the PNP transistor is connected to the collector of the NPN transistor, and the collector of the PNP transistor is connected to the base of the NPN transistor; a first diode, wherein the positive electrode is connected to the collector of the PNP transistor and the base of the NPN transistor, and the negative electrode is connected to the base of the PNP transistor and the collector of the NPN transistor; a first voltage dividing unit, wherein the first end of the PNP transistor is connected to the collector of the NPN transistor; The base of the PNP transistor is connected at the first end, and the emitter of the PNP transistor is connected at the second end; the second voltage dividing unit has a first end connected to the base of the NPN transistor and a second end connected to the emitter of the NPN transistor; the PMOS tube has a drain connected to the collector of the PNP transistor; wherein the second end of the first voltage dividing unit, the emitter of the PNP transistor, the gate and source of the PMOS tube are used to connect the anode, and the emitter of the NPN transistor and the second end of the second voltage dividing unit are used to connect the cathode.

[0021] In the above-mentioned ESD protection circuit, the PMOS tube is a GDPMOS with the gate connected to the anode. When the anode is subjected to ESD stress, the first diode is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. Among them, the electrons drift toward the anode with high voltage, and the generated electronic current produces a voltage drop on the parasitic resistance formed by the N well, so that the PNP transistor in the SCR is turned on. In addition, the GDPMOS will turn on and form a current discharge path. The hole current generated by the avalanche breakdown of the parasitic diode produces a voltage drop on the second voltage divider unit, so that the NPN transistor in the SCR is turned on, and the SCR is turned on to form another current discharge path. The present application utilizes the avalanche breakdown of the first diode D1 to reduce the trigger voltage of the entire ESD protection circuit, and cleverly combines the SCR with the GDPMOS to form more discharge current channels, avoiding the problem of premature burning caused by the uneven conduction of the traditional GGNMOS multi-finger structure, which can greatly improve the device's unit area discharge current capacity and has strong robustness.

[0022] In one embodiment, the first voltage dividing unit is a first resistor, and the second voltage dividing unit is a second resistor.

[0023] It is also necessary to provide a chip, comprising the ESD protection device or ESD protection circuit described in any of the aforementioned embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0025] Figure 1 An exemplary circuit architecture in which an ESD protection device is connected;

[0026] Figure 2 is a schematic diagram of an exemplary structure of a GGNMOS;

[0027] Figure 3 is an exemplary TLP (Transmission Line Pulse) curve of GGNMOS;

[0028] Figure 4 is a circuit schematic diagram of an ESD protection device in an embodiment of the present application;

[0029] Figure 5 is a layout of an ESD protection device in an embodiment of the present application;

[0030] Figure 6 is along Figure 5Sectional view along line A-A';

[0031] Figure 7 is along Figure 5 Cross-sectional view along line BB'. DETAILED DESCRIPTION

[0032] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0034] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0038] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0039] Figure 2 is a schematic diagram of an exemplary GGNMOS structure. When there is a positive ESD pulse at the anode, the voltage of the GGNMOS rises to the trigger voltage Vt1. Figure 3 As shown, the parasitic NPN transistor is turned on and discharged. At this time, there will be a rapid voltage hysteresis phenomenon (snapback). After the voltage drops back to the holding voltage Vh, as the ESD pulse continues to increase, the GGNMOS continues to discharge, and the voltage across the device increases accordingly. After reaching the breakdown voltage Vt2, the device burns out. It can be seen that since Vt2 is generally less than Vt1, after a few parasitic NPN transistors of the multi-finger structure (usually the ones near the middle) are turned on and triggered, the other surrounding parasitic NPN transistors do not have time to turn on, and the device burns out. This is what the industry calls the uneven conduction phenomenon of ESD devices, which will result in a lower secondary breakdown current of the GGNMOS. In addition, the GGNMOS structure needs to ensure that the emitter junction voltage of the parasitic NPN tube reaches the threshold voltage before it will turn on, so the trigger voltage of the device is relatively high. If Vt1 is higher than V DD , which will make the device unsuitable for use in low power supply voltage scenarios.

[0040] In view of the problems existing in the above-mentioned designs, the present application designs an ESD protection device with low trigger voltage and high secondary breakdown current, which can greatly improve the robustness of the ESD protection device.

[0041] Figure 4 1 is a circuit diagram of an ESD protection device in an embodiment of the present application. In this embodiment, the ESD protection device includes a thyristor, a first diode D1, a first voltage divider unit, a second voltage divider unit and a PMOS tube Mp. The thyristor includes a PNP transistor Qp and an NPN transistor Qn. The PMOS tube Mp is a GDPMOS (the gate is connected to V DD P-channel metal oxide semiconductor field effect transistor). The base of the PNP transistor Qp is connected to the collector of the NPN transistor Qn, and the collector of the PNP transistor Qp is connected to the base of the NPN transistor Qn. The drain of the PMOS tube Mp is connected to the collector of the PNP transistor Qp. The anode of the first diode D1 is connected to the collector of the PNP transistor Qp and the base of the NPN transistor Qn, and the cathode is connected to the base of the PNP transistor Qp and the collector of the NPN transistor Qn. The first end of the first voltage dividing unit is connected to the base of the PNP transistor Qp, and the second end is connected to the emitter of the PNP transistor Qp. The first end of the second voltage dividing unit is connected to the base of the NPN transistor Qn, and the second end is connected to the emitter of the NPN transistor Qn. Figure 4In the embodiment shown, the first voltage dividing unit is a resistor Rnw, and the second voltage dividing unit is a resistor Rpw. The second end of the first voltage dividing unit, the gate and source of the PMOS transistor Mp, and the emitter of the PNP transistor Qp are connected to the anode. The second end of the second voltage dividing unit and the emitter of the NPN transistor Qn are connected to the cathode.

[0042] In the above-mentioned ESD protection device, when the anode is subjected to ESD stress, the first diode D1 is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The electrons drift toward the anode with high voltage, and the generated electronic current generates a voltage drop on the first voltage divider unit, causing the PNP transistor Qp in the SCR to turn on. In addition, GDPMOS will turn on and form a current discharge path. The hole current generated by the avalanche breakdown of the first diode D1 generates a voltage drop on the second voltage divider unit, causing the NPN transistor Qn in the SCR to turn on, and the SCR turns on to form another current discharge path. The present application utilizes the avalanche breakdown of the first diode D1 to reduce the trigger voltage of the entire ESD protection device, and cleverly combines the SCR with the GDPMOS to form more discharge current channels, avoiding the problem of premature burning caused by the uneven conduction of the traditional GGNMOS multi-finger structure, which can greatly improve the device's unit area discharge current capacity and has strong robustness.

[0043] exist Figure 4 In the illustrated embodiment, the ESD protection device further includes a second diode D2. The cathode of the second diode D2 is connected to the cathode, and the anode is connected to the drain of the PMOS transistor Mp.

[0044] Figure 5 is a layout diagram of an ESD protection device in an embodiment of the present application, Figure 6 is along Figure 5 The cross-sectional view of the A-A' line, Figure 7 is along Figure 5 The ESD protection device includes an N-well 122, a P-well 124, a first P-type region 132, a second P-type region 134, an N-type region 142 and a gate 152 ( Figure 5 The first P-type region 132 is located in the N-well 122. The N-type region 142 is located in the P-well 124. The first P-type region 132 and the second P-type region 134 are separated by the N-well 122. The gate 152 is located on the N-well 122 between the second P-type region 134 and the first P-type region 132. The first P-type region 132, the N-well 122 and the gate 152 are connected to the anode, and the N-type region 142 and the P-well 124 are connected to the cathode. The second P-type region 134 is a floating P-type region. Figure 5 The circuit schematic diagram of the ESD protection device shown can be referred to Figure 4 .exist Figure 5In the illustrated embodiment, the N-well 122 is located below the second P-type region 134 .

[0045] In the above-mentioned ESD protection device, the first P-type region 132, the second P-type region 134, the N-well 122 and the gate 152 constitute a GDPMOS, the first P-type region 132, the N-well 122, the P-well 124, and the N-type region 142 constitute an SCR structure, and the second P-type region 134 and the N-well 122 constitute a parasitic diode (i.e., the first diode D1). When the anode is subjected to ESD stress, the parasitic diode is reverse biased, and avalanche breakdown will first occur, generating a large number of holes and electrons. Among them, the electrons drift toward the anode with high voltage, and the generated electronic current generates a voltage drop on the parasitic resistance (i.e., resistance Rnw) formed by the N-well 122, so that the PNP transistor in the SCR is turned on. In addition, the GDPMOS will turn on and form a current discharge path. The hole current generated by the avalanche breakdown of the parasitic diode generates a voltage drop on the parasitic resistance (i.e., resistance Rpw) formed by the P-well 124, so that the NPN transistor in the SCR is turned on, and the SCR is turned on to form another current discharge path. This application utilizes the avalanche breakdown of the parasitic diode to reduce the trigger voltage of the entire ESD protection device, and cleverly combines the SCR with the GDPMOS to form more discharge current channels, avoiding the premature burning problem caused by the uneven conduction of the traditional GGNMOS multi-finger structure, which can greatly improve the device's discharge current capacity per unit area and has strong robustness.

[0046] In one embodiment of the present application, the ESD protection device further includes an N-well lead-out region 146 and a P-well lead-out region 138. The N-well lead-out region 146 is located in the N-well 122, the doping concentration of the N-well lead-out region 146 is greater than the doping concentration of the N-well 122, and the N-well 122 is connected to the anode through the N-well lead-out region 146. The P-well lead-out region 138 is located in the P-well 124, the doping concentration of the P-well lead-out region 138 is greater than the doping concentration of the P-well 124, and the P-well 124 is connected to the cathode through the P-well lead-out region 138.

[0047] In one embodiment of the present application, the gate 152 is made of polysilicon material, and in other embodiments, metal, metal nitride, metal silicide or other similar compounds can also be used as the material of the gate 152. A gate dielectric layer is also provided below the gate 152. In one embodiment of the present application, the gate dielectric layer may include a conventional dielectric material such as silicon oxide, nitride and oxynitride with a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material with a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and lead zirconate titanate (PZTs).

[0048] In one embodiment of the present application, the doping concentration of the first P-type region 132 is greater than the doping concentration of the P-well 124. In one embodiment of the present application, the doping concentration of the second P-type region 134 is greater than the doping concentration of the P-well 124, so that the reverse breakdown voltage of the first diode D1 is lower than the PN junction formed by the N-well 122 and the P-well 124. In one embodiment of the present application, the doping concentration of the N-type region 142 is greater than the doping concentration of the N-well 122. Figure 5 In the illustrated embodiment, the first P-type region 132 , the second P-type region 134 , and the P-well lead-out region 138 are P+ regions, and the N-type region 142 and the N-well lead-out region 146 are N+ regions.

[0049] In one embodiment of the present application, the N-well lead-out region 146 is surrounded by the first P-type region 132 in cross section, and the P-well lead-out region 138 is surrounded by the N-type region 142 in cross section. That is, the N-well lead-out region 146 is surrounded by the P+ ring of the first P-type region 132, and the P-well lead-out region 138 is surrounded by the N+ ring of the N-type region 142.

[0050] In one embodiment of the present application, the layout of the ESD protection device is a honeycomb-like repeated arrangement structure, and each P well 124 is surrounded by an N well 122. The second P-type region 134 is located between adjacent P wells 124. The honeycomb-like ESD protection device has a high electrostatic protection area efficiency.

[0051] exist Figure 5 In the illustrated embodiment, the layouts of the N-well 122 and the P-well 124 are regular octagons, and the layout of the second P-type region 134 is a quadrilateral and is located in a region enclosed by the layouts of the two N-wells 122 and the layouts of the two P-wells 124. Each side of the second P-type region 134 may be a common side with one N-well 122 or P-well 124. In other embodiments, the layouts of the N-well 122 and the P-well 124 may also be other shapes, such as a hexagon.

[0052] exist Figure 5 In the illustrated embodiment, the cross-sections of the N-well lead-out region 146 and the P-well lead-out region 138 are octagonal, and the outer contours of the cross-sections of the first P-type region 132 and the N-type region 142 are octagonal.

[0053] In one embodiment of the present application, the substrate 110 is a P-type substrate.

[0054] In one embodiment of the present application, the ESD protection device further includes a floating gate structure 156. The floating gate structure 156 is located above the P-well 124 and the N-well 122 between the first P-type region 132 and the N-type region 142, and the floating gate structure 156 includes a dielectric layer and a gate layer on the dielectric layer. In one embodiment of the present application, a floating gate structure 156 is also provided on the P-well 124 between the N-type region 142 and the second P-type region.

[0055] The present application accordingly provides a chip, comprising the ESD protection device or ESD protection circuit described in any of the aforementioned embodiments.

[0056] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0057] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An ESD protection device, characterized in that: include: substrate; An N-well located in the substrate; A P well located in the substrate; A first P-type region, located in the N-well; An N-type region located in the P-well; a second P-type region, wherein the first P-type region and the second P-type region are separated by the N-well; a gate, located on the N-well between the second P-type region and the first P-type region; The first P-type region, N-well and gate are used to connect to the anode, and the N-type region and P-well are used to connect to the cathode.

2. The ESD protection device according to claim 1, characterized in that: Each of the P-wells is surrounded by the N-well, and the second P-type region is located between adjacent P-wells.

3. The ESD protection device according to claim 1, characterized in that: Also includes: An N-well lead-out region, located in the N-well, the doping concentration of the N-well lead-out region is greater than the doping concentration of the N-well, and the N-well is connected to the anode through the N-well lead-out region; A P-well lead-out region is located in the P-well, the doping concentration of the P-well lead-out region is greater than the doping concentration of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

4. The ESD protection device according to claim 3, characterized in that: The N-well lead-out region is surrounded by the first P-type region in a cross section, and the P-well lead-out region is surrounded by the N-type region in a cross section.

5. The ESD protection device according to claim 4, characterized in that: The cross section of the N-well lead-out region and the cross section of the P-well lead-out region are octagonal, and the outer contour of the cross section of the first P-type region and the outer contour of the cross section of the N-type region are octagonal.

6. The ESD protection device according to claim 1, characterized in that: It also includes a floating gate structure, which is located above the P-well and the N-well between the first P-type region and the N-type region, and includes a dielectric layer and a gate layer on the dielectric layer.

7. The ESD protection device according to claim 1, characterized in that: The substrate is a P-type substrate; and / or The doping concentration of the second P-type region is greater than the doping concentration of the P-well.

8. An ESD protection circuit, characterized in that: include: The thyristor comprises a PNP transistor and an NPN transistor, wherein the base of the PNP transistor is connected to the collector of the NPN transistor, and the collector of the PNP transistor is connected to the base of the NPN transistor; A first diode, wherein the positive electrode is connected to the collector of the PNP transistor and the base of the NPN transistor, and the negative electrode is connected to the base of the PNP transistor and the collector of the NPN transistor; A first voltage dividing unit, a first end of which is connected to the base of the PNP transistor, and a second end of which is connected to the emitter of the PNP transistor; A second voltage dividing unit, a first end of which is connected to the base of the NPN transistor, and a second end of which is connected to the emitter of the NPN transistor; A PMOS tube, the drain of which is connected to the collector of the PNP transistor; Among them, the second end of the first voltage divider unit, the emitter of the PNP transistor, the gate and source of the PMOS tube are used to connect the anode, and the emitter of the NPN transistor and the second end of the second voltage divider unit are used to connect the cathode.

9. The ESD protection circuit according to claim 8, characterized in that: The first voltage dividing unit is a first resistor, and the second voltage dividing unit is a second resistor.

10. A chip, characterized in that: The invention comprises the ESD protection device according to any one of claims 1 to 7, or the ESD protection circuit according to claim 8 or 9.

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