Aging system and method of three-phase brushless motor driver

Abstract

The invention relates to an aging system and method of a three-phase brushless motor driver. The aging system comprises a clock and control signal generation module, an analog Hall signal generation module, a logic control module, a signal acquisition and processing module and a load module. The clock and control signal generation module, the analog Hall signal generation module and the logic control module are electrically connected in sequence; the logic control module is electrically connected with the clock and control signal generation module and the input end of the signal acquisition and processing module respectively; the device is reasonable in design, compact in structure and convenient to use.

Description

Technical Field

[0001] The invention relates to a burn-in system and method for a three-phase brushless motor driver, and relates to a burn-in system for a three-phase brushless motor driver. Background Art

[0002] At present, domestic and foreign three-phase brushless motor drive manufacturers mostly use voltage aging to implement steady-state life aging tests for their products. For high-power and wide temperature range products, for example, the current steady-state life aging test requirements for three-phase brushless motor drive products with a maximum of 1200V / 200A in the full temperature range (-55℃~125℃) cannot fully verify their reliability and cannot eliminate products that may fail early. Summary of the invention

[0003] The technical problem to be solved by the present invention is generally to provide a burn-in system and method for a three-phase brushless motor driver.

[0004] To solve the above problems, the technical solution adopted by the present invention is:

[0005] A burn-in system for a three-phase brushless motor driver, characterized in that it includes a clock and control signal generating module, an analog Hall signal generating module, a logic control module, a signal acquisition and processing module, and a load module;

[0006] The clock and control signal generating module, the analog Hall signal generating module and the logic control module are electrically connected in sequence;

[0007] The logic control module is electrically connected to the input ends of the clock and control signal generating module and the signal collecting and processing module respectively.

[0008] Further, the aging system also includes a power supply;

[0009] The power supply supplies power to the clock and control signal generating module, the analog Hall signal generating module and the logic control module respectively.

[0010] Further, the output terminal of the logic control module gives a signal to the load module of the test product;

[0011] The load module feeds back the electrical signal to the signal acquisition and processing module.

[0012] Furthermore, the signal acquisition and processing module is a current sampling circuit or a voltage sampling circuit.

[0013] Furthermore, the analog Hall signal generation module includes chips U6A, U6B, U7A and logic AND gates U8A, U8B, U8C; wherein the clock signal is divided into three paths, which are respectively connected to pin 3 of chip U6A, pin 13 of U6B, and pin 13 of U7A;

[0014] The signal terminal HA is electrically connected to the positive output terminal 1 of the chip U6 B and the pin 11 of the chip U7A respectively;

[0015] The signal terminal HB is electrically connected to the input terminal 6 of the logic AND gate U8B, the input terminal 5 of the chip U6 B, and the positive output terminal 15 of the chip U6A;

[0016] The signal terminal HC is electrically connected to the input terminal 2 of the logic AND gate U8A, the input terminal 9 of the logic AND gate U8C, and the positive output terminal 15 of the chip U7A;

[0017] In chip U6B, pin 6 is connected to output terminal 3 of logic AND gate U8A; pin 5 is also connected to positive output terminal 15 of chip U6A; pins 4 and 7 are grounded; negative output terminal 2 is connected to input terminal 5 of logic AND gate U8B and negative input 8 of logic AND gate U8C;

[0018] In chip U6A, pin 10 is connected to the negative output terminal 14 of chip U7A; pin 11 is connected to the output terminal 10 of op amp UBC; pins 6 and 12 are grounded; negative output terminal 14 is connected to input terminal 1 of logic AND gate U8A;

[0019] In chip U7A, pin 10 is connected to output terminal 4 of logic AND gate U8B; pins 6 and 12 are grounded;

[0020] A clock and control signal generating module, the clock and control signal generating module includes a chip U1;

[0021] In chip U1, pin 1 is grounded, pin 3 outputs CLK clock signal; CLK clock signal is also electrically connected to oscilloscope XSC1, pin 5 is grounded through capacitor C2, pin 2 is connected to pin 6, pin 2 is grounded through capacitor C1, resistor R3 is connected between pin 7 and pin 2, pin 8 and pin 4 are connected to VCC respectively; VCC is connected to pin 7 through resistor R1;

[0022] The logic control module includes logic gates U1A-U1D, U2A-U2C, U3A-U3D, U4A-U4C;

[0023] The three analog Hall signals HB, HC, and HA are connected to one input end of the XOR gate U1A-U1C through resistors R4, R3, and R2 respectively, and the other output end of the XOR gate U1A-U1C is connected to the reference signal through resistor R1;

[0024] The output terminals of XOR gates U1A-U1C correspond to the input terminals of NAND gates U3A, U3B, and U3D respectively;

[0025] The output of XOR gate U1A is also electrically connected to the input of JK NAND gates U4C and U2C respectively;

[0026] The output end of XOR gate U1B is also electrically connected to the input ends of NAND gates U2A and U4B respectively;

[0027] The output end of XOR gate U1C is also electrically connected to the input ends of NAND gates U2B and U4A respectively;

[0028] The output ends of the NAND gates U3A, U3B, and U3D are electrically connected to the input ends of the NAND gates U2A, U2B, and U2C respectively;

[0029] NAND gates U2A, U2B, and U2C output PWM control signals HB, HC, and HA respectively;

[0030] The output ends of the NAND gates U3A, U3B, and U3D are also connected to the input ends of the JK NAND gates U4A, U4B, and U4C respectively;

[0031] The signal acquisition and processing module adopts an overcurrent feedback control signal circuit; the overcurrent feedback control signal circuit includes NOT gates U5A and U5B;

[0032] The current sampling signal OC connected to the load module outputs the enable signal EN through the NOT gates U5A and U5B; the enable signal EN and PWM are connected to the input end of the XOR gate U1D through the NAND gate U3C; the output end of the XOR gate U1D is respectively connected to one input end of the NAND gates U2A-U2C;

[0033] JK NAND gates U4A, U4B, and U4C output PWM control signals LA, LC, and LB respectively;

[0034] The load module includes a three-phase brushless motor driver;

[0035] The test product is a three-phase brushless motor.

[0036] A burn-in method for a three-phase brushless motor driver, using the above system, performs the following steps:

[0037] S1, power on and check the clock and control signal generation module, the analog Hall signal generation module, and the logic control module, and power off after the verification is completed;

[0038] S2, install the three-phase brushless motor driver to be aged;

[0039] S3, setting aging parameters according to preset technical requirements;

[0040] S3, power-on test;

[0041] S4, first, the clock and control signal generating module generates a 1kHz square wave, which is sent to the analog Hall signal generating module as the clock signal CLK; then, the analog Hall signal generating module generates an analog Hall signal through logic transformation, and the analog Hall signal acts on the logic control module to generate a PWM six-way commutation signal; secondly, the PWM six-way commutation signal is output to the three-phase brushless motor driver; thirdly, the signal acquisition and processing module collects and processes the load module and feeds back to the logic control module.

[0042] The present invention adopts full hardware design, and will not cause the problem of product burnout due to program runaway caused by various factors. The present invention can achieve the steady-state life aging test requirements for three-phase brushless motor driver products with a maximum of 1200V / 200A in the full temperature range (-55℃~125℃), and adopts modular design for easy use and maintenance.

[0043] The invention has reasonable design, low cost, durability, safety and reliability, simple operation, time and labor saving, money saving, compact structure and convenient use. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a circuit schematic diagram of the present invention.

[0045] Figure 2 It is a schematic diagram of the analog Hall signal generating module of the present invention.

[0046] Figure 3 It is a clock signal generating circuit diagram of the present invention.

[0047] Figure 4 It is a partial circuit diagram of the logic control module of the present invention.

[0048] Figure 5 Logic flow diagram of the present invention. DETAILED DESCRIPTION

[0049] like Figure 1-5 , the present invention adopts modular design, including a clock and control signal generating module, an analog Hall signal generating module, a logic control module, a signal acquisition and processing module, a power supply and load module;

[0050] The power supply is used to supply power to the clock and control signal generating module, the analog Hall signal generating module and the logic control module respectively;

[0051] The clock and control signal generating module, the analog Hall signal generating module and the logic control module are electrically connected in sequence;

[0052] The logic control module is electrically connected to the input ends of the clock and control signal generating module and the signal acquisition and processing module respectively;

[0053] The output end of the logic control module gives a signal to the load module of the test product;

[0054] The load module feeds back the electrical signal to the signal acquisition and processing module;

[0055] The present invention generates six-channel PWM control signals through a clock generation module, an analog Hall signal generation module, and a logic control module. The signal acquisition and processing module realizes the acquisition and processing of the real-time state of the test product, and realizes the protection function through the logic control module. The power supply and load module provides power and load for the system.

[0056] The analog Hall signal generation module uses pure hardware to realize the cyclic analog Hall signal. It can imitate the motor Hall position sensor to realize the simulation control of the test product. There is no failure problem of magnetic components exceeding the Curie point at high temperature.

[0057] The clock and control signal generation module, analog Hall signal generation module, logic control module, signal acquisition and processing module all adopt pure hardware design to achieve the steady-state life aging test requirements for three-phase brushless motor driver products with a maximum of 1200V / 200A in the full temperature range (-55℃~125℃). The modular design is easy to use and maintain.

[0058] As a specific circuit introduction, the analog Hall signal generation module includes chips U6A, U6B, U7A and logic AND gates U8A, U8B, U8C; among them, the clock signal is divided into three paths, which are respectively connected to pin 3 of chip U6A, pin 13 of U6B, and pin 13 of U7A;

[0059] The signal terminal HA is electrically connected to the positive output terminal 1 of the chip U6 B and the pin 11 of the chip U7A respectively;

[0060] The signal terminal HB is electrically connected to the input terminal 6 of the logic AND gate U8B, the input terminal 5 of the chip U6 B, and the positive output terminal 15 of the chip U6A;

[0061] The signal terminal HC is electrically connected to the input terminal 2 of the logic AND gate U8A, the input terminal 9 of the logic AND gate U8C, and the positive output terminal 15 of the chip U7A;

[0062] In chip U6B, pin 6 is connected to output terminal 3 of logic AND gate U8A; pin 5 is also connected to positive output terminal 15 of chip U6A; pins 4 and 7 are grounded; negative output terminal 2 is connected to input terminal 5 of logic AND gate U8B and negative input 8 of logic AND gate U8C;

[0063] In chip U6A, pin 10 is connected to the negative output terminal 14 of chip U7A; pin 11 is connected to the output terminal 10 of op amp UBC; pins 6 and 12 are grounded; negative output terminal 14 is connected to input terminal 1 of logic AND gate U8A;

[0064] In chip U7A, pin 10 is connected to output terminal 4 of logic AND gate U8B; pins 6 and 12 are grounded;

[0065] Clock and control signal generation module, outputting CLK clock signal;

[0066] The logic control module adopts PLC, which is connected to the signal terminals HA, HB, and HC respectively;

[0067] The signal acquisition and processing module can be current sampling or voltage sampling on a conventional circuit.

[0068] like Figure 4 The present invention generates six PWM control signals through a clock generation module, a simulated Hall signal generation module, and a logic control module, and outputs them to a three-phase brushless motor driver. The signal acquisition and processing module realizes the acquisition and processing of the real-time status of the test product, and realizes the protection function through the logic control module. The power supply and load module provides power supply and load for the system.

[0069] When the analog signal is generated, each chip in the analog Hall signal generation module operates according to the logical relationship of the three equations in the above formula.

[0070] The analog Hall signal generation module receives the CLK clock signal when working, and generates the timing signal through logic transformation. It has a self-starting function and can run cyclically from sequence 1 to sequence 6.

[0071] The system working principle of the present invention:

[0072] The clock and control signal generation module is used to generate a 1kHz square wave, which acts on the analog Hall signal generation module as a clock signal CLK; then, a control signal is generated, which acts on the logic control module to control the start and stop of the entire system.

[0073] The analog Hall signal generation module generates analog Hall signals through logic transformation and acts on the logic control module to generate PWM six-way commutation signals.

[0074] The logic control module generates six-channel PWM commutation signals to control the operation of the three-phase brushless motor driver, and receives over-temperature and overload signals generated by the signal acquisition and processing module to control the system status.

[0075] The power module provides weak and strong electrical signals for the entire system.

[0076] The load module provides a resistive load that meets the specification requirements for the three-phase brushless motor driver.

[0077] like Figure 1-5 , the test steps of the present invention are:

[0078] S1, power on and check the control end modules including the clock and control signal generation module, the analog Hall signal generation module, and the logic control module, and power off after the check is completed;

[0079] S2. Install the three-phase brushless motor driver to be aged;

[0080] S3. Setting aging parameters according to preset technical requirements;

[0081] S3, power on the control end module;

[0082] S4. Power on the power end module.

[0083] The present invention is fully described for a clearer disclosure, and the prior art is not listed one by one.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein with equivalents; it is obvious for those skilled in the art to combine multiple technical solutions of the present invention. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention. The technical contents not described in detail in the present invention are all known technologies.

Claims

1. A burn-in system for a three-phase brushless motor driver, characterized in that: It includes a clock and control signal generation module, an analog Hall signal generation module, a logic control module, a signal acquisition and processing module and a load module; The clock and control signal generating module, the analog Hall signal generating module and the logic control module are electrically connected in sequence; The logic control module is electrically connected to the input ends of the clock and control signal generating module and the signal collecting and processing module respectively.

2. The burn-in system for the three-phase brushless motor driver according to claim 1, characterized in that: The aging system also includes a power supply; The power supply supplies power to the clock and control signal generating module, the analog Hall signal generating module and the logic control module respectively.

3. The burn-in system for the three-phase brushless motor driver according to claim 1, characterized in that: The output end of the logic control module gives a signal to the load module of the test product; The load module feeds back the electrical signal to the signal acquisition and processing module.

4. The burn-in system for the three-phase brushless motor driver according to claim 1, characterized in that: The signal acquisition and processing module is a current sampling circuit or a voltage sampling circuit.

5. The burn-in system for the three-phase brushless motor driver according to claim 1, characterized in that: The analog Hall signal generation module includes chips U6A, U6B, U7A and logic AND gates U8A, U8B, U8C; wherein the clock signal is divided into three paths, which are respectively connected to pin 3 of chip U6A, pin 13 of U6B, and pin 13 of U7A; The signal terminal HA is electrically connected to the positive output terminal 1 of the chip U6 B and the pin 11 of the chip U7A respectively; The signal terminal HB is electrically connected to the input terminal 6 of the logic AND gate U8B, the input terminal 5 of the chip U6 B, and the positive output terminal 15 of the chip U6A; The signal terminal HC is electrically connected to the input terminal 2 of the logic AND gate U8A, the input terminal 9 of the logic AND gate U8C, and the positive output terminal 15 of the chip U7A; In chip U6B, pin 6 is connected to output terminal 3 of logic AND gate U8A; pin 5 is also connected to positive output terminal 15 of chip U6A; pins 4 and 7 are grounded; negative output terminal 2 is connected to input terminal 5 of logic AND gate U8B and negative input 8 of logic AND gate U8C; In chip U6A, pin 10 is connected to the negative output terminal 14 of chip U7A; pin 11 is connected to the output terminal 10 of op amp UBC; pins 6 and 12 are grounded; negative output terminal 14 is connected to input terminal 1 of logic AND gate U8A; In chip U7A, pin 10 is connected to output terminal 4 of logic AND gate U8B; pins 6 and 12 are grounded; A clock and control signal generating module, the clock and control signal generating module includes a chip U1; In chip U1, pin 1 is grounded, pin 3 outputs CLK clock signal; CLK clock signal is also electrically connected to oscilloscope XSC1, pin 5 is grounded through capacitor C2, pin 2 is connected to pin 6, pin 2 is grounded through capacitor C1, resistor R3 is connected between pin 7 and pin 2, pin 8 and pin 4 are connected to VCC respectively; VCC is connected to pin 7 through resistor R1; The logic control module includes logic gates U1A-U1D, U2A-U2C, U3A-U3D, U4A-U4C; The three analog Hall signals HB, HC, and HA are connected to one input terminal of the XOR gate U1A-U1C through resistors R4, R3, and R2 respectively, and the other output terminal of the XOR gate U1A-U1C is connected to the reference signal through resistor R1; The output terminals of XOR gates U1A-U1C correspond to the input terminals of NAND gates U3A, U3B, and U3D respectively; The output of XOR gate U1A is also electrically connected to the input of JK NAND gates U4C and U2C respectively; The output end of XOR gate U1B is also electrically connected to the input ends of NAND gates U2A and U4B respectively; The output end of XOR gate U1C is also electrically connected to the input ends of NAND gates U2B and U4A respectively; The output ends of the NAND gates U3A, U3B, and U3D are electrically connected to the input ends of the NAND gates U2A, U2B, and U2C respectively; NAND gates U2A, U2B, and U2C output PWM control signals HB, HC, and HA respectively; The output ends of the NAND gates U3A, U3B, and U3D are also connected to the input ends of the JK NAND gates U4A, U4B, and U4C respectively; The signal acquisition and processing module adopts an overcurrent feedback control signal circuit; the overcurrent feedback control signal circuit includes NOT gates U5A and U5B; The current sampling signal OC connected to the load module outputs the enable signal EN through the NOT gates U5A and U5B; the enable signal EN and PWM are connected to the input end of the XOR gate U1D through the NAND gate U3C; the output end of the XOR gate U1D is respectively connected to one input end of the NAND gates U2A-U2C; JK NAND gates U4A, U4B, and U4C output PWM control signals LA, LC, and LB respectively; The load module includes a three-phase brushless motor driver; The test product is a three-phase brushless motor.

6. A burn-in method for a three-phase brushless motor driver, characterized in that: By means of the system according to claim 1; Follow these steps; S1, power on and check the clock and control signal generation module, the analog Hall signal generation module, and the logic control module, and power off after the verification is completed; S2, install the three-phase brushless motor driver to be aged; S3, setting aging parameters according to preset technical requirements; S3, power-on test; S4, first, the clock and control signal generating module generates a 1kHz square wave, which is sent to the analog Hall signal generating module as the clock signal CLK; then, the analog Hall signal generating module generates an analog Hall signal through logic transformation, and the analog Hall signal acts on the logic control module to generate a PWM six-way commutation signal; secondly, the PWM six-way commutation signal is output to the three-phase brushless motor driver; thirdly, the signal acquisition and processing module collects and processes the load module and feeds back to the logic control module.

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