Cross-chip clock synchronization system, chip and electronic equipment

Abstract

The invention relates to a cross-chip clock synchronization system, chips and electronic equipment. The clock synchronization system comprises a first clock adjustment link, a second clock adjustment link and a clock phase difference detection module, the first clock adjustment link is configured to adjust the phase delay of an input clock signal and generate a first clock signal based on the adjusted input clock signal; the first clock adjusting link is arranged in the two chips in a crossing manner, and the first clock adjusting link comprises a first cross-chip transmission circuit; the second clock adjustment link is configured to adjust the phase delay of the input clock signal and generate a second clock signal based on the adjusted input clock signal; the second clock adjusting link comprises a delay copy circuit, and the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay copy circuit; the clock phase difference detection circuit is configured to detect a phase difference between the first clock signal and the second clock signal. According to the invention, clock skew across chips can be reduced.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to a cross-chip clock synchronization system, chip and electronic equipment. Background Art

[0002] In cross-chip application scenarios, data and clock interaction is required between chips. In some cases, chip 1 (die1) and chip 2 (die2) are synchronized clocks. However, since the two clocks are distributed on different chips, and different chips may have large clock skews (clock skew) due to differences in manufacturing processes and manufacturing process angles, the clocks of chip 1 and chip 2 may have large clock skews (clock skew), and timing problems may be encountered when transmitting synchronous data. For example, if the trigger in die1 sends data to the trigger in die2 based on the clk1 clock, and the trigger in die2 receives data based on the clk2 clock, or, conversely, the trigger in die2 sends data to the trigger in die1 based on the clk2 clock, and the trigger in die1 receives data based on the clk1 clock, if the clock skews (clock skew) of clk1 and clk2 are too large, the setup and hold of the trigger timing may not meet the requirements at the same time.

[0003] In the prior art, clock alignment is mainly achieved through a delay-locked loop. The disadvantage of the delay-locked loop clock alignment technology is that it will introduce a clock cycle difference, such as a clock cycle difference between the aligned clock clk2 and the reference clock clk1. In some scenarios (such as dynamic frequency modulation scenarios), the clock cycle difference introduced by the delay-locked loop clock alignment technology is not allowed. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a cross-chip clock synchronization system, chip and electronic device to reduce clock skew caused by cross-chip transmission.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a cross-chip clock synchronization system, including: a first clock adjustment link, a second clock adjustment link, and a clock phase difference detection module; the first clock adjustment link is configured to adjust the phase delay of an input clock signal and generate a first clock signal based on the adjusted input clock signal; the first clock adjustment link is arranged across two chips, the first clock adjustment link includes a first cross-chip transmission circuit, the first cross-chip transmission circuit is used to transmit a target clock signal and / or the first clock signal, the target clock signal is the input clock signal or the adjusted input clock signal; the second clock adjustment link is configured to adjust the input clock signal The phase delay of the first clock signal is adjusted, and a second clock signal is generated based on the adjusted input clock signal; the second clock adjustment link includes a delay replication circuit, and the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay replication circuit; a clock phase difference detection module is connected to the first clock adjustment link and the second clock adjustment link respectively, and the clock phase difference detection circuit is configured to detect the phase difference between the first clock signal and the second clock signal to obtain a first detection value; wherein the first detection value is used to adjust the phase delay of the first clock adjustment link and / or the second clock adjustment link to synchronize the phases of the first clock signal and the second clock signal.

[0007] In the above embodiment, by introducing a delay replication circuit in the second clock adjustment link, since the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay replication circuit, the delay effect increased in the first clock adjustment link due to the introduction of the first cross-chip transmission circuit is offset, so that only one clock phase difference detection circuit is required to accurately detect the phase difference of the clock signals output by the first clock adjustment link and the second clock adjustment link to obtain a first detection value, so that the phase delay of the first clock adjustment link and / or the second clock adjustment link can be adjusted according to the first detection value to synchronize the phases of the first clock signal and the second clock signal, thereby reducing the clock skew caused by cross-chip transmission, reducing the clock skew caused by different manufacturing processes, reducing the clock skew caused by different manufacturing process angles, and will not introduce clock cycle differences.

[0008] In combination with a possible implementation manner of the embodiment of the first aspect, the two chips include: a first chip and a second chip; the clock phase difference detection module is located in the second chip, the second chip is used to generate the input clock signal, and the first clock adjustment link includes two first cross-chip transmission circuits, wherein one first cross-chip transmission circuit is used to transmit the target clock signal, and the other first cross-chip transmission circuit is used to transmit the second clock signal.

[0009] In the above embodiment, when the clock phase difference detection module is located in the second chip and the input clock signal is generated by the second chip, two first cross-chip transmission circuits can be set, one for transmitting the target clock signal and the other for transmitting the second clock signal. In this way, the first clock adjustment link can be distributed in the two chips to realize cross-chip design.

[0010] In combination with a possible implementation manner of the embodiment of the first aspect, the first clock adjustment link includes a first clock delay adjustment circuit, a first cross-chip transmission circuit, a first clock network, and another first cross-chip transmission circuit connected in sequence; or, the first clock adjustment link includes a first cross-chip transmission circuit, a first clock delay adjustment circuit, a first clock network, and another first cross-chip transmission circuit connected in sequence; the first clock delay adjustment circuit is configured to adjust the phase delay of the input clock signal; the first clock network is configured to generate the first clock signal based on the adjusted input clock signal.

[0011] In the above embodiment, the first clock adjustment link may include the above two structures to adapt to different scenario requirements. The phase delay of the input clock signal is adjusted by introducing a first clock delay adjustment circuit to ensure the phase synchronization of the first clock signal and the second clock signal. At the same time, the first clock network is introduced to generate a clock signal with stronger driving capability, thereby improving the driving capability and stability of the system.

[0012] In combination with a possible implementation manner of the embodiment of the first aspect, the second clock adjustment link includes a second clock delay adjustment circuit, one of the delay replication circuits, a second clock network, and another of the delay replication circuits connected in sequence; or, the second clock adjustment link includes one of the delay replication circuits, a second clock delay adjustment circuit, a second clock network, and another of the delay replication circuits connected in sequence; the second clock delay adjustment circuit is configured to adjust the phase delay of the input clock signal; the second clock network is configured to generate the second clock signal based on the adjusted input clock signal.

[0013] In the above embodiment, the second clock adjustment link may include the above two structures. Since the first clock adjustment link includes two cross-chip transmission circuits, two delay replication circuits are also introduced in the second clock adjustment link to offset the influence of the cross-chip transmission circuit on the delay. At the same time, the phase delay of the input clock signal is adjusted by introducing the second clock delay adjustment circuit to ensure the phase synchronization between the first clock signal and the second clock signal, and the second clock network is introduced to generate a clock signal with stronger driving capability, thereby improving the driving capability and stability of the system. In this way, the structure of the second clock adjustment link is similar to that of the first clock adjustment link, which is beneficial to reduce the clock skew caused by cross-chip transmission, reduce the clock skew caused by different manufacturing processes, and reduce the clock skew caused by different manufacturing process angles.

[0014] In combination with a possible implementation manner of the embodiment of the first aspect, the two chips include: a first chip and a second chip; the clock phase difference detection module is located in the first chip, and the second chip is used to generate the input clock signal; the second clock adjustment link is arranged across the two chips, and the delayed replication circuit is a second cross-chip transmission circuit, and the second cross-chip transmission circuit is used to transmit the second clock signal.

[0015] In the above embodiment, if the clock phase difference detection module is located in the first chip and the second chip is used to generate the input clock signal, the delay replication circuit adopts a cross-chip transmission circuit design, so that the second clock adjustment link can be dispersedly arranged in the two chips to achieve a cross-chip design.

[0016] In combination with a possible implementation manner of the embodiment of the first aspect, the reference clock input end of the clock phase difference detection module is used to receive the second clock signal, and the feedback clock input end of the clock phase difference detection module is used to receive the first clock signal; if the product of the first detection value and the detection accuracy of the clock phase difference detection module is a positive value, it indicates that the phase of the second clock signal is ahead of the phase of the first clock signal; if the product of the first detection value and the detection accuracy of the clock phase difference detection module is a negative value, it indicates that the phase of the second clock signal is behind the phase of the first clock signal.

[0017] In the above embodiment, the phase relationship between the first clock signal and the second clock signal can be quickly determined in the above manner, thereby improving efficiency.

[0018] In combination with a possible implementation manner of the embodiment of the first aspect, the clock phase difference detection module is also configured to detect the phase difference between the divided signal and the delayed signal of the target reference signal to obtain a second detection value; wherein the delayed signal is obtained by delaying the divided signal by N times the clock period of the target reference signal, and N is a positive number greater than 0; the second detection value is used to determine the detection accuracy of the clock phase difference detection module.

[0019] In the above embodiment, due to different environments (such as changes in voltage on the path, deviations in frequency response or different temperatures), the measurement accuracy of the clock phase difference detection module may deviate. By measuring the phase difference between two signals with a known phase difference, the detection accuracy of the clock phase difference detection module can be accurately obtained, thereby maximizing the phase synchronization of the first clock signal and the second clock signal.

[0020] In combination with a possible implementation manner of the first aspect embodiment, the clock synchronization system also includes: a control module, which is respectively connected to the clock phase difference detection module, the first clock adjustment link, and the second clock adjustment link, and the control module is configured to adjust the phase delay of the first clock adjustment link and / or the first clock adjustment link according to the first detection value to synchronize the phases of the first clock signal and the second clock signal.

[0021] In the above embodiment, a control module is introduced to adjust the first clock adjustment link and / or the phase delay of the first clock adjustment link according to the first detection value so as to synchronize the phases of the first clock signal and the second clock signal. This eliminates the need for real-time interaction with external devices, which is beneficial to improving the timeliness of control and thus improving the adjustment efficiency.

[0022] In the second aspect, an embodiment of the present application also provides a chip, including: a first chip, a second chip and a clock synchronization system provided by any possible implementation method of the first aspect embodiment mentioned above, wherein the first clock adjustment link in the clock synchronization system is arranged across the first chip and the second chip.

[0023] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a chip provided in the embodiment of the second aspect described above.

[0024] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0026] Figure 1 A schematic structural diagram of a cross-chip clock synchronization system provided in an embodiment of the present application is shown.

[0027] Figure 2 A schematic diagram showing the relationship between the delay between the input and output and the control word of a clock delay adjustment circuit provided in an embodiment of the present application is shown.

[0028] Figure 3a A first layout diagram of a clock synchronization system provided in an embodiment of the present application is shown.

[0029] Figure 3b A second layout schematic diagram of the clock synchronization system provided in an embodiment of the present application is shown.

[0030] Figure 4a A third layout schematic diagram of the clock synchronization system provided in an embodiment of the present application is shown.

[0031] Figure 4b A fourth layout schematic diagram of the clock synchronization system provided in an embodiment of the present application is shown.

[0032] Figure 5 A schematic structural diagram of a cross-chip transmission circuit provided in an embodiment of the present application is shown.

[0033] Figure 6 A schematic diagram showing the relationship between an input signal and an output value of a clock phase difference detection module provided in an embodiment of the present application is shown.

[0034] Figure 7 A schematic diagram showing the principles of a cross-chip clock synchronization system provided in an embodiment of the present application is shown.

[0035] Figure 8 A schematic diagram showing the principle of adjusting clock skew by a control module provided in an embodiment of the present application is shown.

[0036] Fig. 9 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0038] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device.

[0039] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0040] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0041] In view of the shortcomings of the existing delay-locked loop clock alignment technology, this application proposes a cross-chip clock alignment solution, which can reduce the clock skew caused by cross-chip transmission, reduce the clock skew caused by different manufacturing processes, reduce the clock skew caused by different manufacturing process angles, and will not introduce clock cycle differences. Figure 1 The cross-chip clock synchronization system provided in an embodiment of the present application is described.

[0042] like Figure 1 As shown, the clock synchronization system includes: a first clock adjustment link, a second clock adjustment link and a clock phase difference detection module. The clock phase difference detection module is connected to the first clock adjustment link and the second clock adjustment link respectively.

[0043] The first clock adjustment link is configured to adjust the phase delay of the input clock signal (such as represented by clkin), and generate a first clock signal (such as represented by clk1) based on the adjusted input clock signal. The second clock adjustment link is configured to adjust the phase delay of the input clock signal, and generate a second clock signal (such as represented by clk2) based on the adjusted input clock signal. The clock phase difference detection circuit is configured to detect the phase difference between the first clock signal and the second clock signal to obtain a first detection value.

[0044] The first detection value is used to adjust the phase delay of the first clock adjustment link and / or the second clock adjustment link so that the phases of the first clock signal and the second clock signal are synchronized (or aligned). The phase relationship of the first clock signal relative to the second clock signal can be learned based on the first detection value. When adjusting the phase delay of the first clock adjustment link and / or the second clock adjustment link so that the phases of the first clock signal and the second clock signal are synchronized, if the first clock signal is ahead of the phase of the second clock signal, the first clock adjustment link is controlled to increase the phase delay, and / or the second clock adjustment link is controlled to reduce the phase delay; if the first clock signal is behind the phase of the second clock signal, the first clock adjustment link is controlled to reduce the phase delay, and / or the second clock adjustment link is controlled to increase the phase delay.

[0045] The phase synchronization of the first clock signal and the second clock signal mentioned in the present application does not mean that the phases of the first clock signal and the second clock signal must be equal or aligned. It can be to make the phases of the first clock signal and the second clock signal as equal as possible, or to make the phase relationship between the two as certain as possible, for example, the first clock signal is always faster (or slower) than the second clock signal by a certain time.

[0046] The first clock adjustment link is arranged across two chips (including the first chip and the second chip), and the first clock adjustment link includes a first cross-chip transmission circuit, and the first cross-chip transmission circuit is used to transmit a target clock signal and / or a first clock signal, and the target clock signal is an input clock signal or an adjusted input clock signal. Signal transmission across the two chips is achieved by introducing the first cross-chip transmission circuit.

[0047] The second clock adjustment link includes a delay replication circuit, and the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay replication circuit. By introducing the delay replication circuit in the second clock adjustment link, since the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay replication circuit, the delay effect increased by the introduction of the first cross-chip transmission circuit in the first clock adjustment link can be offset. In some possible implementations, the circuit structure of the delay replication circuit can be the same as the structure of the first cross-chip transmission circuit. In some possible implementations, the delay replication circuit can also be implemented using an inverter, as long as the transmission delay of the delay replication circuit is consistent with the transmission delay of the first cross-chip transmission circuit.

[0048] A circuit spanning two chips usually refers to "cross-chip design" in circuit design, which involves distributing a complete circuit system across two or more physical chips instead of integrating it on a single chip.

[0049] In addition, the first clock adjustment link and the second clock adjustment link also include a clock delay adjustment circuit and a clock network (clockmesh). The clock delay adjustment circuit in the first clock adjustment link can be called a first clock delay adjustment circuit, and the clock delay adjustment circuit in the second clock adjustment link can be called a second clock delay adjustment circuit; similarly, the clock network in the first clock adjustment link can be called a first clock network, and the clock network in the second clock adjustment link can be called a second clock network. The first clock adjustment link and the second clock adjustment link have similar structures, but there may be a clock skew between the first clock signal and the second clock signal due to differences in manufacturing processes and manufacturing process angles. Therefore, the clock delay is adjusted by introducing a clock delay adjustment circuit in the first clock adjustment link and the second clock adjustment link, and ultimately the phase synchronization of the first clock signal and the second clock signal is ensured.

[0050] The first clock delay adjustment circuit is configured to adjust the phase delay of the input clock signal, which may be to increase or decrease the phase delay of the input clock signal. The first clock network is configured to generate a first clock signal based on the adjusted input clock signal, wherein the driving capability of the first clock signal is stronger than the driving capability of the input clock signal, that is, the first clock network is configured to generate a clock signal with a stronger driving capability based on the adjusted input clock signal.

[0051] The second clock delay adjustment circuit is configured to adjust the phase delay of the input clock signal, which may be to increase or decrease the phase delay of the input clock signal. The second clock network is configured to generate a second clock signal based on the adjusted input clock signal, wherein the driving capability of the second clock signal is stronger than the driving capability of the input clock signal, that is, the second clock network is configured to generate a clock signal with a stronger driving capability based on the adjusted input clock signal.

[0052] The main function of the first clock delay adjustment circuit and the second clock delay adjustment circuit is to adjust the delay between the input clock and the output clock under the control of the control word (such as represented by dlysel[7:0]), the frequency range can be 100MHz~5000MHz, the adjustment step is about 2ps, and the output duty cycle is 45%~55%. Definition T step is the adjustment step of the first clock delay adjustment circuit (or the second clock delay adjustment circuit), then the delay between the input clock and the output clock: delay = T step *dlysel[7:0]+delay0, dlysel[7:0] is the control word, delay0 is the initial delay. Define delay_min and delay_max as the minimum delay and maximum delay of the first clock delay adjustment circuit (or the second clock delay adjustment circuit), respectively. In this application, delay_min≈100ps and delay_max≈500ps. The corresponding relationship between the delay between the input clock and the output clock of the first clock delay adjustment circuit (or the second clock delay adjustment circuit) and the control word dlysel[7:0] can be as follows: Figure 2 As shown. The control word dlysel[7:0] for controlling the first clock delay adjustment circuit and the second clock delay adjustment circuit is not limited to the 8 bits in the above example, and can be other bits.

[0053] The first clock delay adjustment circuit and the second clock delay adjustment circuit may include a delay unit for adjusting the delay, and the delay unit may be implemented by using a delay unit in the related art. The first clock network and the second clock network may also be implemented by using a clock network in the related art.

[0054] In the first implementation mode, the above-mentioned two chips include: a first chip (such as represented by die1) and a second chip (such as represented by die2), the clock phase difference detection module can be located in the second chip, and the second chip can include a clock source for generating an input clock signal clkin. At this time, the first clock adjustment link includes two first cross-chip transmission circuits, wherein one first cross-chip transmission circuit is used to transmit the target clock signal, and the other first cross-chip transmission circuit is used to transmit the second clock signal.

[0055] In the first implementation, if Figure 3a As shown, the first clock adjustment link includes a first clock delay adjustment circuit, a first cross-chip transmission circuit, a first clock network, and another first cross-chip transmission circuit connected in sequence. At this time, one first cross-chip transmission circuit is used to transmit the adjusted input clock signal, and another first cross-chip transmission circuit is used to transmit the first clock signal. Or, Figure 3b As shown, the first clock adjustment link includes a first cross-chip transmission circuit, a first clock delay adjustment circuit, a first clock network, and another first cross-chip transmission circuit connected in sequence. At this time, one first cross-chip transmission circuit is used to transmit the input clock signal, and the other first cross-chip transmission circuit is used to transmit the first clock signal.

[0056] In the first embodiment, the second clock adjustment link may include a second clock delay adjustment circuit, a delay replication circuit, a second clock network, and another delay replication circuit connected in sequence; or, the second clock adjustment link may include a delay replication circuit, a second clock delay adjustment circuit, a second clock network, and another delay replication circuit connected in sequence.

[0057] In the second implementation, the above two chips include: a first chip and a second chip; the clock phase difference detection module can be located in the first chip, and the second chip can include a clock source for generating an input clock signal. In this case, the second clock adjustment link is arranged across the two chips, the delay replication circuit is a second cross-chip transmission circuit, and the second cross-chip transmission circuit is used to transmit the second clock signal.

[0058] In a second implementation manner, the second clock adjustment link includes a second clock delay adjustment circuit, a second clock network, and a second cross-chip transmission circuit connected in sequence. In a possible implementation manner, Figure 4a As shown, the first clock adjustment link includes a first clock delay adjustment circuit, a first cross-chip transmission circuit, and a first clock network connected in sequence. Figure 4b As shown, the first clock adjustment link includes a first cross-chip transmission circuit, a first clock delay adjustment circuit, and a first clock network which are connected in sequence.

[0059] In some possible implementations, the second chip and the first chip are both independent large chips, and different chips implement different functions. In some possible implementations, the second chip and the first chip can also be sub-chips under the large chip, and the large chip can include multiple small chips. For example, the large chip can be a processor, and the first chip and the second chip are both functional chips inside the processor.

[0060] In one possible implementation, the first cross-chip transmission circuit and the second cross-chip transmission circuit can both be cross-chip transmission circuits implemented by through silicon via (TSV) technology. TSV is a technology that opens holes in silicon wafers to allow electrical signals to be transmitted vertically between different layers of a chip. Through TSV technology, chips can be electrically interconnected in a vertical direction to achieve multi-layer chip stacking, significantly improving the interconnection density and integration of the chip and reducing signal delay and power consumption.

[0061] The first cross-chip transmission circuit and the second cross-chip transmission circuit may both include a TSV through hole and a TSVIO interface located on both sides of the TSV through hole, and the TSVIO interface is connected to the TSV through hole. The schematic diagram thereof is shown in FIG. Figure 5 shown.

[0062] The reference clock input terminal (such as represented by detin_rf) of the above-mentioned clock phase difference detection module is used to receive the second clock signal clk2, and the feedback clock input terminal (such as represented by detin_fb) of the clock phase difference detection module is used to receive the first clock signal clk1. If the product of the first detection value and the detection accuracy of the clock phase difference detection module is a positive value, it indicates that the phase of the second clock signal is ahead of the phase of the first clock signal; if the product of the first detection value and the detection accuracy of the clock phase difference detection module is a negative value, it indicates that the phase of the second clock signal is behind the phase of the first clock signal. Of course, the reference clock input terminal of the clock phase difference detection module can also be used to receive the first clock signal clk1, and the feedback clock input terminal of the clock phase difference detection module can also be used to receive the second clock signal clk2. At this time, if the product of the first detection value and the detection accuracy of the clock phase difference detection module is a negative value, it indicates that the phase of the second clock signal is ahead of the phase of the first clock signal; if the product of the first detection value and the detection accuracy of the clock phase difference detection module is a positive value, it indicates that the phase of the second clock signal is behind the phase of the first clock signal.

[0063] Assume T res is the detection accuracy of the clock phase difference detection module, td tsv is the delay of the first cross-chip transmission circuit (or delay replication circuit), detout is the first detection value; then the phase of the detin_rf end is: ph clk2 +td tsv ; The phase of detin_fb terminal is: ph clk1 +td tsv , then T res *detout=(ph clk1 +td tsv )-(ph clk2 +td tsv ), about to go to tdtsv And simplify, we have: ph clk1 -ph clk2 =T res *detout, define code = T res *detout. When code = 0, it can be considered that the rising edges of the clocks of die1 and die2 are aligned, that is, the clock skew is close to 0.

[0064] In some possible implementations, detout can be a 7-bit signal, namely detout[6:0], the highest bit is the sign bit, and the output range is (-64, 63). If the rising edge of the detin_rf terminal signal is earlier than the rising edge of the detin_fb terminal signal (Tdelay>0), the output of the clock phase difference detection module (detout[6:0]) is a positive value. If the rising edge of the detin_rf terminal signal is later than the rising edge of the detin_fb terminal signal (Tdelay<0), the output of the clock phase difference detection module (detout[6:0]) is a negative value. The relationship between the detin_rf terminal, the detin_rf terminal signal and the output value of the clock phase difference detection module is as follows: Figure 6 As shown in the figure, Tdelay represents the rising edge delay between the two signals at the detin_fb and detin_rf ends.

[0065] The output bits of detout are not limited to the 7 bits in the above example, but may also be other bits, such as 8 bits, 6 bits, etc. The clock phase difference detection module adopts a circuit or device for detecting a clock phase difference in the prior art.

[0066] In some embodiments, the clock phase difference detection module is further configured to detect the phase difference between the divided signal of the target reference signal and the delayed signal to obtain a second detection value. The delayed signal is obtained by delaying the divided signal by N times the clock period of the target reference signal, where N is a positive number greater than 0. The second detection value is used to determine the detection accuracy of the clock phase difference detection module.

[0067] The process of configuring the clock phase difference detection module to detect the phase difference between the divided signal of the target reference signal and the delayed signal to obtain the second detection value can be called the calibration process of the clock phase difference detection module. In actual products, the manufacturing process, manufacturing process angle, temperature, and voltage of the chip may be different. These factors will affect the detection accuracy of the clock phase difference detection module (such as using T res Therefore, when using the clock phase difference detection module, it is necessary to calibrate the clock phase difference detection module first to obtain the detection accuracy. In the calibration mode, the period of the target reference signal at the input detin_rf end is defined as T clkThe target reference signal is usually a high-speed clock, which is divided into a low-speed clock (such as calclk). For example, the high-speed clock is divided by 16 to obtain the divided signal of the low-speed clock, and then the divided signal calclk is delayed by N times T using the clock period of the target reference signal. clk , get the delayed signal (such as calclk_d), so the phase difference between calclk_d and calclk is N times T clk ; Afterwards, the clock phase difference detection module is used to detect the phase difference between calclk_d and calclk, and the second detection value is output, such as calout, which is:

[0068] Right now When N=1,

[0069] In some possible implementations, the clock synchronization system further includes: a control module. The control module is connected to the clock phase difference detection module, the first clock adjustment link, and the second clock adjustment link respectively. The control module is configured to adjust the first clock adjustment link and / or the phase delay of the first clock adjustment link according to the first detection value to synchronize the phases of the first clock signal and the second clock signal.

[0070] When the control module adjusts the phase delay of the first clock adjustment link and / or the second clock adjustment link to synchronize the phases of the first clock signal and the second clock signal, if the phase of the first clock signal is ahead of the second clock signal, the control module controls the first clock adjustment link to increase the phase delay, and / or controls the second clock adjustment link to reduce the phase delay; if the phase of the first clock signal is behind the second clock signal, the control module controls the first clock adjustment link to reduce the phase delay, and / or controls the second clock adjustment link to increase the phase delay.

[0071] The control module may be arranged in the first chip or in the second chip. If the clock phase difference detection module is arranged in the first chip and the control module is arranged in the second chip, the clock phase difference detection module is connected to the control module via a cross-chip transmission circuit.

[0072] In some possible implementations, the schematic diagram of the cross-chip clock synchronization system provided in the embodiment of the present application can be as follows: Figure 7 shown. Figure 7 This is only one example of many clock synchronization system embodiments of the present application. Figure 7 In the example shown, the control module and the clock phase difference detection module are both located in die2. Figure 7The structure of the delay replication circuit in is the same as that of the first cross-chip transmission circuit, and the implementation method of the delay replication circuit is not limited thereto. In the power-on state, the control words of dlyseldie1[7:0] and dlyseldie2[7:0] can be defaulted to 0. By introducing the delay replication circuit 1, the phase alignment of phdie1_2 and phdie2_2 under the power-on default control word can be ensured, and the convergence time of the negative feedback regulation loop can be reduced. The introduction of the delay replication circuit 2 can ensure that the delay from phclk1 to phfb is very close to the delay from phclk2 to phrf. In this way, the input phase difference (phfb-phrf) of the clock phase difference detection module is approximately equal to the phase difference between the two clock meshes (phclk1-phclk2), so that only one clock phase difference detection module is required to accurately detect the phase difference between the two clock meshes.

[0073] When reducing clock skew, the adjustment principle is as follows Figure 8 As shown, the control words of dlyseldie1[7:0] and dlyseldie2[7:0] can be configured to be 0 first, and the initial phase difference ph between the first clock signal and the second clock signal under the default control word is detected. clk1 -ph clk2 =T res *detout, define code = T res *detout. After that, calculate code and determine whether its value is positive or negative. If the initial value of code is greater than 0, it means that the phase of clk2 is ahead of the phase of clk1. It is necessary to gradually increase dlyseldie2[7:0] to gradually increase the delay of the second clock delay adjustment circuit, and calculate the value of code in real time. When code changes from a positive value to a negative value, the adjustment ends. If the initial value of code is less than 0, it means that the phase of clk2 lags behind the phase of clk1. It is necessary to gradually increase dlyseldie1[7:0] to gradually increase the delay of the first clock delay adjustment circuit, and calculate the value of code in real time. When code changes from a negative value to a positive value, the adjustment ends.

[0074] Figure 8In the figure, skewadjustdie1 represents the first clock delay adjustment circuit, and skewadjustdie2 represents the second clock delay adjustment circuit. In some possible implementations, in the initial state, the control words of dlyseldie1[7:0] and dlyseldie2[7:0] can also be set to the maximum value. If the initial value of code is greater than 0, it indicates that the phase of clk2 is ahead of the phase of clk1, and it is necessary to gradually reduce dlyseldie1[7:0] to gradually reduce the delay of the first clock delay adjustment circuit, and calculate the value of code in real time. When code changes from a positive value to a negative value, the adjustment ends. If the initial value of code is less than 0, it indicates that the phase of clk2 lags behind the phase of clk1, and it is necessary to gradually reduce dlyseldie2[7:0] to gradually reduce the delay of the second clock delay adjustment circuit, and calculate the value of code in real time. When code changes from a negative value to a positive value, the adjustment ends.

[0075] The above control module can be implemented by using a controller in the related art. In one implementation, the controller can be a FSM (Finite State Machine).

[0076] The embodiment of the present application also provides a chip, including the above-mentioned first chip, second chip and clock synchronization system, wherein the first clock adjustment link in the clock synchronization system is arranged across the first chip and the second chip. In some possible ways, the second clock adjustment link in the clock synchronization system can also be arranged across the first chip and the second chip.

[0077] In some possible implementations, the chip may be a processor, wherein the first chip and the second chip correspond to different functional modules in the processor, respectively. The processor may be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence), an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a data processing core of a DSP (Digital Signal Processor), etc. It may also be a processor chip used in some large-scale data computing scenarios. The above is only an example and should not be a limitation to this application.

[0078] The clock synchronization system provided by the chip embodiment has the same implementation principle and technical effects as those of the aforementioned clock synchronization system embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference can be made to the corresponding contents in the aforementioned clock synchronization system embodiment.

[0079] The present application also provides an electronic device, which includes the clock synchronization system described above. In some possible implementations, Fig. 9 As shown, Fig. 9 The structure block diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device comprises: a transceiver, a memory, a communication bus and a processor. The processor may be the above-mentioned chip.

[0080] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store a computer program, wherein the computer program includes at least one software function module that can be stored in the memory in the form of software or firmware or solidified in the operating system (OS) of the electronic device. The processor is used to execute the software function module or computer program stored in the memory.

[0081] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (ElectricErasable Programmable Read-Only Memory, EEPROM), etc.

[0082] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor may also be any conventional processor, etc.

[0083] Among them, the above-mentioned electronic devices include but are not limited to mobile phones, tablets, notebooks, servers, etc.

[0084] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0085] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0086] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A cross-chip clock synchronization system, characterized in that: include: A first clock adjustment link is configured to adjust a phase delay of an input clock signal and generate a first clock signal based on the adjusted input clock signal; The first clock adjustment link is arranged across two chips, the first clock adjustment link comprises a first cross-chip transmission circuit, the first cross-chip transmission circuit is used to transmit a target clock signal and / or the first clock signal, the target clock signal is the input clock signal or the adjusted input clock signal; a second clock adjustment link configured to adjust a phase delay of the input clock signal and generate a second clock signal based on the adjusted input clock signal; the second clock adjustment link comprises a delay replication circuit, and the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay replication circuit; A clock phase difference detection module is connected to the first clock adjustment link and the second clock adjustment link respectively, and the clock phase difference detection circuit is configured to detect the phase difference between the first clock signal and the second clock signal to obtain a first detection value; wherein the first detection value is used to adjust the phase delay of the first clock adjustment link and / or the second clock adjustment link to synchronize the phases of the first clock signal and the second clock signal.

2. The clock synchronization system according to claim 1, characterized in that: The two chips include: a first chip and a second chip; the clock phase difference detection module is located in the second chip, the second chip is used to generate the input clock signal, and the first clock adjustment link includes two of the first cross-chip transmission circuits, wherein one of the first cross-chip transmission circuits is used to transmit the target clock signal, and the other first cross-chip transmission circuit is used to transmit the second clock signal.

3. The clock synchronization system according to claim 2, characterized in that: The first clock adjustment link includes a first clock delay adjustment circuit, one of the first cross-chip transmission circuits, a first clock network, and another of the first cross-chip transmission circuits connected in sequence; or, the first clock adjustment link includes one of the first cross-chip transmission circuits, a first clock delay adjustment circuit, a first clock network, and another of the first cross-chip transmission circuits connected in sequence; The first clock delay adjustment circuit is configured to adjust the phase delay of the input clock signal; The first clock network is configured to generate the first clock signal based on the adjusted input clock signal.

4. The clock synchronization system according to claim 3, characterized in that: The second clock adjustment link includes a second clock delay adjustment circuit, one of the delay replication circuits, a second clock network, and another of the delay replication circuits connected in sequence; or, the second clock adjustment link includes one of the delay replication circuits, the second clock delay adjustment circuit, the second clock network, and another of the delay replication circuits connected in sequence; The second clock delay adjustment circuit is configured to adjust the phase delay of the input clock signal; The second clock network is configured to generate the second clock signal based on the adjusted input clock signal.

5. The clock synchronization system according to claim 1, characterized in that: The two chips include: a first chip and a second chip; the clock phase difference detection module is located in the first chip, and the second chip is used to generate the input clock signal; the second clock adjustment link is arranged across the two chips, and the delay replication circuit is a second cross-chip transmission circuit, and the second cross-chip transmission circuit is used to transmit the second clock signal.

6. The clock synchronization system according to claim 1, characterized in that: The reference clock input terminal of the clock phase difference detection module is used to receive the second clock signal, and the feedback clock input terminal of the clock phase difference detection module is used to receive the first clock signal; If the product of the first detection value and the detection accuracy of the clock phase difference detection module is a positive value, it indicates that the phase of the second clock signal is ahead of the phase of the first clock signal; If the product of the first detection value and the detection accuracy of the clock phase difference detection module is a negative value, it indicates that the phase of the second clock signal lags behind the phase of the first clock signal.

7. The clock synchronization system according to claim 6, characterized in that: The clock phase difference detection module is also configured to detect the phase difference between the divided signal and the delayed signal of the target reference signal to obtain a second detection value; wherein the delayed signal is obtained by delaying the divided signal by N times the clock period of the target reference signal, and N is a positive number greater than 0; the second detection value is used to determine the detection accuracy of the clock phase difference detection module.

8. The clock synchronization system according to any one of claims 1 to 7, characterized in that: The clock synchronization system also includes: The control module is connected to the clock phase difference detection module, the first clock adjustment link, and the second clock adjustment link, respectively. The control module is configured to adjust the phase delay of the first clock adjustment link and / or the first clock adjustment link according to the first detection value to synchronize the phases of the first clock signal and the second clock signal.

9. A chip, characterized in that: include: A first chip, a second chip, and a clock synchronization system according to any one of claims 1 to 8, wherein a first clock adjustment link in the clock synchronization system is arranged across the first chip and the second chip.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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