Approximate addition circuit control method based on memristor and approximate addition operation device

Abstract

The invention discloses an approximate addition circuit control method based on a memristor and an approximate addition operation device, and belongs to the technical field of microelectronic logic operation. In the approximate addition circuit, the majority gate logic operation M (a, b, c) can be realized by inputting logic values to be subjected to majority gate logic operation into the first memristor, the second memristor and the third memristor and regulating and controlling the voltage, and the majority gate logic operation # imgabs0 # can be realized by inputting logic values to be subjected to majority gate logic operation into the first memristor, the second memristor and the fourth memristor and regulating and controlling the voltage. And carrying out iteration on the two kinds of majority gate logic operations to realize approximate addition operation. According to the invention, because the two different majority gate logic operations can reuse the operation unit, the integration level of the device is relatively high, and the calculation speed is relatively high.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic logic operation, and more specifically, relates to an approximate addition circuit control method based on a memristor and an approximate addition operation device. Background Art

[0002] The addition operation can be implemented through the majority-inverter graph (MIG) logic. MIG consists of majority gate logic (MAJ) and inverter logic (INV). The logic expression of the three-input majority decision gate is: M(a,b,c) = a·b + a·c + b·c, and the expression of the inverter logic is: , the addition operation can be realized by iterating MAJ and negating logic.

[0003] Since memristors have the advantages of low power consumption, small size and compatibility with CMOS processes, they are ideal candidate devices for in-memory computing architectures. Therefore, memristors are usually used to implement majority gate logic operations. The existing implementation scheme of majority gate logic based on memristors uses three memristor units to operate a, b, and c respectively, realizing a three-input majority gate logic M(a,b,c) = a·b + a·c + b·c. Although it can reduce hardware complexity, this logic scheme only supports a single logic operation and lacks the implementation of inversion logic. In the addition operation implemented based on majority gate logic, it often involves not only the traditional majority gate logic M(a,b,c) = a·b + a·c + b·c, but also the majority gate logic including inversion logic. ; Since two different types of majority gate logic are involved at the same time, if the existing memristor-based majority gate logic is used to implement addition operations, the number of devices required is large, the integration is low, and the calculation speed is also low, which cannot meet the needs of adders in practical applications with high integration and calculation speed.

[0004] Therefore, it is urgent to propose a new solution to improve the integration and calculation speed of addition operations. Summary of the invention

[0005] In view of the above defects or improvement needs of the prior art, the present invention provides an approximate addition circuit control method based on a memristor and an approximate addition operation device, so as to improve the integration and calculation speed of the addition operation device.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a control method for an approximate addition circuit based on a memristor, wherein the majority gate circuit comprises: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to a common node of the three memristors and the resistor; the resistance value of the resistor is the low-resistance resistance value of the memristor; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c used in the i-th round of addition into the third memristor i ; Select the first to third memristors to participate in the calculation: Apply voltage V to the positive electrodes of the first to third memristors respectively 1 , connect the reference voltage V to the second input of the voltage comparator Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c used in the i+1th round of addition i+1 ; Write c into the fourth memristor i+1 , Select the first, second and fourth memristors to participate in the calculation: apply voltage V to the positive electrodes of the first and second memristors respectively. 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the fourth memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition i ; After completing the nth round of addition, c n+1 s n ......s 2 s 1 for a n ......a 2 a 1 With b n ......b 2 b 1 The addition result of Where i=1,2,...,n; 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; the high-resistance state of the memristor corresponds to a logic value of "0", and the low-resistance state corresponds to a logic value of "1". When the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

[0007] Optionally, the first input terminal is a positive terminal, the second input terminal is a negative terminal, the first level is a high level, and the second level is a low level.

[0008] In a second aspect, the present invention provides an approximate addition operation device based on a memristor, comprising: an approximate addition circuit and a controller; The approximate addition circuit comprises: a voltage comparator, a resistor and four identical memristors, from the first to the fourth; the negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low-resistance resistance value of the memristor; The controller is used to execute the control method provided by the first aspect of the present invention.

[0009] Optionally, the resistance values ​​of the low resistance state and the high resistance state of the memristor differ by at least two orders of magnitude.

[0010] In a third aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect of the present invention when executing the computer program.

[0011] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect of the present invention.

[0012] In a fifth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect of the invention.

[0013] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects: 1. The present invention is for M(a, b, c) and The two majority gate logics are combined to achieve approximate addition. Although the approximate adder sacrifices some accuracy, it can simplify the circuit structure, reduce power consumption, shorten operation delay and reduce chip area. It can greatly improve the integration and calculation speed of addition operations, and has good application prospects in image processing, artificial intelligence and signal processing.

[0014] 2. The key to the approximate addition operation of the present invention lies in the Two majority gate logic designs, where M(a,b,c) and Both majority gate logics can be realized by manipulating the same approximate addition circuit. The approximate addition circuit only needs to set up four memristors, one resistor and one voltage comparator. By inputting the logic value to be operated on the majority gate logic operation to the first, second and third memristors and adjusting the voltage, the result of the majority gate logic operation is determined by the voltage comparator according to the comparison result between the common node voltage and the reference voltage, and the majority gate logic operation M(a, b, c) can be realized. By inputting the logic value to be operated on the majority gate logic operation to the first, second and fourth memristors and adjusting the voltage, the result of the majority gate logic operation is determined by the voltage comparator according to the comparison result between the common node voltage and the reference voltage, and the majority gate logic operation can be realized. By iterating the two majority gate logic operations, approximate addition operations can be realized. In the present invention, since two different majority gate logic operations can reuse multiple operation units, the addition operation device has a high integration level and a high calculation speed.

[0015] 3. In the present invention, the majority gate logic is realized When performing the operation, the decomposition into two independent logic operations of majority gate logic M(a, b, c) and negation logic is avoided, and the operation can be achieved by applying voltage in one step without increasing the number of memristors. The majority gate logic operation can be achieved with fewer devices and faster computing speed. Based on this, the present invention can meet the demand for approximate adders in practical applications with higher integration and faster computing speed.

[0016] 4. In the present invention, after the logic calculation is completed, the states of the three input memristors still maintain the written input information values, which is non-destructive to the input information and non-volatile, thereby realizing a logic circuit whose input is the resistance value of the memristor and whose operation process is non-destructive; the data reuse of the circuit is strong, and in practical applications, no additional copying operation is required to save data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of an approximate addition circuit provided in one embodiment of the present invention.

[0018] Figure 2 A schematic diagram of a gate-level representation of an addition operation based on majority gate logic provided in one embodiment of the present invention.

[0019] Figure 3 A schematic diagram of a majority gate circuit for implementing majority gate logic provided by an embodiment of the present invention.

[0020] Figure 4 A control schematic diagram of majority gate logic M(a, b, c) provided in one embodiment of the present invention.

[0021] Figure 5 A schematic diagram of the design concept of majority gate logic M(a, b, c) provided in one embodiment.

[0022] Figure 6 An equivalent circuit of a memristor after a logic value is written into it provided by an embodiment.

[0023] Figure 7 A majority gate logic provided by an embodiment of the present invention Control diagram of .

[0024] Figure 8 A majority gate logic provided by an embodiment of the present invention Schematic diagram of the design concept.

[0025] Fig. 9 The figure is a graph of experimental results of implementing 1-bit addition approximation operation using the addition operation method proposed in the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] In a first aspect, the present invention provides a control method for an approximate addition circuit based on a memristor, for realizing an n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The addition operation.

[0029] like Figure 1 As shown, the adding circuit includes: a voltage comparator, a resistor and four identical memristors from the first to the fourth; the negative electrodes of the four memristors are connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Select three memristors and record them as the first memristor M a , the second memristor M b and the third memristor M c ; Write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c of the i-th round of addition into the third memristor i ; Wherein, logic "1" means setting the memristor resistance state to low resistance, and logic "0" means setting the memristor resistance state to high resistance. When i=1, the carry c 1 Input by the user, can be either logic "1" or logic "0".

[0030] Select the first to third memristors to participate in the calculation: apply voltage V to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively. 1 , connect the reference voltage V to the second input of the voltage comparator Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry used in the i+1th round of addition In this process, the first memristor, the second memristor, the third memristor, the resistor and the voltage comparator realize the majority gate logic operation M(a i ,b i ,c i) = a i b i + a i ·c i + b i ·c i .

[0031] The remaining unset memristor is denoted as the fourth memristor M d , write M(a i ,b i ,c i ), that is, write the carry bit into the fourth memristor , Select the first, second and fourth memristors to participate in the calculation: apply voltage V to the positive electrodes of the first memristor and the second memristor respectively 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the third memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , which is denoted as s i ; In this process, the first memristor, the second memristor, the fourth memristor, the resistor and the voltage comparator realize the majority gate logic operation .

[0032] After n rounds of addition sub-processes, s n ......s 2 s 1 and c n+1 This is the desired n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The addition result of Where i=1,2,...,n; 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2; V setis the threshold for the memristor to change from a high-resistance state to a low-resistance state; the corresponding logic value is written by setting the high and low resistance states of the memristor, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1"; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs the first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs the second level, and the second level is used as the result of the majority gate logic operation "0".

[0033] Specifically, the first input terminal is a positive terminal, the second input terminal is a negative terminal, the first level is a high level, and the second level is a low level.

[0034] It can be understood that the corresponding relationship between the output level of the voltage comparator and the logic value can be flexibly set. For example, the first input terminal is the positive terminal, the second input terminal is the negative terminal, the first level is the high level, the second level is the low level, the high level is used as the result of the majority gate logic operation "1", and the low level is used as the result of the majority gate logic operation "0". Alternatively, the first input terminal can be used as the negative terminal, the second input terminal can be used as the positive terminal, the first level is the low level, the second level is the high level, the low level is used as the result of the majority gate logic operation "1", and the high level is used as the result of the majority gate logic operation "0".

[0035] The gate-level representation diagram of the addition operation based on majority gate logic is as follows Figure 2 The control method of the memristor-based approximate addition circuit provided by the present invention performs two majority gate logic operations. The first majority gate logic operation M(a i ,b i ,c i ) Output the carry of the next bit , the second majority gate logic operation Output calculation results i , by combining the results of n addition sub-processes, we can get an n-bit approximate addition result.

[0036] The following describes the majority gate logic operation M(a, b, c) and the majority gate logic operation M(a, b, c) performed in each round of addition sub-process in the approximate addition operation of the present invention. The implementation process is described in detail.

[0037] In the approximate addition operation, the first memristor, the second memristor, the third memristor, the resistor and the voltage comparator realize the majority gate logic operation M(a, b, c); the first memristor, the second memristor, the fourth memristor, the resistor and the voltage comparator realize the majority gate logic operation It can be seen that the majority gate circuit structures based on the two different majority gate logic operations are the same, and both can be based on Figure 3The majority gate circuit shown is controlled, and different majority gate logic operations can be achieved by different controls.

[0038] like Figure 3 As shown, the majority gate circuit of each majority gate logic includes: M 1 、M 2 and M 3 Three memristors, a fixed resistor and a voltage comparator; among them, the memristor M 1 、M 2 and M 3 The positive electrode passes through the control terminal T 1 、T 2 and T 3 To control, one end of the fixed resistor passes through the control terminal T 4 The other end of the fixed resistor is connected to the memristor M 1 、M 2 and M 3 The voltage of the common node is V Com Indicates that the remaining four control ports T 1 、T 2 、T 3 and T 4 The control voltages are V T1 、V T2 、V T3 and V T4 The positive terminal of the voltage comparator is connected to the common node of the memristor and the series resistor, and the negative terminal is connected to the reference voltage V Ref , the output voltage is V o .

[0039] The memristor has two resistance states, namely high resistance state (HRS) and low resistance state (LRS). By applying a port voltage of a specific direction and magnitude, the memristor can switch between the two resistance states. set The memristor can be set from a high-resistance state to a low-resistance state by applying a forward voltage less than V reset The memristor can change from a low resistance state to a high resistance state by applying a negative voltage V set V is the threshold voltage at which the memristor changes from a high-resistance state to a low-resistance state; reset is the threshold voltage at which the memristor changes from a low resistance state to a high resistance state.

[0040] The high and low configuration resistances of the memristor are R H and R L , R H < <R LPreferably, in this embodiment, the resistance of the resistor is equal to the resistance of the low resistance of the memristor. H =100KΩ, low resistance R L =1KΩ, the resistance R=1KΩ.

[0041] The three input variables a, b, and c of the majority gate logic are mapped to memristors M 1 、M 2 and M 3 The resistance state of the memristor is the logic value "0", and the low resistance state of the memristor is the logic value "1". The output of the logic is the voltage value of the comparator output port, where the output V o = V+ indicates that the output is high level, and the corresponding logic result is "1"; the output V o = V- indicates that the output is low level, and the corresponding logic result is "0".

[0042] Based on the above logic circuit, only the control port T needs to be changed. 1 、T 2 、T 3 and T 4 The applied control voltage can realize M(a,b,c) and Two types of majority gate logic.

[0043] (1) Implementation of majority gate logic M(a,b,c).

[0044] like Figure 4 As shown, by controlling the port T 1 、T 2 、T 3 and T 4 Apply voltage V 1 、V 1 、V 1 , 0, V Ref = V Ref1 ; The result of the logic operation is obtained through the output of the voltage comparator, the port voltage V 1 The voltage comparator reference voltage V Ref The following constraints must be met: 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; V 1 The value of V must ensure that the logic value currently written into the memristor cannot be changed, and V Ref1 The value of must ensure that the voltage comparator can output the correct calculation result. The design idea is as follows Figure 5 shown.

[0045] The principle of the logic implementation is that when the input memristor M1 、M 2 and M 3 When at least two memristors are in low resistance state, the voltage V Com Greater than the comparator reference voltage V Ref1 , thus outputting a high level "1"; conversely, when the input memristor M 1 、M 2 and M 3 When at most one memristor is in low resistance state, the voltage V Com Less than the comparator reference voltage V Ref1 , thus outputting a low level "0". This realizes the majority gate logic M(a,b,c).

[0046] by Figure 5 The second combination in the example further illustrates that the above method can obtain the correct logical operation result, and the other combinations are analogous. In the second combination, a logic value "1" and two logic values ​​"0" are input and written into the memristor M respectively. 1 、M 2 and M 3 , the memristor corresponding to the logic value "1" is in a low resistance state, and the memristor corresponding to the logic value "0" is in a high resistance state. Therefore, the equivalent circuit after writing the logic value is as follows: Figure 6 As shown, at this time, the voltage of the common node V Com for: ; That is, the voltage V Com Smaller than and close to V 1 / 2, and V 1 / 2<V Ref1 , therefore, the voltage V Com Less than V Ref1 Therefore, the voltage comparator outputs a low level, indicating a logical value of "0", and the results of most gate logic operations are correct.

[0047] (2) Majority gate logic Implementation.

[0048] like Figure 7 As shown, by controlling the port T 1 、T 2 、T 3 and T 4 Apply voltage V 2 、V 2 , 0, 0, V Ref = V Ref2 ; The result of the logic operation is obtained through the output of the voltage comparator, the port voltage V 2 The comparator reference voltage V Ref2 The following constraints must be met: 0<V2 <V set ; V 2 / 3<V Ref2 <V 2 / 2,V 2 The value of V must ensure that the logic value currently written into the memristor cannot be changed, and V Ref2 The value of must ensure that the voltage comparator can output the correct calculation result. The design idea is as follows Figure 8 shown.

[0049] The principle of the logic implementation is that when the input memristor M 1 、M 2 When both are low resistance "1", the voltage V of the common node can be pulled up Com , the voltage of the common node V Com Greater than the comparator reference voltage V Ref2 , thus outputting a high level "1"; and when the input memristor M 1 、M 2 There is a high impedance "0" and the input memristor M 3 When it is low resistance "1", it will pull down the voltage V of the common node Com , the voltage of the common node V Com Less than the comparator reference voltage V Ref2 , thus outputting a low level "0". This is how most gate logic is realized .

[0050] In the present invention, the approximate addition calculation formula implemented based on the above two different majority gate logics in the i-th round of addition sub-process is as follows: ; The truth table corresponding to the calculation formula is shown in Table 1 below, where type A is the approximate addition result obtained by the present invention. It can be seen that there are only two summation errors, and the rest of the summation results are correct, indicating that the present invention can achieve approximate addition. Moreover, although a certain degree of calculation accuracy is sacrificed, M(a, b, c) and The two majority gate logics can be implemented based on the same approximate addition circuit, and the majority gate logic operation can reuse multiple operation units, especially the first memristor and the second memristor, because M(a, b, c) and The two majority gate logics multiplex the logic values ​​of the first memristor and the second memristor, so there is no need to set more memristors and perform more logic write operations, so the addition operation device has a higher integration level and a faster calculation speed.

[0051] Furthermore, a 1-bit addition circuit (n = 1) based on two majority gate logics is used as an example for explanation. Specifically, the high resistance R H =100KΩ, low resistance R L =1KΩ, the resistor R = 1KΩ. Verify the adder function and get Fig. 9 The experimental results shown in Figure 2 show that R M represents the resistance of the memristor, a i , b i 、c i is the input logic value, c i+1 is the measured result of carry, m i The measured result of summation, s i For the accurate result of the summation, the accuracy of the summation result is 6 / 8, the carry does not produce an error, and all are correct. It can be seen from the figure that the one-bit approximate full adder provided by the present invention functions correctly, and the calculation accuracy of the present invention is high.

[0052] In a second aspect, the present invention provides an approximate addition operation device, comprising: an approximate addition circuit and a controller; The approximate addition circuit includes: a voltage comparator, a resistor and four memristors; the negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method provided by the first aspect of the present invention.

[0053] Preferably, in an optional implementation manner, the resistance value of the resistor is a low-resistance resistance value of the memristor.

[0054] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0055] In a third aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect of the present invention when executing the computer program.

[0056] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0057] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect of the present invention.

[0058] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0059] In a fifth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect of the invention.

[0060] In summary, the present invention aims to solve the problems of high latency and high hardware overhead when using single-logic memristor majority gates to implement addition arithmetic by designing an approximate addition circuit control method and an approximate addition operation device based on memristors. By multiplexing memristors, it is possible to implement a three-input majority gate logic M(a,b,c) = a·b + a·c +b·c, and a new majority gate logic including negation logic. By iterating the two logical operations, approximate addition operations can be realized. Therefore, the present invention can effectively improve the performance of the arithmetic function of the adder, significantly reduce hardware resource consumption and delay, and provide a new technical path for efficiently realizing in-memory computing.

[0061] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for an approximate adding circuit based on a memristor, characterized in that: Used to implement n-bit number a n ......a2a1 and b n ......approximate addition operation of b2b1; the approximate addition circuit comprises: a voltage comparator, a resistor and four identical memristors from the first to the fourth; the negative electrodes of the four memristors are connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c used in the i-th round of addition into the third memristor i ; Select the first to third memristors to participate in the calculation: apply voltage V1 to the positive electrodes of the first to third memristors respectively, and connect the reference voltage V to the second input terminal of the voltage comparator. Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c used in the i+1th round of addition i+1 ; Write c into the fourth memristor i+1 , Select the first, second and fourth memristors to participate in the calculation: apply voltage V2 to the positive electrodes of the first and second memristors respectively, apply a voltage with an amplitude of 0 to the positive electrode of the fourth memristor, and connect the reference voltage V to the second input terminal of the voltage comparator. Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition i ; After completing the nth round of addition, c n+1 s n ......s2s1 is a n ......a2a1 and b n ......the result of adding b2b1; Where i=1,2,...,n; 0<V1<V set ; V1 / 2<V Ref1 <2V1 / 3;0<V2<V set ; V2 / 3<V Ref2 <V2 / 2;V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; the high-resistance state of the memristor corresponds to a logic value "0", and the low-resistance state corresponds to a logic value "1". When the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

2. The control method according to claim 1, characterized in that: The first input terminal is a positive terminal, the second input terminal is a negative terminal, the first level is a high level, and the second level is a low level.

3. A memristor-based approximate addition device, characterized in that: include: Approximate adding circuits and controllers; The approximate adding circuit comprises: a voltage comparator, a resistor and four identical memristors, from first to fourth; The negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method as claimed in claim 1 or 2.

4. The approximate addition operation device according to claim 3, characterized in that: The resistance values ​​of the low-resistance state and the high-resistance state of the memristor differ by at least two orders of magnitude.

5. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to claim 1 or 2 when executing the computer program.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method according to claim 1 or 2.

7. A computer program product, characterized in that The invention comprises a computer program / instruction, which implements the control method as claimed in claim 1 or 2 when executed by a processor.

Images