LQG-controlled state matrix static and dynamic separation configuration circuit and method

Abstract

The invention belongs to the technical field of computer application, and particularly discloses an LQG-controlled state matrix static and dynamic separation configuration circuit and method. A static element configuration unit in the circuit comprises a sequential logic circuit module, a first digital circuit module and a second digital circuit module, and a judgment result of the sequential logic circuit module is output to the first digital circuit module and the second digital circuit module; the static element configuration unit outputs the initialized static matrix to the dynamic element configuration unit, and the dynamic element configuration unit comprises a third digital circuit module. The method comprises the following steps: S1, judging whether a static matrix storage block is initialized or not according to a sequential logic circuit module; s2, the dynamic element configuration unit generates a continuous time state matrix; and calculating dynamic matrix elements of the matrix through a third digital circuit module, and jointly storing the dynamic matrix elements in a dynamic matrix storage block. According to the method, the reusability of the state equation matrix can be improved, the computing resources are saved, and the computing time is shortened.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer application, and in particular relates to a static and dynamic separation configuration circuit and method for a state matrix controlled by an LQG. Background Art

[0002] A controllable seismic source generates seismic fluctuations by continuously impacting the ground with a vibrator mounted on a car. A hydraulically driven controllable seismic source generates vibrations through hydraulic drive and couples with the ground through the vibrator's flat plate, causing synchronous vibrations of the ground in a reaction manner, thereby generating artificial seismic waves as output signals.

[0003] The quality of seismic data obtained by seismic exploration mainly depends on the consistency between the waveform of the coupled ground force signal and the waveform of the scanning drive signal, that is, the consistency between the output signal and the reference signal. The closer the output signal and the reference signal are, the higher the quality and credibility of the data obtained by exploration. Vibroseis sources require a reliable control system to ensure the consistency between the output signal coupled into the ground and the reference signal, thereby ensuring the reliability of the obtained data.

[0004] LQG control refers to the closed-loop control of the controllable vibrator using linear quadratic optimal control combined with Kalman filtering. This method obtains the LQG control system equation through mathematical modeling in advance, and then finds the optimal solution of the input signal under the current reference signal and output signal. When mathematically modeling, it is necessary to calculate the continuous form state equation matrix of the system based on the parameters of the servo valve, cylinder, weight, plate and earth.

[0005] Currently, the continuous form state equation matrix configuration adopts a one-time calculation method, which does not take advantage of the reusability of the system equations. For dynamically changing earth parameters, the state equation matrix needs to be recalculated, which takes up a lot of computing resources and increases the calculation time. Summary of the invention

[0006] In order to solve the above deficiencies existing in the known technology, the present invention aims to provide a dynamic and static separation, reusable state matrix configuration circuit to achieve the purpose of improving the reusability of the state equation matrix, saving computing resources and reducing computing time.

[0007] The present invention also provides a dynamic and static separation, reusable state matrix configuration method to solve the problems of poor reusability, high resource occupation and long calculation time in state equation matrix calculation.

[0008] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0009] A state matrix static and dynamic separation configuration circuit controlled by LQG, comprising a static element configuration unit and a dynamic element configuration unit;

[0010] The static element configuration unit is used to calculate the constant matrix elements of matrices A and B, and initialize the static matrix storage blocks [A] and [B]. The static element configuration unit includes a sequential logic circuit module for determining whether the static matrix storage blocks [A] and [B] are initialized, a first digital circuit module for initializing the static matrix storage blocks [A] and [B], and a second digital circuit module for initializing the static matrix storage blocks [A] and [B]. The determination result of the sequential logic circuit module is output to the first digital circuit module and the second digital circuit module, and the first digital circuit module and the second digital circuit module transmit the initialized static matrix to the dynamic element configuration unit.

[0011] The dynamic element configuration unit is used to calculate the dynamic matrix elements of matrices A and B, generate continuous-time state matrices Ac and Bc, and store them in the dynamic matrix storage block [Ac][Bc]; the dynamic element configuration unit includes a third digital circuit module.

[0012] As a limitation, the static matrix storage block [A] is composed of 9*9 storage units, each storage unit is represented by A[a][b], a∈[1,9], b∈[1,9], and the static matrix storage block [B] is composed of 9*1 storage units, each storage unit is represented by B[m][1], m∈[1,9]; each storage unit is a 32-bit single-precision floating-point storage unit;

[0013] The dynamic matrix storage block [Ac] consists of 9*9 storage units, each storage unit is represented as Ac[p][q], p∈[1,9], q∈[1,9]; the dynamic matrix storage block [Bc] consists of 9*1 storage units, each storage unit is represented as Bc[n][1], n∈[1,9], and each storage unit is a 32-bit single-precision floating-point storage unit.

[0014] As a further limitation, the sequential logic circuit module includes a counter;

[0015] The first digital circuit module includes a first register R1 to a fourth register R4 for storing servo valve parameters and coefficients, a first multiplier A1 to a second multiplier A2, a first squarer B1 and a first inverter C1;

[0016] The output end of the first register R1 is connected to the input end of the first multiplier A1, and the output end of the first multiplier A1 outputs the calculation result to B[3][1]; the output end of the second register R2 is connected to the first squarer B1 and the input end of the second multiplier A2, the output end of the first squarer is connected to the input end of the first multiplier A1 and the first inverter C1, and the output end of the first inverter C1 outputs the calculation result to A[3][2]; the output end of the third register R3 and the output end of the fourth register R4 are connected to the input end of the second multiplier A2, and the output end of the second multiplier A2 outputs the calculation result to A[3][3].

[0017] As a second limitation, the second digital circuit module includes a quality selection module, a calculation multiplexing module and a negation selection module, the output end of the quality selection module is connected to the input end of the calculation multiplexing module, and the output end of the calculation multiplexing module is connected to the input end of the negation selection unit;

[0018] The quality selection module includes a fifth register R5 to a sixth register R6, and a first two-way selector D1; the calculation multiplexing module includes a seventh register R7 to a fourteenth register R14, a first adder F1 to a fourth adder F4, a third multiplier A3 to a sixth multiplier A6, a first divider E1 to a fifth divider E5, a second squarer B2, a second inverter C2 to a fourth inverter C4; the inversion selection module includes a second two-way selector D2 to a sixth two-way selector D6, and a fifth inverter C5 to a ninth inverter C9;

[0019] The output end of the fifth register R5 is connected to the first input end of the second two-way selector D2, the output end of the sixth register R6 is connected to the second input end of the second two-way selector D2, the external mode output end is connected to the third input end of the second two-way selector D2; the output end of the second two-way selector D2 is connected to the input end of the fourteenth register R14;

[0020] The output end of the seventh register R7 and the output end of the eighth register R8 are connected to the input end of the first adder F1, the output end of the first adder F1 is connected to the input end of the third multiplier A3 and the input end of the fifth multiplier A5; the input end of the third multiplier A3 is connected to the output end of the ninth register R9, the output end of the third multiplier A3 is connected to the input end of the second adder F2, the tenth register R10 is connected to the input end of the second adder F2 through the second squarer B2, the output end of the second adder F2 is connected to the input end of the first divider E1, and the tenth register R10 is connected to the input end of the second adder F2 through the second squarer B2. The output ends of the third register R13 and the fourteenth register R14 are connected to the input end of the sixth multiplier A6, the output end of the sixth multiplier A6 is connected to the input end of the first divider E1, the output end of the first divider E1 is connected to the input end of the third adder F3, the twelfth register is connected to the input end of the third adder F3 through the fourth divider E4, the output end of the third adder F3 is divided into two branches for output, the first branch is connected to the input end of the second two-way selector D2, and the second branch is connected to the input end of the third two-way selector D3 through the second inverter C2;

[0021] The output end of the ninth register R9 and the output end of the fourteenth register R14 are connected to the input end of the second divider E2, the first output end of the second divider E2 is connected to the input end of the fourth adder F4, and the second output end of the second divider E2 is connected to the input end of the fourth two-way selector D4;

[0022] The output end of the thirteenth register R13 and the output end of the fourteenth register R14 are connected to the input end of the sixth multiplier A6, the output end of the fifth register R5 is connected to the input end of the fifth multiplier A5, the output end of the fifth multiplier A5 and the output end of the sixth multiplier A6 are connected to the input end of the fifth divider E5, the output end of the fifth divider E5 is connected to the input end of the fourth adder F4, and the output end of the fourth adder F4 is connected to the input end of the fifth two-way selector D5 through the third inverter C3;

[0023] The output end of the tenth register R10 and the output end of the eleventh register R11 are connected to the input end of the fourth multiplier A4, the output end of the fourth multiplier A4 is connected to the input end of the third divider E3, the output end of the sixth multiplier A6 is the input end of the third divider E3, and the output end of the third divider E3 is connected to the input end of the sixth two-way selector D6 through the fourth inverter C4;

[0024] The second input terminals of the second to sixth two-way selectors D2 to D6 are all connected to inverters, and the external mode output terminals are respectively connected to the third input terminals of the second to sixth two-way selectors D2 to D6, and the output terminals of the second to sixth two-way selectors D2 to D6 are correspondingly output to A[6][8], A[6][5], A[6][9], A[6][6], A[6][1] or A[9][8], A[9][5], A[9][9], A[9][6], A[9][1].

[0025] As a third limitation, the third digital circuit module includes a fifteenth register R15 to an eighteenth register R18, a fifth adder F5, a sixth adder F6, a seventh multiplier A7, an eighth multiplier A8 and a sixth divider E6;

[0026] The output end of the seventeenth register R17 and the output end of the eighteenth register R18 are connected to the input end of the sixth divider E6, the output end of the sixth divider E6 and the output end of the sixteenth register R16 are connected to the input end of the eighth multiplier A8, the output end of the eighth multiplier A8 is connected to the input end of the fifth adder F5, the elements stored in Ac[9][8] are output to the fifth adder F5, and the output end of the fifth adder F5 outputs the calculation result to Ac[9][8];

[0027] The output end of the fifteenth register R15 and the output end of the eighteenth register R18 are connected to the input end of the seventh multiplier A7, the output end of the seventh multiplier A7 is connected to the input end of the sixth adder F6, the elements stored in Ac[9][8] are output to the sixth adder F6, and the output end of the sixth adder F6 outputs the calculation result to Ac[9][8].

[0028] The present invention also discloses a method for static and dynamic separation configuration of a state matrix of LQG control, which is implemented by using the static and dynamic separation configuration circuit of the state matrix of LQG control according to any one of claims 1 to 5. The method comprises the following steps performed in sequence:

[0029] S1, judging whether the static matrix storage blocks [A] and [B] are initialized according to the sequential logic circuit module;

[0030] S1, judging whether the static matrix storage blocks [A] and [B] are initialized according to the sequential logic circuit module;

[0031] If the sequential logic circuit module determines that the output is 1, it proves that it is not initialized, and then enters the three-stage initialization of the static matrix, calculates the constant matrix elements of matrices A and B through the first digital circuit module and the second digital circuit module, and initializes the static matrix storage blocks [A] and [B];

[0032] If the sequential logic circuit module determines that the output is not 1, it proves that the initialization has been performed, and the initialized matrices A and B are directly used to execute step S2;

[0033] S2. The dynamic element configuration unit generates continuous-time state matrices Ac and Bc; the dynamic matrix elements of matrices A and B are calculated through the third digital circuit module; the constant matrix elements and dynamic matrix elements of matrices A and B are stored together in the dynamic matrix storage block [Ac][Bc].

[0034] As a limitation, the three-stage initialization of the static matrix in step S1 includes:

[0035] In the first stage of initialization, first set the matrix elements in the static matrix storage block [A] and the static matrix storage block [B] of matrices A and B to 0, and then set A[1][2], A[2][3], A[4][5], A[5][6], A[7][8], and A[8][9] in the static matrix storage block [A] to 1;

[0036] The second stage is initialized, and the first digital circuit module is used to calculate the element of the third row and first column of matrix B. Where, k1 is the servo valve gain, ω0 is the cutoff frequency of the servo valve;

[0037] Calculate the element stored in A[3][2]

[0038] Calculate the element A[3][3]=-2ω0ξ stored in A[3][3], where ξ is the damping coefficient of the servo valve;

[0039] The third stage is initialization, which assigns a value to the equivalent mass according to the value of the external mode and calculates it through the second digital circuit module;

[0040] When the external mode value is 0, set M = M m , where M is the equivalent mass, M m For the equivalent mass of the hammer and the oil, the calculation reuse module is called to calculate five intermediate results, which are output and assigned one by one to A[6][1], A[6][8], A[6][5], A[6][6], and A[6][9] in the static matrix storage block [A];

[0041] When the external mode value is 1, set M = M p , where M pTo obtain the equivalent mass of the piston rod and the plate, the calculation multiplexing module is called to calculate five intermediate results, and the five intermediate results are inverted through the inversion selection module, and are output and assigned one by one to A[9][1], A[9][8], A[9][5], A[9][6], and A[9][9] in the static matrix storage block [A].

[0042] As a further limitation, the calculation process of calling the calculation reuse module to calculate the five intermediate results in step S13 is:

[0043] Define tmp1 = B*M, where B is the hydraulic cylinder oil compression coefficient;

[0044] tmp2=A p *k q , where A p is the piston area of ​​the hydraulic cylinder, k q is the flow gain of the main valve of the hydraulic cylinder;

[0045] tmp3=k c +C tp , where k c is the hydraulic cylinder flow pressure coefficient, C tp is the total leakage coefficient of the hydraulic cylinder;

[0046] tmp4=A p 2 ;

[0047] Among them, H s is the rigidity coefficient between the weight and the piston;

[0048] Among them, H v is the viscous damping coefficient between the weight and the piston;

[0049] The five intermediate results are:

[0050] Var3 = -Var2;

[0051] Var5=tmp6.

[0052] As a second limitation, the calculation of the dynamic storage unit matrix elements in step S2 includes the following steps performed in sequence:

[0053] S21, copy the constant matrix elements of matrices A and B to the continuous-time state matrices Ac and Bc;

[0054] S22. Definition Where S p is the area of ​​the plate;

[0055] S23, calculate two intermediate results Var1'=G s *tmp1', Var2' = G v *tmp1', where G s is the earth rigidity coefficient, G v is the earth damping coefficient;

[0056] S24, obtain the element stored in Ac[9][8] in the continuous-time state matrix Ac, add the element stored in Ac[9][8] to the intermediate result Var1', and write it back to Ac[9][8];

[0057] Add the elements stored in Ac[9][9] to the intermediate result Var2' and write them back to Ac[9][9] to obtain the complete continuous-time state matrix Ac, Bc.

[0058] Due to the adoption of the above technical solution, the present invention has the following beneficial effects compared with the prior art:

[0059] (1) The method of the present invention improves the reusability of the state equation matrix. The improvement of reusability is reflected in that when the static element configuration unit determines that the static matrix storage block has been initialized, the static matrix storage block after the first initialization is directly used; the improvement of reusability is also reflected in that the calculation reuse module performs calculations and initializations according to the changes in parameters of the external servo valve, cylinder, weight, plate and earth;

[0060] (2) The method of the present invention reduces the circuit resources and computing time occupied when configuring the controllable seismic source LQG control calculation state matrix.

[0061] In summary, the present invention can improve the reusability of the state equation matrix, save computing resources, and reduce computing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] Figure 1 This is a circuit diagram of a first digital circuit module in accordance with Embodiment 1 of the present invention;

[0064] Figure 2 This is a circuit diagram of a second digital circuit module in accordance with Embodiment 1 of the present invention;

[0065] Figure 3 is a circuit diagram of a third digital circuit module of Embodiment 1 of the present invention;

[0066] Figure 4 is a flow chart of the method of embodiment 2 of the present invention;

[0067] Figure 5 This is a schematic diagram of the first stage initialization of the static element configuration module of Example 2 of the present invention. DETAILED DESCRIPTION

[0068] In order to better explain the present invention and facilitate understanding, the preferred embodiments of the present invention are described in detail below through specific implementation modes in conjunction with the accompanying drawings.

[0069] Embodiment 1 LQG controlled state matrix static and dynamic separation configuration circuit

[0070] This embodiment includes a static element configuration unit and a dynamic element configuration unit; the static element configuration unit is used to calculate the constant matrix elements of matrices A and B and initialize the static matrix storage blocks [A] and [B]; the static element configuration unit includes a sequential logic circuit module for determining whether the static matrix storage blocks [A] and [B] are initialized, a first digital circuit module for initializing the static matrix storage blocks [A] and [B], and a second digital circuit module for initializing the static matrix storage blocks [A] and [B]; the judgment result of the sequential logic circuit module is output to the first digital circuit module and the second digital circuit module, and the first digital circuit module and the second digital circuit module transmit the initialized static matrix to the dynamic element configuration unit. The second digital circuit module includes a quality selection module, a calculation multiplexing module, and a negation selection module, the output end of the quality selection module is connected to the input end of the calculation multiplexing module, and the output end of the calculation multiplexing module is connected to the input end of the negation selection unit.

[0071] The dynamic element configuration unit is used to calculate the dynamic matrix elements of matrices A and B, generate continuous-time state matrices Ac and Bc, and store them in the dynamic matrix storage block [Ac][Bc]; the dynamic element configuration unit includes a third digital circuit module.

[0072] In this embodiment, the static matrix storage block [A] is composed of 9*9 storage units, each storage unit can be expressed as A[a][b], a∈[1,9], b∈[1,9], the static matrix storage block [B] is composed of 9*1 storage units, each storage unit is expressed as B[m][1], m∈[1,9]; the dynamic matrix storage block [Ac] is composed of 9*9 storage units, each storage unit is expressed as Ac[p][q], p∈[1,9], q∈[1,9]; the dynamic matrix storage block [Bc] is composed of 9*1 storage units, each storage unit is expressed as Bc[n][1], n∈[1,9], and each storage unit in the static matrix storage blocks [A], [B] and the dynamic matrix storage blocks [Ac], [Bc] is a 32-bit single-precision floating-point storage unit.

[0073] The sequential logic circuit module includes a counter. Figure 1As shown, the first digital circuit module includes a first register R1 to a fourth register R4, a first multiplier A1 to a second multiplier A2, a first squarer B1 and a first inverter C1 for storing servo valve parameters and coefficients; the first register R1 stores the servo valve gain, the second register R2 stores the servo valve cutoff frequency, the third register R3 stores the servo valve damping coefficient, and the fourth register stores the coefficient -2.

[0074] The output end of the first register R1 is connected to the input end of the first multiplier A1, and the output end of the first multiplier A1 outputs the calculation result to B[3][1]; the output end of the second register R2 is connected to the first squarer B1 and the input end of the second multiplier A2, the output end of the first squarer is connected to the input end of the first multiplier A1 and the first inverter C1, and the output end of the first inverter C1 outputs the calculation result to A[3][2]; the output end of the third register R3 and the output end of the fourth register R4 are connected to the input end of the second multiplier A2, and the output end of the second multiplier A2 outputs the calculation result to A[3][3].

[0075] like Figure 2 As shown, the mass selection module includes the fifth register R5 to the sixth register R6, and the first two-way selector D1. The fifth register R5 stores the equivalent mass of the weight and the oil, and the sixth register R6 stores the equivalent mass of the piston rod and the plate. If the external mode value is 0, the plate mass is output to the sixth register R6. If the mode value is 1, the weight mass is output to the sixth register R6.

[0076] The calculation multiplexing module includes the seventh register R7 to the fourteenth register R14, the first adder F1 to the fourth adder F4, the third multiplier A3 to the sixth multiplier A6, the first divider E1 to the fifth divider E5, the second squarer B2, the second inverter C2 to the fourth inverter C4, the seventh register R7 stores the flow pressure coefficient of the hydraulic cylinder, the eighth register R8 stores the total leakage coefficient of the hydraulic cylinder, the ninth register R9 stores the viscous damping coefficient between the weight and the piston, the tenth register R10 stores the piston area of ​​the hydraulic cylinder, the eleventh register R11 stores the flow gain of the hydraulic cylinder main valve, the twelfth register R12 stores the rigidity coefficient between the weight and the piston, the thirteenth register R13 stores the hydraulic cylinder oil compression coefficient, and the fourteenth register R14 stores the equivalent mass.

[0077] The inversion selection module includes a second two-way selector D2 to a sixth two-way selector D6 and a fifth inverter C5 to a ninth inverter C9.

[0078] The output end of the fifth register R5 is connected to the first input end of the second two-way selector D2, the output end of the sixth register R6 is connected to the second input end of the second two-way selector D2, the external mode output end is connected to the third input end of the second two-way selector D2; the output end of the second two-way selector D2 is connected to the input end of the fourteenth register R14;

[0079] The output end of the seventh register R7 and the output end of the eighth register R8 are connected to the input end of the first adder F1, the output end of the first adder F1 is connected to the input end of the third multiplier A3 and the input end of the fifth multiplier A5; the input end of the third multiplier A3 is connected to the output end of the ninth register R9, the output end of the third multiplier A3 is connected to the input end of the second adder F2, the tenth register R10 is connected to the input end of the second adder F2 through the second squarer B2, the output end of the second adder F2 is connected to the input end of the first divider E1, and the tenth register R10 is connected to the input end of the second adder F2 through the second squarer B2. The output ends of the third register R13 and the fourteenth register R14 are connected to the input end of the sixth multiplier A6, the output end of the sixth multiplier A6 is connected to the input end of the first divider E1, the output end of the first divider E1 is connected to the input end of the third adder F3, the twelfth register is connected to the input end of the third adder F3 through the fourth divider E4, the output end of the third adder F3 is divided into two branches for output, the first branch is connected to the input end of the second two-way selector D2, and the second branch is connected to the input end of the third two-way selector D3 through the second inverter C2;

[0080] The output end of the ninth register R9 and the output end of the fourteenth register R14 are connected to the input end of the second divider E2, the first output end of the second divider E2 is connected to the input end of the fourth adder F4, and the second output end of the second divider E2 is connected to the input end of the fourth two-way selector D4;

[0081] The output end of the thirteenth register R13 and the output end of the fourteenth register R14 are connected to the input end of the sixth multiplier A6, the output end of the fifth register R5 is connected to the input end of the fifth multiplier A5, the output end of the fifth multiplier A5 and the output end of the sixth multiplier A6 are connected to the input end of the fifth divider E5, the output end of the fifth divider E5 is connected to the input end of the fourth adder F4, and the output end of the fourth adder F4 is connected to the input end of the fifth two-way selector D5 through the third inverter C3;

[0082] The output end of the tenth register R10 and the output end of the eleventh register R11 are connected to the input end of the fourth multiplier A4, the output end of the fourth multiplier A4 is connected to the input end of the third divider E3, the output end of the sixth multiplier A6 is the input end of the third divider E3, and the output end of the third divider E3 is connected to the input end of the sixth two-way selector D6 through the fourth inverter C4;

[0083] The second input ends of the second two-way selector D2 to the sixth two-way selector D6 are all connected to inverters, the second input end of the second two-way selector D2 is connected to the output end of the fifth inverter C5, the second input end of the third two-way selector D3 is connected to the output end of the sixth inverter C6, the second input end of the fourth two-way selector D4 is connected to the output end of the seventh inverter C7, the second input end of the fifth two-way selector D5 is connected to the output end of the eighth inverter C8, the second input end of the sixth two-way selector D6 is connected to the output end of the ninth inverter C9, the external mode output end is respectively connected to the third input ends of the second two-way selector D2 to the sixth two-way selector D6, and the output ends of the second two-way selector D2 to the sixth two-way selector D6 are correspondingly output to A[6][8], A[6][5], A[6][9], A[6][6], A[6][1] or A[9][8], A[9][5], A[9][9], A[9][6], A[9][1].

[0084] When the external mode value is 0, the five values ​​output by the calculation multiplexing module are inverted and input into A[9][8], A[9][5], A[9][9], A[9][6], and A[9][1] respectively; when the external mode value is 1, the five values ​​output by the calculation multiplexing module are directly output into A[6][8], A[6][5], A[6][9], A[6][6], and A[6][1].

[0085] like Figure 3 As shown, the third digital circuit module includes the fifteenth register R15 to the eighteenth register R18, the fifth adder F5, the sixth adder F6, the seventh multiplier A7, the eighth multiplier A8 and the sixth divider E6. The fifteenth register R15 stores the earth damping coefficient, the sixteenth register R16 stores the earth rigidity coefficient, the seventeenth register R17 stores the plate area, and the eighteenth register R18 stores the equivalent mass of the piston rod and the plate.

[0086] The output end of the seventeenth register R17 and the output end of the eighteenth register R18 are connected to the input end of the sixth divider E6, the output end of the sixth divider E6 and the output end of the sixteenth register R16 are connected to the input end of the eighth multiplier A8, the output end of the eighth multiplier A8 is connected to the input end of the fifth adder F5, the elements stored in Ac[9][8] are output to the fifth adder F5, and the output end of the fifth adder F5 outputs the calculation result to Ac[9][8];

[0087] The output end of the fifteenth register R15 and the output end of the eighteenth register R18 are connected to the input end of the seventh multiplier A7, the output end of the seventh multiplier A7 is connected to the input end of the sixth adder F6, the elements stored in Ac[9][8] are output to the sixth adder F6, and the output end of the sixth adder F6 outputs the calculation result to Ac[9][8].

[0088] In this embodiment, at least eighteen registers are required, and the actual number may be more than eighteen.

[0089] Embodiment 2: Static and dynamic separation configuration method of state matrix of LQG control

[0090] This embodiment needs to adopt the state matrix static and dynamic separation configuration circuit of LQG control in Embodiment 1, such as Figure 4 As shown, this embodiment includes the following steps performed in sequence:

[0091] S1, judging whether the static matrix storage blocks [A] and [B] are initialized according to the sequential logic circuit module;

[0092] If the output of the sequential logic circuit module is "1", it proves that it is not initialized, and then enters the three-stage initialization of the static matrix, calculates the constant matrix elements of matrices A and B through the first digital circuit module and the second digital circuit module, and initializes the static matrix storage blocks [A] and [B];

[0093] If the sequential logic circuit module determines that the output is not "1", it proves that the initialization has been performed, and the initialized matrices A and B are directly used to execute step S2;

[0094] The three-stage initialization of the static matrix in step S1 includes the first stage initialization to the third stage initialization, and the first stage initialization to the third stage initialization can be performed simultaneously;

[0095] The first stage is initialized, such as Figure 5 As shown, first, the matrix elements in the static matrix storage block [A] and the static matrix storage block [B] of matrices A and B are set to 0, and then A[1][2], A[2][3], A[4][5], A[5][6], A[7][8], and A[8][9] in the static matrix storage block [A] are set to 1.

[0096] The second stage is initialized, and the first digital circuit module is used to calculate the element of the third row and first column of matrix B. Where, k1 is the servo valve gain, ω0 is the cutoff frequency of the servo valve;

[0097] Calculate the element stored in A[3][2]

[0098] Calculate the element A[3][3]=-2ω0ξ stored in A[3][3], where ξ is the damping coefficient of the servo valve;

[0099] The third stage is initialization, which assigns a value to the equivalent mass according to the value of the external mode and calculates it through the second digital circuit module;

[0100] When the external mode value is 0, set M = M m , where M is the equivalent mass, M m For the equivalent mass of the hammer and the oil, the calculation reuse module is called to calculate five intermediate results, which are output and assigned one by one to A[6][1], A[6][8], A[6][5], A[6][6], and A[6][9] in the static matrix storage block [A];

[0101] When the external mode value is 1, set M = M p , where M p To obtain the equivalent mass of the piston rod and the plate, the calculation multiplexing module is called to calculate five intermediate results, and the five intermediate results are inverted through the inversion selection module, and are output and assigned one by one to A[9][1], A[9][8], A[9][5], A[9][6], and A[9][9] in the static matrix storage block [A].

[0102] The calculation process of calling the calculation reuse module to calculate five intermediate results in step S13 is as follows:

[0103] Define tmp1 = B*M, where B is the hydraulic cylinder oil compression coefficient;

[0104] tmp2=A p *k q , where A p is the piston area of ​​the hydraulic cylinder, k q is the flow gain of the main valve of the hydraulic cylinder;

[0105] tmp3=k c +C tp , where k c is the hydraulic cylinder flow pressure coefficient, C tp is the total leakage coefficient of the hydraulic cylinder;

[0106]

[0107] Among them, H s is the rigidity coefficient between the weight and the piston;

[0108] Among them, H v is the viscous damping coefficient between the weight and the piston;

[0109] The five intermediate results are:

[0110] Var3 = -Var2;

[0111] Var5=tmp6.

[0112] S2. The dynamic element configuration unit generates continuous-time state matrices Ac and Bc; the dynamic matrix elements of matrices A and B are calculated through the third digital circuit module; the constant matrix elements and dynamic matrix elements of matrices A and B are stored together in the dynamic matrix storage block [Ac][Bc].

[0113] Calculating the dynamic storage unit matrix elements in step S2 includes the following steps performed in sequence:

[0114] S21, copy the constant matrix elements of matrices A and B to the continuous-time state matrices Ac and Bc;

[0115] S22. Definition Where S p is the area of ​​the plate;

[0116] S23, calculate two intermediate results Var1'=G s *tmp1', Var2' = G v *tmp1', where G s is the earth rigidity coefficient, G v is the earth damping coefficient;

[0117] S24. Obtain the elements stored in Ac[9][8] in the continuous-time state matrix Ac, add the elements stored in Ac[9][8] to the intermediate result Var1', and write them back to Ac[9][8]; add the elements stored in Ac[9][9] to the intermediate result Var2', and write them back to Ac[9][9] to obtain the complete continuous-time state matrices Ac and Bc.

Claims

1. A state matrix static and dynamic separation configuration circuit controlled by LQG, characterized in that: It includes a static element configuration unit and a dynamic element configuration unit; The static element configuration unit is used to calculate the constant matrix elements of matrices A and B, and initialize the static matrix storage blocks [A] and [B]. The static element configuration unit includes a sequential logic circuit module for determining whether the static matrix storage blocks [A] and [B] are initialized, a first digital circuit module for initializing the static matrix storage blocks [A] and [B], and a second digital circuit module for initializing the static matrix storage blocks [A] and [B]. The determination result of the sequential logic circuit module is output to the first digital circuit module and the second digital circuit module, and the first digital circuit module and the second digital circuit module transmit the initialized static matrix to the dynamic element configuration unit. The dynamic element configuration unit is used to calculate the dynamic matrix elements of matrices A and B, generate continuous-time state matrices Ac and Bc, and store them in the dynamic matrix storage block [Ac][Bc]; the dynamic element configuration unit includes a third digital circuit module.

2. The state matrix static and dynamic separation configuration circuit of LQG control according to claim 1, characterized in that: The static matrix storage block [A] is composed of 9*9 storage units, each storage unit is represented by A[a][b], a∈[1,9], b∈[1,9], and the static matrix storage block [B] is composed of 9*1 storage units, each storage unit is represented by B[m][1], m∈[1,9]; each storage unit is a 32-bit single-precision floating-point storage unit; The dynamic matrix storage block [Ac] consists of 9*9 storage units, each storage unit is represented as Ac[p][q], p∈[1,9], q∈[1,9]; the dynamic matrix storage block [Bc] consists of 9*1 storage units, each storage unit is represented as Bc[n][1], n∈[1,9], and each storage unit is a 32-bit single-precision floating-point storage unit.

3. The state matrix static and dynamic separation configuration circuit of LQG control according to claim 2, characterized in that: The sequential logic circuit module includes a counter; The first digital circuit module includes a first register R1 to a fourth register R4 for storing servo valve parameters and coefficients, a first multiplier A1 to a second multiplier A2, a first squarer B1 and a first inverter C1; The output end of the first register R1 is connected to the input end of the first multiplier A1, and the output end of the first multiplier A1 outputs the calculation result to B[3][1]; the output end of the second register R2 is connected to the first squarer B1 and the input end of the second multiplier A2, the output end of the first squarer is connected to the input end of the first multiplier A1 and the first inverter C1, and the output end of the first inverter C1 outputs the calculation result to A[3][2]; the output end of the third register R3 and the output end of the fourth register R4 are connected to the input end of the second multiplier A2, and the output end of the second multiplier A2 outputs the calculation result to A[3][3].

4. The LQG controlled state matrix static and dynamic separation configuration circuit according to claim 2 or 3, characterized in that: The second digital circuit module includes a quality selection module, a calculation multiplexing module and a negation selection module, the output end of the quality selection module is connected to the input end of the calculation multiplexing module, and the output end of the calculation multiplexing module is connected to the input end of the negation selection unit; The quality selection module includes a fifth register R5 to a sixth register R6, and a first two-way selector D1; the calculation multiplexing module includes a seventh register R7 to a fourteenth register R14, a first adder F1 to a fourth adder F4, a third multiplier A3 to a sixth multiplier A6, a first divider E1 to a fifth divider E5, a second squarer B2, a second inverter C2 to a fourth inverter C4; the inversion selection module includes a second two-way selector D2 to a sixth two-way selector D6, and a fifth inverter C5 to a ninth inverter C9; The output end of the fifth register R5 is connected to the first input end of the second two-way selector D2, the output end of the sixth register R6 is connected to the second input end of the second two-way selector D2, the external mode output end is connected to the third input end of the second two-way selector D2; the output end of the second two-way selector D2 is connected to the input end of the fourteenth register R14; The output end of the seventh register R7 and the output end of the eighth register R8 are connected to the input end of the first adder F1, the output end of the first adder F1 is connected to the input end of the third multiplier A3 and the input end of the fifth multiplier A5; the input end of the third multiplier A3 is connected to the output end of the ninth register R9, the output end of the third multiplier A3 is connected to the input end of the second adder F2, the tenth register R10 is connected to the input end of the second adder F2 through the second squarer B2, the output end of the second adder F2 is connected to the input end of the first divider E1, and the tenth register R10 is connected to the input end of the second adder F2 through the second squarer B2. The output ends of the third register R13 and the fourteenth register R14 are connected to the input end of the sixth multiplier A6, the output end of the sixth multiplier A6 is connected to the input end of the first divider E1, the output end of the first divider E1 is connected to the input end of the third adder F3, the twelfth register is connected to the input end of the third adder F3 through the fourth divider E4, the output end of the third adder F3 is divided into two branches for output, the first branch is connected to the input end of the second two-way selector D2, and the second branch is connected to the input end of the third two-way selector D3 through the second inverter C2; The output end of the ninth register R9 and the output end of the fourteenth register R14 are connected to the input end of the second divider E2, the first output end of the second divider E2 is connected to the input end of the fourth adder F4, and the second output end of the second divider E2 is connected to the input end of the fourth two-way selector D4; The output end of the thirteenth register R13 and the output end of the fourteenth register R14 are connected to the input end of the sixth multiplier A6, the output end of the fifth register R5 is connected to the input end of the fifth multiplier A5, the output end of the fifth multiplier A5 and the output end of the sixth multiplier A6 are connected to the input end of the fifth divider E5, the output end of the fifth divider E5 is connected to the input end of the fourth adder F4, and the output end of the fourth adder F4 is connected to the input end of the fifth two-way selector D5 through the third inverter C3; The output end of the tenth register R10 and the output end of the eleventh register R11 are connected to the input end of the fourth multiplier A4, the output end of the fourth multiplier A4 is connected to the input end of the third divider E3, the output end of the sixth multiplier A6 is the input end of the third divider E3, and the output end of the third divider E3 is connected to the input end of the sixth two-way selector D6 through the fourth inverter C4; The second input terminals of the second to sixth two-way selectors D2 to D6 are all connected to inverters, and the external mode output terminals are respectively connected to the third input terminals of the second to sixth two-way selectors D2 to D6, and the output terminals of the second to sixth two-way selectors D2 to D6 are correspondingly output to A[6][8], A[6][5], A[6][9], A[6][6], A[6][1] or A[9][8], A[9][5], A[9][9], A[9][6], A[9][1].

5. The state matrix static and dynamic separation configuration circuit of LQG control according to claim 4, characterized in that: The third digital circuit module includes a fifteenth register R15 to an eighteenth register R18, a fifth adder F5, a sixth adder F6, a seventh multiplier A7, an eighth multiplier A8 and a sixth divider E6; The output end of the seventeenth register R17 and the output end of the eighteenth register R18 are connected to the input end of the sixth divider E6, the output end of the sixth divider E6 and the output end of the sixteenth register R16 are connected to the input end of the eighth multiplier A8, the output end of the eighth multiplier A8 is connected to the input end of the fifth adder F5, the elements stored in Ac[9][8] are output to the fifth adder F5, and the output end of the fifth adder F5 outputs the calculation result to Ac[9][8]; The output end of the fifteenth register R15 and the output end of the eighteenth register R18 are connected to the input end of the seventh multiplier A7, the output end of the seventh multiplier A7 is connected to the input end of the sixth adder F6, the elements stored in Ac[9][8] are output to the sixth adder F6, and the output end of the sixth adder F6 outputs the calculation result to Ac[9][8].

6. A method for static and dynamic separation configuration of a state matrix of LQG control, implemented by using the static and dynamic separation configuration circuit of the state matrix of LQG control according to any one of claims 1 to 5, characterized in that: The method comprises the following steps performed in sequence: S1, judging whether the static matrix storage blocks [A] and [B] are initialized according to the sequential logic circuit module; If the sequential logic circuit module determines that the output is 1, it proves that it is not initialized, and then enters the three-stage initialization of the static matrix, calculates the constant matrix elements of matrices A and B through the first digital circuit module and the second digital circuit module, and initializes the static matrix storage blocks [A] and [B]; If the sequential logic circuit module determines that the output is not 1, it proves that the initialization has been performed, and the initialized matrices A and B are directly used to execute step S2; S2. The dynamic element configuration unit generates continuous-time state matrices Ac and Bc; the dynamic matrix elements of matrices A and B are calculated through the third digital circuit module; the constant matrix elements and dynamic matrix elements of matrices A and B are stored together in the dynamic matrix storage block [Ac][Bc].

7. According to the LQG controlled state matrix static and dynamic separation configuration method of claim 6, the LQG controlled state matrix static and dynamic separation configuration circuit adopted also includes a static matrix storage block [A] composed of 9*9 storage units, each storage unit is represented by A[a][b], a∈[1,9], b∈[1,9]; a static matrix storage block [B] composed of 9*1 storage units, each storage unit is represented by B[m][1], m∈[1,9]; A dynamic matrix storage block [Ac] composed of 9*9 storage units, each storage unit is represented by Ac[p][q], p∈[1,9], q∈[1,9]; a dynamic matrix storage block [Bc] composed of 9*1 storage units, each storage unit is represented by Bc[n][1], n∈[1,9]; each storage unit in the static matrix storage blocks [A], [B] and the dynamic matrix storage blocks [Ac], [Bc] is a 32-bit single-precision floating-point storage unit, characterized in that: The three-stage initialization of the static matrix in step S1 includes: In the first stage of initialization, first set the matrix elements in the static matrix storage block [A] and the static matrix storage block [B] of matrices A and B to 0, and then set A[1][2], A[2][3], A[4][5], A[5][6], A[7][8], and A[8][9] in the static matrix storage block [A] to 1; The second stage is initialized, and the first digital circuit module is used to calculate the element of the third row and first column of matrix B. Where, k1 is the servo valve gain, ω0 is the cutoff frequency of the servo valve; Calculate the element stored in A[3][2] Calculate the element A[3][3]=-2ω0ξ stored in A[3][3], where ξ is the damping coefficient of the servo valve; The third stage is initialization, which assigns a value to the equivalent mass according to the value of the external mode and calculates it through the second digital circuit module; When the external mode value is 0, set M = M m , where M is the equivalent mass, M m For the equivalent mass of the hammer and the oil, the calculation reuse module is called to calculate five intermediate results, which are output and assigned one by one to A[6][1], A[6][8], A[6][5], A[6][6], and A[6][9] in the static matrix storage block [A]; When the external mode value is 1, set M = M p , where M p To obtain the equivalent mass of the piston rod and the plate, the calculation multiplexing module is called to calculate five intermediate results, and the five intermediate results are inverted through the inversion selection module, and are output and assigned one by one to A[9][1], A[9][8], A[9][5], A[9][6], and A[9][9] in the static matrix storage block [A].

8. The static and dynamic separation configuration method of the state matrix of LQG control according to claim 7 is characterized in that: The calculation process of calling the calculation reuse module to calculate five intermediate results in step S13 is: Define tmp1 = B*M, where B is the hydraulic cylinder oil compression coefficient; tmp2=A p *k q , where A p is the piston area of ​​the hydraulic cylinder, k q is the flow gain of the main valve of the hydraulic cylinder; tmp3=k c +C tp , where k c is the hydraulic cylinder flow pressure coefficient, C tp is the total leakage coefficient of the hydraulic cylinder; Among them, H s is the rigidity coefficient between the weight and the piston; Among them, H v is the viscous damping coefficient between the weight and the piston; The five intermediate results are: Var3=-Var2; 9. The static and dynamic separation configuration method of the state matrix of LQG control according to claim 6, characterized in that: The calculation of the dynamic storage unit matrix elements in step S2 includes the following steps performed in sequence: S21, copy the constant matrix elements of matrices A and B to the continuous-time state matrices Ac and Bc; S22. Definition Where S p is the area of ​​the plate; S23, calculate two intermediate results Var1'=G s *tmp1', Var2' = G v *tmp1', where G s is the earth rigidity coefficient, G v is the earth damping coefficient; S24, obtain the element stored in Ac[9][8] in the continuous-time state matrix Ac, add the element stored in Ac[9][8] to the intermediate result Var1', and write it back to Ac[9][8]; Add the elements stored in Ac[9][9] to the intermediate result Var2' and write them back to Ac[9][9] to obtain the complete continuous-time state matrix Ac, Bc.

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